Semiconductor package and semiconductor electronic device

Abstract

A semiconductor package includes an insulating substrate (11), a pair of signal electrodes (121), a pair of differential lines (14) connected to the signal electrodes (121) respectively, and a ground conductor. The differential lines (14) each include a first signal line (142), a second signal line (144), a first via conductor (141), and a second via conductor (143). The ground conductor includes a ground plane (11g), a ground plane (15g) sandwiching the first signal line (142) between the ground plane (11g) and forming a strip line configuration, and a ground via conductor (145) provided along the second via conductor and forming a coaxial configuration. In a planar perspective of the first surface, a position on a surface having the ground plane (11g) including the second end portion (143c) is a gap region (11f).

Description

Technical Field

[0001] This disclosure relates to semiconductor packages and semiconductor electronic devices. Background Technology

[0002] In a semiconductor package, signals transmitted and received between signal terminals and electronic components located within the package's internal space are transmitted via signal paths such as signal lines and through conductors (via conductors) within the package. Japanese Patent Application Publication No. 2020-53533 discloses a technique where an insulating substrate with a gap between the electrode conductors of a pair of signal lines transmitting a differential signal is used. By constructing the bottom surface of this gap as a ground plane, crosstalk caused by interference of high-frequency signals in the 1-60 GHz band is reduced between the signal lines. Summary of the Invention

[0003] Methods for solving problems

[0004] One aspect of this disclosure is a semiconductor package comprising:

[0005] An insulating substrate having a first surface and a second surface opposite to the first surface;

[0006] A pair of first electrodes are arranged side by side along one side of the first surface;

[0007] A pair of differential circuits are electrically connected to the pair of first electrodes respectively and transmit signals; and

[0008] Grounding conductor,

[0009] The insulating substrate has: a first groove located on the first surface, extending between the pair of first electrodes.

[0010] The pair of differential circuits each include:

[0011] The first signal line is located inside the insulating substrate and extends along the first surface;

[0012] The second signal line is located on the second surface;

[0013] A first connecting conductor electrically connects the first electrode and the first signal line inside the insulating substrate; and

[0014] The second connecting conductor is located inside the insulating substrate between the first signal line and the second signal line.

[0015] The grounding conductor comprises:

[0016] The first ground surface is located on the first surface;

[0017] The first groove is connected to the ground and is located on the bottom surface of the first groove;

[0018] The second ground plane is located inside the insulating substrate, sandwiching the first signal line between itself and the first surface; and

[0019] A grounding connection conductor is disposed inside the insulating substrate along the second connection conductor.

[0020] A portion of the grounding connection conductor is located around the second connection conductor, forming a coaxial structure together with the second connection conductor.

[0021] The first signal line forms a stripline structure in the area facing the first ground plane and the second ground plane.

[0022] In planar perspective of the first surface, the position of the first surface, which includes the end of the second connecting conductor on the opposite side to the contact of the second signal line, is a gap area without the first ground plane. Attached Figure Description

[0023] Figure 1 This is a perspective view of the semiconductor electronic device of this embodiment with the top cover removed.

[0024] Figure 2 This is a bottom view showing the first side of a semiconductor electronic device.

[0025] Figure 3A It is a diagram that enlarges a portion of the first side to show it in detail.

[0026] Figure 3B It is a bottom view that is enlarged to show a portion of the first side in detail.

[0027] Figure 4 This is a diagram showing a cross-section of a signal electrode that includes a wiring substrate.

[0028] Figure 5A This is a cross-sectional view of the wiring substrate.

[0029] Figure 5B This is a cross-sectional view of the wiring substrate.

[0030] Figure 6 This is a graph showing the simulation results related to the frequency dependence of the wiring board of this embodiment on the insertion loss of the signal.

[0031] Figure 7A This is a diagram illustrating the semiconductor package of Modified Example 1.

[0032] Figure 7B This is a diagram illustrating the semiconductor package of Modified Example 1.

[0033] Figure 8 This is a cross-sectional view showing one signal electrode of the wiring substrate including Modified Example 2.

[0034] Figure 9 This is a diagram illustrating the location of the differential lines in the wiring substrate of Modified Example 2. Detailed Implementation

[0035] The following description of the implementation method is based on the accompanying drawings.

[0036] Figure 1 This is a perspective view of the semiconductor electronic device 1 of this embodiment with the top cover removed.

[0037] The semiconductor electronic device 1 includes a semiconductor package 6, electronic components 7, and a cover 8.

[0038] The semiconductor package 6 includes a wiring substrate 10 and a frame 20, etc. In addition, the semiconductor package 6 may also have a fixture 3 for fixing to a substrate, etc.

[0039] The wiring substrate 10 and the frame 20 are joined together vertically (in the z-direction). The wiring substrate 10 is generally rectangular in shape when viewed from above in the z-direction (the corners may be rounded or omitted), but is not limited to this. The lower surface (first surface 10a) of the wiring substrate 10 is planar. The upper surface of the wiring substrate 10 includes: a planar portion one level lower in the center (third surface 10d); and a planar portion surrounding the third surface 10d and higher than the third surface 10d (second surface 10c).

[0040] Viewed from above, the frame 20 has an annular shape surrounding the outer edge of the wiring substrate 10. The frame 20 is joined to the second surface 10c. The second surface 10c has a portion wider than the width of the frame 20, forming a stepped shape. Here, the upper surface of the frame 20 has a uniform height. The semiconductor package 6 has the following shape: with the third surface 10d of the wiring substrate 10 as the bottom surface, and surrounded by the protrusions of the surrounding second surface 10c and the frame 20 in the direction of the side surface 4, it has an upwardly opening recess 201.

[0041] The wiring substrate 10 or frame 20 may have an opening 101 on one side of the semiconductor package 6. For example, in the case where the electronic component 7 includes optical components such as photodiodes or laser diodes, light energy can pass through this opening 101. The opening 101 can separate the inside and outside of the semiconductor package 6 with light-transmitting members such as glass or transparent resin.

[0042] The cover 8 is joined to the upper surface of the frame 20, covering the upper surface of the recess 201. Both the frame 20 and the cover 8 are conductors, such as metals containing iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or alloys thereof. The frame 20 and the cover 8 may be made of the same or different materials.

[0043] Wiring substrate 10 has insulating substrate 11 (reference) Figure 4 The circuit includes a grounding conductor and signal lines. The signal lines pass through the surface and interior of the insulating substrate 11, electrically connecting the terminal located on the second surface 10c to a lead 12a (lead terminal) protruding outward from the side 10b, which is one side of the first surface 10a. Furthermore, the grounding conductor is electrically connected to the ground of the lead 13a.

[0044] Electronic component 7 is located on the third surface 10d and converges inside the recess 201. The terminals of electronic component 7 are connected to the terminals of the second surface 10c (not shown) via bonding wires to transmit and receive signals.

[0045] Figure 2 This is a bottom view of the first side 10a of the semiconductor package 6 (wiring substrate 10).

[0046] Along the lower surface of the wiring substrate 10, at the end in the -x direction, i.e., edge 10b (one side of the first surface 10a), a plurality of signal electrodes 12 (first electrodes) and ground electrodes 13 (second electrodes) are arranged side by side with several gaps. The signal electrodes 12 have leads 12a (conductor connection portions), and the ground electrodes 13 have leads 13a (here, only one lead 12a and one lead 13a are shown). The remaining portion of the first surface 10a is not particularly limited, and the area around the signal electrodes 12 and most of the space outside the gap region 11f constitutes the ground plane 11g (first ground plane).

[0047] Figure 3A as well as Figure 3B This is a diagram showing a portion of the first face 10a in detail. Figure 3A It's a 3D image. Figure 3B It is a bottom view. Also, in the description, in... Figure 3A The leading lines 12a and 13a are omitted.

[0048] Signal electrode 12 comprises two (a pair) signal electrodes 121, 122 arranged side-by-side in the y-direction, which transmit differential signals as a pair. Ground electrode 13 is located on either side of the pair of signal electrodes 121, 122 in the y-direction. A coating film 11s is formed on the surface around the ground electrode 13. The coating film 11s is, for example, an aluminum oxide film. The ground electrode 13 and the surrounding ground plane 11g are connected below the coating film 11s.

[0049] Signal electrode 12 and ground electrode 13 are connected to edge 10b at one end, for example. Furthermore, these signal electrodes 12 and ground electrodes 13 extend in a direction perpendicular to edge 10b (x-direction). Lead 12a extends along the extension direction (x-direction) of the exposed surface on the first surface 10a of signal electrode 12 and engages with the exposed surface. Lead 13a extends along the extension direction (x-direction) of the exposed surface on the first surface 10a of ground electrode 13 and engages with the exposed surface. The remaining portions of leads 12a and 13a that are not engaged with the exposed surface are bent and led out to the outside of the wiring substrate 10 when viewed from above. The width of signal electrode 12 in the y-direction is, for example, 0.5-2 mm, and its length in the x-direction is 1-20 mm. The size of ground electrode 13 may be different from (and possibly slightly larger than) the size of signal electrode 12, or it may be the same.

[0050] The pair of signal lines transmitting differential signals, namely differential lines 14, will be described in detail later. They include a first via conductor 141 and a second via conductor 143. The first via conductor 141, when viewed from above, at least partially overlaps with the lead 12a (here, a partial overlap), extending directly from the first surface 10a into the interior (+z direction) of the insulating substrate 11. The differential line 14, as described later, bends inside the wiring substrate 10 and connects to the second via conductor 143, which is configured not to overlap with the frame 20. The gap region 11f, when viewed from a planar perspective through the interior of the insulating substrate 11 in the z direction, lies within the area (including both sides) overlapping the second via conductors 143 of the pair of differential lines 14. It is, for example, oblong (a shape combining two semicircles and a rectangle connecting these semicircles, also called a rounded rectangle). That is, the pair of second via conductors 143 overlap mutually with respect to a single gap region 11f when viewed from above.

[0051] exist Figure 3A The diagram shows three pairs of differential lines 14, in which adjacent differential lines 14 may share a ground electrode 13. The number of pairs of differential lines 14 can be appropriately determined according to the number of signals to be transmitted. Furthermore, in this… Figure 3A In this context, only any pair of structures is marked with a symbol, but the same structure applies to other pairs where the symbol is omitted.

[0052] Between a pair of signal electrodes 121 and 122, a first groove 111 is provided on the first surface 10a of the wiring substrate 10 (insulating substrate 11). The first groove 111 extends along the signal electrode 12, for example from the edge 10b in a direction perpendicular to the edge 10b (x direction) at a certain depth (distance from the first surface 10a, for example, 0, 5-5 mm, etc.).

[0053] Furthermore, a second groove 112 is provided between each signal electrode 12 and the ground electrode 13 adjacent to each signal electrode 12. The second groove 112 extends along the signal electrode 12, for example, from the side 10b in a direction perpendicular (x-direction) to the side 10b. The depth of the second groove 112 can be the same as the depth of the first groove 111 (e.g., 0.5-5 mm) or different (e.g., it can be shallower). Because the second groove 112 is shallower than the first groove 111, the arrangement of the differential line 14 extending from the signal electrode 12 within the wiring substrate 10 (insulating substrate 11) becomes relatively easier.

[0054] The shapes of the first groove 111 and the second groove 112 are, for example, roughly elongated rectangles with a width (length in the y-direction) of 0.2-2 mm and a length (length in the x-direction) slightly shorter than the length of the signal electrode 12 (1-20 mm) when viewed from above (bottom view). They are rounded (for the second groove 112, the radius of curvature is approximately 0.1-1 mm; the shape of the front end of the first groove 111 will be described later) and taper near the point furthest from the edge 10b (the front end). Furthermore, the first groove 111 may be longer than the second groove 112. The shape in the depth direction is rectangular when viewed from the side in the x-direction, with a flat bottom. The shapes of the first groove 111 and the second groove 112 may also differ from these. For example, the first groove 111 and / or the second groove 112 may also be conical, inverted conical, or multi-tiered stepped when viewed from the side.

[0055] like Figure 3B As shown, the first groove 111 is divided into a base 111a and a protrusion 111b. The base 111a has a semi-circular, rounded portion with a radius of curvature of about 0.1-1 mm at its long rectangular front end (the end furthest from the edge 10b), similar to that of the second groove 112. The protrusion 111b is connected to the aforementioned semi-circular front end of the first groove 111 (the other end of the side opposite to one side of the edge 10b of the base 111a). For example, the center position of the semi-circular front end of the base 111a and the center position of the semi-circular portion of the protrusion 111b are equal in the y-direction. The protrusion 111b is narrower in the y-direction along the edge 10b than the base 111a (e.g., 0.2 mm in width). Furthermore, the protrusion 111b has a shape that is narrower towards the front end (where the x-component is larger). The shape of the protrusion 111b is, for example, a semi-cylindrical shape with a radius of 0.05 mm (semi-circular when viewed from above), which can achieve better stress dispersion than a rectangular shape, but is not limited to this.

[0056] Thus, the wiring substrate 10 is constructed such that the length of the first slot 111 is obtained within a possible range, and the distance from the first slot 111 to the position of the first via conductor 141 is made relatively large. Since if the first via conductor 141 and the first slot 111 and the second slot 112 are too close, cracks or the like are likely to occur during their formation. Therefore, the first slot 111 and the second slot 112 need to be at least a given distance away from the first via conductor 141 (to obtain clearance). On the other hand, if the first slot 111 and the second slot 112 are too short, problems such as a decrease in the characteristic impedance of the differential line 14 are likely to occur.

[0057] Grounding conductors 111g (grounding the ground in the first slot) and 112g (grounding the ground in the second slot) are respectively provided on the bottom surfaces of the first slot 111 and the second slot 112 (planes parallel to the first surface 10a on the +z side relative to the first surface 10a). By providing the signal electrode 121 with not only a ground plane 11g but also a wider ground plane, crosstalk between the signal electrodes 12 can be reduced, thereby improving high-frequency characteristics.

[0058] The protrusion 111b can be the same depth as the base 111a (e.g., 0.5-5 mm) or shallower. The grounding conductor 111g in the first groove 111 can extend to the bottom surface of the protrusion 111b. These depths can be determined by taking into account the length of the first via conductor 141, i.e., the distance of the first signal line 142 from the ground plane 11g. Furthermore, when the material (dielectric constant) of the insulating substrate 11 varies depending on the application, the depth can be different between the base 111a and the protrusion 111b to adjust the characteristic impedance, etc.

[0059] The front end of the grounding conductor 111g in the first slot 111 (protrusion 111b) is located closer to the edge 10b than the front end of the signal electrode 12 when viewed from above. Here, the grounding conductor 111g does not extend further away from the aforementioned edge 10b than the position of the first via conductor 141 when viewed from above.

[0060] Alternatively, a ground plane can also be provided on the inner wall (side) of the protrusion 111b, replacing the through hole to electrically connect the ground plane 11g and the ground plane 15g.

[0061] Furthermore, as in this embodiment, by having the first slot 111 and the grounding conductor 111g symmetrical about the center lines of the two signal electrodes 121 and 122 in the y-direction, the difference in the influence of the first slot 111 and the grounding conductor 111g on the signal electrodes 121 and 122 can be reduced. This reduces deviations in signal transmission characteristics, such as transmission speed (propagation delay) and differences in signal loss.

[0062] Thus, by constructing a region between a pair of signal electrodes 121 and 122 with a dielectric constant lower than that of the insulating substrate 11, the dielectric constant between the signal electrodes 12 can be reduced compared to their arrangement side-by-side on the plane of the insulating substrate 11. Therefore, even with a narrower spacing between the signal electrodes 121 and 122, a decrease in characteristic impedance is suppressed. Furthermore, the depth of the first trench 111 and / or the second trench 112, i.e., the distance from the first surface 10a, can also be equal to the distance from the first surface 10a to the ground plane 15g (described later) located inside the insulating substrate 11 (see reference). Figure 4 The distances are the same. In this case, the ground plane 15g can extend to the grounding conductors l11g and 112g on the bottom surfaces of the first slot 111 and the second slot 112. Alternatively, the first slot 111 and the second slot 112 can be filled with other insulating members with a dielectric constant lower than that of the insulating substrate 11.

[0063] Ground plane 11g and ground electrode 13 are electrically connected to other ground planes inside the wiring board 10 through a large number of grounding via conductors (black circles in the figure).

[0064] Figure 4 This is a cross-sectional view showing a signal electrode 121 of the wiring substrate 10 and a differential line 14 in the xz plane. Furthermore, Figure 5A It includes Figure 4 A cross-sectional view of section line AA. Figure 5B It includes Figure 4 A cross-sectional view of section line BB. The structure of the section containing signal electrode 122 is basically the same as that of the section containing signal electrode 121, and the description is omitted.

[0065] As described above, a differential circuit 14 is connected within the wiring substrate 10 via the signal electrode 121. Each signal line of the differential circuit 14 includes a first via conductor 141 (first connecting conductor), a first signal line 142, a second via conductor 143 (second connecting conductor), and a second signal line 144. The first signal line 142 extends parallel to the lower surface (first surface 10a) of the wiring substrate 10 within the insulating substrate 11. The second signal line 144 is located on the upper surface (second surface 10c) of the wiring substrate 10. The first via conductor 141 extends perpendicularly to the first surface 10a, electrically connecting the signal electrode 121 and the first signal line 142. The second via conductor 143, located between the first signal line 142 and the second signal line 144 in the differential circuit 14, extends perpendicularly to the first surface 10a. Here, one end of the second via conductor 143 (the second end 143c on the side opposite to the contact of the second signal line 144) is directly connected to one end of the first signal line 142 (the first end 142c on the side opposite to the contact of the first via conductor 141), thereby electrically connecting the first signal line 142 and the second signal line 144.

[0066] The insulating substrate 11 has a ground plane 15g (second ground plane) inside it, parallel to the ground plane 11g of the first surface 10a. The ground plane 11g and the ground plane 15g are separated by... Figure 2 , Figure 3A , Figure 3B The conductors are electrically connected via multiple grounding vias, as shown by the black circles.

[0067] The wiring, including signal electrode 12, ground electrode 13, ground planes 11g and 15g, and differential line 14, is, for example, a metal layer containing metal materials such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese, or combinations thereof. Furthermore, a nickel plating or gold plating layer can be further superimposed on the surface of this metal layer. Such a plating layer improves corrosion resistance and weather resistance. In addition, it improves the wettability of bonding materials such as solder and brazing filler metal that bond with the metal layer.

[0068] As described above, the first via conductor 141 overlaps with the frame 20 when viewed from above. Therefore, if the first via conductor 141 were to pass through the insulating substrate 11 in this manner, it would be too close to the frame 20 to allow for adjustment of the characteristic impedance. Therefore, it is connected via the first signal line 142 to the second via conductor 143, which does not overlap with the frame 20 when viewed from above.

[0069] The first signal line 142 is located between ground plane 11g and ground plane 15g. Thus, the portion of the first signal line 142 sandwiched between ground plane 11g and ground plane 15g (opposite to ground planes 11g and 15g) together forms a stripline structure. The distances of the first signal line 142 from ground plane 11g and from ground plane 15g are determined based on the characteristic impedance involved in the stripline structure.

[0070] Furthermore, between grounding ground surfaces 11g and 15g and grounding ground surface 16g of the second surface 10c, there are multiple grounding via conductors 145 (grounding connection conductors) arranged parallel to the second via conductor 143. In the cross-sectional view, one grounding via conductor 145 is shown on each side, but as... Figure 5A As shown, a portion of the grounding via conductor 145 is positioned to surround the second via conductor 143 at a given distance. The second via conductor 143 and the grounding via conductor 145 in this positional relationship form a coaxial configuration. The given distance between the second via conductor 143 and the surrounding grounding via conductor 145 is determined based on the characteristic impedance related to the coaxial configuration. Furthermore, other grounding surfaces exist within the insulating substrate 11, such as between ground surfaces 15g and 16g, and the grounding via conductor 145 can also be electrically connected to them.

[0071] like Figure 5B As shown, on the second surface 10c, the second signal line 144 is examined at the end facing the recess 201 and is electrically connected to the electronic component 7 via bonding wires, etc., as described above.

[0072] In this way, a pair of differential lines 14 are directly connected from the signal electrode 12 to the interior of the wiring substrate 10 (insulating substrate 11), without any signal lines extending into the first surface 10a. As a result, in this wiring substrate 10, losses from signal lines, especially in high-frequency signals above tens of GHz, can be reduced.

[0073] Furthermore, a pair of differential lines 14 inside the wiring substrate 10 generate a mode change between a coaxial structure and a stripline structure. In order to reduce the change in characteristic impedance at the bending portion involved in the mode change, when viewed from a plane perpendicular to the first surface 10a (Z direction), at the bending position, i.e., the position of the junction containing the first signal line 142 and the second via conductor 143, the wiring substrate 10 has no ground plane 11g on the first surface 10a, becoming a gap region 11f where the insulating substrate 11 is exposed (or a protective coating may be applied).

[0074] like Figure 2As shown in the diagram, the gap region 11f is common to the pair of second via conductors 143 of the pair of differential lines 14. The outer periphery of the gap region 11f is not particularly defined and can be defined as the inner edge of the plurality of grounding via conductors forming the coaxial structure. As a result, the loss caused by high-frequency signals radiated from this gap region can be reduced while suppressing variations in characteristic impedance.

[0075] In addition, such as Figure 3A as well as Figure 3B As shown in the diagram, the first via conductor 141 is configured such that at least a portion overlaps with the lead 12a when viewed from above. Therefore, since no signal lines are routed on the first surface 10a, the lead 12a and the inner layer of the insulating substrate 11 directly below it are connected to allow high-frequency signals to pass through, thus suppressing radiation of high-frequency signals from the first surface 10a.

[0076] Lead 12a (lead 13a) is connected to an external substrate 2, such as a PCB (printed circuit board). Fixture 3 securely supports the semiconductor package 6 on the substrate 2.

[0077] In the manufacture of the wiring substrate 10, for example, multiple insulating sheets (ceramic green sheets) obtained by laminating a slurry made by mixing powdered materials (e.g., alumina and silicon oxide) with organic binders and solvents into sheets can be laminated, pressed, and fired (e.g., heated at approximately 1600°C in a reducing environment) to produce the insulating substrate 11. The fired substrate is suitable for processing such as cutting and punching. Furthermore, in the manufacture of the ground plane 15g and the first signal line 142 inside the insulating substrate 11, for example, firstly, the aforementioned conductor metal, binder, and organic solvent are mixed to prepare a metal paste. Next, the metal paste is applied to the insulating sheet that is either above or below the insulating sheet during the lamination of the above-mentioned insulating sheets by screen printing or the like. Then, as described above, it is laminated with a regular insulating sheet, pressed, and fired.

[0078] For example, through-holes can be formed during or after the aforementioned layering process, the aforementioned metal paste can be filled into the holes, and then the process can be completed by firing, thereby obtaining the first through-hole conductor 141, the second through-hole conductor 143, and the grounding through-hole conductor 145, etc. The through-holes can be formed, for example, by punching with a metal pin or by laser processing. The metal paste can be filled, for example, by using or using vacuum suction.

[0079] The first groove 111 and the second groove 112 can be formed by slotting the corresponding portions of the formed insulating substrate 11.

[0080] The ground planes 11g and 16g, signal electrode 12, ground electrode 13, and second signal line 144 located on the exposed surface of the insulating substrate 11 can be obtained by sintering a metallization layer on the surface of the insulating substrate 11, or by plating. In addition, nickel plating or gold plating layers can be further superimposed on the surface of the metal layer.

[0081] Figure 6 This is a graph showing the simulation results, comparing the insertion loss (b) of a frequency-dependent signal based on the wiring board 10 of this embodiment with the insertion loss (a) of a signal based on a conventional wiring board. Furthermore, the insertion loss is measured from the tip of lead 12a to the end of the second signal line 144. A larger value, closer to 0 [dB], indicates lower insertion loss.

[0082] In existing wiring boards, the second via conductor 143 directly connects the first surface 10a and the second surface 10c, and a signal line electrically connecting the second via conductor 143 and the signal electrode 12 is provided on the surface of the first surface 10a. Compared with this existing wiring board, the insertion loss of high-frequency signals, especially 60-80 GHz signals, can be reduced.

[0083] [Variation Example]

[0084] Figure 7A as well as Figure 7B This is a diagram illustrating a modified example 1 of the semiconductor package 6.

[0085] As described above, a gap is required around the signal electrodes 121 and 122, between them and the ground plane 11g. Figure 7A In the bottom view, the position of the first via conductor 141 extends across the width w. In planar perspective, the first signal line 142a does not overlap with the ground plane 11g.

[0086] To compensate for the insufficient capacitance of the first signal line 142a within this range, in the semiconductor package 6 of Modified Example 1, the first signal line 142a has a wide portion 1421 between the connection portion with the first via conductor 141 and the portion that does not overlap with the ground plane 11g in planar view (different from the gap region 11f). The wide portion 1421 can extend throughout the entire width w, including the portions that overlap with the signal electrodes 121 and 122 in planar view. By widening the width of the first signal line 142a, capacitance is added at this portion, thereby reducing the characteristic impedance. The width of the wide portion 1421 can be determined based on the characteristic impedance.

[0087] At this time, the first signal line 142a can have a wide portion 1421 so as not to narrow the spacing between the pair of differential lines 14. That is, the first signal line 142a expands in the Y direction in planar perspective, opposite to the first slot 111. By not unnecessarily narrowing the distance between the first signal lines 142a, the increase in the influence on the signal between the pair of first signal lines 142a can be suppressed.

[0088] Furthermore, in the above embodiment, the first via conductor 141 and the second via conductor 143 are located at the same position with respect to the Y direction, but they can also be located at different positions with respect to the Y direction depending on the setting of the spacing (pitch) of the leads 12a. In this case, the width between the differential lines 14 (the first signal line 142a) can also be adjusted within the range of the width w.

[0089] exist Figure 7B The simulation results show the results of calculating the insertion loss of the portion between the lead 12a corresponding to the width portion 1421 and the second via conductor 143.

[0090] As described in the above embodiment, compared to case (b) without the wide portion 1421, even in case (c) where the portion overlapping with the signal electrodes 121 and 122 does not have the wide portion 1421, the insertion loss decreases in the high-frequency range above 60 GHz. Furthermore, it can be seen that in case (d) where the entire width w, including the portion overlapping with the signal electrodes 121 and 122, has the wide portion 1421, the insertion loss decreases even more significantly in the high-frequency range.

[0091] Figure 8 This is a diagram showing a cross-section in the xz plane of a signal electrode 121 and a differential line 14 of the wiring substrate 10 in Modified Example 2, which includes the semiconductor package 6. Furthermore, as will be described later, in this Modified Example 2, since the differential line 14 includes a portion bent in the y-direction, the positions of the cross-sections (with respect to the y-direction) are different on the left and right sides of the dashed line C.

[0092] Here, the differential line 14 is bent at multiple points between the first signal line 142b and the second via conductor 143 so that, along a curve such as a hyperbola, the third signal line 146 and the third via conductor 147 (the third connecting conductor) are alternately arranged side by side. That is, between the first signal line 142b and the second via conductor 143, multiple sets of the third via conductor 147 and the third signal line 146, which are connected at one end to each other, are connected in series.

[0093] By making the differential line 14 curved, reflection loss can be significantly reduced. However, since it is difficult to arrange multiple curved wirings in a suitable positional relationship within the insulating substrate 11, reflection loss is reduced in the wiring substrate 10 by bending. This bending is a small scale shorter than the signal length, so as to approximate a curved shape. Therefore, in the differential line 14, the ratio of the length of the third via conductor 147 to the length of the third signal line 146 in each group is greater than the ratio of the length of the first via conductor 141 to the length of the first signal line 142b, and this ratio is larger the closer to the second end 143c.

[0094] The ground plane 15g is also divided into different z-direction positions within the insulating substrate 11 according to the positions of the first signal line 142b and multiple third signal lines 146, and the multiple ground planes 15g are connected by grounding via conductors 145.

[0095] In Modification 2, the gap region 11f is independent of each differential line 14. In planar perspective, the gap region 11f contains at least the second via conductor 143 of each differential line 14, and may also contain part or all of the third via conductor 147.

[0096] Figure 9 This is to explain from Figure 8 A diagram showing the position of the differential line 14 as viewed from the bottom side of the wiring substrate 10 in Modified Example 2.

[0097] The first signal line 142b, extending parallel to the ground plane 15g within the insulating substrate 11, has a bend 142e between the first via conductor 141 and the second via conductor 143. While bringing the distance between the differential lines 14 closer together enhances the signal bonding, the minimum distance between the second via conductors 143 is limited. The bend 142e, in planar perspective, is located near the boundary of the gap region 11f, forming a shape that partially brings the distance between the differential lines 14 closer together outside the gap region 11f. A specific distance is determined to obtain a suitable characteristic impedance. In addition to being coaxial lines associated with the second via conductor 143 and stripline lines associated with the first signal line 142b, in the gap region 11f, the third signal line 146, etc., are grounded coplanar lines located around the ground plane in the xy direction. The appropriate inter-line distance between the differential lines of the coaxial line is wider than that between the differential lines of other lines. Therefore, the distance is adjusted to a suitable level before and after the aforementioned bend 142e. By enhancing the bonding force between the differential signals, the signal characteristics in the high-frequency band are improved.

[0098] As described above, the semiconductor package 6 of this embodiment includes: an insulating substrate 11 having a first surface 10a and a second surface 10c opposite to the first surface 10a; a pair of signal electrodes 12 arranged side by side along one side of the first surface 10a; a pair of differential lines 14 electrically connected to the pair of signal electrodes 12 respectively to transmit signals; and a grounding conductor. The insulating substrate 11 has a first groove 111 located on the first surface 10a and extending between the pair of signal electrodes 12. The pair of differential lines 14 each includes: a first signal line 142 located inside the insulating substrate 11 and extending along the first surface 10a; a second signal line 144 located on the second surface 10c; a first via conductor 141 electrically connecting the signal electrodes 12 and the first signal line 142 inside the insulating substrate 11; and a second via conductor 143 located inside the insulating substrate 11 between the first signal line 142 and the second signal line 144. The grounding conductor includes: a ground plane 11g located on the first surface 10a; a grounding conductor 111g located on the bottom surface of the first groove 111; a ground plane 15g located inside the insulating substrate 11, sandwiching the first signal line 142 between it and the first surface 10a; and a grounding via conductor 145 disposed inside the insulating substrate 11 along the second via conductor. A portion of the grounding via conductor 145 is located around the second via conductor 143, forming a coaxial structure together with the second via conductor. The first signal line 142 forms a stripline structure with the ground plane 11g and the ground plane 15g in the area opposite to them. In planar perspective of the first surface 10a, the position of the second end 143c of the second via conductor 143 is a gap region 11f without the ground plane 11g.

[0099] In this way, by directly advancing from the signal electrode 121 to the insulating substrate 11 via the differential line 14, high-frequency signals radiated from the surface of the first surface 10a are suppressed, thereby reducing signal loss. Furthermore, for this purpose, the differential line 14 generates a mode change between a stripline structure and a coaxial structure within the insulating substrate 11. By configuring a structure in which a gap region 11f is provided at the ground plane 11g of the first surface 10a corresponding to this switching portion, adverse effects on the characteristic impedance can be suppressed. Therefore, even for signals at higher frequencies than before, a suitable characteristic impedance can be maintained and signal loss can be reduced more effectively. Consequently, higher frequency signals can be transmitted in this semiconductor package 6.

[0100] Furthermore, when viewed from above on the first surface 10a, the furthest point of the grounding conductor 111g from the edge 10b is located closer to the edge 10b than the furthest point of the signal electrode 12 from the edge 10b. Therefore, the grounding conductor 111g can be positioned within a range that does not affect signal transmission.

[0101] Furthermore, the first trench 111 has a base 111a and a protrusion 111b, which is connected to a front end opposite to one side of the edge 10b of the base 111a, and its width in the y direction perpendicular to the x-direction in which the first trench 111 extends is narrower than that of the base 111a. Therefore, since the surface area (volume) of the first trench 111 can be widened while ensuring a given distance between the first trench 111 and the first via conductor 141, the generation of defects such as cracks during the formation of the first trench 111 and the first via conductor 141 is suppressed. On the other hand, by reducing the dielectric constant corresponding to the first trench 111, the distance between the signal electrodes 121 and 122 can be narrowed, thereby achieving miniaturization of the semiconductor package 6.

[0102] Furthermore, the first end 142c of the first signal line 142, which is opposite to the contact of the first via conductor 141, and the second end 143c of the second via conductor 143, which is opposite to the contact of the second signal line 144, can be directly connected. With such a configuration, it can be easily formed without significantly increasing the effort required, thereby reducing signal loss.

[0103] Furthermore, as in Modification 1, the first signal line 142a, in a plane perspective view of the first surface 10a, has a wide portion 1421 within a width w that is different from the gap region 11f and does not overlap with the ground plane 11g, having a locally wider linewidth in the Y direction perpendicular to the extension direction (X direction) of the first signal line 142a. Since a gap is required between the signal electrode 12 and the ground plane 11g, the ground plane corresponding to the first signal line 142a is insufficient on the connection side between the first via conductor 141 and the first signal line 142a. In contrast, in the semiconductor package 6, by locally widening the linewidth of the first signal line 142a in this portion, the capacitance of the signal line is locally increased, the characteristic impedance can be appropriately determined, thereby stably transmitting signals with less loss than before.

[0104] Furthermore, the wide portion 1421 can extend as a whole between the location where the first signal line 142a is connected to the first via conductor 141 and the boundary of the area where the first signal line 142a overlaps with the ground plane 11g in a planar perspective of the first surface.

[0105] Furthermore, the width of the wide portion 1421 can also be extended to the side opposite to the first slot 111 when viewed in plan view of the first surface 10a. That is, since the distance between the two adjacent first signal lines 142a is not reduced, the situation where the first signal lines 142a interfere with each other and thus degrade the signal can be suppressed.

[0106] Furthermore, as in Modification 2, the first end 142c of the first signal line 142b is located closer to the first surface 10a and closer to the first via conductor 141 in planar perspective of the first surface 10a than the second end 143c of the second via conductor 143. The first end 142c and the second end 143c are connected via a third via conductor 147 parallel to the first via conductor 141 and a third signal line 146 parallel to the first signal line 142.

[0107] In this way, by changing the direction of the differential line 14 in a small, step-like manner instead of bending it all at once, the signal loss caused by abrupt changes in direction can be reduced.

[0108] Furthermore, particularly between the first end 142c and the second end 143c, multiple sets of third via conductors 147 and third signal lines 146, which are connected at one end to each other, are connected in series. The ratio of the length of the third via conductor 147 to the length of the third signal line 146 is greater than the ratio of the length of the first via conductor 141 to the length of the first signal line 142b, and the ratio is larger the closer the set is to the second end 143c.

[0109] In this way, by changing the average tilt of the differential line so that the direction from the first signal line 142b to the second via conductor 143 gradually tends to be upward and downward (z direction), signal loss can be further reduced.

[0110] Furthermore, the spacing of the first signal lines 142b in the differential line 14 is wider than the spacing of the second via conductors 143. That is, the spacing can be changed midway through the differential line 14 so that the spacing of the differential line 14 can be appropriately determined according to both the stripline line configuration and the coaxial line configuration. Moreover, even when the spacing of the vias cannot be narrowed in the configuration, the signal bonding force can be improved by locally narrowing the spacing of the differential line 14 in a portion of the stripline line, thereby enhancing the characteristics in the high-frequency region.

[0111] Furthermore, in planar perspective, the position of the third via conductor 147 can be contained within the gap region 11f. In this case, the third signal line 146 is constructed as a grounded coplanar line, which allows for easy and appropriate adjustment of characteristics between the first signal line 142b and the second via conductor 143.

[0112] Furthermore, the gap regions 11f involved in each pair of differential lines 14 are interconnected single regions. This reduces the variation in the characteristic impedance of the differential signal, thereby enabling better transmission of high-frequency signals.

[0113] Alternatively, the gap region 11f can be isolated by each of the second via conductors 143 of the differential line 14. In this case, better transmission of high-frequency signals than before can also be achieved through appropriately designed paths.

[0114] Furthermore, in planar perspective of the first surface 10a, the outer edge of the gap region 11f overlaps semi-circularly with the inner edge of the grounding via conductor 145, which forms a coaxial structure for each of the pair of second via conductors 143. This suppresses the influence of characteristic impedance variations involved in signal transmission within the coaxial structure and reduces the radiation of high-frequency signals from the gap region 11f, thereby enabling better transmission of high-frequency signals than before.

[0115] Furthermore, the semiconductor package 6 includes a pair of ground electrodes 13, located on the opposite side of the pair of signal electrodes 12 along the y-direction of the edge 10b, respectively, and electrically connected to a ground plane 11g. The insulating substrate 11 has a second groove 112 located between the signal electrode 12 and the ground electrode 13. A grounding conductor 112g is provided on the bottom surface of the second groove 112.

[0116] This reduces the dielectric constant between the signal electrode 12 and the ground electrode 13, thereby suppressing the possibility of a decrease in the characteristic impedance of the high-frequency signal line.

[0117] Furthermore, each of the pair of signal electrodes 12 has a lead 12a. When viewed from above on the first surface 10a, the lead 12a overlaps with at least a portion of the first via conductor 141. Thus, by suppressing signal transmission along the first surface 10a as much as possible between the lead 12a and the first via conductor 141, signal loss in the high-frequency band can be further reduced, in particular.

[0118] Furthermore, the semiconductor electronic device 1 of this embodiment includes: the semiconductor package 6 described above; electronic components 7 electrically connected to a pair of differential lines 14; and a cover 8.

[0119] According to the semiconductor electronic device 1, even if the signal output from the electronic component 7 and / or the signal input to the electronic component 7 is at a higher frequency than in the past, it can still be transmitted.

[0120] Furthermore, the above implementation is illustrative and various modifications can be made.

[0121] For example, in the above embodiment, it was described that ceramic green sheets were stacked, pressed, and fired to produce the insulating substrate 11, but this method is not limited to this. Other methods can also be used as long as the differential circuit 14 is appropriately provided inside.

[0122] Furthermore, the front end of the first groove 111 may not be located closer to the edge 10b than the front end of the signal electrode 12, as shown in the above embodiment. Where there are no dimensional issues, the front end of the first groove 111 may be located slightly further away from the edge 10b than the front end of the signal electrode 12.

[0123] Furthermore, the first groove 111 may not be connected to the edge 10b. That is, the first groove 111 may be a hole-like groove located inside the first surface 10a. The shape of the hole is not particularly limited, for example, it may be oblong.

[0124] Furthermore, the first groove 111 may not be a combination of the base 111a and the protrusion 111b as described above. For example, the protrusion 111b may be triangular or the like. Alternatively, it may not be divided into the base 111a and the protrusion 111b, but may be a single conical shape or the like.

[0125] Furthermore, the gap region 11f can be set separately for each pair of differential lines 14, or it can be common to multiple pairs of differential lines 14.

[0126] Furthermore, the shape of the gap region 11f is not limited to an oblong shape as described above. For example, it may have a dumbbell shape, where the rectangular portion connecting the inner edges of a pair of grounding via conductors 145 to each other is narrowed to a width narrower than the diameter of the coaxial structure. In addition, it may be slightly offset from the inner edge of the grounding via conductors 145 forming the coaxial structure, for example, it may be a polygonal shape such as a rectangle.

[0127] Furthermore, in the above embodiment, it is described that the first via conductor 141 overlaps with the lead wire 12a by half when viewed from above, but it may be a different range, for example, it may overlap with the lead wire 12a entirely.

[0128] Furthermore, in the above embodiment, a configuration is described as having two ground electrodes 13 arranged side-by-side on the outer sides of the signal electrode 12 (GSSG configuration), with a second groove 112 between the signal electrode 12 and the ground electrode 13, but it is not limited to this. The second groove 112 may be omitted, and the position of the ground electrode 13 may also be different.

[0129] Furthermore, the shape of the semiconductor package 6 shown in the above embodiments is not limited. For example, the second surface 10c, located at a position higher than the third surface 10d, may not be a plane, or it may have portions with multiple heights. In addition, the first surface 10a may not be entirely a wiring substrate 10, but a portion of it may be another base plate, etc.

[0130] Furthermore, in the above embodiments, it is explained that the differential line 14 extends in the x-direction and z-direction, except for the portion where the interval is adjusted as shown in variations 1 and 2, but it may also have a component that extends in the y-direction.

[0131] Furthermore, in the above-described variation 1, it is described that the wide portion 1421 extends from the boundary of the ground plane 11g to the connection position between the first signal line 142a and the first via conductor 141 in planar perspective, but it is not limited to this. Figure 7B As shown in the diagram, even localized areas improve characteristic impedance. Furthermore, the wide portion 1421 does not necessarily extend to the position overlapping with the ground plane 11g in planar perspective, but it is not limited to the case where there is no overlap.

[0132] Furthermore, the wide portion 1421 is not limited to extending only to the side opposite to the first groove 111 in planar perspective. It can also extend to the side of the first groove 111 in a range that does not overlap with the grounding conductor 111g in planar perspective, for example.

[0133] Furthermore, the aforementioned semiconductor package 6 can be manufactured and sold separately from the electronic component 7. In this case, the cover 8 can be sold without being attached to the frame 20. Alternatively, the semiconductor package 6 may be without the frame 20. Furthermore, the semiconductor electronic device 1 may also be without the cover 8.

[0134] Otherwise, the specific structures, positional relationships, and materials shown in the above embodiments can be appropriately modified without departing from the spirit of this disclosure. The scope of this invention includes the scope of the invention as set forth in the claims and its equivalents.

[0135] Industrial availability

[0136] This invention can be used in semiconductor packages and semiconductor electronic devices.

Claims

1. A semiconductor package comprising: An insulating substrate having a first surface and a second surface opposite to the first surface; A pair of first electrodes are arranged side by side along one side of the first surface; A pair of differential circuits are electrically connected to the pair of first electrodes respectively and transmit signals; and Grounding conductor, The insulating substrate has: a first groove located on the first surface, extending between the pair of first electrodes. The pair of differential circuits each include: The first signal line is located inside the insulating substrate and extends along the first surface; The second signal line is located on the second surface; The first connecting conductor electrically connects the first electrode and the first signal line inside the insulating substrate; and The second connecting conductor, located inside the insulating substrate between the first signal line and the second signal line, electrically connects the first signal line and the second signal line. The grounding conductor comprises: The first ground surface is located on the first surface; The first groove is connected to the ground and is located on the bottom surface of the first groove; The second ground plane is located inside the insulating substrate, sandwiching the first signal line between itself and the first surface; and A grounding connection conductor is disposed inside the insulating substrate along the second connection conductor. A portion of the grounding connection conductor is located around the second connection conductor, forming a coaxial structure together with the second connection conductor. The first signal line forms a stripline structure in the area facing the first ground plane and the second ground plane. In planar perspective of the first surface, the position of the first surface, which includes the end of the second connecting conductor on the opposite side to the contact of the second signal line, is a gap area without the first ground plane.

2. The semiconductor package according to claim 1, wherein, When viewed from above on the first surface, the position of the ground plane in the first groove that is furthest from the side is located closer to the side than the position of the first electrode that is furthest from the side.

3. The semiconductor package according to claim 2, wherein, The first groove has: Base; and The protrusion, located on the opposite side of the base from the other side, has a width that is narrower than the base and is perpendicular to the direction in which the first groove extends.

4. The semiconductor package according to any one of claims 1 to 3, wherein, The first end of the first signal line, on the side opposite to the contact of the first connecting conductor, and the second end of the second connecting conductor, on the side opposite to the contact of the second signal line, are directly connected.

5. The semiconductor package according to any one of claims 1 to 3, wherein, The first signal line, in planar perspective of the first surface, has a wide portion that is not overlapping with the first ground plane and is different from the gap area. This wide portion has a line width that is locally wider and perpendicular to the extension direction of the first signal line.

6. The semiconductor package according to claim 5, wherein, The wide portion extends integrally between the location where the first signal line connects to the first connecting conductor and the boundary of the area where the first signal line overlaps with the first ground plane in planar perspective of the first surface.

7. The semiconductor package according to claim 5, wherein, The wide portion extends in width to the side opposite to the first groove when viewed in planar perspective of the first surface.

8. The semiconductor package according to any one of claims 1 to 3, wherein, The first end of the first signal line, on the side opposite to the contact of the first connecting conductor, is located closer to the first surface and closer to the first connecting conductor in planar perspective than the second end of the second connecting conductor, on the side opposite to the contact of the second signal line. The first end and the second end are connected via a third connecting conductor parallel to the first connecting conductor and a third signal line parallel to the first signal line.

9. The semiconductor package according to claim 8, wherein, The third connecting conductor, whose ends are connected to each other, is connected in series with multiple groups of the third signal lines. The ratio of the length of the third connecting conductor to the length of the third signal line is greater than the ratio of the length of the first connecting conductor to the length of the first signal line, and the ratio is larger closer to the second end.

10. The semiconductor package according to claim 8, wherein, The spacing between the first signal lines in the differential circuit is narrower than the spacing between the second signal lines.

11. The semiconductor package according to claim 8, wherein, In planar perspective, the position of the third connecting conductor is contained within the gap region.

12. The semiconductor package according to any one of claims 1 to 3, wherein, The gap regions involved in each of the pair of differential lines are single, interconnected regions.

13. The semiconductor package according to claim 8, wherein, The gap regions are isolated for each of the second connecting conductors.

14. The semiconductor package according to any one of claims 1 to 3, wherein, The outer edge of the gap region, when viewed in planar perspective of the first surface, overlaps with the inner edge of the grounding connection conductor forming the coaxial structure.

15. The semiconductor package according to any one of claims 1 to 3, wherein, The semiconductor package includes: a pair of second electrodes, located on the side opposite to one side of the first trench of each of the pair of first electrodes along the direction of said side, and electrically connected to the first ground plane. The insulating substrate has a second groove located between the first electrode and the second electrode. The grounding conductor includes a grounding point located in the second groove at the bottom of the second groove.

16. The semiconductor package according to any one of claims 1 to 3, wherein, The pair of first electrodes each have a conductor connection portion. When viewed from above on the first surface, the conductor connection portion overlaps with at least a portion of the first connecting conductor.

17. A semiconductor electronic device comprising: The semiconductor package according to any one of claims 1 to 16; and Electronic components electrically connected to the pair of differential lines.

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