Semiconductor devices, power conversion devices, and methods for manufacturing semiconductor devices

Abstract

The semiconductor device (100) includes a semiconductor element (1), a metal component (2), a metal thin film layer (3), a solder portion (51), and an alloy portion (41). The metal thin film layer (3) covers the metal component (2). The metal thin film layer (3) includes a first region (R1). The solder portion (51) bonds the semiconductor element (1) to the first region (R1) of the metal thin film layer (3). The alloy portion (41) is disposed outside the first region (R1). The alloy portion (41) is an alloy of the metal component (2) and the metal thin film layer (3). The metal thin film layer (3) has a higher wettability to the solder portion (51) than the metal component (2). The alloy portion (41) has a lower wettability to the solder portion (51) than the metal thin film layer (3).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, power conversion devices, and methods for manufacturing semiconductor devices. Background Technology

[0002] Due to the increasing severity of environmental problems such as global warming and acid rain, power modules, as semiconductor devices used in power generation, transmission, and regeneration, are rapidly gaining popularity. A key development focus for power modules is how to efficiently dissipate the significant heat generated within them due to the high current and voltage they handle. Aluminum is frequently used for the heat sink base and fins of power modules. Aluminum has high thermal conductivity and is lightweight.

[0003] However, aluminum cannot be bonded with ordinary solder. Therefore, to improve wettability with solder, metal plating such as copper or nickel is often applied to the surface of aluminum. In ceramic substrates with an aluminum conductor layer, the conductor layer is partially covered by a metal plating layer to limit the solder wetting range. That is, the solder wetting range is limited by the portion of the conductor layer exposed from the metal plating layer by removing the metal plating layer. For example, in Japanese Patent Application Publication No. 2011-60969 (Patent Document 1), after a metal plating layer (metal thin film layer) is applied to the entire surface of a resin substrate, unwanted portions of the metal plating layer are removed by etching with an etching solution.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2011-60969 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In the wiring substrate manufacturing method described in the aforementioned literature, unwanted portions of the metal thin film layer (metal plating) are removed by etching with an etching solution. Therefore, waste liquid is generated from the wet processing of the etching step.

[0009] This disclosure was made in view of the above-mentioned issues, and its purpose is to provide a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device that does not generate waste liquid from a wet processing procedure involving etching.

[0010] Methods for solving problems

[0011] The semiconductor device disclosed herein includes a semiconductor element, a metal component, a metal thin film layer, a solder portion, and an alloy portion. The metal thin film layer covers the metal component. The metal thin film layer includes a first region. The solder portion bonds the semiconductor element to the first region of the metal thin film layer. The alloy portion is disposed outside the first region. The alloy portion is an alloy of the metal component and the metal thin film layer. The metal thin film layer has higher wettability to the solder portion than the metal component. The alloy portion has lower wettability to the solder portion than the metal thin film layer.

[0012] Invention Effects

[0013] The alloy portion of this disclosure is positioned outside the first region. The alloy portion has lower wettability to the solder portion than the metal thin film layer. Therefore, the alloy portion can be used to limit the solder portion from extending to a position outside the first region. Consequently, the metal thin film layer can be removed without etching using an etching solution. Therefore, waste liquid generated by the wet processing of the etching step is not produced. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view that schematically shows the structure of the semiconductor device according to Embodiment 1.

[0015] Figure 2 This is a flowchart that schematically illustrates the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 3 This is a cross-sectional view that schematically shows the metal components, substrate, and metal thin film layer of the semiconductor device according to Embodiment 1.

[0017] Figure 4 This is a cross-sectional view that schematically shows the formation of an alloy portion by heating the metal components and metal thin film layer of the semiconductor device of Embodiment 1 using a laser.

[0018] Figure 5 This is a top view that schematically shows the semiconductor device of Embodiment 1 with an alloy portion formed.

[0019] Figure 6 This is a cross-sectional view that schematically shows the semiconductor element of the semiconductor device of Embodiment 1 being bonded to the metal thin film layer via a solder section.

[0020] Figure 7 This is a top view that schematically shows the solder section of the semiconductor device of Embodiment 1 being disposed on a metal thin film layer.

[0021] Figure 8 This is a cross-sectional view that schematically shows the case where the base plate of the semiconductor device of Embodiment 1 is bonded to the housing by an adhesive.

[0022] Figure 9 This is a cross-sectional view that schematically shows the structure of a semiconductor device according to a variation of Embodiment 1.

[0023] Figure 10 This is a top view that schematically shows a modified example of Embodiment 1 in which an alloy portion is formed in the form of a semiconductor device.

[0024] Figure 11 This is a top view that schematically shows the solder section of a semiconductor device in a modified embodiment 1, where the solder section is disposed on a metal thin film layer.

[0025] Figure 12 This is a cross-sectional view that schematically shows the structure of the semiconductor device according to Embodiment 2.

[0026] Figure 13 This is a cross-sectional view that schematically shows the formation of an alloy portion and a spacer by heating the metal components and metal thin film layer of the semiconductor device of Embodiment 2 using a laser.

[0027] Figure 14 This is a top view that schematically shows the semiconductor device of Embodiment 2 having an alloy portion and a spacer.

[0028] Figure 15 This is a cross-sectional view that schematically shows the formation of a back spacer by heating the metal components and metal thin film layer of the semiconductor device of Embodiment 2 using a laser.

[0029] Figure 16 This is a top view that schematically shows the solder section of the semiconductor device of Embodiment 2 being disposed on a metal thin film layer.

[0030] Figure 17 This is a cross-sectional view that schematically shows the case where the metal thin film layer of the semiconductor device of Embodiment 2 is bonded to the base plate through the back-side solder section.

[0031] Figure 18 This is a cross-sectional view that schematically shows the structure of the semiconductor device according to Embodiment 3.

[0032] Figure 19 This is a cross-sectional view that schematically shows the formation of a heat sink side spacer by heating the heat sink and the back metal thin film layer of the semiconductor device of Embodiment 3 using a laser.

[0033] Figure 20 This is a top view that schematically shows the semiconductor device of Embodiment 3 having a heat sink-side alloy portion and a heat sink-side spacer.

[0034] Figure 21This is a cross-sectional view that schematically shows the case where the metal thin film layer of the semiconductor device of Embodiment 3 is bonded to the back metal thin film layer through the back solder section.

[0035] Figure 22 This is a block diagram that schematically illustrates the structure of the power conversion device according to Embodiment 4.

[0036] Figure 23 This is a top view of the semiconductor element in Embodiment 5.

[0037] Figure 24 This is a top view of the semiconductor element with an alloy portion formed according to Embodiment 5.

[0038] Figure 25 This is a cross-sectional view of the semiconductor device with an alloy portion formed according to Embodiment 5. Detailed Implementation

[0039] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in the following description, the same or equivalent parts will be labeled with the same reference numerals, and will not be described repeatedly.

[0040] Implementation method 1.

[0041] use Figure 1 The structure of the semiconductor device 100 in Embodiment 1 will be described.

[0042] like Figure 1 As shown, the semiconductor device 100 includes a semiconductor element 1, a metal component 2, a substrate 23, a metal thin film layer 3, an alloy portion 41, and a solder portion 51. The semiconductor device 100 may also include a back-side solder portion 52, a base plate 6, a housing 7, a signal terminal 81, a main terminal 82, a first lead portion 83, a second lead portion 84, a sealing material 91, and an adhesive 92. The semiconductor device 100 is a power semiconductor device for electrical applications.

[0043] Semiconductor element 1 is a power semiconductor element used for electrical applications. In this embodiment, semiconductor element 1 includes an insulated gate bipolar transistor (IGBT). Semiconductor element 1 may also include, for example, a diode or a metal oxide semiconductor field-effect transistor (MOSFET). Semiconductor element 1 is, for example, a silicon (Si) semiconductor.

[0044] The metal component 2 is configured as a conductive layer. The metal component 2 has a higher thermal conductivity than the metal thin film layer 3. The metal component 2 may also have a lower density than the metal thin film layer 3. In this embodiment, the material of the metal component 2 is aluminum (Al). The material of the metal component 2 may also be, for example, titanium (Ti), stainless steel, iron (Fe), etc.

[0045] The metal component 2 may also include a first metal portion 21 and a second metal portion 22. The first metal portion 21 and the second metal portion 22 sandwich the substrate 23. The first metal portion 21 and the second metal portion 22 are each configured as a conductive layer. For example, the first metal portion 21 and the second metal portion 22 of the metal component 2 have a length of 45 mm, a width of 45 mm, and a thickness of 0.8 mm (the dimensions of the first metal portion 21 and the second metal portion 22 are, for example, 45 mm × 45 mm × 0.8 mm). In this embodiment, the material of the first metal portion 21 and the second metal portion 22 is aluminum (Al).

[0046] The substrate 23 is sandwiched between the first metal portion 21 and the second metal portion 22. The substrate 23 is, for example, a ceramic substrate. For example, the substrate 23 has a length of 45 mm, a width of 45 mm, and a thickness of 1.32 mm (the dimensions of the substrate 23 are 45 mm × 45 mm × 1.32 mm). In this embodiment, the material of the substrate 23 is silicon nitride (SiN). The material of the substrate 23 may also be, for example, aluminum nitride (AlN), alumina, or a zirconia-alumina composite material of zirconium oxide and alumina. For example, the substrate 23 with the first metal portion 21 and the second metal portion 22 attached has a length of 45 mm, a width of 45 mm, and a thickness of 1.92 mm (the dimensions of the substrate 23 with the first metal portion 21 and the second metal portion 22 attached are, for example, 45 mm × 45 mm × 1.92 mm).

[0047] A metal thin film layer 3 covers the metal component 2. The metal thin film layer 3 partially covers the metal component 2. The metal thin film layer 3 includes a first region R1. In this embodiment, the first region R1 is surrounded by an alloy portion 41. The first region R1 faces the semiconductor element 1. The first region R1 covers the metal component 2. The first region R1 is covered by a solder portion 51.

[0048] The metal thin film layer 3 has higher wettability to the solder portion 51 than the metal component 2. Furthermore, wettability refers to the wettability defined, for example, in JIS C 60068-2-83:2014.

[0049] In this embodiment, the metal thin film layer 3 is a nickel (Ni) plating. The thickness of the metal thin film layer 3 is, for example, an average of 5 μm. The nickel (Ni) plating is formed by electrolytic plating or electroless plating. The metal thin film layer 3 may also be a copper (Cu) plating.

[0050] Furthermore, the method for forming the metal thin film layer 3 is not limited to plating; it can also be vapor deposition, cold spraying, etc. Additionally, the metal component 2 and the metal thin film layer 3 can be pre-pressed cladding materials. When the metal component 2 and the metal thin film layer 3 are cladding materials, the metal component 2 is aluminum (Al), and the metal thin film layer 3 is nickel (Ni). Furthermore, the metal thin film layer 3 can also be a zinc (Zn) layer, a gold (Au) layer, or a silver (Ag) layer.

[0051] The metal thin film layer 3 may also include a first metal thin film portion 31 and a second metal thin film portion 32. The first metal thin film portion 31 and the second metal thin film portion 32 respectively cover the first metal portion 21 and the second metal portion 22. The first metal thin film portion 31 is bonded to the semiconductor element 1 via a solder portion 51. A first region R1 is provided in the first metal thin film portion 31. In this embodiment, the second metal thin film portion 32 is bonded to the base plate 6 via a back-side solder portion 52.

[0052] The alloy portion 41 is positioned outside the first region R1. In this embodiment, the alloy portion 41 completely surrounds the first region R1. That is, the alloy portion 41 has a ring shape. Therefore, the alloy portion 41 is configured to completely surround the solder portion 51. The alloy portion 41 is in contact with the solder portion 51.

[0053] The alloy portion 41 has a lower wettability to the solder portion 51 than the metal thin film layer 3. Therefore, the alloy portion 41 is configured as a photoresist. As a result, the wetting range of the solder portion 51 is limited by the alloy portion 41.

[0054] Alloy 41 is an alloy of metal component 2 and metal thin film layer 3. In this embodiment, alloy 41 is an aluminum (Al)-nickel (Ni) alloy. Pure nickel (Ni) is wettable, but when nickel (Ni) is alloyed, the alloy functions as a non-wetting corrosion resist. Specifically, the solid solution limit of aluminum (Al) relative to nickel (Ni) is 0% to 1% by mass, therefore, when aluminum (Al) is mixed into nickel (Ni), the aluminum (Al)-nickel (Ni) alloy can function as a corrosion resist.

[0055] The solder section 51 bonds the semiconductor element 1 to the first region R1 of the metal thin film layer 3. The semiconductor element 1 and the first region R1 of the metal thin film layer 3 sandwich the solder section 51. In this embodiment, the outer periphery of the solder section 51 is completely surrounded by the alloy section 41. Alternatively, although not shown, the outer periphery of the solder section 51 may also be partially surrounded by the alloy section 41. The back-side solder section 52 bonds the metal thin film layer 3 to the base plate 6.

[0056] In this embodiment, the solder section 51 and the back-side solder section 52 are solders with a composition of 95.5% by mass of lead (Pb), 3.0% by mass of tin (Sn), and 0.5% by mass of copper (Cu). The melting point of the solder section 51 and the back-side solder section 52 is, for example, 219°C. Alternatively, the solder section 51 and the back-side solder section 52 may also be solders with a composition of 99.3% by mass of lead (Pb) and 0.7% by mass of copper (Cu). In this case, the melting point of the solder section 51 and the back-side solder section 52 is 217°C. Alternatively, the solder section 51 and the back-side solder section 52 may also be solders with a composition of 95% by mass of lead (Pb) and 5% by mass of 5% tin (Sn). In this case, the melting point of the solder section 51 and the back-side solder section 52 is 240°C. The solder section 51 and the back-side solder section 52 are, for example, plate-shaped. For example, the solder part 51 has a length of 12mm, a width of 12mm, and a thickness of 0.1mm (the dimensions of the solder part 51 are, for example, 12mm × 12mm × 0.1mm).

[0057] The base plate 6 is configured to dissipate heat generated by the semiconductor element 1 to the outside of the semiconductor device 100. The bottom surface of the base plate 6 is exposed from the sealing material 91. The material of the base plate 6 is, for example, copper (Cu). For example, the base plate 6 has a length of 55 mm, a width of 55 mm, and a thickness of 3 mm (the dimensions of the base plate 6 are, for example, 55 mm × 55 mm × 3 mm).

[0058] The housing 7 surrounds the semiconductor element 1, the metal component 2, the metal thin film layer 3, the alloy part 41, the solder part 51, the back solder part 52, the base plate 6, the first lead part 83, the second lead part 84, and the sealing material 91. The material of the housing 7 is, for example, PPS (Polyphenylene Sulfide).

[0059] Signal terminal 81 is electrically connected to semiconductor element 1 via first lead portion 83. Main terminal 82 is electrically connected to semiconductor element 1 via second lead portion 84. In this embodiment, signal terminal 81 and main terminal 82 are copper (Cu) lead frames. The thickness of signal terminal 81 is, for example, 0.4 mm. The thickness of main terminal 82 is, for example, 0.64 mm.

[0060] The first lead portion 83 and the second lead portion 84 are, for example, aluminum (Al) leads. The first lead portion 83 and the second lead portion 84 are bonded to the semiconductor element 1, for example, by wire bonding. The first lead portion 83 electrically connects a signal pad (not shown) of the semiconductor element 1 to a signal terminal 81. This constitutes a control circuit. The wire diameter of the first lead portion 83 is, for example, 0.15 mm. The second lead portion 84 electrically connects a main terminal pad (not shown) of the semiconductor element 1 to a main terminal 82. This constitutes a main circuit. The wire diameter of the second lead portion 84 is, for example, 0.4 mm.

[0061] A sealing material 91 is filled inside the housing 7. The sealing material 91 seals the semiconductor element 1, metal component 2, metal thin film layer 3, alloy portion 41, solder portion 51, back-side solder portion 52, first lead portion 83, and second lead portion 84. The sealing material 91 is, for example, silicone gel. An adhesive 92 bonds the outer periphery of the base plate 6 to the inner periphery of the housing 7. The adhesive 92 is, for example, made of silicone resin.

[0062] Next, use Figures 1 to 8 The manufacturing method of the semiconductor device 100 according to Embodiment 1 will be described.

[0063] like Figure 2 As shown, the manufacturing method of semiconductor device 100 includes a preparation step S101, a forming step S102, and a bonding step S103.

[0064] First, such as Figure 3 As shown, in the preparation process S101 (refer to...) Figure 2 In the preparation of semiconductor element 1 (refer to...), Figure 1 The metal component 2 and the metal film layer 3 are respectively attached to both sides of the substrate 23. The metal component 2 is covered by the metal film layer 3. The first metal part 21 is covered by the first metal film part 31, and the second metal part 22 is covered by the second metal film part 32.

[0065] Next, as Figure 4 As shown, in the forming process S102 (refer to...) Figure 2 In this embodiment, an alloy portion 41, which is an alloy of the metal component 2 and the metal thin film layer 3, is formed on the outer side of the first region R1 by heating the metal component 2 and the metal thin film layer 3. The metal component 2 and the metal thin film layer 3 are heated to a temperature above the eutectic reaction temperature of the metal component 2 and the metal thin film layer 3. In this embodiment, the metal component 2 and the metal thin film layer 3 are heated to 640°C or higher, which is the eutectic reaction temperature of the metal component 2 made of aluminum (Al) and the metal thin film layer 3 made of nickel (Ni). When the metal thin film layer 3 is aluminum (Al) and the metal thin film layer 3 is copper (Cu), the metal component 2 and the metal thin film layer 3 are heated to 540°C or higher, which is the eutectic reaction temperature of aluminum (Al) and copper (Cu). Thus, the alloy portion 41 is formed.

[0066] The alloy portion 41 is formed by generating a liquid phase between the metal component 2 and the metal thin film layer 3 by irradiating the metal thin film layer 3 with laser L. Specifically, the liquid phase is generated by heating the metal component 2 and the metal thin film layer 3 to above the eutectic reaction temperature. Since the liquid phase moves as droplets, the alloy portion 41 can be raised higher due to surface tension, compared to simply oxidizing the metal (metal component 2 or metal thin film layer 3). The thickness of the alloy portion 41 can be, for example, tens of μm or more and 100 μm or less. Therefore, the alloy portion 41 can function as a spacer. Furthermore, in the reflow process of the semiconductor device 100 as a power module, a reduction furnace using formic acid and hydrogen is often used. In the case of simply oxidizing the metal (metal component 2 or metal thin film layer 3), the oxide is reduced in the reduction furnace, and thus the solder wettability is restored. In contrast, according to this embodiment, since the alloy portion 41 is not an oxide, even if it is reduced, it will not return to the metal that produces solder wettability. In other words, the effect of reduction on the alloy portion 41 can be suppressed.

[0067] In this embodiment, in the forming process S102 (refer to...) Figure 2 In this embodiment, the metal component 2 and the metal thin film layer 3 are heated by irradiating the metal thin film layer 3 with a laser L, thereby forming the alloy portion 41. In this embodiment, the laser L is a YAG (Yttrium Aluminum Garnet) laser. The wavelength of the YAG laser in this embodiment is 1064 nm. Furthermore, the output of the YAG laser in this embodiment is 100 W. The alloy portion 41 is formed along the irradiation pattern of the laser L.

[0068] Alternatively, the metal thin film layer 3 can be heated using light sources such as carbon dioxide lasers and electron beams. Furthermore, the method for heating the metal thin film layer 3 is not limited to lasers; it can also be achieved using localized heating tools such as pulse heating devices.

[0069] In this embodiment, such as Figure 5 As shown, the alloy portion 41 is formed in a ring shape. Therefore, the alloy portion 41 includes a ring-shaped portion 411. The alloy portion 41 may also include multiple ring-shaped portions 411. The width of the ring-shaped portion 411 is, for example, 1 mm. For example, it may also include a resist pattern with a longitudinal length of 15 mm and a transverse length of 15 mm, and a resist pattern with a longitudinal length of 15 mm and a transverse length of 13 mm. The metal thin film layer 3 includes: a first region R1, which is surrounded by the ring-shaped portion 411; and an outer region R0, which is disposed outside the ring-shaped portion 411.

[0070] Next, as Figure 6 As shown, in the joining process S103 (refer to...) Figure 2In this process, the semiconductor element 1 is bonded to the metal thin film layer 3 using the solder section 51 disposed in the first region R1. For example, the semiconductor element 1, the metal thin film layer 3, and the solder section 51 are heated at 260°C for 5 minutes using a reflow oven, thereby bonding the semiconductor element 1 to the metal thin film layer 3 using the solder section 51.

[0071] Furthermore, the metal film layer 3 is bonded to the base plate 6 using the back-side solder section 52. The back-side solder section 52 is sandwiched between the metal film layer 3 and the base plate 6 with a thickness of 0.3 mm. For example, the metal film layer 3 and the base plate 6 are heated at 260°C for 5 minutes in a reflow oven, thereby bonding the metal film layer 3 to the base plate 6 using the back-side solder section 52.

[0072] like Figure 7 As shown, the solder section 51 is configured to be surrounded by the annular portion 411. Therefore, the annular portion 411 surrounds the solder section 51. From the semiconductor element 1 and the metal component 2 (see reference...) Figure 1 Viewed from the overlapping direction, the annular portion 411 surrounds the semiconductor element 1 and the solder portion 51. The semiconductor element 1 can also form a 2-in-1 module. For example, the semiconductor element 1 in a 2-in-1 module includes two IGBTs and two diodes. For example, the IGBTs have a vertical length of 12 mm and a horizontal length of 12 mm. The diodes have a vertical length of 12 mm and a horizontal length of 10 mm. The first region R1 of the metal thin film layer 3 (refer to...) Figure 5 The outer region R0 of the metal film layer 3 is not covered by the solder section 51.

[0073] Next, as Figure 8 As shown, the base plate 6 is joined to the housing 7 using adhesive 92. Signal terminals 81 and main terminals 82 are formed on the housing 7 by insert molding. Next, as... Figure 1 As shown, sealing material 91 is filled inside the housing 7. Sealing material 91 is processed by heating at 130°C for 1 hour. As a result, sealing material 91 is cured.

[0074] The semiconductor device 100 is manufactured through the above steps.

[0075] Next, use Figures 9-11 The structure of the semiconductor device 100 in a modified example of Embodiment 1 will be described.

[0076] like Figure 9 and Figure 10 As shown, the alloy portion 41 of the semiconductor device 100 in the modified embodiment 1 further includes a plurality of protrusions 412.

[0077] like Figure 11As shown, multiple protrusions 412 protrude from the annular portion 411 toward the solder portion 51. Viewed from the direction in which the semiconductor element 1 and the metal thin film layer 3 overlap, the multiple protrusions 412 protrude from the annular portion 411 toward the semiconductor element 1. The solder portion 51 includes multiple protrusions 511. The multiple protrusions 511 respectively enter between adjacent protrusions 412 in the multiple protrusions 412. Thus, unevenness is provided on the outer periphery of the solder portion 51. The multiple protrusions 511 have a thickness.

[0078] Next, the effects of this embodiment will be explained.

[0079] According to the semiconductor device 100 of Embodiment 1, such as Figure 1 As shown, the alloy portion 41 is positioned outside the first region R1. The alloy portion 41 has a lower wettability to the solder portion 51 than the metal thin film layer 3. Therefore, the alloy portion 41 can be used to limit the solder portion 51 from extending to a position outside the first region R1. Consequently, the metal thin film layer 3 can be removed without etching using an etching solution. Therefore, waste liquid generated by the wet processing of the etching step is not produced.

[0080] Since the alloy portion 41 can be used to limit the solder portion 51 from extending to a position outside the first region R1, the metal thin film layer 3 can be left uncut. Therefore, it is not necessary to implement countermeasures against the dust generated during cutting.

[0081] Because the solder portion 51 is prevented from extending to a position further outward than the first region R1, the thinning of the solder portion 51 can be prevented. This, in turn, prevents a decrease in the reliability of the semiconductor device 100 due to temperature cycling, etc. Furthermore, it prevents the solder portion 51 from wetting and extending beyond the alloy portion 41 to the end of the metal component 2 and reaching the substrate 23. This, in turn, prevents a decrease in the insulation of the substrate 23.

[0082] like Figure 7 As shown, the annular portion 411 surrounds the solder portion 51. Therefore, it is possible to further suppress the solder portion 51 from expanding beyond the first region R1 (see reference). Figure 5 The outermost position.

[0083] According to a variation of the semiconductor device 100 of Embodiment 1, such as Figure 11 As shown, multiple protrusions 412 protrude from the annular portion 411 toward the solder portion 51. Therefore, the multiple protrusions 511 of the solder portion 51 respectively enter between adjacent protrusions 412. Consequently, the outer periphery of the solder portion 51 is provided with irregularities. Therefore, compared to the case where the outer periphery of the solder portion 51 is straight, the surface area of ​​the solder portion 51 can be increased. That is, the cooling rate of the solder portion 51 can be accelerated. Therefore, shrinkage cavities caused by the solidification shrinkage of the solder portion 51 can be suppressed.

[0084] According to the manufacturing method of the semiconductor device 100 in Embodiment 1, such as Figure 4 As shown, in the forming process S102 (refer to...) Figure 2 In this process, an alloy portion 41, which is an alloy of the metal component 2 and the metal thin film layer 3, is formed on the outer side of the first region R1 by heating the metal component 2 and the metal thin film layer 3. The alloy portion 41 has a lower solder-resistant portion 51 (see reference 3) than the metal thin film layer 3. Figure 1 The alloy portion 41 can be used to limit the solder portion 51 from extending to a position outside the first region R1. Therefore, the metal thin film layer 3 can be removed without etching using an etching solution. Thus, waste liquid generated by the wet processing of the etching step is not produced.

[0085] like Figure 4 and Figure 5 As shown, in the forming process S102 (refer to...) Figure 2 In this process, the metal component 2 and the metal thin film layer 3 are heated by irradiating the metal thin film layer 3 with a laser L, thereby forming an alloy portion 41. The temperature of the areas of the metal component 2 and the metal thin film layer 3 irradiated by the laser L rises sharply due to the laser L. As a result, warping or deformation of the metal component 2 and the metal thin film layer 3 due to heating can be suppressed. Furthermore, since the alloy portion 41 is formed in the area irradiated by the laser L, the shape of the alloy portion 41 can be easily controlled using the laser L.

[0086] Implementation method 2.

[0087] Next, use Figure 12 The structure of the semiconductor device 100 in Embodiment 2 will be described. Unless otherwise specified, Embodiment 2 has the same structure, manufacturing method, and effects as Embodiment 1 described above. Therefore, the same reference numerals are used for structures identical to those in Embodiment 1, and the description will not be repeated.

[0088] like Figure 12 As shown, the semiconductor device 100 of this embodiment also includes a spacer 42 and a back-side spacer 43. The spacer 42 protrudes further toward the semiconductor element 1 than the metal thin film layer 3 in the first region R1. Specifically, the spacer 42 protrudes further toward the semiconductor element 1 than the first metal thin film portion 31 in the first region R1.

[0089] The protrusion of the spacer 42 is, for example, 0.03 mm or more. If the protrusion of the spacer 42 is 0.03 mm or more, even if the aluminum (Al) ratio in the alloy of the spacer 42 is 1.0% or less and the spacer 42 reacts with the solder portion 51, melting of the spacer 42 into the solder portion 51 can be suppressed. Since the dissolution rate of nickel (Ni) relative to tin (Sn) based solder is 0.01 μm / s, melting of the spacer 42 into the solder portion 51 can be suppressed even if the spacer 42 is heated to above the melting point of the solder for 2000 seconds or more. The semiconductor element 1 overlaps with the spacer 42 across the solder portion 51.

[0090] The protrusion of the back side spacer 43 is, for example, 0.03 mm or more. The back side spacer 43 protrudes further toward the base plate 6 than the second metal film portion 32. The base plate 6 overlaps with the back side spacer 43 via the back side solder portion 52.

[0091] Spacer 42 and back-side spacer 43 are alloys of metal component 2 and metal thin film layer 3. Therefore, the wettability of spacer 42 and back-side spacer 43 to solder portion 51 and back-side solder portion 52 is lower than the wettability of metal thin film layer 3 to solder portion 51 and back-side solder portion 52. In this embodiment, the materials of spacer 42 and back-side spacer 43 are the same as the material of alloy portion 41.

[0092] Next, use Figures 13-17 The manufacturing method of the semiconductor device 100 according to Embodiment 2 will be described.

[0093] like Figure 13 As shown, in the forming process S102 (refer to...) Figure 2 In the process, by heating the metal component 2 and the metal thin film layer 3 in the first region R1 of the metal thin film layer 3, a spacer 42, which is an alloy between the metal thin film layer 3 and the metal component 2, is formed. Specifically, in the formation process S102 (see...), Figure 2 In this process, by heating the metal component 2 and the metal thin film layer 3 in the first region R1 of the first metal thin film portion 31, a spacer 42 is formed as an alloy of the metal thin film layer 3 and the metal component 2.

[0094] like Figure 13 and Figure 14 As shown, in this embodiment, laser L is irradiated at the four corners of the first region R1 of the metal thin film layer 3. Therefore, the spacer 42 includes four spacer portions 421. The four spacer portions 421 are respectively disposed at the four corners of the first region R1.

[0095] In addition, such as Figure 15 As shown, in the joining process S103 (refer to...) Figure 2In this embodiment, a back-side spacer 43, which is an alloy of the metal thin film layer 3 and the metal component 2, is formed by heating the metal component 2 and the metal thin film layer 3 in the second metal thin film portion 32. Although not shown, in this embodiment, the back-side spacer 43 includes four back-side spacers. The four back-side spacers are respectively disposed at the four corners of the second metal thin film portion 32.

[0096] Next, as Figure 16 and Figure 17 As shown, in the joining process S103 (refer to...) Figure 2 In the bonding process S103 (see reference 51), the semiconductor element 1 is configured to overlap with the spacer 42 across the solder portion 51. Figure 2 In this configuration, the base plate 6 is configured to overlap with the back side spacer 43 across the back side solder section 52.

[0097] Next, the effects of this embodiment will be explained.

[0098] According to the semiconductor device 100 of Embodiment 2, such as Figure 12 As shown, the spacer 42 protrudes further toward the semiconductor element 1 than the metal thin film layer 3 in the first region R1. The semiconductor element 1 overlaps with the spacer 42 via the solder portion 51. Therefore, the spacing between the semiconductor element 1 and the metal thin film layer 3 is greater than or equal to the protrusion of the spacer 42. This ensures that a distance greater than or equal to the protrusion of the spacer 42 is maintained as the spacing between the semiconductor element 1 and the metal thin film layer 3. This also helps to suppress the thinning of the solder portion 51 between the semiconductor element 1 and the metal thin film layer 3. Therefore, it helps to suppress the decrease in reliability of the semiconductor device 100 due to temperature cycling, etc.

[0099] Furthermore, since the thickness of the solder portion 51 between the semiconductor element 1 and the metal thin film layer 3 is suppressed, the tilting of the semiconductor element 1 can be suppressed. As a result, it is possible to prevent the first lead portion 83 and the second lead portion 84 from failing to properly bond with the semiconductor element 1.

[0100] like Figure 12 As shown, the back-side spacer 43 protrudes further toward the base plate 6 than the metal thin film layer 3. The base plate 6 overlaps with the back-side spacer 43 across the back-side solder portion 52. Therefore, the distance between the metal thin film layer 3 and the base plate 6 is greater than or equal to the protrusion of the back-side spacer 43. This ensures that the distance between the metal thin film layer 3 and the base plate 6 is greater than or equal to the protrusion of the back-side spacer 43. This helps to suppress the thinning of the back-side solder portion 52. This helps to suppress the decrease in reliability of the semiconductor device 100 due to temperature cycling, etc. Furthermore, it helps to suppress the tilting of the substrate 23.

[0101] According to the manufacturing method of the semiconductor device 100 in Embodiment 2, such as Figure 16and Figure 17 As shown, in the joining process S103 (refer to...) Figure 2 In this configuration, the semiconductor element 1 is arranged to overlap with the spacer 42 via the solder portion 51. Therefore, the spacing between the semiconductor element 1 and the metal thin film layer 3 is greater than or equal to the protrusion of the spacer 42. This prevents the solder portion 51 between the semiconductor element 1 and the metal thin film layer 3 from becoming too thin. Consequently, it prevents a decrease in reliability of the semiconductor device 100 due to temperature cycling, etc.

[0102] Implementation method 3.

[0103] Next, use Figure 18 The structure of the semiconductor device 100 in Embodiment 3 will be described. Unless otherwise specified, Embodiment 3 has the same structure, manufacturing method, and effects as Embodiment 1 described above. Therefore, the same reference numerals are used for structures identical to those in Embodiment 1, and the description will not be repeated.

[0104] like Figure 18 As shown, the semiconductor device 100 of this embodiment also includes a heat sink HS, a heat sink-side metal thin film layer 35, a back-side alloy portion 44, a heat sink-side spacer 45, and a back-side solder portion 52.

[0105] The heat sink HS includes a base portion HS1 and multiple fin portions HS2. The base portion HS1 is bonded to the metal thin film layer 3 via a back-side solder portion 52. The multiple fin portions HS2 are respectively connected to the base portion HS1 on the side opposite to the semiconductor element 1. The heat sink HS has a higher thermal conductivity than the heat sink-side metal thin film layer 35. The heat sink HS may also have a lower density than the heat sink-side metal thin film layer 35. The material of the heat sink HS is, for example, aluminum (Al). The material of the heat sink HS may also be the same as the material of the metal component 2.

[0106] A heat sink-side metal film layer 35 covers the heat sink HS. The heat sink-side metal film layer 35 covers the base portion HS1 and each of the plurality of fin portions HS2 of the heat sink HS. The heat sink-side metal film layer 35 includes a second region R2. The second region R2 is disposed on the base portion HS1. The second region R2 faces the second metal film portion 32. In this embodiment, the second region R2 is surrounded by a back-side alloy portion 44.

[0107] The heat sink-side metal film layer 35 has higher wettability to the back-side solder portion 52 than the heat sink HS. The heat sink-side metal film layer 35 is, for example, a nickel (Ni) plating. The material of the heat sink-side metal film layer 35 can also be the same as the material of the metal film layer 3.

[0108] The back-side alloy portion 44 is positioned further outward than the second region R2. In this embodiment, the back-side alloy portion 44 surrounds the back-side solder portion 52. The back-side alloy portion 44 is an alloy of the heat sink HS and the heat sink-side metal film layer 35. The material of the back-side alloy portion 44 may also be the same as the material of the alloy portion 41. The back-side alloy portion 44 has lower wettability to the back-side solder portion 52 than the heat sink-side metal film layer 35.

[0109] The back-side solder section 52 bonds the heat sink HS to the second region R2 of the heat sink-side metal thin film layer 35. The back-side solder section 52 is disposed in the second region R2.

[0110] The heat sink side spacer 45 protrudes further toward the metal film layer 3 than the heat sink side metal film layer 35 in the second region R2. Specifically, the heat sink side spacer 45 protrudes further toward the second metal film portion 32 than the heat sink side metal film layer 35 in the second region R2. The metal film layer 3 overlaps with the heat sink side spacer 45 across the back side solder portion 52.

[0111] Next, use Figures 18-21 The manufacturing method of the semiconductor device 100 according to Embodiment 3 will be described.

[0112] like Figure 19 As shown, in the forming process S102 (refer to...) Figure 2 In this embodiment, a back-side alloy portion 44, which is an alloy of the heat sink side metal film layer 35 and the heat sink HS, is formed by heating the heat sink HS and the heat sink side metal film layer 35. Specifically, the back-side alloy portion 44 is formed on the base portion HS1 of the heat sink HS by heating the base portion HS1 of the heat sink HS and the heat sink side metal film layer 35. In this embodiment, the heat sink side metal film layer 35 and the heat sink HS are heated using a laser L (YAG laser).

[0113] Furthermore, in the forming process S102 (reference) Figure 2 In the process, a heat sink side spacer 45 is formed as an alloy of the heat sink side metal film layer 35 and the heat sink HS by heating the heat sink side metal film layer 35 and the heat sink HS in the second region R2 of the heat sink side metal film layer 35.

[0114] like Figure 19 and Figure 20 As shown, in this embodiment, laser L is irradiated at the four corners of the second region R2 of the heat sink-side metal thin film layer 35. Therefore, the heat sink-side spacer 45 includes four heat sink-side spacers 451. The four heat sink-side spacers 451 are respectively disposed at the four corners of the second region R2.

[0115] Next, as Figure 21As shown, in the joining process S103 (refer to...) Figure 2 In this configuration, the metal thin film layer 3 is configured to overlap the heat sink side spacer 45 with respect to the back-side solder portion 52. Specifically, the second metal thin film portion 32 of the metal thin film layer 3 is configured to overlap the heat sink side spacer 45 with respect to the back-side solder portion 52. For example... Figure 18 As shown, the base plate 6 of the radiator HS is joined to the housing 7 by adhesive 92.

[0116] Next, the effects of this embodiment will be explained.

[0117] According to the semiconductor device 100 of Embodiment 3, such as Figure 18 As shown, the back-side alloy portion 44 is positioned further outward than the second region R2. The back-side alloy portion 44 has a lower wettability to the back-side solder portion 52 than the heat sink-side metal film layer 35. Therefore, it is possible to prevent the back-side solder portion 52 from wetting and extending beyond the back-side alloy portion 44 beyond the second region R2. This, in turn, prevents the thickness of the back-side solder portion 52 in the second region R2 from becoming too thin. Therefore, it is possible to suppress the decrease in reliability of the semiconductor device 100 due to temperature cycling, etc. Furthermore, it is possible to suppress the decrease in the bonding strength between the housing 7 and the heat sink HS caused by the back-side solder portion 52 wetting and extending to the end of the base portion HS1.

[0118] like Figure 18 As shown, the heat sink-side spacer 45 protrudes further toward the metal thin film layer 3 than the heat sink-side metal thin film layer 35 in the second region R2. The metal thin film layer 3 overlaps with the heat sink-side spacer 45 across the back-side solder portion 52. Therefore, a distance greater than the protrusion of the heat sink-side spacer 45 can be ensured as the spacing between the metal thin film layer 3 and the heat sink-side metal thin film layer 35. As a result, the thickness of the solder portion 51 between the metal thin film layer 3 and the heat sink-side metal thin film layer 35 can be suppressed. Therefore, the reliability reduction of the semiconductor device 100 due to temperature cycling, etc., can be suppressed. Furthermore, the tilting of the semiconductor element 1 can be suppressed. As a result, the failure of the first lead portion 83 and the second lead portion 84 to properly bond with the semiconductor element 1 can be suppressed.

[0119] Implementation method 4.

[0120] This embodiment applies the semiconductor devices described in Embodiments 1 to 3 to a power conversion device. This disclosure is not limited to a specific power conversion device; hereinafter, Embodiment 4 will describe the application of this disclosure to a three-phase inverter.

[0121] Figure 22 This is a block diagram showing the structure of a power conversion system using the power conversion device of this embodiment.

[0122] Figure 22The power conversion system shown consists of a power supply PW, a power conversion device 200, and a load LO. The power supply PW is a DC power source that supplies DC power to the power conversion device 200. The power supply PW can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the power supply PW can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0123] The power conversion device 200 is a three-phase inverter connected between the power supply PW and the load LO, which converts the DC power supplied from the power supply PW into AC power and supplies AC power to the load LO. Figure 22 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; and a control circuit 202 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0124] The load LO is a three-phase motor driven by AC power supplied from the power conversion device 200. Furthermore, the load LO is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors used in hybrid or electric vehicles, railway vehicles, elevators, or air conditioning systems.

[0125] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). The switching elements switch to convert DC power supplied from the power source PW into AC power, which is then supplied to the load LO. The main conversion circuit 201 has various specific circuit structures, but in this embodiment, it is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in reverse parallel with each switching element. At least one of the switching elements and freewheeling diodes in the main conversion circuit 201 is a switching element or freewheeling diode equivalent to any of the semiconductor devices in embodiments 1 to 3 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load LO.

[0126] Furthermore, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. This drive circuit can be integrated into the semiconductor device 100 or it can be separate from the semiconductor device 100. The drive circuit generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements. Specifically, according to the control signal from the control circuit 202 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is maintained in the on state, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is maintained in the off state, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0127] Control circuit 202 controls the switching elements of main conversion circuit 201 to supply the desired power to load LO. Specifically, it calculates the time (on-time) during which each switching element of main conversion circuit 201 should be in the on state based on the power to be supplied to load LO. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Then, control commands (control signals) are output to the drive circuit of main conversion circuit 201, such that an on signal is output to the switching element that should be in the on state at each time, and an off signal is output to the switching element that should be in the off state. The drive circuit outputs an on signal or off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0128] In the power conversion device of this embodiment, the semiconductor device of embodiments 1 to 3 is used as the semiconductor device 100 constituting the main conversion circuit 201. Therefore, a power conversion device that does not generate waste liquid caused by the wet processing of the etching process can be realized.

[0129] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. Furthermore, when supplying power to DC loads, the present disclosure can also be applied to DC / DC converters or AC / DC converters.

[0130] Furthermore, the power conversion device using this disclosure is not limited to the case where the load is an electric motor, as described above. For example, it can also be used as a power supply device for electrical discharge machining or laser processing machines, or induction heating cookers or contactless power supply systems, and can also be used as a power regulator for solar power generation systems or energy storage systems.

[0131] Implementation method 5.

[0132] Next, use Figures 23-25 The structure of the semiconductor device 100 in Embodiment 5 will be described. Unless otherwise specified, Embodiment 5 has the same structure, manufacturing method, and effects as Embodiment 1 described above. Therefore, the same reference numerals are used for structures identical to those in Embodiment 1, and the description will not be repeated.

[0133] like Figure 23 As shown, the semiconductor device 1 of this embodiment has wire bonding pads 10. The semiconductor device 1 has signal electrode pads 11 and main electrode pads 12 as wire bonding pads 10.

[0134] like Figure 24 As shown, laser L (refer to) is applied to the outer periphery of the wire bonding pad 10 of semiconductor element 1. Figure 25 This forms the alloy portion 41. The alloy portion 41 surrounds the entire circumference of the wire bonding pad 10 of the semiconductor element 1. Figure 25 As shown, the alloy portion 41 is thicker than the wire bonding pad 10. In this embodiment, the wire bonding pad 10 (signal electrode pad 11 and main electrode pad 12) includes a metal component 2 and a metal thin film layer 3. Furthermore, the method of the semiconductor device 100 of this embodiment can also be implemented in conjunction with the methods of embodiments 1 to 4.

[0135] Next, the effects of this embodiment will be explained.

[0136] When using the solder section 51 to bond the semiconductor device 1, molten solder sometimes scatters as solder balls S toward the wire bonding pads 10 of the semiconductor device 1. This scattering is particularly common when using a vacuum reflow oven or similar equipment. Consequently, contamination of the wire bonding pads 10 can sometimes affect the wire bonding process.

[0137] In contrast, according to the semiconductor device 100 of Embodiment 5, an alloy portion 41 is formed by irradiating the outer periphery of the wire bonding pad 10 of the semiconductor element 1 with laser L. Therefore, the alloy portion 41 can be formed on the outer periphery of the wire bonding pad 10. Consequently, when the solder portion 51 bonding the semiconductor element 1 is heated and melted, and the solder balls S scatter, the alloy portion 41 can be used to suppress the solder balls S from adhering to a region closer to the inner side of the alloy portion 41. Furthermore, when the alloy portion 41 is thicker than the signal electrode pad 11 or the main electrode pad 12, it can be prevented that the solder balls S cross the alloy portion 41 and adhere to a region closer to the inner side of the alloy portion 41.

[0138] The embodiments disclosed herein should be considered exemplary in all respects and not limiting. The scope of this disclosure is defined not by the foregoing description but by the claims, and is intended to include all modifications in the same sense and scope as the claims.

[0139] Label Explanation

[0140] 1: Semiconductor component; 10: Wire bonding pad; 11: Signal electrode pad; 12: Main electrode pad; 2: Metal component; 3: Metal thin film layer; 41: Alloy section; 42: Spacer; 43: Back side alloy section; 44: Heat sink side metal thin film layer; 51: Solder section; 52: Back side solder section; 100: Semiconductor device; 200: Power conversion device; 201: Main conversion circuit; 202: Control circuit; 411: Annular section; 412: Protrusion; HS: Heat sink; LO: Load; PW: Power supply; R1: Region 1; R2: Region 2.

Claims

1. A semiconductor device, wherein, The semiconductor device includes: Semiconductor components; Metal parts; A thin metal film layer covers the metal component and includes a first region; A solder section that bonds the semiconductor element to the first region of the metal thin film layer; as well as The alloy portion, which is disposed on the outer side of the first region, is an alloy of the metal component and the metal thin film layer. The metal thin film layer has higher wettability to the solder portion than the metal component. The alloy portion has lower wettability to the solder portion than the metal thin film layer.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a spacer, which is an alloy of the metal component and the metal thin film layer. The spacer protrudes towards the semiconductor element in the first region more than the metal thin film layer. The semiconductor element overlaps with the spacer through the solder portion.

3. The semiconductor device according to claim 1 or 2, wherein, The alloy portion includes an annular portion. The annular portion surrounds the solder portion.

4. The semiconductor device according to claim 3, wherein, The alloy portion also includes multiple protrusions. The plurality of protrusions extend from the annular portion toward the solder portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor device also includes: heat sink; A heat sink-side metal film layer covers the heat sink and includes a second region; The back-side solder section bonds the heat sink to the second region of the heat sink-side metal film layer; as well as The rear-side alloy portion, which is positioned further outward than the second region, is an alloy of the heat sink and the heat sink-side metal thin film layer. The metal film layer on the heat sink side has higher wettability to the solder portion on the back side than the heat sink itself. The back-side alloy portion has lower wettability to the back-side solder portion than the heat sink-side metal film layer.

6. A power conversion device, wherein, The power conversion device includes: A main conversion circuit having a semiconductor device as described in any one of claims 1 to 5, and converting and outputting the input power; and The control circuit outputs control signals to the main conversion circuit to control the main conversion circuit.

7. A method for manufacturing a semiconductor device, wherein, The method for manufacturing the semiconductor device includes: The preparation process includes preparing a semiconductor element, a metal component, and a metal thin film layer, wherein the metal thin film layer covers the metal component and includes a first region; The forming process involves heating the metal component and the metal thin film layer to form an alloy portion, which is an alloy of the metal component and the metal thin film layer, on the outer side of the first region; and In the bonding process, the semiconductor element is bonded to the metal thin film layer using a solder portion disposed in the first region. The metal thin film layer has higher wettability to the solder portion than the metal component. The alloy portion has lower wettability to the solder portion than the metal thin film layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein, In the forming process, the metal component and the metal thin film layer are heated by irradiating the metal thin film layer with a laser, thereby forming the alloy part.

9. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein, In the forming process, the metal component and the metal thin film layer are heated in the first region of the metal thin film layer, thereby forming a spacer that serves as an alloy between the metal thin film layer and the metal component. In the bonding process, the semiconductor element is configured to overlap the spacer with respect to the solder portion.

10. A method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein, The alloy portion is formed by irradiating the metal thin film layer with a laser to generate a liquid phase between the metal component and the metal thin film layer.

11. The semiconductor device according to claim 1, wherein, The alloy portion is formed by irradiating the outer periphery of the wire bonding pads of the semiconductor element with a laser.

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