Biphasic marker code edge recovery

Abstract

An integrated circuit is described. Such an integrated circuit can include an input connector coupled to a signal line that conveys an input signal corresponding to encoded data, where the encoded data is encoded using BMC, and the input signal can have different rise times and fall times. Moreover, the integrated circuit can include a recovery circuit coupled to the input connector that outputs data based at least in part on a first threshold and a second threshold, where the output data can include data values having equal half bit periods and variable frequencies. Note that the recovery circuit can implement a state machine corresponding to the data.

Description

Technical Field

[0001] This disclosure relates to techniques for decoding signals carrying clock and data information. Note that this disclosure relates to techniques for decoding signals using Biphasic Marker Codes (BMCs), which are part of the Universal Serial Bus (USB) power delivery standard. Background Technology

[0002] The USB Power Delivery standard is part of the USB standard. This power delivery standard defines the power supply interface via a USB cable. Note that the USB Power Delivery standard allows the power source and receiver to negotiate power information and activity using a communication protocol based on BMC technology.

[0003] BMC (Binary Memory Coding) technology is a widely used information transmission technology, for example, for audio signal transmission. BMC is a type of encoding of binary data streams where data and clock signals are combined to form a single two-level self-synchronizing data stream. It was developed to address known difficulties in traditional digital signal processing. Note that BMC achieves clock and data recovery by ensuring at least one transition on the channel for each unit interval. Furthermore, BMC-encoded signals have zero average DC offset voltage because the high and low levels of the signal last for equal periods.

[0004] USB is currently the standard charging format for many handheld electronic devices. USB connectors come in three standard sizes: the standard size for desktop or portable equipment; a mini size for mobile devices; and an ultra-small size for smart devices and tablets. In addition to charging electronic devices, USB offers five data transfer speeds: Low Speed, Full Speed, High Speed, Ultra-High Speed, and Ultra-High Speed+. Unlike data buses such as Ethernet, USB features direct connection, meaning the host electronic device has a downstream-facing port that connects to the upstream port of the electronic device.

[0005] Furthermore, note that USB is a single-ended communication system that can provide up to 100 watts of power. Therefore, due to the voltage drop of the USB cable, the definition of ground on one side or the other is highly variable.

[0006] Furthermore, there is no guarantee that the current in a USB cable will not change suddenly. For example, even during communication, the current can change abruptly. This requires long data transition rise and fall times to eliminate the chance of radiation. Therefore, the duty cycle of some or all bits will change. While the USB specification provides a margin to support significant duty cycle changes, it is very low.

[0007] Furthermore, to meet the need for exchanging information when negotiating power contracts between electronic devices, the existing USB standard added a second data communication pair within the USB cable. Unfortunately, adding a signal line to the USB cable resulted in a problematic communication standard that often struggles to acquire data from one end to the other at an acceptable data rate. For example, line quality is typically poor due to reflections, impedance mismatches, and random effects. Moreover, poorly controlled transmitters and cables can severely impact the quality of incoming signals. Additionally, the specification's writing style allows communicators to operate on inconsistent time bases, leading to time base uncertainty.

[0008] The widespread use of USB for charging and communication has led to a large influx of vendors into the market. However, some of these vendors offer poorly designed electronic devices, which can exacerbate signal quality issues. Furthermore, many of these devices include poorly controlled connectors for USB cables from third parties, further impacting the quality of the incoming signal.

[0009] To complicate matters further, BMC data with different rising and falling edge rates can lead to asymmetric edge detection results, making it more difficult to determine the difference between the unit interval representing 1 and the unit interval representing 0 using a threshold from the middle to the end of a single cell. Summary of the Invention

[0010] An embodiment of an integrated circuit is described. This integrated circuit includes an input connector coupled to a signal line that transmits an input signal corresponding to encoded data, wherein the encoded data is BMC encoded, and the input signal may have different rise and fall times. Furthermore, the integrated circuit includes a recovery circuit coupled to the input connector, which outputs data based at least in part on a first threshold and a second threshold, wherein the output data may include data values ​​having equal half-bit periods and a variable frequency.

[0011] Furthermore, the integrated circuit may include: an edge circuit coupled to an input connector, the edge circuit detecting an edge and edge timing position in the input signal corresponding to a predefined preamble sequence in the encoded data; a time interval circuit coupled to the edge circuit, the time interval circuit identifying a unit time interval in a set of predefined unit time intervals in the encoded data based at least in part on the detected edge and edge timing position; and a threshold circuit coupled to the edge circuit, the threshold circuit selecting a first threshold and a second threshold based at least in part on the identified unit time interval.

[0012] Note that the identified unit time intervals may include a reference unit time interval, which has the longest unit time interval relative to the remaining identified unit time intervals, and does not include edges during the reference unit time interval. Furthermore, the identified unit time intervals may include a first subset of unit time intervals corresponding to data values ​​encoded in the first type and a second subset of unit time intervals corresponding to data values ​​encoded in the second type. In some embodiments, the data values ​​encoded in the first type include zeros and the data values ​​encoded in the second type include one.

[0013] Furthermore, the recovery circuit may include a first-in-first-out (FIFO) buffer.

[0014] In addition, the recovery circuit can implement a state machine corresponding to the data.

[0015] In addition, the first threshold may include a rising edge threshold and the second threshold may include a falling edge threshold.

[0016] In some embodiments, the integrated circuit may include clock data recovery (CDR) coupled to a recovery circuit, which recovers the clock at least in part based on data.

[0017] Another embodiment provides an electronic device including an integrated circuit.

[0018] Another embodiment provides a system including an integrated circuit.

[0019] Another embodiment provides a method for outputting data. This method includes at least some of the operations performed by an integrated circuit.

[0020] The present invention is provided to illustrate some exemplary embodiments in order to provide a basic understanding of some aspects of the subject matter described herein. Therefore, it will be appreciated that the above features are exemplary and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become clear from the following detailed description, the accompanying drawings, and the claims. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating a receiving circuit according to some embodiments of the present disclosure.

[0022] Figure 2 This is a diagram illustrating an example of biphase marker code (BMC) signal regeneration according to some embodiments of the present disclosure.

[0023] Figure 3 This is a diagram illustrating an example of a simulated BMC signal trace according to some embodiments of the present disclosure.

[0024] Figure 4 This is a diagram illustrating an example of a BMC preamble sequence according to some embodiments of the present disclosure.

[0025] Figure 5 This is a diagram illustrating an example of a BMC edge recovery circuit according to some embodiments of the present disclosure.

[0026] Figure 6 This is a diagram illustrating an example of a BMC edge recovery state machine according to some embodiments of the present disclosure.

[0027] Figure 7 This is a diagram illustrating an example of a threshold according to some embodiments of the present disclosure.

[0028] Figure 8 This is a diagram illustrating an example of BMC generation according to some embodiments of the present disclosure.

[0029] Figure 9 This is a flowchart illustrating an example of a method for outputting data according to some embodiments of the present disclosure.

[0030] Note that in all the figures, similar reference numerals refer to corresponding parts. Furthermore, multiple instances of the same part are specified by a common prefix separated from the instance number by a dash. Detailed Implementation

[0031] An integrated circuit is described. This integrated circuit may include an input connector coupled to a signal line, the input connector transmitting an input signal corresponding to encoded data, wherein the encoded data is encoded using BMC, and the input signal may have different rise and fall times. Furthermore, the integrated circuit includes a recovery circuit coupled to the input connector, the recovery circuit outputting data based at least in part on a first threshold and a second threshold, wherein the output data may include data values ​​having equal half-bit periods and variable frequencies. Note that the recovery circuit may implement a state machine corresponding to the data.

[0032] These circuitry techniques can solve USB power delivery problems by receiving and decoding data. Note that the circuitry techniques can use BMC technology to negotiate power supply information and activity between the source and receiver. Furthermore, the circuitry techniques can enable data communication at high data rates or speeds, with poor line quality, poor signal quality, and / or timing uncertainties. In addition, the circuitry techniques can enable data communication even in situations where there are variations in ground on a given side of the USB cable, variations in duty cycle, and / or different rise and fall edge rates. Therefore, the circuitry techniques can improve the performance of communication via USB cable and USB power delivery. One or more of these capabilities allow embodiments of integrated circuits or receiving circuits (such as BMC processing circuits or USB power delivery controllers) to be used in a wide variety of systems, electronic devices, and applications.

[0033] Note that from a communication theory perspective, there are two types of receivers. One approach uses edge detection (e.g., incoherent edge detection receiver technology). However, most standards do not use edge detection. Instead, they use a variety of other techniques. The existing USB standard does not use edges to detect data.

[0034] We now describe embodiments of the circuit technology and receiving circuitry. In the disclosed circuit technology, the receiving circuitry can receive and decode input signals including data encoded using BMC codes. This is in... Figure 1 As shown in the figure, Figure 1 A block diagram illustrating a receiver circuit 100 according to some embodiments of the present disclosure is presented. This receiver circuit may include an input connector 110 that may be coupled to a signal line transmitting an input signal corresponding to encoded data, wherein the encoded data is encoded using a BMC. For example, the signal line may be included in a USB cable, and the data may be associated with the USB Power Delivery standard. Furthermore, the receiver circuit 100 may include an edge circuit 112 coupled to the input connector 110 that detects an edge and edge timing position in the input signal corresponding to a predefined preamble sequence in the encoded data. Additionally, the receiver circuit 100 may include: a time interval circuit 114 coupled to the edge circuit 112 that identifies a unit time interval from a set of predefined unit time intervals in the encoded data, at least partially based on the detected edge and edge timing position; and a threshold circuit 116 coupled to the edge circuit 112 that selects a first threshold and a second threshold, at least partially based on the identified unit time interval. In addition, the receiving circuit 100 may include a recovery circuit 118 coupled to the edge circuit 112, the time interval circuit 114 and the threshold circuit 116, which outputs data based at least in part on the first threshold and the second threshold.

[0035] Note that due to the known repeatability of the preamble sequence and the predictive nature of BMC patterns or sequences outside the preamble, a unit interval of 1 or 0 can be determined based on a threshold comparing similar edges (both rising or both falling). This is achieved by capturing the elapsed time value for each segment of the BMC sequence during the preamble (e.g., "10101010") and identifying the maximum captured value as a "large 0". The position and polarity of the large 0s in the captured values ​​allow them to be identified based on the position of all other elements in the sequence relative to the large 0. In circuit techniques, these appropriate segments of the preamble can be used to limit rising and falling edge thresholds. Note: At the end of the current unit interval, only two possible unit interval types can follow; regardless of whether the next unit interval is 1 or 0, the next edge will always be in the same direction. Combining these facts, the threshold can allow the determination of the next unit interval bit value, at least in part, based on whether the next edge arrives before or after the threshold, which is evenly distributed between the middle edge and the end edge of the cell. This eliminates the significant difference between rise and fall times and enables more robust acquisition of the receiving mode.

[0036] These communication techniques can provide the identification and capture of incoming BMC unit interval sequences as states driving a state machine. These captured states can be fed into a First-In-First-Out (FIFO) system, which provides circuitry to output these captured states as a recovered BMC, which has equal half-bit periods and a variable frequency based at least in part on the number of entries currently in the FIFO. Therefore, it is now possible to reproduce an input BMC with varying edges detected at a constant frequency using an output with a more easily detectable constant edge. This allows data to be recovered from the encoded BMC via a state machine whose frequency varies with the pattern generated at the FIFO's output.

[0037] We now describe the significant difference between BMC signal regeneration and finite difference injection. To better understand the problem, the BMC signal from the configuration channel (CC) line can be regenerated as follows. The analog front end of the receiver circuit 100 can have, for example, a ladder of 10 comparators used to detect the amplitude of the received BMC signal. The output of this comparator can be fed into finite difference (FD) logic, which compares the delayed sample of the comparator with the current sample of the comparator. If a sufficiently large difference is seen between the samples, the FD logic can declare an edge and can recreate the BMC signal using edge filtering of some level. However, different edge rates on the received BMC can affect this edge detection, especially if the rise time and fall time are significantly disproportionate. This is because the distance between sampled edges can sometimes cause a slow edge to be followed by a fast edge (and vice versa), which can make the detected edges appear closer or farther apart. Moreover, this effect makes it difficult to determine whether the next unit interval in a BMC pattern or sequence is "1" or "0", because different edges can make recovery more difficult when using a single threshold to distinguish between "1" and "0".

[0038] The significant difference in FD injection lies in Figure 2 The figure illustrates an example of BMC signal regeneration according to some embodiments of the present disclosure. Note that the signal on CC line 210 can be converted into a comparator value, as indicated by the number in the box, which indicates the value of the comparator output when the input signal is monitored. Furthermore, the FD logic can set the sliding sample comparison 212 distance to, for example, seven to provide optimal noise filtering for signal edges. In this example, the threshold is five, meaning that a finite difference of five must exist between two sample points to declare an edge. Figure 2 As shown, if the rising edge (in this example) is slow and the falling edge is fast, edge detection may make the rising edge detection time longer than the falling edge detection time. This will have the effect of pushing the edge closer or pulling it further apart depending on the edge rate. It can be seen that as sliding sample comparisons occur, the threshold is reached more slowly on the rising edge and more quickly on the falling edge. This causes a difference in the boundary of edge detection relative to the ideal unit interval (which is the time to transmit one BMC bit through CC line 210), in which edge detection would be more evenly spaced. The different positions of the edges in the middle of the rising and falling cells make the detection of 1s and 0s more difficult because the margin is reduced when the same detection threshold is used for both edges.

[0039] Note that ideal timing 214 illustrates the detection timing of an undistorted ideal signal. Furthermore, FD detection 216 demonstrates the change in edge timing. Note that the rising edge will be further away than the ideal value (or delayed relative to the ideal value), while the falling edge will be closer to the ideal value (or faster relative to the ideal value).

[0040] Figure 3 A diagram illustrating examples of simulated BMC signal traces according to some embodiments of the present disclosure is presented. Figure 3 In this context, the pulse or edge 310 entering the "fixed BMC" logic may be different, and the output BMC 312 may have a variable frequency with a well-centered cell transition. Furthermore, in Figure 3 Ideally, the edges 310 should be equidistant, but this is not the case.

[0041] We now describe embodiments of a circuit technique for capturing BMCs from an FD logic or detector using dual thresholds at the frequency of the received BMC, wherein the dual thresholds enable more robust capture of the BMC sequence. Furthermore, embodiments of the circuit technique can use a FIFO to capture the received BMC state and output a new BMC pattern or sequence with varying frequency to prevent FIFO overflow and underflow by removing the state faster or slower depending on the FIFO level. Additionally, the output state can be used to recreate a recovered BMC pattern or sequence with variable frequency unit intervals, but with well-centered cell transitions that can be more easily recovered using a single threshold.

[0042] Note that the disclosed receiving circuitry may include a variety of functions, including: FD logic; "fixed BMC" logic that employs BMCs with different edges and outputs a variable-frequency BMC with a centered cell mid-transition; and receiving the variable-frequency BMC by tracking the frequency of the input stream and averaging a single threshold between cell mid-transitions (now equal for both rising and falling information), thereby facilitating single-threshold recovery. In some embodiments, the fixed BMC logic and the reception of the variable-frequency BMC can be combined, and the receiving circuitry may not need to convert the data back to the BMC.

[0043] Figure 4 A diagram illustrating an example of a BMC preamble sequence 400 according to some embodiments of the present disclosure is presented. Note that the bmc_rx_data 412 of the BMC mode can be included in the BMC preamble sequence 400 or a segment of a stream having alternating 1s and 0s. Furthermore, the BMC preamble sequence 400 can include one of six possible time values ​​410. This results in an edge pattern that repeats after six edge transitions. Note that these six values ​​can be captured to define the width of the six time intervals 410 present during the BMC preamble mode 400, which can precede the header and data fields in the currently received message.

[0044] As mentioned earlier, since these six values ​​are captured, the maximum value captured can be limited to a large 0. The position of the large 0 and its polarity can limit the position of the captured values. Table 1 presents examples of values ​​in the BMC preamble sequence.

[0045]

[0046] Table 1.

[0047] Data in a BMC pattern or sequence can be recovered using a BMC recovery state machine. In this BMC recovery state machine, each state can have an unconditional transition, or transition to one of two states depending on the position of the next edge relative to a low or high threshold. Figure 5 The illustration shows a receiver circuit 100 according to some embodiments of the present disclosure. Figure 1 A diagram of an example of the BMC edge recovery circuit 500 in ).

[0048] exist Figure 5 The following event sequence exists. The state can be aligned with the current segment of the received edge generated from the input BMC serial stream of BMC data 510. When a BMC edge from the FD logic begins to appear on the interface, pulse generator 512 can generate a single-cycle pulse (system clock) at each edge, defined as the bmc_edge_detected signal 516. bmc_polarity 514 can also be captured each time an edge is captured.

[0049] When the pulse generator bmc_edge_detected signal 516 begins generating pulses indicating the occurrence of a BMC edge, one or more edge timers (such as edge timer 518) can count the number of system clock cycles occurring between edges. At each bmc_edge_detected 516, the edge_timer 520 value can be captured, and the edge timer 518 can be reset simultaneously to begin counting the next edge. Furthermore, edge_count 522 can define the location, count edges (e.g., one of six edges in a sequence enters a register), and edge_capture_enable 524 can implement capture based on the edge count. Additionally, the edge counter 518 can increment at each edge and can toggle when the count reaches five or when it reaches five to construct the BMC preamble sequence and create a time window, where six edge_count_values ​​(ecv 0 to 5) 528 are captured in the edge count register (ECR) 526. Edge count register 526 can capture the edge_timer 520 value of a sequence of six edges used to define various sequence states in the BMC preamble. As edge count register 526 is captured, the value of each captured value can be compared with previous values ​​to determine whether the currently captured value is greater than the values ​​of all previously captured values.

[0050] Edge_count_values ​​528 can be fed into the big-zero logic 530, where they can be identified by their position relative to the big-zero value 532. The edge threshold generator 534 can use these values ​​to generate a threshold 536 to distinguish between 1s and 0s in the BMC stream. Furthermore, start_state 538 can tell the BMC recovery state machine 540 where to start. Note that start_state 538 can determine where the preamble sequence is when the BMC recovery state machine 540 starts.

[0051] This allows the Big-Zone logic 530 to determine the largest edge-to-edge time value and assign it as the Big-Zone value 532. This is deterministic because the largest edge time value is guaranteed to be zero, since there is no cell transition during BMC 1. Furthermore, the Big-Zone logic 530 can determine the location of the Big-Zone in the edge count register 526, its value, and its polarity. This allows the Big-Zone logic 530 to correctly correlate the edge count with the levels in the preamble sequence. The full-bit time calculation logic can use the Big-Zone value 532 to start the BMC output timer with a count close to the received BMC frequency. This value can also be fed to the BMC decoding logic (not shown), so it also starts at the same BMC frequency. Note that the values ​​lo_zero 542 and lo_hi_lo 544 can be used to calculate lo_threshold 536-1, while the values ​​hi_zero 546 and hi_lo_hi 548 can be used to calculate hi_threshold 536-2. These thresholds can be used to identify the state that will be pushed to the edge of the fifo550.

[0052] Once the large zero value 532 and its polarity 552 and position 554 in the edge count register 526 are determined, the other values ​​of the preamble sequence can be determined at least in part based on their positions in the edge count register 526 relative to the position 554 of the large zero value 532.

[0053] Furthermore, the BMC recovery state machine 540 can identify, at least in part, the next state that should be pushed into the edge FIFO 550 based on whether the next edge it sees is a transition in the middle of a cell or at the end of a cell. FIFO_in_pulse 556 can capture the current state bmc_rec_curr_st 558 of the BMC recovery state machine 540 into the edge FIFO 550. Each transition of the BMC recovery state machine 540 can be pushed into the edge FIFO 550, which will later be read by the BMC generation state machine. These states can constrain the order of received BMCs, which will be used to generate a re-timing BMC stream from the FIFO output fifo_data_out 560. Additionally, fifo_out_pulse 562 can output data from the BMC recovery state machine 540, which is then output from the BMC output engine 566 when the next state is needed. The FIFO level 564 threshold can be used to ensure that there is no underflow. Furthermore, the BMC output engine 566 can retrieve the output of the edge-triggered FIFO 550 and can recreate the BMC sequence with clean timing intervals. bmc_rx_data_out 568 can be the data created by the BMC output engine 566.

[0054] Note that the edge timer 518 can increment as the edge counter scrolls through the frame, counting one preamble sequence at a time.

[0055] The BMC generating state machine can take a bit stream captured by the BMC edge recovery circuit 500 and can output a re-timing BMC stream (or pattern or sequence) with equal half-bit timing for each "1" unit interval. This simplifies the process via clock data recovery (CDR) circuitry (such as...). Figure 1 The CDR circuit 120 in the BMC decodes the BMC stream. The frequency generated by the BMC can vary relative to the number of FIFO entries present at any given time. The BMC decoding logic can also track this frequency in order to reliably decode the 4b5b data from the BMC.

[0056] For example, if a large 0 value is at position 3 in edge_count_value 528-4 and its polarity is high, then Table 2 presents examples of the positions of all other segments in the BMC preamble sequence.

[0057]

[0058] Table 2.

[0059] Furthermore, Table 3 presents examples of possible transitions.

[0060] LZ 410-6 HLH 410-1 HZ 410-3 HLH 410-1 HLL 410-2 HLL 410-2 HLH 410-1 HZ 410-3 HZ 410-3 LHL 410-4 LZ 410-6 LHL 410-4 LHH 410-5 LHH 410-5 LHL 410-4 LZ 410-6

[0061] Table 3.

[0062] As shown in Table 3, two states (HLH 410-1 and LHL 410-4) unconditionally transition to a single state, thus guaranteeing that this transition always occurs. Furthermore, the other states have only two possible transitions, both resulting in the same edge polarity. This means that a threshold can be generated to determine the difference between subsequent "1"s and "0"s by using the time value between similar edges (two rising edges or two falling edges) associated with the BMC preamble segment. By understanding the current state of the BMC mode and applying an appropriate rising or falling edge threshold to determine the next state, these thresholds can be used during the data field following the preamble.

[0063] Figure 6 The illustration shows a receiver circuit 100 according to some embodiments of the present disclosure. Figure 1A diagram illustrating an example of a BMC edge-recovery state machine 600. Starting from the idle state 610, there are six possible new states: s_hz 612, s_lhl 614, s_lhh 616, s_lz 618, s_hlh 620, and s_hll 622. Each state can transition to the next state, as shown in Table 2.

[0064] Note that idle state 610 can be entered upon reset. When an edge begins to be received, the edge timer and edge counter can begin counting, and when the edge count reaches five, based at least in part on the sequence determined by the big-zero logic, the next edge can transition to one of start states 612-622, which is the state expected by the BMC edge recovery state machine 600 for the FIFO output. The transition to the next state is defined by one of start states 612-622, such as... Figure 6 As shown in the image.

[0065] Furthermore, when the start state equals s_hz 612, it can enter the hz state 624 from the idle state 610. When the edge timer is greater than hi_threshold 630 or 632, it can also enter this state from the lz state 626 or the hll state 628.

[0066] Furthermore, when the start state equals s_lhl 614, it can enter the lhl state 634 from idle 610. It can also enter this state from hz state 624 or lhh state 636 if the edge timer is below the lo_threshold value when the next edge is detected 638 or 640.

[0067] Furthermore, when the starting state is equal to lhh 616, it can enter the lhh state 636 from the idle state 610. It can also enter this state unconditionally from the lhl state 634 when the next edge is detected 642.

[0068] Note that when the start state equals s_lz 618, it can enter the lz state 626 from the idle state 610. When the edge timer is greater than lo_threshold 644 or 646, it can also enter this state from the hz state 624 or the lhh state 636.

[0069] Furthermore, when the start state equals s_hlh 620, it can enter the hlh state 648 from the idle state 610. When the edge timer is lower than the lo_threshold value when the next edge is detected at 650 or 652, it can also enter this state from the lz state 626 or the hll state 628.

[0070] Furthermore, when the starting state equals s_hll 622, it transitions from idle 610 to hll state 628. It can also unconditionally transition from hlh state 648 when the next edge is detected 654.

[0071] We now describe threshold determination. When BMC sequence capture is enabled, the edge count register can be loaded with values ​​from the edge timer, which is reset at each edge. Furthermore, when the first value is captured into the `edge_count_value` 0 register and also becomes a big zero, its polarity and position in the `edge_count_value` register can also be captured. Additionally, when the next edge arrives, the edge timer count can be loaded into the `edge_count_value` 1 register. If the new value is greater than the current big zero, then this value can become a big zero, and its polarity and position can replace the previous value. This happens for each subsequent `edge_count_value` register until all six values ​​have been loaded.

[0072] At this point, the capture ends, and the large zero value, position, and polarity are available. Since the edge_count_value register containing the large zero value and its polarity are known, other values ​​in the edge count register can now also be identified, as the preamble pattern is known and repeatable. Therefore, a threshold can be set to distinguish whether the current unit interval being received is "1" or "0". The threshold setting can be based at least in part on the midpoint between the middle edge and the end edge of the cell. In some embodiments, different thresholds can be used for rising and falling edges, which can be determined by calculating the threshold between the middle edge of the next cell and the end edge of the next cell.

[0073] Due to the characteristics of BMC encoding, these edges can be either rising or falling, so the edge rates will be consistent. For example, if the current state is LZ, then there are only two possible transitions immediately following the rising edge at the end of the LZ state. The next state will either be HLH, which is a high-level time of the following "1" unit interval, or HZ, which is a high-level time of the following "0" unit interval. In this example, the threshold can be found by ((HZ-HLH) / 2)+HLH.

[0074] Figure 7 A diagram illustrating examples of thresholds according to some embodiments of this disclosure is presented. Note that the current state of the BMC recovery state machine can be hz 624, so the only possible transitions are lhl 634 and lz 626, both of which are entered via high-to-low transitions. Which state is detected is determined by the next rising edge occurring before or after the low threshold 710.

[0075] The next bit is determined to be either "1" (the LH part of LHL) or "0" by subtracting LHL edge_count_value from LZ edge_count_value, dividing it by 2, and adding that result to LHL edge_count_value. This evenly distributes the low threshold 710 across the next state low time intervals, so that if the next rising edge occurs before the low threshold 710, it can be determined as "1", and if the edge occurs after the low threshold 710, it can be determined as "0". This determination also limits the transition to the next state. Note that if the edge occurs before the transition, then the transition proceeds to LHL state 634. If it occurs after the low threshold 710, then the transition proceeds to LZ state 626.

[0076] Note that high thresholds can be generated in the same way, except for using HZ 410-3 and HLH 410-1 time values.

[0077] Furthermore, a start state may exist for the BMC recovery state machine to align with the first state transition of a segment of the preamble present when the BMC recovery state machine begins at the end of the edge capture sequence, since there may be random alignment of segments in the edge_count_value register. The large 0 positions in the preamble can identify all other values ​​(edges), thus determining where the BMC recovery state machine begins its start state.

[0078] We will now describe BMC generation. Figure 8 The illustration shows a receiver circuit 100 according to some embodiments of the present disclosure. Figure 1 A diagram illustrating an example of BMC generation in the example. Note that state transitions can be fed into an edge FIFO. The edge FIFO can store these transitions at the frequency of the received BMC edges, and the FIFO's output can be controlled by a variable frequency engine that tracks to the frequency required to ensure no information is lost due to overflow or underflow in the edge FIFO. As the output engine frequency changes, it can also output the initially captured BMC transitions, where the cell-center transition is now at the center of the unit interval. This can be implemented via a small state machine that detects the current state from the edge FIFO and outputs the edge at the beginning or middle of the unit interval.

[0079] exist Figure 8During reset, the state machine can enter the bmc_gen_idle state 810. After setting start_fifo_out, on full_bit_pulse or half_bit_pulse (bit_pulse), if the FIFO output is lhl, lhh, hll, or hlh 814, then the state machine can transition to the bmc_gen_edge state 812. Alternatively, if the FIFO output is lz or hz 816, then the state machine can transition to the bmc_gen_skip state 818.

[0080] Furthermore, when the FIFO starts and the bit pulse begins while the FIFO data is lhl, lhh, hlh, or hll (814), it can transition from the bmc_gen_idle state (810) to the bmc_gen_edge state (812). It can also unconditionally transition from the bmc_gen_skip state (818) on the next bit pulse (820), or return to itself if the FIFO output is lhl, lhh, hlh, or hll (822). When entering this state, an edge can be generated on bmc_rx_data_out.

[0081] Furthermore, when the FIFO starts and the bit pulse begins, and the FIFO data is lz or hz 816, it is possible to enter the bmc_gen_skip state 818 from the bmc_gen_idle state 810. When the FIFO data output is lz or hz 824, it is also possible to enter this state from the bmc_gen_edge state 812. This state allows skipping the transition between cells.

[0082] We will now describe an embodiment of the method. Figure 9 The diagram illustrates the use of recovery circuitry (such as receiver circuit 100). Figure 1 The flowchart illustrates an example of a method 900 for outputting data using a recovery circuit 118 in the circuit. During operation, the recovery circuit may receive an input signal corresponding to the encoded data on a signal line (operation 910), wherein the encoded data is encoded using a BMC, and wherein the input signals have different rise and fall times. Furthermore, the recovery circuit may output data based at least in part on a first threshold and a second threshold (operation 912), wherein the output data comprises data values ​​having equal half-bit periods and a variable frequency.

[0083] In some embodiments of method 900, there may be additional or fewer operations. Moreover, the order of operations may be changed, and / or two or more operations may be combined into one operation.

[0084] The disclosed receiving circuitry and circuitry technology can be any electronic device (or can be included therein). For example, electronic devices can include: cellular phones or smartphones, tablet computers, laptop computers, notebook computers, personal or desktop computers, netbook computers, media player devices, e-book devices, etc. Equipment, smartwatches, wearable computing devices, portable computing devices, consumer electronic devices, access points, routers, switches, communication equipment, testing equipment, vehicles, ships, airplanes, automobiles, trucks, buses, motorcycles, manufacturing equipment, agricultural implements, construction equipment, or another type of electronic equipment.

[0085] While specific components are used to describe embodiments of the receiving circuit and the integrated circuit including the receiving circuit, in alternative embodiments, different components and / or subsystems may exist in the receiving circuit and / or the integrated circuit including the receiving circuit. Therefore, embodiments of the receiving circuit and / or the integrated circuit including the receiving circuit may include fewer components, additional components, different components, combinations of two or more components into a single component, division of a single component into two or more components, changes in one or more locations of one or more components, and / or the presence of components of different types.

[0086] Furthermore, the circuitry and components in the embodiments of the receiving circuitry and / or the integrated circuitry including the receiving circuitry can be implemented using any combination of analog and / or digital circuitry systems, including bipolar, PMOS, and / or NMOS gates or transistors. Additionally, the signals in these embodiments can include digital signals with substantially discrete values ​​and / or analog signals with continuous values. Furthermore, the components and circuitry may be single-ended or differential, and the power supply may be unipolar or bipolar. Note that the electrical coupling or connection in the preceding embodiments can be direct or indirect. In the preceding embodiments, a single line corresponding to a route may indicate one or more single lines or routes.

[0087] As mentioned earlier, an integrated circuit can implement some or all of the functions of circuit technology. This integrated circuit may include hardware and / or software mechanisms for implementing the functions associated with the circuit technology.

[0088] In some embodiments, the output of the process for designing an integrated circuit or a portion thereof (including one or more of the circuits described herein) may be a computer-readable medium, such as, for example, magnetic tape, optical disc, or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing the circuit system, which may be physically instantiated as an integrated circuit or a portion thereof. Such encoding may be performed in various formats, but these data structures are typically written in formats such as Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Exchange Format (EDIF), OpenAccess (OA), or Open Prototype Systems Exchange Standard (OASIS). Those skilled in the art of integrated circuit design can develop such data structures from the schematic diagrams and corresponding descriptions of the types detailed above and encode the data structures on a computer-readable medium. Those skilled in the art of integrated circuit design may use such encoded data to fabricate integrated circuits including one or more of the circuits described herein.

[0089] Some of the operations in the preceding embodiments are implemented in hardware or software, but the operations in the preceding embodiments can typically be implemented with various configurations and architectures. Therefore, some or all of the operations in the above embodiments can be performed in hardware, software, or both. For example, at least some of the operations in circuit technology can be implemented using program instructions executed by firmware in a processor or integrated circuit.

[0090] Furthermore, while numerical examples have been provided in the foregoing discussion, different numerical values ​​are used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0091] In the foregoing description, we refer to “some embodiments”. Note that “some embodiments” describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0092] The foregoing description is intended to enable any person skilled in the art to make and use this disclosure, and is provided in the context of a particular application and its requirements. Moreover, the foregoing description of embodiments of this disclosure is presented for illustrative and descriptive purposes only. It is not intended to be exhaustive or to limit the present disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure, and the general principles defined herein may be applied to other embodiments and applications. Furthermore, the discussion of the foregoing embodiments is not intended to limit this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown, but should be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. An integrated circuit, comprising: An input connector is configured to couple to a signal line corresponding to an input signal that transmits and encodes data, wherein the encoded data is encoded using a biphase mark code (BMC) and wherein the input signal has a different rise time and fall time; An edge circuit, coupled to the input connector, is configured to detect the edge and edge timing position in the input signal that corresponds to a predefined preamble sequence in the encoded data; A time interval circuit, coupled to an edge circuit, is configured to identify a unit time interval in a set of predefined unit time intervals in the encoded data, based at least in part on the detected edge and the edge time position. A threshold circuit coupled to an edge circuit is configured to select a first threshold and a second threshold based at least in part on an identified unit time interval, wherein the first threshold includes a rising edge threshold and the second threshold includes a falling edge threshold. as well as The recovery circuit, coupled to the input connector, is configured to output data based at least in part on a first threshold and a second threshold, wherein the output data includes data values ​​having equal half-bit periods and variable frequencies.

2. The integrated circuit of claim 1, wherein the identified unit time interval includes a reference unit time interval having the longest unit time interval relative to the remaining identified unit time intervals and excluding edges during the reference unit time interval.

3. The integrated circuit of claim 1, wherein the identified unit time interval includes a first subset of unit time intervals corresponding to data values ​​encoded in the first type and a second subset of unit time intervals corresponding to data values ​​encoded in the second type.

4. The integrated circuit of claim 3, wherein the first type of encoded data value includes zero and the second type of encoded data value includes one.

5. The integrated circuit of claim 1, wherein the recovery circuit includes a first-in-first-out (FIFO) buffer.

6. The integrated circuit of claim 1, wherein the recovery circuit is configured to implement a state machine corresponding to the data.

7. The integrated circuit of claim 1, wherein the integrated circuit further comprises a clock data recovery CDR coupled to the recovery circuit, the CDR being configured to recover the clock at least in part based on the data.

8. A method for outputting data by a recovery circuit in an integrated circuit as claimed in claim 1, comprising: By recovery circuit: The input signal corresponding to the encoded data is received on the signal line, wherein the encoded data is encoded using biphase mark code (BMC), and the input signal has different rise and fall times; and The output data is based at least in part on a first threshold and a second threshold, wherein the output data includes data values ​​with equal half-bit periods and variable frequencies.

9. An integrated circuit, comprising: The input connector is configured to couple to the signal line of the input signal corresponding to the transmitted and encoded data, wherein the encoded data is encoded using biphase mark code (BMC); An edge circuit, coupled to the input connector, is configured to detect the edge and edge timing position in the input signal that corresponds to a predefined preamble sequence in the encoded data; A time interval circuit, coupled to an edge circuit, is configured to identify a unit time interval in a set of predefined unit time intervals in the encoded data, based at least in part on the detected edge and the edge time position. A threshold circuit coupled to an edge circuit is configured to select a first threshold and a second threshold based at least in part on an identified unit time interval, wherein the first threshold includes a rising edge threshold and the second threshold includes a falling edge threshold. as well as The recovery circuit, coupled to the edge circuit, the time interval circuit, and the threshold circuit, is configured to output data based at least in part on the first threshold and the second threshold.

10. The integrated circuit of claim 9, wherein the identified unit time interval includes a reference unit time interval having the longest unit time interval relative to the remaining identified unit time intervals and excluding edges during the reference unit time interval.

11. The integrated circuit of claim 9, wherein the recovery circuit includes a first-in-first-out (FIFO) buffer.

12. The integrated circuit of claim 9, wherein the recovery circuit is configured to implement a state machine corresponding to the data.

13. The integrated circuit of claim 9, wherein the identified unit time interval includes a first subset of unit time intervals corresponding to data values ​​encoded in the first type and a second subset of unit time intervals corresponding to data values ​​encoded in the second type.

14. The integrated circuit of claim 13, wherein the first type of encoded data value includes zero and the second type of encoded data value includes one.

15. The integrated circuit of claim 9, wherein the output data includes data values ​​having equal half-bit periods and variable frequencies.

16. The integrated circuit of claim 9, wherein the input signals have different rise times and fall times.

17. The integrated circuit of claim 9, wherein the integrated circuit further comprises a clock data recovery CDR coupled to the recovery circuit, the CDR being configured to recover the clock at least in part based on the data.

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