Adaptive equalization method and system for a wide range of signal amplitudes

Abstract

An adaptive equalization method and system for compensating for channel losses is described. One method includes detecting a peak amplitude of an equalizer output signal (504), and selecting a set of reference voltage levels from M sets based on the peak amplitude of the equalizer output signal (508), each of the M sets having N reference voltage levels. The method includes continuing to increase the equalization level to a next higher equalization level in predetermined steps (528) if the applied equalization level does not correspond to the over equalization level, and evaluating a distribution of resulting hit counts for each increase to the next higher equalization level until the applied equalization level corresponds to the over equalization level. The method includes decreasing to the previously applied lower equalization level (524) if the applied equalization level corresponds to the over equalization level.

Description

Technical Field

[0001] This paper generally deals with adaptive equalization for compensating for channel loss. Background technology:

[0002] Equalizers are essential for the operation of telecommunications and electronic systems. In telecommunications, equalization is used to compensate for losses caused by signals transmitted through a channel. Equalization reverses the distortions caused by signals transmitted through a channel. When a channel is equalized, the frequency properties of the signal are reproduced at the output.

[0003] Because channel loss caused by the signal can vary depending on the channel (e.g., HDMI, USB), equalizers are typically adapted to reproduce the frequency properties of the signal. Without equalizer adaptation, the equalizer output may be under-equalized or over-equalized. Existing adaptive equalization systems only equalize signals with a limited amplitude range. If the amplitude is too low, the existing adaptive system may over-equalize, and if the amplitude is too high, the existing adaptive system may under-equalize, thus failing to reverse the distortion caused by the signal. Summary of the Invention

[0004] On one hand, a method includes: detecting the peak amplitude of an equalizer output signal; and selecting a set of reference voltage levels from M groups, each of the M groups having N reference voltage levels, based on the peak amplitude. The method includes: initially applying zero equalization to generate the equalizer output signal, and comparing the equalizer output signal with the N reference voltage levels of the selected group. The method includes: generating a hit count in response to the comparison of the equalizer output signal with the N reference voltage levels. The method includes: increasing from zero equalization to a first equalization level, and applying the first equalization level to generate a hit count in response to the comparison of the equalizer output signal with the N reference voltage levels, and evaluating the distribution of the resulting hit count to determine whether the applied equalization level corresponds to an over-equalization level. The method includes: if the applied equalization level corresponds to the over-equalization level, decreasing to a previously applied lower equalization level, wherein the previously applied lower equalization level corresponds to an optimal equalization level. The method includes: if the applied equalization level does not correspond to the over-equalization level, then continuing to increase the equalization level to the next higher equalization level in predetermined steps, and evaluating the distribution of the resulting hit counts for each increase to the next higher equalization level, until the applied equalization level corresponds to the over-equalization level, and if the applied equalization level corresponds to the over-equalization level, then decreasing it to the previously applied lower equalization level.

[0005] In another aspect of this document, a method for detecting the peak amplitude of the equalizer output signal includes: selecting a subset of the M groups that includes the highest reference voltage level from each of the M groups; and applying zero equalization and comparing the equalizer output signal with the reference voltage level having the highest value in the selected subset. The method includes: if any hit count exists in response to the comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, determining the peak amplitude of the equalizer output signal based on the reference voltage level having the highest value in the subset and the reference voltage level having a second highest value in the selected subset. The method includes: if no hit count exists in response to the comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, comparing the equalizer output signal with the reference voltage level having the second highest value in the subset. The method includes: if any hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having a second highest value in the subset, then determining the peak amplitude of the equalizer output signal based on the reference voltage level having a second highest value in the subset and the reference voltage level having a third highest value in the subset. The method further includes: if no hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having a second highest value in the subset, then continuing to compare the equalizer output signal with the reference voltage level having a second highest value in the subset until at least one hit count exists, and determining the peak amplitude based on the compared reference voltage level and the reference voltage level having a second highest value.

[0006] In another aspect of this document, an adaptive equalization system includes an equalizer having a first input, a second input, and an output. The first input is configured to receive an input signal, the second input is configured to receive a boost control signal, and the output is configured to provide an equalizer output signal. The system also includes a comparator circuit having a first input, a second input, and an output. The first input is configured to receive the equalizer output signal, the second input is configured to receive a reference voltage, and the output is configured to provide a comparison signal. Finally, the system includes an equalizer control circuit having an input, a first output, and a second output. The input is configured to receive the comparison signal, the first output is configured to provide the boost control signal, and the second output is configured to provide a reference voltage level control signal. The system includes a digital-to-analog (DAC) converter having a first input and an output, the first input being configured to receive a reference voltage level control signal and the output being configured to provide the reference voltage, wherein the equalizer control circuit is configured to determine the peak amplitude of the equalizer output signal and, in response, provide the reference voltage level control signal.

[0007] On the other hand, the adaptive equalization system includes a divider circuit having an input and an output, the input being configured to receive the comparison signal and the output being configured to provide a division signal; and includes a counter having an input and an output, the input being configured to receive the division signal and the output being configured to provide a hit count in response to the division signal.

[0008] On the other hand, a non-transitory computer-readable medium having program code recorded thereon includes: program code for detecting the peak amplitude of an equalizer output signal; program code for selecting a set of reference voltage levels from M groups based on the peak amplitude of the equalizer output signal, each of the M groups having N reference voltage levels; program code for initially applying zero equalization to generate the equalizer output signal and comparing the equalizer output signal with the N reference voltage levels of the selected group; program code for generating a hit count in response to the comparison of the equalizer output signal with the N reference voltage levels; and program code for performing the following: increasing from zero equalization to a first equalization level and applying the first equalization level in response to the comparison of the equalizer output signal with the N reference voltage levels. Generate a hit count and evaluate the distribution of the resulting hit count to determine whether the applied equalization level corresponds to an over-equalization level; program code for reducing the applied equalization level to a previously applied lower equalization level when the applied equalization level corresponds to the over-equalization level, wherein the previously applied lower equalization level corresponds to the optimal equalization level; program code for performing the following: if the applied equalization level does not correspond to the over-equalization level, continue to increase the equalization level to the next higher equalization level in predetermined steps, and evaluate the distribution of the resulting hit count for each increase to the next higher equalization level until the applied equalization level corresponds to the over-equalization level, and if the applied equalization level corresponds to the over-equalization level, reduce the applied equalization level to the previously applied lower equalization level. Attached Figure Description

[0009] Figures 1A to 1B This is a block diagram of a system in an example embodiment.

[0010] Figures 2 to 3 The diagram illustrates multiple sets of reference voltage levels.

[0011] Figures 4A to 4B The diagram illustrates channel loss and equalization.

[0012] Figure 5 This is a flowchart of an example embodiment. Detailed Implementation

[0013] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, which show some, but not all, of the embodiments. In fact, these concepts may be implemented in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided so that this document will satisfy applicable requirements.

[0014] Figure 1A This is a block diagram of an adaptive equalization system 100 according to an example embodiment. System 100 detects the peak amplitude of a signal and selects the optimal equalization level to compensate for losses caused by the signal transmitted through the channel. Furthermore, system 100 compensates for channel losses of signals with a wide amplitude range.

[0015] The adaptive equalization system 100 includes an equalizer 104 having a first input 106, a second input 108, and an output 110. The first input is configured to receive an input signal, the second input is configured to receive a boost control signal, and the output is configured to provide an equalizer output signal. The system 100 also includes a comparator circuit 112 having a first input 114, a second input 116, and an output 118. The first input is configured to receive the equalizer output signal, the second input is configured to receive a reference voltage, and the output is configured to provide a comparison signal. In an example embodiment, the comparator circuit 112 is an analog comparator configured to compare the equalizer output signal with the reference voltage and, in response, provide a comparison signal.

[0016] Continue to refer to Figure 1A If the input signal has a high frequency, the transition at the output of comparator circuit 112 (referred to as the hit count) can be very fast. Therefore, divider 124 can optionally be used to divide the hit count and reduce those hit counts. For example, divider 124 can be configured to reduce the hit count by dividing with an integer (e.g., 4, 8, 16, or 32). Divider 124 has an input 126 configured to receive a comparator signal. Divider 124 provides a reduced hit count at its output 128. System 100 includes equalizer control circuitry 132 having an input 134 and a first output 136 and a second output 138. The input is configured to receive a comparator signal, the first output is configured to provide a boost control signal, and the second output is configured to provide a reference voltage level control signal.

[0017] In an example embodiment, the equalizer control circuit 132 includes a counter 140 that counts hits. The equalizer control circuit 132 evaluates the distribution of the hit counts and, in response, provides a boost control signal at a first output 136. In an example embodiment, a divider 124 may be implemented internally to the equalizer control circuit 132, and in this case, the equalizer control circuit 132 may receive the hit count from the comparator circuit 112 and perform division by the divider 124 to decrease the hit count. In an example embodiment, the equalizer control circuit 132 also determines the peak amplitude of the equalizer output signal and provides a reference voltage level control signal at a second output 138. The reference voltage level control signal may indicate the peak amplitude and multiple sets (e.g., M sets) of reference voltage levels. System 100 includes a digital-to-analog converter (DAC) 144 having an input 142 configured to receive the reference voltage level control signal and an output configured to provide a reference voltage. In an example embodiment, the equalizer control circuit 132 includes a finite state machine (FSM) 150 configured to evaluate or assess the distribution of hit counts and to provide boost control signals and reference voltage level control signals. The FSM 150 is described in more detail below.

[0018] In another example embodiment, Figure 1B The illustrated system 156 may optionally include an analog peak detector 160 configured to detect the peak amplitude of the equalizer output signal and provide an analog peak detection signal at output 162. Peak detector 160 monitors the voltage of the equalizer output signal and maintains its peak value at output 162. Analog-to-digital converter (ADC) 164 converts the analog peak detection signal and provides a digital peak detection signal at output 166. DAC 144 receives the digital peak detection signal and receives a reference voltage level control signal from equalizer control circuitry 132, and in response, provides a reference voltage.

[0019] Figure 2 M groups (e.g., M = 8) of reference voltage levels are shown, where M is an integer. Each group has N (e.g., N = 8) reference voltage levels, where N is an integer. Within each group, one reference voltage level has a minimum or lowest value, while another has a maximum or highest value. Furthermore, within each group, the reference voltage level increases from the minimum to the maximum value in a predetermined increment. Additionally, the maximum or highest value in the M groups also increases in a predetermined increment. Therefore, these multiple groups of reference voltage levels have different maximum reference voltage levels.

[0020] By way of example, in group #1, the reference voltage level increases from a minimum of 140mV to a maximum of 200mV; in group #2, the reference voltage level increases from a minimum of 140mV to a maximum of 300mV; and in group #3, the reference voltage level increases from a minimum of 140mV to a maximum of 400mV. The highest or maximum value in all eight groups also increases from 200mV to 900mV in increments of 100mV.

[0021] In the example embodiment, M sets of reference voltage levels are generated by the equalizer control circuit 132, and the set whose maximum value is slightly higher than the peak amplitude of the equalizer output signal is selected. For example, if the peak amplitude of the equalizer output signal is 380mV, set #3 is selected because its maximum value is 400mV, which is slightly higher than that peak amplitude. Because system 100 generates M sets of reference voltage levels, where the highest or maximum value in the M sets rises from the minimum to the maximum value in predetermined increments, system 100 can equalize and reproduce signals with a wide range of peak amplitudes. System 100 detects the peak amplitude of the equalizer output signal and selects the set whose maximum value is slightly higher than the peak amplitude.

[0022] Figure 3 This shows a set of reference voltage levels selected from group M. The highest voltage level in the selected group is slightly higher than the peak amplitude of the equalizer output signal. With the equalizer gain (i.e., equalization level) initially set to zero, the equalizer output signal is compared to the reference voltage levels in the selected group. A hit count is generated based on the comparison between the equalizer output signal and the reference voltage levels. Figure 3 As shown, a hit count is generated in each instance where the signal intersects (i.e., crosses) the reference voltage level. Next, the equalizer gain is increased to the next higher level (e.g., the first equalization level), and the equalizer output signal is compared to the reference voltage level. Based on this comparison, a hit count is generated, and the distribution of the hit count is re-evaluated or assessed by the equalizer control circuit 132 to determine whether the applied equalization level corresponds to an over-equalization level. If the distribution of the hit count indicates that the applied equalization level corresponds to an over-equalization level, the equalizer gain is reduced to the previously applied lower equalization level, and the reduced equalizer gain is determined as the optimal equalization level.

[0023] If the applied equalizer level does not correspond to an over-equalizer level, the equalizer gain is increased to the next higher equalizer level (e.g., a second equalizer level), and the distribution of the resulting hit counts is evaluated again. This process is repeated for each increase to the next higher equalizer level in predetermined steps, and the distribution of the resulting hit counts is evaluated for each increase until the applied equalizer level corresponds to an over-equalizer level. The equalizer level is then reduced to the previously applied lower equalizer level, which is determined to be the optimal equalizer level.

[0024] In an example embodiment, if the hit count distribution indicates overshoot and undershoot caused by ringing, then the distribution indicates an over-equalization level.

[0025] In an example embodiment, the equalizer control circuit 132 determines the peak amplitude of the equalizer output signal by selecting the highest reference voltage level from each of the M groups. Thus, a subset comprising the highest reference voltage levels from each of the M groups is formed. With zero equalization applied, the equalizer output signal is compared to the reference voltage level with the highest value in the selected subset. If any hit count exists in response to the comparison of the equalizer output signal with the reference voltage level with the highest value in the subset, the peak amplitude is determined based on the reference voltage level with the highest value in the subset and the reference voltage level with the second highest value in the selected subset. In the example embodiment, the peak amplitude is determined to be approximately midway between the highest and second highest values ​​in the subset.

[0026] If no hit count is found in the comparison between the equalizer output signal and the reference voltage level with the highest value in the subset, the equalizer output signal is compared with the reference voltage level with the second highest value in the subset. If any hit count exists in the comparison between the equalizer output signal and the reference voltage level with the second highest value in the subset, the peak amplitude is determined based on the second and third highest values ​​in the subset. In the example embodiment, the peak amplitude is determined to be approximately at the midpoint between the second and third highest values.

[0027] If no hit count is found in response to a comparison of the equalizer output signal with a reference voltage level having the second highest value in the subset, the process continues by comparing the equalizer output signal with a reference voltage level having the second highest value in the subset until at least one hit count is found, and the peak amplitude is determined based on the compared reference voltage level and the reference voltage level having the second highest value.

[0028] In an example embodiment, a finite state machine (FSM) 150 is configured to evaluate or assess the distribution of hit counts and, in response, provide a boost control signal to the equalizer 104. The FSM 150 includes an algorithm that tracks multiple equalizer response graphs and scans a reference voltage level against the response graphs to generate hit counts. The FSM 150 evaluates the distribution of the resulting hit counts to identify the response graph corresponding to the optimal equalizer curve. Figure 4A and Figure 4B The diagram illustrates the operation of the FSM 150. Figure 4A The channel loss characteristics of the cable through which the signal is transmitted are shown. The signal transmitted through the cable exhibits 0 dB loss at DC (0 Hz) and -10 dB loss at 6 GHz. Therefore, the signal transmitted through the cable exhibits linear channel loss as the frequency increases from 0 Hz to 6 GHz. The signal is then equalized by an equalizer to reverse the distortion that occurred during transmission through the cable. Figure 4B Three example response graphs of the equalizer are shown: underbalanced response graph 404, optimal equalization response graph 408, and overbalanced response graph 412. The FSM 150 tracks the response graphs and scans the reference voltage level against the response graphs to generate a hit count. The FSM 150 evaluates the distribution of the resulting hit counts and identifies response graph 408 as the optimal equalization curve. Figure 4A The channel loss characteristics of the cable shown are almost the opposite of those in the optimal equalization curve 408. Therefore, by selecting the optimal equalization curve 408, the equalizer can compensate for channel loss, that is, reverse the distortion caused by the signal during transmission.

[0029] In the example embodiment, the FSM 150 also determines the peak amplitude of the equalizer output signal and, in response, provides a reference voltage level control signal. The reference voltage level control signal indicates multiple sets of reference voltage levels (e.g., M sets) and the detected peak amplitude. The DAC 144 receives the reference voltage level control signal and, in response, provides a reference voltage to the comparator circuit 112.

[0030] Modifications to system 100 are possible within the scope of this document. ADC 164 can provide a digital peak detection signal to DAC 144, and FSM 150 can provide a reference voltage level control signal to DAC 144 indicating multiple sets of reference voltage levels. In response, DAC 144 provides a reference voltage.

[0031] Other modifications to system 100 are possible within the scope of this document. FSM 150 may be replaced by an FPGA, ASIC, microprocessor, finite state machine (FSM), or software configured to perform the operations described above.

[0032] Figure 5 This is a flowchart of an example embodiment. At block 504, the peak amplitude of the equalizer output signal is determined. At block 508, a set of reference voltage levels is selected from M groups based on the peak amplitude of the equalizer output signal, each group having N reference voltage levels. At block 512, zero equalization is applied to generate the equalizer output signal, and the equalizer output signal is compared with the N reference voltage levels of the selected group, generating a hit count in response to the comparison between the equalizer output signal and the N reference voltage levels.

[0033] At block 516, the equalization level is increased from zero equalization to a first equalization level, and this first equalization level is applied to generate a hit count in response to a comparison of the equalizer output signal with N reference voltage levels. The distribution of the resulting hit count is evaluated to determine whether the applied equalization level corresponds to an over-equalization level. In decision block 520, a decision is made regarding whether the applied equalization level corresponds to an over-equalization level. If the applied equalization block corresponds to an over-equalization level, the process moves to block 524, where the equalization level is reduced to a previously applied lower equalization level, which corresponds to the optimal equalization level.

[0034] If the applied equalization level does not correspond to an over-equalization level, the process moves to block 528, where the equalization level is increased in predetermined steps to the next higher equalization level. For each increase to the next higher equalization level, the distribution of the resulting hit counts is evaluated until the applied equalization level corresponds to an over-equalization level. If the applied equalization level corresponds to an over-equalization level, the equalization level is reduced to the previously applied lower equalization level. The previously applied lower equalization level is determined as the optimal equalization level.

[0035] On one hand, a non-transitory computer-readable medium having program code recorded thereon includes: program code for detecting the peak amplitude of an equalizer output signal; program code for selecting a set of reference voltage levels from M groups based on the peak amplitude of the equalizer output signal, each of the M groups having N reference voltage levels; program code for initially applying zero equalization to generate an equalizer output signal and comparing the equalizer output signal with the N reference voltage levels of the selected group; program code for generating a hit count in response to the comparison of the equalizer output signal with the N reference voltage levels; and program code for performing the following: increasing from zero equalization to a first equalization level and applying the first equalization level in response to the comparison of the equalizer output signal with the N reference voltage levels. Generate a hit count and evaluate the distribution of the resulting hit count to determine whether the applied equalization level corresponds to an over-equalization level; program code for reducing the applied equalization level to a previously applied lower equalization level when the applied equalization level corresponds to an over-equalization level, wherein the previously applied lower equalization level corresponds to the optimal equalization level; program code for performing the following: if the applied equalization level does not correspond to an over-equalization level, continue to increase the equalization level to the next higher equalization level in predetermined steps, and evaluate the distribution of the resulting hit count for each increase to the next higher equalization level until the applied equalization level corresponds to an over-equalization level, and if the applied equalization level corresponds to an over-equalization level, reduce the applied equalization level to the previously applied lower equalization level.

[0036] The various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. For each specific application, the described functionality may be implemented in different ways, but such implementation decisions should not be construed as leading off the scope of this document.

[0037] For the sake of simplicity and clarity, this paper does not depict or describe the complete structure and operation of all systems applicable to this paper. Instead, only systems that are unique to this paper or necessary for understanding this paper are depicted and described.

Claims

1. An adaptive equilibrium method, comprising: Detect the peak amplitude of the equalizer output signal; A set of reference voltage levels is selected from M groups based on the peak amplitude of the equalizer output signal, where each of the M groups has N reference voltage levels; Initially, zero equalization is applied to generate the equalizer output signal, and the equalizer output signal is compared with N reference voltage levels of a selected group; A hit count is generated in response to a comparison between the equalizer output signal and the N reference voltage levels; The equalization level is raised from zero to a first equalization level, and the first equalization level is applied to generate a hit count in response to a comparison of the equalizer output signal with the N reference voltage levels, and the distribution of the resulting hit count is evaluated to determine whether the applied equalization level corresponds to an over-equalization level. If the applied equalization level corresponds to the over-equalization level, then the level is reduced to the previously applied lower equalization level, wherein the previously applied lower equalization level corresponds to the optimal equalization level. If the applied equalization level does not correspond to the over-equalization level, the equalization level is increased to the next higher equalization level in predetermined steps, and the distribution of the resulting hit count is evaluated for each increase to the next higher equalization level, until the applied equalization level corresponds to the over-equalization level, and if the applied equalization level corresponds to the over-equalization level, it is reduced to the previously applied lower equalization level.

2. The method according to claim 1, wherein, The reference voltage level with the highest value in the selected group is greater than the peak amplitude of the equalizer output signal.

3. The method according to claim 1, wherein, Detecting the peak amplitude of the equalizer output signal includes: Select a subset of the M groups that includes the highest reference voltage level from each of the M groups; Zero equalization is applied and the equalizer output signal is compared with the reference voltage level with the highest value in a selected subset; If any hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, the peak amplitude of the equalizer output signal is determined based on the reference voltage level having the highest value in the subset and the reference voltage level having the second highest value in the selected subset. If, in response to a comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, there is no hit count, then the equalizer output signal is compared with the reference voltage level having the second highest value in the subset. If any hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset, then the peak amplitude of the equalizer output signal is determined based on the reference voltage level having the second highest value and the reference voltage level having the third highest value in the subset; and If no hit count is found in response to the comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset, the comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset continues until at least one hit count is found, and the peak amplitude is determined based on the compared reference voltage level and the reference voltage level having the second highest value.

4. The method according to claim 3, wherein, If a hit count exists, the peak amplitude of the equalizer output signal is between the compared reference voltage level and the reference voltage level with the second-highest value.

5. The method according to claim 1, wherein, The hit count is generated in response to the intersection of the equalizer output signal and the reference voltage level being compared.

6. The method according to claim 1, wherein, If the distribution of the hit count indicates overshoot and undershoot, then the applied equalization level corresponds to the over-equalization level.

7. The method according to claim 1, wherein, M and N are integers.

8. An adaptive equilibrium system, comprising: An equalizer having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive an input signal, the second input terminal is configured to receive a boost control signal, and the output terminal is configured to provide an equalizer output signal; A comparator circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive the output signal of the equalizer, the second input terminal is configured to receive a reference voltage, and the output terminal is configured to provide a comparison signal; An equalizer control circuit has an input terminal, a first output terminal, and a second output terminal. The input terminal is configured to receive the comparison signal, the first output terminal is configured to provide the boost control signal, and the second output terminal is configured to provide a reference voltage level control signal. as well as A digital-to-analog converter (DAC) having a first input terminal and an output terminal, the first input terminal being configured to receive the reference voltage level control signal, and the output terminal being configured to provide the reference voltage. The equalizer control circuit is configured to detect the peak amplitude of the equalizer output signal and, in response, provide the reference voltage level control signal. The adaptive equalization system further includes: A divider circuit having an input terminal and an output terminal, the input terminal being configured to receive the comparison signal, and the output terminal being configured to provide a division signal; and A counter having an input and an output, the input being configured to receive the division signal and the output being configured to provide a hit count in response to the division signal.

9. The adaptive equalization system according to claim 8, wherein, The equalizer control circuit includes a finite state machine configured to evaluate the distribution of hit counts and provide the boost control signal in response to the distribution of hit counts.

10. The adaptive equalization system according to claim 8, wherein, The equalizer control circuit includes a finite state machine configured to provide the reference voltage level control signal in response to the peak amplitude.

11. The adaptive equalization system according to claim 8, wherein, The highest reference voltage level is greater than the peak amplitude of the equalizer output signal.

12. An adaptive equilibrium system, comprising: An equalizer having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive an input signal, the second input terminal is configured to receive a boost control signal, and the output terminal is configured to provide an equalizer output signal; A peak detector circuit having an input terminal and an output terminal, the input terminal being configured to receive the equalizer output signal, and the output terminal being configured to provide an analog peak detection signal indicating the peak amplitude of the equalizer output signal; An analog-to-digital converter having an input terminal and an output terminal, the input terminal being configured to receive the analog peak detection signal and the output terminal being configured to provide a digital peak detection signal; A digital-to-analog converter having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive a reference voltage level control signal, the second input terminal is configured to receive a digital peak detection signal, and the output terminal is configured to provide a reference voltage; A comparator circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive the output signal of the equalizer, the second input terminal is configured to receive the reference voltage, and the output terminal is configured to provide a comparison signal; as well as An equalizer control circuit has an input terminal, a first output terminal, and a second output terminal. The input terminal is configured to receive the comparison signal, the first output terminal is configured to provide the boost control signal, and the second output terminal is configured to provide the reference voltage level control signal. The equalizer control circuit includes a finite state machine configured to evaluate the distribution of hit counts and provide the boost control signal in response to the distribution of hit counts.

13. The adaptive equalization system according to claim 12, further comprising: A divider circuit having an input terminal and an output terminal, the input terminal being configured to receive the comparison signal, and the output terminal being configured to provide a division signal; as well as A counter having an input and an output, the input being configured to receive the division signal and the output being configured to provide a hit count in response to the division signal.

14. The adaptive equalization system according to claim 12, wherein, The equalizer control circuit includes a finite state machine configured to provide the reference voltage level control signal.

15. An adaptive equilibrium method, comprising: Detect the peak amplitude of the equalizer output signal; A set of reference voltage levels is selected from M groups based on the peak amplitude of the equalizer output signal. Each of the M groups has N reference voltage levels, wherein the reference voltage level with the highest value in the selected group is greater than the peak amplitude of the equalizer output signal. Initially, zero equalization is applied to generate the equalizer output signal, and the equalizer output signal is compared with N reference voltage levels of a selected group; A hit count is generated in response to a comparison between the equalizer output signal and the N reference voltage levels; The equalization level is raised from zero to a first equalization level, and the first equalization level is applied to generate a hit count in response to a comparison of the equalizer output signal with the N reference voltage levels, and the distribution of the resulting hit count is evaluated to determine whether the applied equalization level corresponds to an over-equalization level. If the applied equalization level corresponds to the over-equalization level, then the level is reduced to the previously applied lower equalization level, wherein the previously applied lower equalization level corresponds to the optimal equalization level. If the applied equalization level does not correspond to the over-equalization level, the equalization level continues to be increased to the next higher equalization level in predetermined steps, and the distribution of the resulting hit count is evaluated for each increase to the next higher equalization level, until the applied equalization level corresponds to the over-equalization level, and if the applied equalization level corresponds to the over-equalization level, the level is reduced to the previously applied lower equalization level. The hit count is generated in response to the intersection of the equalizer output signal and the compared reference voltage level. Wherein, if the distribution of the hit count indicates overshoot and undershoot, the applied equalization level corresponds to the over-equalization level.

16. The method according to claim 15, wherein, Detecting the peak amplitude of the equalizer output signal includes: Select a subset of the M groups that includes the highest reference voltage level from each of the M groups; Zero equalization is applied and the equalizer output signal is compared with the reference voltage level with the highest value in a selected subset; If any hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, the peak amplitude of the equalizer output signal is determined based on the reference voltage level having the highest value in the subset and the reference voltage level having the second highest value in the selected subset. If, in response to a comparison of the equalizer output signal with the reference voltage level having the highest value in the subset, there is no hit count, then the equalizer output signal is compared with the reference voltage level having the second highest value in the subset. If any hit count exists in response to a comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset, then the peak amplitude of the equalizer output signal is determined based on the reference voltage level having the second highest value and the reference voltage level having the third highest value in the subset; and If no hit count is found in response to the comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset, the comparison of the equalizer output signal with the reference voltage level having the second highest value in the subset continues until at least one hit count is found, and the peak amplitude is determined based on the compared reference voltage level and the reference voltage level having the second highest value.

17. The method according to claim 15, wherein, If a hit count exists, the peak amplitude of the equalizer output signal is between the compared reference voltage level and the reference voltage level with the second-highest value.

18. The method according to claim 15, wherein, The hit count is generated in response to the intersection of the equalizer output signal and the reference voltage level being compared.

19. The method according to claim 15, wherein, M and N are integers.

20. A non-transitory computer-readable medium having program code recorded thereon, comprising: Program code used to detect the peak amplitude of the equalizer output signal; Program code for selecting a set of reference voltage levels from M groups based on the peak amplitude of the equalizer output signal, each of the M groups having N reference voltage levels; Program code for initially applying zero equalization to generate the equalizer output signal and comparing the equalizer output signal with N reference voltage levels of a selected group; Program code for generating a hit count in response to a comparison of the equalizer output signal with the N reference voltage levels; Program code for performing the following: increasing from zero equalization to a first equalization level, applying the first equalization level to generate a hit count in response to a comparison of the equalizer output signal with the N reference voltage levels, and evaluating the distribution of the resulting hit count to determine whether the applied equalization level corresponds to an over-equalization level. Program code for reducing the applied equalization level to a previously applied lower equalization level when the applied equalization level corresponds to the over-equalization level, wherein the previously applied lower equalization level corresponds to the optimal equalization level. The program code is used to perform the following: if the applied equalization level does not correspond to the over-equalization level, the equalization level is continuously increased to the next higher equalization level in predetermined steps, and for each increase to the next higher equalization level, the distribution of the resulting hit count is evaluated until the applied equalization level corresponds to the over-equalization level, and if the applied equalization level corresponds to the over-equalization level, the equalization level is reduced to the previously applied lower equalization level.

21. The non-transitory computer-readable medium according to claim 20, wherein, The hit count is generated in response to the intersection of the equalizer output signal and the reference voltage level being compared.

22. The non-transitory computer-readable medium according to claim 20, wherein, M and N are integers.

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