A fiber optic inertial navigation integrated system and integration method
By integrating the control chip of the fiber optic inertial navigation system, the problems of high hardware cost and bloated circuitry were solved, achieving system miniaturization and improved real-time performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING HUAYU ELECTRIC GRP
- Filing Date
- 2023-01-11
- Publication Date
- 2026-06-02
AI Technical Summary
Existing fiber optic inertial navigation systems suffer from high hardware costs, cumbersome circuitry, large size, heavy weight, and clock asynchrony between navigation data processing and gyroscope data acquisition.
The FPGA control chip inside the gyroscope circuit is integrated with the FPGA control chip of the navigation computer into a main control chip FPGA, and the same clock circuit is used to provide clock signals to the main control chip FPGA and DSP to achieve clock source synchronization.
This system achieves miniaturization and integration, reduces hardware costs, and improves the real-time performance of navigation data processing.
Smart Images
Figure CN116678407B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of fiber optic navigation technology, and specifically to a fiber optic inertial navigation integrated system and integration method. Background Technology
[0002] Fiber optic inertial navigation systems are based on the principle of inertia and mainly consist of inertial devices and corresponding navigation computers. They are used to measure the angular velocity and acceleration of the sensitive carrier platform. After navigation calculation by the navigation computer, three attitude angles are output to provide control for the carrier platform.
[0003] In fiber optic inertial navigation systems, the inertial devices are typically gyroscopes. Each gyroscope contains a data acquisition circuit and a corresponding control chip, an FPGA (Field-Programmable Gate Array). The navigation computer receives navigation data from the gyroscopes via a serial port, and its control chip is also an FPGA. Therefore, existing fiber optic inertial navigation systems often contain multiple FPGA control chips, resulting in a bulky circuit structure and higher overall cost. Furthermore, the navigation computer uses a DSP (Digital Signal Processing) to process the navigation data, which prevents clock synchronization between the acquisition of raw gyroscope data and the processing of navigation data, leading to poor real-time performance. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the existing technology, the technical problem to be solved by the present invention is: how to provide an integrated fiber optic inertial navigation system and integration method that can reduce the hardware cost of the fiber optic inertial navigation system, while meeting the requirements of miniaturization and integration, and further reducing the size and weight of the inertial navigation system.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0006] An integrated fiber optic inertial navigation system includes a gyroscope circuit, a main control chip FPGA, and a power supply circuit.
[0007] The power supply circuit provides power to the gyroscope circuit and the main control chip FPGA.
[0008] The gyroscope circuit includes multiple gyroscope circuits, each of which includes an amplifier circuit and an AD acquisition circuit. The signal output terminal of the amplifier circuit is connected to the signal input terminal of the AD acquisition circuit, and is used to amplify the acquired navigation data and send it to the AD acquisition circuit. The signal output terminal of the AD acquisition circuit is connected to the signal input terminal of the main control chip FPGA, and is used to perform analog-to-digital conversion on the amplified navigation data and send it to the main control chip FPGA.
[0009] The main control chip FPGA is equipped with multiple communication interfaces, which are used to uniformly receive and process the data received from each AD acquisition circuit, so as to complete the navigation data acquisition and external communication of the multi-channel gyroscope circuit.
[0010] Preferably, the fiber optic inertial navigation integrated system further includes a DSP and a clock circuit. The power supply circuit also supplies power to the DSP and the clock circuit. The DSP is communicatively connected to the main control chip FPGA so that the DSP can directly read and write to the random access memory of the main control chip FPGA. The clock circuit provides clock signals to both the DSP and the main control chip FPGA to achieve clock source synchronization between the main control chip FPGA and the DSP.
[0011] Preferably, the main control chip FPGA and the DSP are connected through an external memory interface EMIF, and the DSP and the main control chip FPGA form a master-slave working mode.
[0012] Preferably, the fiber optic inertial navigation integrated system further includes an accelerometer acquisition circuit. The signal output terminal of the accelerometer acquisition circuit is connected to the signal input terminal of the main control chip FPGA to input differential pulse signals to the main control chip FPGA. Under the action of the differential pulse signals, the main control chip FPGA performs shaping and de-glitch processing on the serial port signals input by the gyroscope circuit.
[0013] Preferably, the fiber optic inertial navigation integrated system further includes a DDR interface circuit and a first FLASH circuit. Both the DDR interface circuit and the first FLASH circuit are connected to the DSP through an external memory interface EMIF. The DDR interface circuit is used to expand the random access memory space of the DSP, and the first FLASH circuit is used to store the program and parameters of the DSP.
[0014] Preferably, the fiber optic inertial navigation integrated system further includes a communication interface circuit, wherein the signal output terminal of the communication interface circuit is connected to the signal input terminal of the main control chip FPGA via a serial port, Ethernet port, or CAN.
[0015] Preferably, the fiber optic inertial navigation integrated system further includes a second FLASH circuit, which is communicatively connected to the main control chip FPGA and is used to store the program and parameters of the main control chip FPGA.
[0016] Preferably, the clock circuit uses a temperature-compensated active crystal oscillator circuit, and the drift value of the clock circuit is less than 1ppm.
[0017] An integration method for the fiber optic inertial navigation integrated system described above reduces the system size by integrating the control chip FPGA inside each gyroscope circuit and the control chip FPGA of the navigation computer into a single main control chip FPGA.
[0018] Preferably, clock source synchronization is achieved by using the same clock circuit to provide clock signals to the main control chip FPGA and DSP.
[0019] Compared with the prior art, the present invention has the following advantages:
[0020] 1. This invention extracts the FPGA control chip from the gyroscope circuit and integrates it with the FPGA control chip of the navigation computer into a single main control chip FPGA. This way, the entire system only needs to use one main control chip FPGA. The integrated circuit design layout is beneficial for controlling the overall structural size of the system. This solves the problem of bloated internal circuits in fiber optic inertial navigation systems, achieving the miniaturization and integration requirements of the system. At the same time, it achieves integrated collaborative design of the system and individual components, significantly reducing the number of integrated circuit chips and further reducing costs.
[0021] 2. This invention integrates the FPGA control chip inside the gyroscope circuit and the FPGA control chip of the navigation computer into a single main control chip FPGA. Then, the same clock circuit is used to provide clock signals to both the main control chip FPGA and the DSP, thereby synchronizing the clock source of navigation calculation with the clock source of the gyroscope's original data acquisition and improving real-time performance. Attached Figure Description
[0022] Figure 1 This is a system block diagram of the fiber optic inertial navigation integrated system of the present invention. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which this invention pertains.
[0024] The terms "first," "second," and similar words used in the specification and claims of this patent application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, unless the context clearly indicates otherwise, the singular forms of "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" encompasses the features, integrals, steps, operations, elements, and / or components listed following "comprising" or "including," and do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0025] As attached Figure 1 As shown, an integrated fiber optic inertial navigation system includes a gyroscope circuit, a main control chip FPGA, and a power supply circuit.
[0026] The power supply circuit provides power to the gyroscope circuit and the main control chip FPGA; the power supply circuit performs the required level conversion for the entire circuit, covering ±5V and ±15V.
[0027] The gyroscope circuit includes multiple gyroscope circuits. In this specific embodiment, it includes three gyroscope circuits. Each gyroscope circuit includes an amplifier circuit and an AD acquisition circuit. The signal output terminal of the amplifier circuit is connected to the signal input terminal of the AD acquisition circuit. It is used to amplify the acquired navigation data and send it to the AD acquisition circuit. The signal output terminal of the AD acquisition circuit is connected to the signal input terminal of the main control chip FPGA. It is used to perform analog-to-digital conversion on the amplified navigation data and send it to the main control chip FPGA.
[0028] The main control chip FPGA has multiple communication interfaces, which are used to uniformly receive and process the data received from various AD acquisition circuits, so as to complete the navigation data acquisition and external communication of the multi-channel gyroscope circuit.
[0029] In this embodiment, the fiber optic inertial navigation integrated system also includes a DSP and a clock circuit. The power supply circuit also supplies power to the DSP and the clock circuit. The DSP is connected to the main control chip FPGA so that the DSP can directly read and write to the random access memory of the main control chip FPGA. The clock circuit provides clock signals to both the DSP and the main control chip FPGA to achieve clock source synchronization between the main control chip FPGA and the DSP.
[0030] In this embodiment, the main control chip FPGA and DSP are connected through the external memory interface EMIF, and the DSP and the main control chip FPGA form a master-slave working mode.
[0031] In this embodiment, the fiber optic inertial navigation integrated system also includes an accelerometer acquisition circuit. The signal output terminal of the accelerometer acquisition circuit is connected to the signal input terminal of the main control chip FPGA to input differential pulse signals to the main control chip FPGA. Under the action of the differential pulse signals, the main control chip FPGA performs shaping and de-glitch processing on the serial port signals input from the gyroscope circuit. This completes the shaping of the differential input signals and improves signal quality.
[0032] In this embodiment, the fiber optic inertial navigation integrated system further includes a DDR interface circuit and a first FLASH circuit. Both the DDR interface circuit and the first FLASH circuit are connected to the DSP through the external memory interface EMIF. The DDR interface circuit is used to expand the random access memory space of the DSP, and the first FLASH circuit is used to store the DSP's program and parameters.
[0033] In this embodiment, the fiber optic inertial navigation integrated system also includes a communication interface circuit. The signal output terminal of the communication interface circuit is connected to the signal input terminal of the main control chip FPGA via a serial port (UART), Ethernet port (ETH), or CAN.
[0034] In this embodiment, the fiber optic inertial navigation integrated system further includes a second FLASH circuit, which is communicatively connected to the main control chip FPGA and is used to store the program and parameters of the main control chip FPGA.
[0035] In this embodiment, the clock circuit uses a temperature-compensated active crystal oscillator circuit, and the drift value of the clock circuit is less than 1ppm.
[0036] In this embodiment, a high-performance FPGA, such as the XC7K325T series, is selected as the main control chip to handle logic programming for multi-channel gyroscope data, accelerometer data, communication interfaces, and data interaction with the DSP. A high-performance DSP, such as the TMS320C6748 series, is selected to perform real-time navigation calculations for the inertial navigation system.
[0037] An integration method for the fiber optic inertial navigation integrated system described above reduces the system size by integrating the control chip FPGA inside each gyroscope circuit and the control chip FPGA of the navigation computer into a single main control chip FPGA.
[0038] In this embodiment, clock source synchronization is achieved by using the same clock circuit to provide clock signals to the main control chip FPGA and DSP.
[0039] Compared to existing technologies, this invention extracts the FPGA control chip from the gyroscope circuit and integrates it with the FPGA control chip of the navigation computer into a single main control chip FPGA. This allows the entire system to utilize only a single main control chip FPGA, resulting in an integrated circuit design that facilitates control over the overall system size. This solves the problem of bloated internal circuitry in fiber optic inertial navigation systems, achieving the miniaturization and integration requirements of the system. Furthermore, it achieves integrated and collaborative design between the system and individual components, significantly reducing the number of integrated circuit chips and further lowering costs. By integrating the FPGA control chip within the gyroscope circuit and the FPGA control chip of the navigation computer into a single main control chip FPGA, and using the same clock circuit to simultaneously provide clock signals to both the main control chip FPGA and the DSP, this invention ensures synchronization between the clock source for navigation calculations and the clock source for acquiring raw gyroscope data, improving real-time performance.
[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.
Claims
1. A fiber optic inertial navigation integrated system, characterized in that, This includes the gyroscope circuit, the main control chip FPGA, and the power supply circuit. The power supply circuit provides power to the gyroscope circuit and the main control chip FPGA. The gyroscope circuit includes multiple gyroscope circuits, each of which includes an amplifier circuit and an AD acquisition circuit. The signal output terminal of the amplifier circuit is connected to the signal input terminal of the AD acquisition circuit, and is used to amplify the acquired navigation data and send it to the AD acquisition circuit. The signal output terminal of the AD acquisition circuit is connected to the signal input terminal of the main control chip FPGA, and is used to perform analog-to-digital conversion on the amplified navigation data and send it to the main control chip FPGA. The main control chip FPGA is equipped with multiple communication interfaces, which are used to uniformly receive and process the data received from each AD acquisition circuit, so as to complete the navigation data acquisition and external communication of the multi-channel gyroscope circuit. It also includes a DSP and a clock circuit. The power supply circuit supplies power to the DSP and the clock circuit. The DSP is communicatively connected to the main control chip FPGA, enabling the DSP to directly read and write to the random access memory of the main control chip FPGA. The clock circuit provides clock signals to both the DSP and the main control chip FPGA to achieve clock source synchronization between the main control chip FPGA and the DSP. The clock circuit uses a temperature-compensated active crystal oscillator circuit, and the drift value of the clock circuit is less than 1ppm. It also includes an accelerometer acquisition circuit, the signal output terminal of which is connected to the signal input terminal of the main control chip FPGA to input differential pulse signals to the main control chip FPGA. Under the action of the differential pulse signals, the main control chip FPGA performs shaping and de-glitch processing on the serial port signals input by the gyroscope circuit. It also includes a second FLASH circuit, which is communicatively connected to the main control chip FPGA and is used to store the program and parameters of the main control chip FPGA.
2. The fiber optic inertial navigation integrated system according to claim 1, characterized in that, The main control chip FPGA and the DSP are connected through an external memory interface EMIF, and the DSP and the main control chip FPGA form a master-slave working mode.
3. The fiber optic inertial navigation integrated system according to claim 1, characterized in that, The fiber optic inertial navigation integrated system further includes a DDR interface circuit and a first FLASH circuit. Both the DDR interface circuit and the first FLASH circuit are connected to the DSP through an external memory interface EMIF. The DDR interface circuit is used to expand the random access memory space of the DSP, and the first FLASH circuit is used to store the program and parameters of the DSP.
4. The fiber optic inertial navigation integrated system according to claim 1, characterized in that, The fiber optic inertial navigation integrated system also includes a communication interface circuit, the signal output terminal of which is connected to the signal input terminal of the main control chip FPGA via a serial port, network port or CAN.
5. An integration method for the fiber optic inertial navigation integrated system as described in claim 1, characterized in that, By integrating the control chip FPGA inside each gyroscope circuit and the control chip FPGA of the navigation computer into a single main control chip FPGA, the system size can be reduced.
6. The integration method of the fiber optic inertial navigation integrated system according to claim 5, characterized in that, Clock source synchronization is achieved by using the same clock circuit to provide clock signals to the main control chip FPGA and DSP.