Debugging method and apparatus, computer readable medium, and electronic device
By setting breakpoint locations and watchpoint registers in the artificial intelligence processor, receiving debugging instructions, and pausing the running task, the problems of large debugging workload and low efficiency in the existing technology are solved, achieving finer-grained debugging and higher debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 伟光有限公司(CN)
- Filing Date
- 2022-02-22
- Publication Date
- 2026-07-21
Smart Images
Figure CN116680158B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and more specifically to a debugging method, debugging apparatus, computer-readable medium, and electronic device. Background Technology
[0002] As artificial intelligence scenarios become more complex, the design of AI accelerators is also becoming more complex. In addition, the amount of data that needs to be processed in the execution of algorithms is also increasing. The design of AI processors needs to consider debuggability to facilitate debugging after development.
[0003] Currently, in relevant AI processor debugging solutions, if data errors occur, the common approach is to export data from all data paths in the AI processor and check the correctness of the data in each data path sequentially. However, with the increasing complexity of AI algorithm networks and the increasing complexity of hardware architecture data flows, the amount of data handled by this debugging method is becoming increasingly massive, and the smallest granularity for debugging is too large, resulting in a large debugging workload and low debugging efficiency. Summary of the Invention
[0004] The purpose of this disclosure is to provide a debugging method, debugging apparatus, computer-readable medium, and electronic device, thereby improving the debugging efficiency of artificial intelligence processors at least to some extent.
[0005] According to a first aspect of this disclosure, a debugging method is provided, executed by an electronic device equipped with an artificial intelligence processor, the method comprising:
[0006] Receive debugging instructions and obtain breakpoint location data from the debugging instructions;
[0007] Execute the pending tasks and compare the execution data corresponding to the tasks with the breakpoint location data;
[0008] If the execution data is found to be consistent with the breakpoint location data, the execution of the running task is paused to detect the execution status of the artificial intelligence processor.
[0009] According to a second aspect of this disclosure, a debugging apparatus is provided, disposed in an electronic device having an artificial intelligence processor, the apparatus comprising:
[0010] A breakpoint location acquisition module is used to receive debugging instructions and acquire breakpoint location data in the debugging instructions;
[0011] The data comparison module is used to execute the running task to be processed and compare the execution data corresponding to the running task with the breakpoint position data;
[0012] The pause debugging module is used to pause the execution of the running task in response to the detection that the execution data is consistent with the breakpoint position data, so as to detect the execution status of the artificial intelligence processor.
[0013] According to a third aspect of this disclosure, a computer-readable medium is provided having a computer program stored thereon, which, when executed by an artificial intelligence processor, implements the method of the first aspect.
[0014] According to a fourth aspect of this disclosure, an electronic device is provided, characterized in that it comprises:
[0015] Artificial intelligence processors; and
[0016] A memory for storing one or more programs, which, when executed by one or more artificial intelligence processors, enable the one or more artificial intelligence processors to implement the methods in the first aspect.
[0017] One embodiment of this disclosure provides a debugging method that can acquire breakpoint location data from debugging instructions. During the execution of a task by an AI processor, the method compares the execution data corresponding to the task with the breakpoint location data. When the execution data matches the breakpoint location data, the execution of the task is paused, and the execution status of the AI processor is monitored. On one hand, pausing and debugging the AI processor using breakpoint location data from debugging instructions allows for finer-grained debugging, improving the flexibility of the debugging process and effectively increasing the debugging efficiency of the AI processor. On the other hand, pausing the task and observing the current execution status of the AI processor when the execution data matches the breakpoint location data eliminates the need to export all data paths in the AI processor before debugging, effectively reducing the workload during debugging and further improving the debugging efficiency of the AI processor.
[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:
[0020] Figure 1A schematic diagram of an artificial intelligence processor architecture to which embodiments of the present disclosure may be applied is shown;
[0021] Figure 2 The schematic diagram illustrates a flowchart of a debugging method according to an exemplary embodiment of the present disclosure;
[0022] Figure 3 A schematic diagram of a network structure for an artificial intelligence algorithm network to which embodiments of the present disclosure can be applied is shown;
[0023] Figure 4 This schematic diagram illustrates a convolution operation process in an artificial intelligence network according to an exemplary embodiment of the present disclosure;
[0024] Figure 5 This illustration schematically shows a generation layer operator instruction and a slicing operator instruction in an artificial intelligence network according to an exemplary embodiment of the present disclosure;
[0025] Figure 6 This schematically illustrates a flowchart of performing breakpoint debugging in an exemplary embodiment of the present disclosure;
[0026] Figure 7 This schematic diagram illustrates an embodiment of the present disclosure of a breakpoint debugging function.
[0027] Figure 8 This schematic diagram illustrates an example of implementing an observation point debugging function in an exemplary embodiment of this disclosure.
[0028] Figure 9 This schematic diagram illustrates the composition of a debugging apparatus in an exemplary embodiment of the present disclosure;
[0029] Figure 10 A schematic diagram of an electronic device to which embodiments of the present disclosure may be applied is shown. Detailed Implementation
[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0031] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0032] Figure 1 A schematic diagram of an artificial intelligence processor architecture to which embodiments of the present disclosure may be applied is shown.
[0033] like Figure 1 As shown, the artificial intelligence processor 100 in this embodiment may include at least a tensor engine 110, a vector engine 120, a storage module 130, and a controller module 140.
[0034] Among them, the tensor processing engine 110 is mainly responsible for processing one-dimensional array operations; the vector processing engine 120 is mainly for multi-dimensional array operations. In the AI accelerator, it is responsible for the parallel operation of large-scale convolution, which can significantly improve the computing performance; the storage module 130 can be static random-access memory (SRAM).
[0035] In the debugging scheme of related artificial intelligence processors, the method of exporting data from fixed observation points is generally used. For example, after the artificial intelligence algorithm is executed, if data errors occur, it is necessary to export the data from each data path, such as tensor processing engine 110 to vector processing engine 120, vector processing engine 120 to storage module 130, and check the correctness of the data on each data path in turn.
[0036] However, with the increasing complexity of AI algorithm networks and hardware architecture data flow, the amount of data faced by the data export debugging method in this debugging scheme is becoming increasingly large, resulting in a large workload for debugging. Moreover, the smallest granularity that can be debugged is too large, making it impossible to pause debugging during the execution of AI algorithm networks, resulting in low debugging efficiency.
[0037] To address one or more problems in related technical solutions, this disclosure first provides a debugging method. This debugging method can be executed by an electronic device equipped with an artificial intelligence processor 100. The electronic device can be a terminal device, such as a smartphone or desktop computer, or a server or a server cluster consisting of multiple servers. This example embodiment is not limited to this. The following describes the debugging method of this disclosure in detail using a server executing the method as an example.
[0038] Figure 2 The flowchart of a debugging method in this exemplary embodiment is shown, which may include the following steps S210 to S230:
[0039] In step S210, a debugging instruction is received, and the breakpoint location data in the debugging instruction is obtained.
[0040] In one exemplary embodiment, a debugging instruction refers to an instruction entered when it is necessary to debug the artificial intelligence processor. For example, a debugging instruction may be an instruction entered by a user object through a pre-provided graphical user interface to pause the debugging of the artificial intelligence processor. Of course, a debugging instruction may also be an instruction automatically generated by a pre-written debugging script. This example embodiment does not make any special limitations on this.
[0041] Breakpoint location data refers to data pre-set by debugging instructions for breakpoint debugging of the artificial intelligence processor. For example, breakpoint location data can be layer operator instructions, slice operator instructions, or instruction address data corresponding to layer operator instructions and slice operator instructions. It can also be interactive data read and written from the storage module or data address data corresponding to interactive data. Of course, it can also be any data during the execution process of the artificial intelligence processor used for breakpoint debugging. This example embodiment is not limited to this.
[0042] By using breakpoint location data in the debugging instructions, breakpoint debugging of artificial intelligence processors can be achieved. Compared with debugging schemes in related technologies, this is more flexible and convenient, and can be used for targeted debugging, making the debugging scheme more efficient.
[0043] In step S220, the task to be processed is executed, and the execution data corresponding to the task is compared with the breakpoint location data.
[0044] In one exemplary embodiment, the task to be processed can be a task based on artificial intelligence technology. For example, the task can be an image classification task performed by a convolutional neural network or a speech recognition task performed by a natural language processing (NLP) model. This example embodiment does not impose any special limitations on this.
[0045] Execution data refers to the data generated by the artificial intelligence processor when running the task to be processed. For example, execution data may be layer operator instructions obtained by splitting the running task, slice operator instructions obtained by decoding the layer operator instructions, or data read from or written to the storage module. This example embodiment is not limited to these.
[0046] For example, if the breakpoint location data in the debugging instructions is fine-grained data such as the instruction addresses of layer operator instructions and / or slice operator instructions, a breakpoint register can be set in the controller module of the AI processor, and the breakpoint location data can be stored in the breakpoint register. This way, when the controller module extracts instructions from the layer operator instruction list and / or slice operator instruction list, it can compare the instruction addresses of the extracted instructions with the breakpoint location data in the breakpoint register. If the breakpoint location data in the debugging instructions is fine-grained data such as interaction data with the storage module during task execution, an observation point register can be set, and the breakpoint location data can be stored in the observation point register. A comparison module can also be set at the interface of the storage module. This way, when the storage module writes or reads data, the comparison module can compare the interaction data at the storage module interface (i.e., the data being written or read) with the breakpoint location data in the breakpoint register. Of course, this is merely an illustrative example and should not be construed as limiting this example embodiment in any way.
[0047] In step S230, in response to the detection that the execution data is consistent with the breakpoint location data, the execution of the running task is paused to detect the execution status of the artificial intelligence processor.
[0048] In an exemplary embodiment, the data information or data address in the execution data can be compared with the data information or data address in the breakpoint location data. For example, the breakpoint location data can be the instruction address of a certain layer operator instruction. Correspondingly, the execution data can be the instruction address corresponding to the layer operator instruction generated when executing the task. If the instruction address in the breakpoint location data matches the instruction address in the execution data, it indicates that the breakpoint location has been found. At this time, a pause signal can be generated by a relevant module, such as the central processing unit in the controller module, to notify all modules in the artificial intelligence processor to stop working and maintain the current execution state for debugging. Of course, this is only an illustrative example and is not limited to this embodiment.
[0049] The following is a detailed description of steps S220 to S230.
[0050] In an exemplary embodiment, the artificial intelligence processor may include a controller module, which may be the central scheduling unit of the artificial intelligence processor. When a running task is executed, it may be broken down into multiple instructions with smaller computational loads. Therefore, the execution data of the running task may include a micro-instruction list. For example, the micro-instruction list may be a layer operator instruction list or a slice operator instruction list. This embodiment is not limited to this.
[0051] During the execution of a task, the task can be broken down into a list of micro-instructions, which is then input into the controller module for instruction scheduling. In this process, the controller module can compare the instruction addresses in the micro-instruction list with the breakpoint location data.
[0052] First, for artificial intelligence processors, the tasks they execute are generally based on artificial intelligence algorithm networks. The network structure of artificial intelligence algorithm networks can be referenced from... Figure 3 As shown, each circle can represent an algorithm layer. For example, an algorithm layer may include a convolution (Conv) algorithm layer 310, a max pooling (Maxpool) algorithm layer 320, etc.
[0053] The AI processor executes each algorithm layer sequentially and then outputs the result. For each algorithm layer, the input is an input feature image tensor, and the output is a feature image tensor. (Reference) Figure 4 As shown, the input to the algorithm layer can be an input feature image tensor 410 (e.g., the length, width, and height of the input feature image tensor 410 can be IW, IC, or IH), which is then convolved by a convolution kernel 420 (e.g., the length and width of the convolution kernel 420 are OC / IC, and the kernel size is K), and the output feature image tensor 430 (e.g., the length, width, and height of the output feature image tensor 430 can be OW, OC, or OH).
[0054] However, in actual execution, the granularity of an algorithm layer is too large, requiring it to be broken down into multiple smaller-granularity slice instructions. For example, each slice instruction could be a small input feature tensor convolved with different convolution kernels to generate the result. (Continue to refer to...) Figure 4 As shown, the data tensor 450 in the input feature image tensor 440 is processed by each convolution kernel 460, outputting a smaller feature image tensor 470, until all slicing instructions have been executed, resulting in the final feature image tensor 480. Of course, Figure 4 The examples provided are merely illustrative and are not intended to limit the scope of the embodiments described herein.
[0055] Therefore, in the actual execution process, for each layer of computation instructions, after entering the artificial intelligence processor, the instructions need to be decomposed into multiple slice instructions.
[0056] Figure 5 The illustration shows a schematic diagram of generation layer operator instructions and slicing operator instructions in an artificial intelligence network according to an exemplary embodiment of the present disclosure.
[0057] refer to Figure 5 As shown, each running task may include multiple algorithm layers 510, and each algorithm layer corresponds to a layer operator instruction list 520. The layer operator instruction list 520 may include multiple layer operator instructions, such as the convolution calculation layer instruction Conv, the max pooling layer instruction Maxpool, etc. Then, each layer operator instruction can be decomposed into a slice operator instruction list 530, which may include multiple slice operator instructions. For example, the convolution calculation layer instruction Conv can be decomposed into multiple slice operator instructions "Conv3_3arg0 arg1", and the max pooling layer instruction Maxpool can be decomposed into multiple slice operator instructions "Maxpool3_3arg0 arg1". Of course, this is only an illustrative example and should not impose any special limitations on this example embodiment.
[0058] In one exemplary embodiment, the microinstruction list can be a layer operator instruction list and a slice operator instruction list; it can be... Figure 6 The steps described in the document involve comparing the instruction addresses in the microinstruction list with the breakpoint location data through the controller module. (Refer to...) Figure 6 As shown, it can specifically include:
[0059] Step S610: Set a breakpoint register in the controller module based on the breakpoint location data, wherein the breakpoint location data includes the target instruction address;
[0060] Step S620: During the instruction fetching operation of the layer operator instruction list and the slice operator instruction list, the controller module compares the instruction addresses corresponding to the extracted layer operator instructions and / or slice operator instructions with the target instruction address.
[0061] The breakpoint register is a register used to store breakpoint location data and can be set in the controller module of the artificial intelligence processor.
[0062] The target instruction address refers to the instruction address corresponding to the breakpoint location data. For example, if the breakpoint location data can be a slice operator instruction, then the target instruction address can be the instruction address corresponding to that slice operator instruction.
[0063] Specifically, the controller module can fetch instructions from the layer operator instruction list and decode the extracted layer operator instructions to obtain multiple slice operator instruction lists; then, the controller module can fetch instructions from the slice operator instruction list and decode the extracted slice operator instructions to obtain the output results.
[0064] Continue to refer to Figure 5 As shown, the first input to the controller module is the layer operator instruction in the layer operator instruction list 520. After the layer operator instruction list 520 is input to the controller module, it needs to be fetched. Then, it goes through the decoding stage of the layer operator instruction. In this stage, a layer operator instruction is split into multiple slice operator instructions, namely the slice operator instruction list 530. Then, the instruction fetching unit performs the instruction fetching operation from the slice operator instruction list 530 obtained by splitting the layer operator instruction, and sends it to the decoding module corresponding to the slice operator instruction one by one. Finally, the slice operator instructions are executed one by one and the results are written back. In the whole process, two instruction fetching operations are required: the first is to fetch the layer operator instruction, and the second is to fetch the slice operator instruction.
[0065] Specifically, the controller module may include an instruction fetch unit and a central processing unit. When the controller module detects that the execution data is consistent with the breakpoint location data, it can send a pause signal to the instruction fetch unit, causing the instruction fetch unit to pause the instruction fetching operation and thus suspend the execution of the task. It can also send a pause signal to the central processing unit, causing the central processing unit to control all modules in the artificial intelligence processor to pause the operation and maintain the current execution state.
[0066] Figure 7 The illustration shows a schematic diagram of an implementation of breakpoint debugging functionality in an exemplary embodiment of the present disclosure.
[0067] refer to Figure 7 As shown, when entering debug mode, if the user needs to pause the execution of the artificial intelligence algorithm network using breakpoints and observe the current execution status in the artificial intelligence processor, a breakpoint register can be set through debug instructions. The breakpoint position data stored in the breakpoint register tells the artificial intelligence processor which instruction needs to be paused and the execution status observed. This instruction can be a large-granularity layer operator instruction or a small-granularity slice operator instruction.
[0068] During the instruction fetching operation via the instruction fetching unit, the controller module 710 compares the instruction addresses of layer operator instructions or slice operator instructions with the instruction addresses contained in the breakpoint location data pre-set in the breakpoint register 720. If a match is found, the controller module 710 notifies the instruction fetching unit to stop the instruction fetching operation and separately notifies the central processing unit 730 in the controller module 710 that there is a debugging requirement and the entire system needs to be paused. The central processing unit 730 then notifies all modules in the controller module 710 to maintain the current execution state and instructs the tensor calculation engine and vector calculation engine to pause their work. The entire system will then pause and wait for debugging.
[0069] In another exemplary embodiment, the artificial intelligence processor may further include a comparison module and a storage module, and the execution data may include interaction data with the storage module; wherein, the interaction data refers to data that has an interaction process with the storage module, such as data information written into the storage module and the corresponding data address, or data information read from the storage module and the corresponding data address.
[0070] Specifically, an observation point register can be set based on breakpoint location data, which may include target interaction data and the data address of the target interaction data. Then, the interaction data can be compared with the target interaction data, and the data address corresponding to the interaction data can be compared with the data address of the target interaction data through a comparison module.
[0071] If the comparison module detects that the execution data matches the breakpoint data, it can send a pause signal to the controller module in the AI processor, causing the controller module to control all modules in the AI processor to pause and maintain the current execution state.
[0072] Figure 8 The illustration shows a schematic diagram of an implementation of the observation point debugging function in an exemplary embodiment of the present disclosure.
[0073] refer to Figure 8 As shown, it is possible to Figure 1The AI processor 100 includes a comparison unit 850 and an observation point register 860. The observation point register 860 can be set using breakpoint location data included in the debugging instructions input by the user. A comparison unit 850 is also set at the interface of the storage module 130 to compare all data addresses and data information of the storage module during data interaction with the breakpoint location data in the observation point register 860. When the interaction data and data addresses of the storage module meet the breakpoint location data set by the user, the comparison unit 850 will send a pause signal to the controller module 140, informing the controller module 140 that the system needs to be paused.
[0074] Compared to traditional AI processor debugging schemes that require exporting all intermediate path data, which have a larger data granularity, the debugging scheme of this disclosure is more refined. It can not only debug large-granularity layer operator instructions and slice operator instructions, but also pause at breakpoints based on set instruction addresses during execution. It can also set special conditions during the data write-back to the storage module to view the internal execution status of the AI processor, making the debugging more efficient.
[0075] Of course, the debugging method in this disclosure can also be used. As needed, a condition register can be set at a fixed observation point and configured through software. When certain conditions are met, the condition register can stop the operation of the entire system, helping users to observe the internal state. This is also within the protection scope of this disclosure.
[0076] In summary, this exemplary embodiment can acquire breakpoint location data from debugging instructions. During the execution of a task by the AI processor, the execution data corresponding to the task is compared with the breakpoint location data. When the execution data matches the breakpoint location data, the task execution is paused, and the execution status of the AI processor is monitored. On one hand, pausing and debugging the AI processor using breakpoint location data from debugging instructions allows for finer-grained debugging, improving the flexibility of the debugging process and effectively increasing the debugging efficiency of the AI processor. On the other hand, pausing the task execution and observing the current execution status of the AI processor when the execution data matches the breakpoint location data eliminates the need to export all data paths from the AI processor before debugging, effectively reducing the workload during debugging and further improving the debugging efficiency of the AI processor.
[0077] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.
[0078] Further reference Figure 9 As shown, this example embodiment also provides a debugging device 900, which can be installed in an electronic device with an artificial intelligence processor, and may include a breakpoint location acquisition module 910, a data comparison module 920, and a pause debugging module 930. Wherein:
[0079] The breakpoint location acquisition module 910 is used to receive debugging instructions and acquire breakpoint location data in the debugging instructions;
[0080] The data comparison module 920 is used to execute the running task to be processed and compare the execution data corresponding to the running task with the breakpoint position data;
[0081] The pause debugging module 930 is used to pause the execution of the running task in response to the detection that the execution data is consistent with the breakpoint position data, so as to detect the execution status of the artificial intelligence processor.
[0082] In one exemplary embodiment, the artificial intelligence processor may include a controller module, and the execution data may include a list of microinstructions; the data comparison module 920 may be used for:
[0083] The controller module compares the instruction addresses in the microinstruction list with the breakpoint location data.
[0084] In one exemplary embodiment, the microinstruction list may include a layer operator instruction list and a slice operator instruction list; the data comparison module 920 may be used for:
[0085] A breakpoint register is set in the controller module based on the breakpoint location data, wherein the breakpoint location data includes the target instruction address;
[0086] During the instruction fetching operation on the layer operator instruction list and the slice operator instruction list, the controller module compares the instruction addresses corresponding to the extracted layer operator instructions and / or slice operator instructions with the target instruction address.
[0087] In one exemplary embodiment, the data comparison module 920 can be used to:
[0088] The controller module performs instruction fetching operations on the layer operator instruction list and decodes the extracted layer operator instructions to obtain multiple slice operator instruction lists.
[0089] The controller module performs instruction fetching operations on the slice operator instruction list and decodes the extracted slice operator instructions to obtain the output results.
[0090] In one exemplary embodiment, the controller module may include an instruction fetching unit and a central processing unit, and the pause debugging module 930 may be used for:
[0091] In response to the controller module detecting that the execution data matches the breakpoint position data, a pause signal is sent to the instruction fetching unit to cause the instruction fetching unit to pause the instruction fetching operation, thereby pausing the execution of the task; and
[0092] A pause signal is fed back to the central processing unit so that the central processing unit controls all modules in the artificial intelligence processor to pause operation and maintain the current execution state.
[0093] In an exemplary embodiment, the artificial intelligence processor may further include a comparison module and a storage module, and the execution data may include interaction data with the storage module; the data comparison module 920 may also be used for:
[0094] An observation point register is set based on the breakpoint location data, wherein the breakpoint location data includes the target interaction data and the data address of the target interaction data;
[0095] The comparison module compares the interactive data with the target interactive data and compares the data address corresponding to the interactive data with the data address of the target interactive data.
[0096] In one exemplary embodiment, the pause debugging module 930 can also be used for:
[0097] In response to the comparison module detecting that the execution data is consistent with the breakpoint location data, a pause signal is fed back to the controller module in the artificial intelligence processor, so that the controller module controls all modules in the artificial intelligence processor to pause operation and maintain the current execution state.
[0098] The specific details of each module in the above-mentioned device have been described in detail in the method section of the implementation. For any undisclosed details, please refer to the implementation content of the method section, and therefore will not be repeated here.
[0099] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."
[0100] An exemplary embodiment of this disclosure provides an electronic device for implementing a debugging method, which may be a terminal device, a server, or a server cluster. The electronic device includes at least a processor and a memory. The processor may be an artificial intelligence processor, and the memory is used to store executable instructions of the processor. The processor is configured to execute the debugging method by executing the executable instructions.
[0101] The following is based on Figure 10 Taking the electronic device 1000 as an example, the construction of the electronic device in this disclosure will be described by way of example. Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.
[0102] like Figure 10 As shown, the electronic device 1000 is presented in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, a bus 1030 connecting different system components (including storage unit 1020 and processing unit 1010), and a display unit 1040.
[0103] The storage unit 1020 stores program code, which can be executed by the processing unit 1010, causing the processing unit 1010 to execute the debugging method described in this specification.
[0104] Storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 1021 and / or a cache memory unit 1022, and may further include a read-only memory unit (ROM) 1023.
[0105] Storage unit 1020 may also include a program / utility 1024 having a set (at least one) program module 1025, such program module 1025 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.
[0106] Bus 1030 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.
[0107] Electronic device 1000 can also communicate with one or more external devices 1070 (e.g., sensor devices, Bluetooth devices, etc.), one or more devices that enable users to interact with electronic device 1000, and / or any device that enables electronic device 1000 to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication can be performed via input / output (I / O) interface 1050. Furthermore, electronic device 1000 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via network adapter 1060. As shown, network adapter 1060 communicates with other modules of electronic device 1000 via bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and sensor modules (e.g., gyroscope sensors, magnetometers, accelerometers, distance sensors, proximity sensors, etc.).
[0108] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0109] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.
[0110] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.
[0111] In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.
[0112] Furthermore, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java and C++, and conventional procedural programming languages such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).
[0113] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0114] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A debugging method, characterized in that, The method, executed via an electronic device equipped with an artificial intelligence processor, includes: Receive debugging instructions and obtain breakpoint location data from the debugging instructions; The system executes pending tasks and compares the execution data corresponding to the tasks with breakpoint location data. The AI processor includes a controller module, and the execution data includes a microinstruction list, which in turn includes a layer operator instruction list and a slice operator instruction list. If the execution data is found to be consistent with the breakpoint location data, the execution of the running task is paused to detect the execution status of the artificial intelligence processor; The step of comparing the execution data corresponding to the running task with the breakpoint location data includes: Based on the breakpoint location data, a breakpoint register is set in the controller module, the breakpoint location data including the target instruction address; during the instruction fetching operation of the layer operator instruction list and the slice operator instruction list, the controller module compares the instruction addresses corresponding to the extracted layer operator instructions and / or slice operator instructions with the target instruction address; wherein, the process of fetching instructions for the layer operator instruction list and the slice operator instruction list includes: fetching instructions from the layer operator instruction list through the controller module, and decoding the extracted layer operator instructions to obtain multiple slice operator instruction lists; fetching instructions from the slice operator instruction list through the controller module, and decoding the extracted slice operator instructions to obtain the output result.
2. The method according to claim 1, characterized in that, The controller module includes an instruction fetching unit and a central processing unit. The response, upon detecting that the execution data matches the breakpoint location data, pauses the execution of the task to detect the execution status of the artificial intelligence processor, including: In response to the controller module detecting that the execution data matches the breakpoint position data, a pause signal is sent to the instruction fetching unit to cause the instruction fetching unit to pause the instruction fetching operation, thereby pausing the execution of the task; and A pause signal is fed back to the central processing unit so that the central processing unit controls all modules in the artificial intelligence processor to pause operation and maintain the current execution state.
3. The method according to any one of claims 1 to 2, characterized in that, The artificial intelligence processor also includes a comparison module and a storage module, and the execution data includes interaction data with the storage module; The step of comparing the execution data corresponding to the running task with the breakpoint location data includes: An observation point register is set based on the breakpoint location data, wherein the breakpoint location data includes the target interaction data and the data address of the target interaction data; The comparison module compares the interactive data with the target interactive data and compares the data address corresponding to the interactive data with the data address of the target interactive data.
4. The method according to claim 3, characterized in that, The response detects that the execution data matches the breakpoint location data and pauses the execution of the task, including: In response to the comparison module detecting that the execution data is consistent with the breakpoint location data, a pause signal is fed back to the controller module in the artificial intelligence processor, so that the controller module controls all modules in the artificial intelligence processor to pause operation and maintain the current execution state.
5. A debugging device, characterized in that, The device, disposed in an electronic device having an artificial intelligence processor, includes: A breakpoint location acquisition module is used to receive debugging instructions and acquire breakpoint location data in the debugging instructions; The data comparison module is used to execute the running task to be processed and compare the execution data corresponding to the running task with the breakpoint position data; the artificial intelligence processor includes a controller module, the execution data includes a micro-instruction list, and the micro-instruction list includes a layer operator instruction list and a slice operator instruction list; The pause debugging module is used to pause the execution of the running task in response to the detection that the execution data is consistent with the breakpoint position data, so as to detect the execution status of the artificial intelligence processor; The step of comparing the execution data corresponding to the running task with the breakpoint location data includes: Based on the breakpoint location data, a breakpoint register is set in the controller module, the breakpoint location data including the target instruction address; during the instruction fetching operation of the layer operator instruction list and the slice operator instruction list, the controller module compares the instruction addresses corresponding to the extracted layer operator instructions and / or slice operator instructions with the target instruction address; wherein, the process of fetching instructions for the layer operator instruction list and the slice operator instruction list includes: fetching instructions from the layer operator instruction list through the controller module, and decoding the extracted layer operator instructions to obtain multiple slice operator instruction lists; fetching instructions from the slice operator instruction list through the controller module, and decoding the extracted slice operator instructions to obtain the output result.
6. A computer-readable medium having a computer program stored thereon, characterized in that, When the computer program is executed by an artificial intelligence processor, it implements the method as described in any one of claims 1 to 4.
7. An electronic device, characterized in that, include: Artificial intelligence processor; as well as A memory for storing the executable instructions of the artificial intelligence processor; The artificial intelligence processor is configured to execute the method of any one of claims 1 to 4 by executing the executable instructions.