Serial peripheral interface circuit and correction method for serial peripheral interface system

Abstract

A serial peripheral interface circuit includes a serial peripheral interface device, a first lead, a second lead, a first resistor, and a second resistor. The serial peripheral interface device has a master in slave out line, a master out slave in line, a serial clock line, and a slave select line. The first resistor connects the master in slave out line and the first lead. The second resistor connects the master out slave in line and the second lead.

Description

Technical Field

[0001] This invention relates to an interface circuit, and more particularly to a serial peripheral interface (SPI) circuit. Background Technology

[0002] The Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification primarily used for short-range communication in embedded systems. A typical SPI bus defines four logic signal lines: the serial clock (SCLK) line, the master-out-slave-in (MOSI) line, the master-in-slave-out (MISO) line, and the slave select (SS) line. These logic signal lines can be implemented by individually configuring wires on the circuit board.

[0003] However, these wires may short-circuit during the manufacturing process. In particular, when a short circuit occurs between the master-in / slave-out line and the master-out / slave-in line, the serial peripheral interface transmission voltage will be pulled down, which may cause logical results such as incorrect recognition by the serial peripheral interface device. Summary of the Invention

[0004] Therefore, the present invention provides a serial peripheral interface circuit and a calibration method for a serial peripheral interface system.

[0005] According to one or more embodiments of the present invention, a serial peripheral interface circuit includes a serial peripheral interface device, a first wire, a second wire, a first resistor, and a second resistor, wherein the serial peripheral interface device has a master-in-slave output line, a master-out-slave input line, a serial clock line, and a slave select line, the first resistor is connected to the master-in-slave output line and the first wire, and the second resistor is connected to the master-out-slave input line and the second wire.

[0006] According to one or more embodiments of the present invention, a calibration method for a serial peripheral interface system is disclosed. The disclosed calibration method may include: providing a serial peripheral interface system having a serial peripheral interface circuit, the serial peripheral interface circuit being defined by a serial peripheral interface device, a first wire, a second wire, a first resistor, a second resistor, and a slave device; the serial peripheral interface device having a master-in-slave-out line, a master-out-slave-in line, a serial clock line, and a slave select line; the first resistor connecting the master-in-slave-out line and the first wire; the second resistor connecting the master-out-slave-in line and the second wire; the slave device having a master-in-slave-out port, a master-out-slave-in port, a serial clock port, and a slave select port; the master-in-slave-out port... The serial peripheral interface device is connected to the master device via a first wire, a master-slave input / output port via a second wire, a serial clock port via a serial clock line, and a slave select port via a slave select line. When the slave device outputs a first logic high signal via the first wire, a first voltage is measured on the master-slave output line. When the master device outputs a second logic high signal via the master-slave input / output line, a second voltage is measured on the second wire. If the first voltage is not higher than the high-order input voltage of the master device or the second voltage is not higher than the high-order input voltage of the slave device, a third resistor replaces the first resistor, and a fourth resistor replaces the second resistor. It is worth noting that the resistance value of the third resistor is greater than that of the first resistor, and the resistance value of the fourth resistor is greater than that of the second resistor.

[0007] In view of the above, a serial peripheral interface circuit with replaceable resistors in the connection between the master input / slave output ports and the connection between the master output / slave input ports can provide correction for the transmission voltage on the connection. Even if the connection between the master input / slave output ports and the master output / slave input ports is short-circuited, the transmission voltage on the connection can be adjusted to reflect the correction logic to the serial peripheral interface device through appropriate resistors. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of a serial peripheral interface circuit according to an embodiment of the present invention.

[0009] Figure 2 This is a functional block diagram of a serial peripheral interface circuit according to another embodiment of the present invention.

[0010] Figure 3 This is a flowchart of a calibration method for a serial peripheral interface system according to an embodiment of the present invention.

[0011] [Explanation of Labels in the Attached Images]

[0012] 1,1': Serial peripheral interface circuit

[0013] 10,10': First serial peripheral interface device

[0014] 11: First conductor

[0015] 12: Second conductor

[0016] 13: Third conductor

[0017] 14: Fourth conductor

[0018] 15: Fifth conductor

[0019] 16: Sixth conductor

[0020] 20: Second Serial Peripheral Interface Device

[0021] 101: Main player enters, secondary player exits

[0022] 102: Main line out, secondary line in

[0023] 103: Serial clock line

[0024] 104: Subordinate Selection Line

[0025] L11, L12, L21, L22: Lead wires

[0026] P1: Master input / slave output port

[0027] P2: Master / Slave Input Port

[0028] P3: Serial clock port

[0029] P4: Subordinate Selection Port

[0030] R1: First resistor

[0031] R2: Second resistor

[0032] S301~S307: Steps Detailed Implementation

[0033] The following detailed description of the features and advantages of the present invention in the embodiments is sufficient to enable those skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the content, scope of protection, and drawings disclosed in this specification, those skilled in the art can easily understand the related objectives and advantages of the present invention. The following embodiments further illustrate the viewpoints of the present invention, but are not intended to limit the scope of the present invention in any way.

[0034] The methods and steps described herein may be executed by a processor, a programmable logic device, or an application-specific integrated circuit, but this invention is not limited thereto. For ease of explanation, the methods and steps described below are described as being executed by a processor.

[0035] Please refer to Figure 1This is a functional block diagram of a Serial Peripheral Interface (SPI) circuit according to an embodiment of the present invention. Figure 1 As shown, the serial peripheral interface circuit 1 may include a serial peripheral interface device 10, a first resistor R1, a second resistor R2, a first wire 11, and a second wire 12. The serial peripheral interface device 10 may have a master-in-slave-out (MISO) line 101, a master-out-slave-in (MOSI) line 102, a serial clock (SCLK) line 103, and a slave select (SS) line 104. More specifically, the serial peripheral interface device 10 may include a master-in-slave-out port P1, a master-out-slave-in port P2, a serial clock port P3, and a slave select port P4. The master-in-slave-out line 101 can be implemented by a wire extending from the master-in-slave-out port P1. The master-out-slave-in line 102 can be implemented by another wire extending from the master-out-slave-in port P2. The serial clock line 103 and slave select line 104 can be implemented using multiple wires extending from the serial clock port P3 and slave select port P4, respectively. A first resistor R1 can connect the master-slave output line 101 and the first wire 11. A second resistor R2 connects the master-slave input line 102 and the second wire 12. More specifically, the first resistor R1 can have two leads L11 and L12 respectively connected to the master-slave output line 101 and the first wire 11, while the second resistor R2 can have two leads L21 and L22 respectively connected to the master-slave input line 102 and the second wire 12. The first resistor R1 and the second resistor R2 can be zero-ohm resistors and can be interchangeable.

[0036] The first wire 11 can be further connected to the master input / slave output port of another serial peripheral interface device. In the following example, where the serial peripheral interface device 10 is referred to as the "first serial peripheral interface device," the other serial peripheral interface device is referred to as the "second serial peripheral interface device," and the second wire 12 can be further connected to the master output / slave input port of the second serial peripheral interface device. The first or second serial peripheral interface device can be a master device (e.g., a digital signal processor (DSP), microcontroller (MCU)), while others can be slave devices (e.g., electronically eraseable rewritable read-only memory (EEPROM)). The master input / slave output line 101, the first resistor R1, and the first wire 11 can form a first signal line. The master output / slave input line 102, the second resistor R2, and the second wire 12 can form a second signal line. The first serial peripheral interface device can perform data transmission with the second serial peripheral interface device through the first and second signal lines. More specifically, the data transmission can be half-duplex. In other words, valid data is simultaneously transmitted on only one of the first and second signal lines. The serial clock line 103 can be connected to the serial clock port of the second serial peripheral interface device, while the slave select line 104 can be connected to the slave select port of the second serial peripheral interface device. Data transmission via the serial clock line and slave select line is the same as existing data transmission via serial clock lines and slave select lines, and therefore will not be described in detail here. The serial peripheral interface circuit 1 and the second serial peripheral interface device can be mounted on the same circuit board, or they can be mounted on different circuit boards and interconnected via vias.

[0037] Please refer to Figure 2 This is a functional block diagram of a serial peripheral interface circuit according to another embodiment of the present invention. Figure 2 As shown, the serial peripheral interface circuit 1' may include a first serial peripheral interface device 10', a second serial peripheral interface device 20, and a master device 30. Each of the first serial peripheral interface device 10', the second serial peripheral interface device 20, and the master device 30 includes a master input / slave output port P1, a master output / slave input port P2, a serial clock port P3, and a slave selection port P4. More specifically, one of the first serial peripheral interface device 10' and the second serial peripheral interface device 20 may be a master device, while the other may be a slave device. For example, the first serial peripheral interface device 10' may be an electronically eraseable rewritable read-only memory (as a slave device), the second serial peripheral interface device 20 may be a digital signal processor (as a master device), and the master device 30 may be a microcontroller.

[0038] The serial peripheral interface circuit 1' may also include a first resistor R1, a second resistor R2, a first wire 11, and a second wire 12, which may be the same as... Figure 1The components included in the serial peripheral interface circuit 1. The first serial peripheral interface device 10' may have a master-in-slave output line 101, a master-out-slave input line 102, a serial clock line 103, and a slave select line 104, which may be the same as... Figure 1 The lines of the serial peripheral interface device 10. The connection between the master input / slave output ports P1 of the first serial peripheral interface device 10' and the second serial peripheral interface device 20, the connection between the master output / slave input ports P2 of the first serial peripheral interface device 10' and the second serial peripheral interface device 20, and the data transmission between the first serial peripheral interface device 10' and the second serial peripheral interface device 20 can be the same as described in the above embodiments. Figure 1 The connection and data transmission between the first serial peripheral interface device 10 and the second serial peripheral interface device 20 will not be described in detail here. Serial clock line 103 can be connected to the serial clock port P3 of the first serial peripheral interface device 10' and the second serial peripheral interface device 20, while slave select line 104 can be connected to the slave select port P4 of the first serial peripheral interface device 10' and the second serial peripheral interface device 20. Data transmission via serial clock line 103 and slave select line 104 is the same as data transmission via existing serial clock lines and slave select lines, and therefore its details will not be described here.

[0039] The serial peripheral interface circuit 1' may further include a third wire 13, a fourth wire 14, a fifth wire 15, and a sixth wire 16.

[0040] The third wire 13 can connect to the master-slave input / output line 101 and the master-slave input / output port P1 of the master device 30. The fourth wire 14 can connect to the master-slave output / in line 102 and the master-slave output / in port P2 of the master device 30. The fifth wire 15 can connect to the serial clock line 103 and the serial clock port P3 of the master device 30. The sixth wire 16 can connect to the slave select line 104 and the slave select port P4 of the master device 30. As described above, one of the first serial peripheral interface device 10' and the second serial peripheral interface device 20 can be a master device, and the other can be a slave device. The master device 30 can perform corresponding data reception on the slave device through the connection between the master device 30 and the master-slave input / output port P1 of the slave device. The master device 30 can perform corresponding data transmission on the slave device through the connection between the master device 30 and the master-slave output / in port P2 of the slave device. More specifically, the data transmission including the aforementioned data reception and transmission can be half-duplex.

[0041] In yet another embodiment, the serial peripheral interface circuit may be the same as the serial peripheral interface circuit 1', except for the connection of the third wire 13 and the fourth wire 14. More specifically in this embodiment, the third wire 13 may be connected to the first wire 11, and the fourth wire 14 may be connected to the second wire 12.

[0042] It should be noted that the main device 30, the third wire 13, the fourth wire 14, the fifth wire 15 and the sixth wire 16 are optional components.

[0043] By using replaceable resistors on the connections between the master input / slave output ports and between the master output / slave input ports, the serial peripheral interface circuitry can provide possible correction for the transmission voltage on the connections. More specifically, if the master input / slave output line and the master output / slave input line, or the first wire and the second wire, are short-circuited during the manufacturing process of the serial peripheral interface circuitry, the first and second resistors can be replaced with other resistors to adjust the corresponding voltages, thereby maintaining the proper logic level of all serial peripheral interface devices and minimizing transmission failures caused by incorrect logic levels.

[0044] Please refer to Figure 3 The flowchart discloses a calibration method for a serial peripheral interface system according to an embodiment of the present invention. Figure 3 As shown, the calibration method for a serial peripheral interface system may include step S301: providing a serial peripheral interface system including a serial peripheral interface circuit, wherein the serial peripheral interface circuit includes a master device, a first wire, a second wire, a first resistor, a second resistor, and a slave device. The master device has a master-in-slave-out line, a master-out-slave-in line, a serial clock line, and a slave select line. The first resistor is connected to the master-in-slave-out line and the first wire, and the second resistor is connected to the master-out-slave-in line and the second wire. The slave device includes a master-in-slave-out port, a master-out-slave-in port, a serial clock port, and a slave select port. The master-in-slave-out port is connected to the first wire, the master-out-slave-in port is connected to the second wire, the serial clock port is connected to the serial clock line, and the slave select port is connected to the slave select line. The disclosed calibration method may further include step S302: when the slave device outputs a first logic high signal through the first wire, measuring the first voltage on the master-in-slave-out line.

[0045] In step S303, the disclosed calibration method may include measuring a second voltage on a second conductor when the master device outputs a second logic high signal via a master-slave input line. The calibration method disclosed in step S304 may further include determining whether a first voltage is higher than the high-level input voltage (VIH) of the master device. In step S305, the same disclosed calibration method may include determining whether a second voltage is higher than the high-level input voltage of the slave device. In step S306, the disclosed method may include determining that either the determination result of steps S304 and S305 is negative. If yes, the calibration method may proceed to step S307 to replace the first resistor with a third resistor (whose resistance value is greater than that of the first resistor) and replace the second resistor with a fourth resistor (whose resistance value is greater than that of the second resistor). If no, the disclosed calibration method may end.

[0046] It should be noted that the order of steps S302 to S305 can be changed as long as step S304 is followed by step S302 and step S305 is followed by step S303.

[0047] In step S301, the serial peripheral interface system includes a serial peripheral interface circuit that can be accessed via... Figure 1 The serial peripheral interface circuit 1 connecting the slave device is used for implementation, and the serial peripheral interface device 10 in the serial peripheral interface circuit 1 can act as the master device. Steps S302 to S306 can be performed by an operator or by a calibration system including a voltage detector for performing steps S302 and S303, a processor for performing steps S304 to S306, and an output device for outputting the result of step S306. The positive result of step S306 (i.e., "yes") can indicate that the connection between the master-slave input line and the master-slave input line or the connection between the first wire and the second wire may be short-circuited. Step S307 can be performed to reduce the impact associated with the short-circuit connection. By replacing the first resistor with a third resistor and the second resistor with a fourth resistor, the first voltage and the second voltage can be pulled up, while the current of the logic high signal remains unchanged.

[0048] More specifically, after step S307, steps S302 to S306 can be executed again to confirm whether the first and second voltages are adjusted to the correct logic level. If these results are still negative, the third and fourth resistors can be replaced with other resistors. Furthermore, the correction method can be further enhanced after step S307 by determining whether the voltage on the master-slave output line is lower than the low-level input voltage (VIH) of the master device when the slave device outputs a logic low signal through the first wire, and whether the voltage on the second wire is lower than the low-level input voltage of the slave device when the master device outputs a logic low signal through the master-slave input line. If the voltage on either the first or second wire is lower than the low-level input voltage, the third and fourth resistors can be replaced with other resistors. Finally, the first and second resistors can be replaced with resistors that ensure the input voltages of all serial peripheral interface devices reflect the correct logic. The exact value of the resistor replacing the first and second resistors can be determined based on the short-circuit condition.

[0049] In another embodiment, the serial peripheral interface circuit in the serial peripheral interface system can be via Figure 2 The serial peripheral interface circuit 1' is used to implement this. In this embodiment, in addition to the steps S301 to S307 described above, the calibration method may further include several steps between steps S301 and S306. More specifically, the additional steps may include: measuring when the slave device outputs a first logic high signal. Figure 2The third voltage on the third conductor 13, and whether the third voltage is higher than Figure 2 The high-level input voltage of the main device 30. Therefore, the determination step in step S306 may further include the execution of these additional steps.

[0050] In view of the above, serial peripheral interface circuitry with replaceable resistors in the connections between master input / slave output ports and between master output / slave input ports can provide possible correction of the transmission voltage on the connection. Even in the event of a short-circuit connection, by replacing the initially set resistor with an appropriate resistor, the transmission voltage on the connection can be adjusted to reflect the correct logic.

Claims

1. A serial peripheral interface circuit, characterized in that, Include: A serial peripheral interface device has a master input / slave output line, a master output / slave input line, a serial clock line and a slave select line, wherein the serial peripheral interface device is a master device. First conductor; A second conductor; A first resistor is connected to the main input / slave output line and the first wire; A second resistor is connected to the main output / slave input line and the second wire; as well as A slave device includes a master-in / slave-out port, a master-out / slave-in port, a serial clock port, and a slave select port. The master-in / slave-out port is connected to a first conductor, the master-out / slave-in port is connected to a second conductor, the serial clock port is connected to the serial clock line, and the slave select port is connected to the slave select line. The serial peripheral interface circuit is used for calibration in the following manner: When the slave device outputs a first logic high signal through the first wire, a first voltage is measured on the master input-slave output line; When the master device outputs a second logic high signal through the master output slave input line, a second voltage is measured on the second wire; as well as When the first voltage is not higher than a high-level input voltage of the master device or the second voltage is not higher than a high-level input voltage of the slave device, the first resistor is replaced by a third resistor and the second resistor is replaced by a fourth resistor, wherein the resistance value of the third resistor is greater than the resistance value of the first resistor and the resistance value of the fourth resistor is greater than the resistance value of the second resistor.

2. The serial peripheral interface circuit as described in claim 1, characterized in that, The first resistor has two leads that are respectively connected to the main input / slave output line and the first conductor. The second resistor has two leads that are respectively connected to the main output / slave input line and the second conductor.

3. The serial peripheral interface circuit as described in claim 1, characterized in that, The first resistor and the second resistor are zero-ohm resistors.

4. The serial peripheral interface circuit as described in claim 1, characterized in that, It also includes another serial peripheral interface circuit, which includes a master input / slave output port and a master output / slave input port, wherein the master input / slave output port is connected to the first wire, and the master output / slave input port is connected to the second wire.

5. The serial peripheral interface circuit as described in claim 1, characterized in that, It also includes: A third conductor, connected to the main input / slave output line; and A fourth conductor is connected to the main output and slave input lines.

6. The serial peripheral interface circuit as described in claim 5, characterized in that, It further includes a main device, which includes a main input / slave output port and a main output / slave input port, wherein the main input / slave output port is connected to the third wire and the main output / slave input port is connected to the fourth wire.

7. The serial peripheral interface circuit as described in claim 1, characterized in that, It also includes: A third wire, connected to the first wire; and A fourth wire is connected to the second wire.

8. The serial peripheral interface circuit as described in claim 7, characterized in that, It further includes a main device, which includes a main input / slave output port and a main output / slave input port, wherein the main input / slave output port is connected to the third wire and the main output / slave input port is connected to the fourth wire.

9. The serial peripheral interface circuit as described in claim 1, characterized in that, The master input / slave output line, the first resistor, and the first wire form a first signal line, and the master output / slave input line, the second resistor, and the second wire form a second signal line. The serial peripheral interface device is used to perform half-duplex data transmission with another serial peripheral interface device through the first signal line and the second signal line.

10. A calibration method for a serial peripheral interface system, characterized in that, Include: A serial peripheral interface system is provided, comprising a serial peripheral interface circuit, wherein the serial peripheral interface circuit includes: A serial peripheral interface device has a master input / slave output line, a master output / slave input line, a serial clock line, and a slave select line; First conductor; A second conductor; A first resistor is connected to the main input / slave output line and the first wire; A second resistor is connected to the main output / slave input line and the second wire; as well as A slave device includes a master-in / slave-out port, a master-out / slave-in port, a serial clock port, and a slave select port, wherein the master-in / slave-out port is connected to a first wire, the master-out / slave-in port is connected to a second wire, the serial clock port is connected to the serial clock line, and the slave select port is connected to the slave select line. The serial peripheral interface device is the main device. When the slave device outputs a first logic high signal through the first wire, a first voltage is measured on the master input-slave output line; When the master device outputs a second logic high signal through the master output slave input line, a second voltage is measured on the second wire; as well as When the first voltage is not higher than a high-level input voltage of the master device or the second voltage is not higher than a high-level input voltage of the slave device, the first resistor is replaced by a third resistor and the second resistor is replaced by a fourth resistor, wherein the resistance value of the third resistor is greater than the resistance value of the first resistor and the resistance value of the fourth resistor is greater than the resistance value of the second resistor.

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