A gate-all-around silicon carbide device with a staircase trench structure and a method of manufacturing the same

Abstract

This invention discloses a gated silicon carbide device with a stepped trench structure and its manufacturing method. From bottom to top, it includes a drain, a drift region, and a P-well region, and further includes: a deep trench penetrating the P-well region, with its bottom located in the drift region; a shallow trench penetrating the P-well region and located on both sides of the deep trench; and a P-type field-limiting ring formed on the periphery of the bottom of the deep trench; P... + District and N + The device consists of P-well regions that are interconnected, forming shallow trenches on both sides; gates that are formed in the shallow trenches on both sides and are encased in oxide layers; field-limiting ring contact plugs that are formed in the middle region of the deep trenches, with oxide layers on both sides, their tops connected to the source and their bottoms connected to the P-type field-limiting rings; and sources that cover the device surface. The P-type field-limiting rings are connected to the source through field-limiting ring contact plugs to achieve equipotentiality with the source, thereby reducing the electric field in the gate oxide layers on both sides of the trench and confining the device depletion region outside the trench region on both sides under reverse bias.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, specifically to a gate silicon carbide device with a stepped trench structure and its manufacturing method. Background Technology

[0002] Compared to traditional silicon materials, silicon carbide (SiC) has three most significant characteristics: a large bandgap, a high critical breakdown field strength, and high thermal conductivity. Specifically, in terms of bandgap, 4H-type SiC is three times wider than silicon, enabling stable operation at higher temperatures (such as in automotive electronics). Regarding critical breakdown field strength, SiC can reach ten times that of silicon, allowing for the fabrication of high-voltage power devices with higher impurity concentrations and thinner drift layers, thus simultaneously achieving "high voltage withstand," "low on-resistance," and "high frequency." In terms of thermal conductivity, SiC can reach three times that of silicon, improving heat transfer capabilities, and this high thermal conductivity also facilitates the miniaturization of electronic components. Furthermore, the design and fabrication of SiCMOS are similar to those of silicon-based MOS, and its good compatibility makes it a viable alternative to silicon-based power devices.

[0003] SiC MOSFETs also have some issues, most of which are directly related to the gate oxide layer. During reverse bias, a high electric field exists at the gate oxide. To utilize the high breakdown capability of silicon carbide, the electric field at the gate oxide must be mitigated. Especially for trench-gate SiC MOSFETs, the electric field concentrates at the bottom of the gate trench, often leading to long-term reliability problems. Summary of the Invention

[0004] To address the aforementioned problems, this invention discloses a method for manufacturing a gated silicon carbide device with a stepped trench structure, comprising the following steps: in N... - A P-well region is formed at the top of the doped SiC substrate, and an N-well region is formed at the bottom. + The drain electrode is used as a drift region, and P-type electrodes are formed on both sides of the upper part of the P-well region. + The area, the middle area forms N + The area; forming deep trenches, the deep trenches penetrating the N + The deep trench is located in the drift region, encompassing the P-well region and the P-trap region. A P-type field-limiting ring is formed around the bottom of the deep trench. An oxide layer is formed to completely fill the deep trench and extend to cover the N-well regions on both sides. + District and P + The process involves: forming shallow trenches on both sides of the deep trench; forming an oxide layer on the bottom and sidewalls of the shallow trenches; forming a polysilicon layer in the shallow trenches to cover the oxide layer and fill the shallow trenches; forming an oxide layer to cover the device surface, followed by photolithography and etching to remove the oxide layer, exposing the N-silicon on both sides. + District and P +The surface of the trench is exposed, and the oxide layer in the middle region of the deep trench is etched away to expose the P-type field limiting ring, while retaining the oxide layers on both sides of the deep trench. A field limiting ring contact is formed in the deep trench, and the bottom of the field limiting ring contact is connected to the P-type field limiting ring. A source is formed on the device surface, and the source is connected to the top of the field limiting ring contact. The P-type field limiting ring is connected to the source through the field limiting ring contact to achieve equipotential with the source, thereby reducing the electric field in the gate oxide layer on both sides of the trench and confining the device depletion region outside the channel region on both sides of the trench under reverse bias.

[0005] In the method for manufacturing a gated silicon carbide device with a stepped trench structure of the present invention, the preferred step of forming a P-type field limiting ring located at the periphery of the bottom of the deep trench includes: depositing an oxide layer and etching back to form an ion implantation barrier layer on the sidewall of the deep trench; performing ion implantation to form a P-type field limiting ring at the periphery of the bottom of the deep trench; and then removing the oxide layer.

[0006] In the method for manufacturing a gated silicon carbide device with a stepped trench structure according to the present invention, preferably, the steps of forming the field limiting ring contact and the source electrode include: forming a metal to completely fill the trench and cover the device surface, using the metal layer filled in the trench as the field limiting ring contact, and using the metal layer covering the device surface as the source electrode.

[0007] This invention also discloses a gated silicon carbide device with a stepped trench structure, comprising, from bottom to top, a drain, a drift region, and a P-well region, and further comprising: a deep trench penetrating the P-well region and having its bottom located in the drift region; a shallow trench penetrating the P-well region and located on both sides of the deep trench; and a P-type field-limiting ring formed on the periphery of the bottom of the deep trench; P + District and N + The device consists of P-well regions that are interconnected, forming shallow trenches on both sides; gates formed in the shallow trenches on both sides and encased in oxide layers; field-limiting ring contact plugs formed in the middle region of the deep trenches, with oxide layers on both sides, their tops connected to the source and their bottoms connected to the P-type field-limiting rings; and a source covering the device surface. The P-type field-limiting rings are connected to the source via the field-limiting ring contact plugs to achieve equipotentiality with the source, thereby reducing the electric field in the gate oxide layers on both sides of the trenches and confining the device depletion region outside the trench regions on both sides under reverse bias. Attached Figure Description

[0008] Figure 1 This is a flowchart of a method for manufacturing a gated silicon carbide device with a stepped trench structure.

[0009] Figures 2 to 13 This is a schematic diagram of the various stages of the manufacturing process of a gated silicon carbide device with a stepped trench structure. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0011] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0012] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0013] Figure 1 This is a flowchart of a method for manufacturing a silicon carbide device with a stepped trench structure. (Example:) Figure 1 As shown, the method for manufacturing a gated silicon carbide device with a stepped trench structure includes the following steps:

[0014] Step S1: Ion implantation is performed on N-type nanoparticles using photolithography. - A P-well region 101 is formed on the upper part of the doped epitaxial SiC substrate, and an N-well region is formed on the bottom. + Drain 102, with the remaining area serving as drift region 100. P-type P-wells are formed on both sides of the upper part of P-well region 101 via photolithography. + Zone 103, and the area located in the middle and on both sides of P + N adjacent to zone 103 + Section 104, the resulting structure is as follows Figure 2 As shown.

[0015] Step S2: Next, a first oxide layer 105 is deposited to cover the device surface. The deep trench region is defined by photolithography, and the first oxide layer 105 and N are etched. + Region 104, P-well region 101, and drift region 100 form a deep trench. The deep trench penetrates the N-well. + Region 104, P-well region 101, the bottom of the deep trench is located in drift region 100, the resulting structure is as follows Figure 3 As shown.

[0016] Step S3: Then, the first oxide layer 105 is deposited and etched back, so that the first oxide layer 105 covers the P on the sidewalls and both sides of the deep trench. + Zones 103 and N + Region 104 forms a sidewall and ion implantation barrier layer, while exposing the drift region 100 at the bottom of the deep trench. Ion implantation is performed to form a buried P-type field confinement ring 106 at the bottom of the deep trench through self-alignment, resulting in a structure as shown in the image. Figure 4 As shown. Afterwards, all oxide layers were removed, and finally, the implanted ions were activated by annealing at high temperature, resulting in the structure shown. Figure 5 As shown.

[0017] Step S4: Form a second oxide layer 107, completely filling the deep trench and extending to cover the P on both sides of the deep trench. + Zones 103 and N + Section 104, the resulting structure is as follows Figure 6 As shown.

[0018] Step S5: Perform photolithography and etching to remove N. + The portion of the second oxide layer 107 above zone 104 causes part of the N adjacent to the sidewalls of the deep trench to be exposed. + The upper surface of zone 104 is exposed, and the resulting structure is as follows: Figure 7 As shown. The SiC substrate is etched further to form two shallow trenches on either side of the deep trench, allowing them to penetrate the N-type substrate. + Region 104, P-well region 101, the resulting structure is as follows Figure 8 As shown.

[0019] Step S6: Perform dry oxygen oxidation to form a third oxide layer 108 at the bottom and sidewalls of the shallow trench, resulting in the structure shown below. Figure 9 As shown. A polysilicon layer 109 is deposited to cover the third oxide layer 108 and completely fill the shallow trench. Then, part of the polysilicon layer 109 is etched back, leaving only the polysilicon layer 109 within the shallow trench, so that the upper surface of the polysilicon layer 109 is flush with the upper surface of the second oxide layer 107. The resulting structure is shown. Figure 10 As shown. A fourth oxide layer 110 is deposited to cover the device surface, resulting in the structure shown. Figure 11 As shown.

[0020] Step S7: Photolithography defines the metal filling region, and the fourth oxide layer 110 is etched to make the P on both sides of the shallow trench... + Zone 103 surface and N + The surface of region 104 is exposed, and the buried P-type field-limiting ring 106 in the middle region of the bottom of the deep trench is exposed, while the second oxide layer 107 on both sides of the deep trench is retained. This forms isolation sidewalls on the sidewalls of the polysilicon layers 109 on both sides, creating a gate structure, as shown in the figure. Figure 12 As shown.

[0021] Step S8: Form a metal layer 111, ensuring that the metal layer 111 completely fills the deep trench and covers the device surface, resulting in the structure shown below. Figure 13 As shown, the metal layer filling the deep trench serves as the field limiting ring contact, and the metal layer covering the device surface serves as the source. The P-type field limiting ring 106 achieves equipotential with the source through the field limiting ring contact.

[0022] like Figure 13 As shown, the gated silicon carbide device with a stepped trench structure includes, from bottom to top, a drain 102, a drift region 100, and a P-well region 101; it also includes a deep trench that penetrates the P-well region 101 and has its bottom located in the drift region 100; and shallow trenches that penetrate the P-well region 101 and are located on both sides of the deep trench. The depth of the deep trench is greater than the depth of the shallow trench. A P-type field-limiting ring 106 is formed on the periphery of the bottom of the deep trench; P + Zone 103 and N + Regions 104 are interconnected, forming P-well regions 101 on both sides of a shallow trench. Gate 108 is formed in the shallow trenches on both sides and is encased in an oxide layer. Field limiting ring contact plugs are formed in the middle region of the deep trench, with oxide layers formed on both sides. Their tops are connected to the source and their bottoms are connected to the P-type field limiting ring 106; the source covers the device surface.

[0023] By placing a P-type field limiting ring on the periphery of the deep trench bottom and connecting the P-type field limiting ring to the source through a field limiting ring contact, equipotentiality with the source is achieved. This significantly reduces the electric field near the gate oxide layers on both sides of the device under high reverse bias voltage, improving device reliability. In other words, the buried P-type field limiting ring is connected to the source potential through the field limiting ring contact, confining the device's depletion region outside the channel regions on both sides under reverse bias. Simultaneously, this structure also reduces Miller capacitance, improves the device's switching speed, and effectively reduces switching losses.

[0024] Furthermore, in this stepped trench structure silicon carbide device, the P-type field limiting ring is located only at the bottom of the deep trench. The distribution of the P-type field limiting ring is controlled by the width of the deep trench and self-aligned injection, effectively reducing the area of ​​the P-type field limiting ring. This improves device reliability while minimizing damage to the on-resistance. Moreover, the depth of the deep trench can be substantial, extending into the deep drift region. This confines the high electric field under reverse breakdown voltage conditions to the deep drift region, further reducing the on-resistance.

[0025] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a silicon carbide device with a stepped trench structure, characterized in that, Includes the following steps: In N - The upper part of the doped SiC substrate forms a P well region, and the bottom forms an N + Drain, and the other region is a drift region; P is formed on both sides of the upper part of the P-well region. + The area, the middle area forms N + district; A deep trench is formed, the deep trench penetrating the N + The deep trench is located in the drift region, including the P-well region and the P-trap region. A P-shaped field confinement ring is formed on the outer periphery of the bottom of the deep trench; An oxide layer is formed, which completes the filling of the deep trench and extends to cover the N on both sides. + District and P + district; Shallow trenches are formed on both sides of the deep trench, and the depth of the deep trench is greater than the depth of the shallow trench. An oxide layer is formed at the bottom and sidewalls of the shallow trench, and a polycrystalline silicon layer is formed in the shallow trench to cover the oxide layer and fill the shallow trench. An oxide layer is formed to cover the device surface, and then the oxide layer is removed by photolithography and etching, exposing the N₂ on both sides. + District and P + The surface of the area is exposed, and the oxide layer in the middle area of ​​the deep trench is etched away to expose the P-type field confinement ring, while retaining the oxide layer on both sides of the deep trench. A field limiting ring contact plug is formed in a deep trench, and the bottom of the field limiting ring contact plug is connected to the P-type field limiting ring; A source electrode is formed on the surface of the device, and the source electrode is connected to the top of the field limiting ring contact pin; The P-type field limiting ring is connected to the source electrode through the field limiting ring contact bolt to achieve the same potential as the source electrode, thereby reducing the electric field in the gate oxide layer on both sides of the trench and confining the device depletion region outside the channel region on both sides of the trench under reverse bias.

2. The method for manufacturing a silicon carbide device with a stepped trench structure according to claim 1, characterized in that, The steps for forming a P-type field confinement ring located on the outer periphery of the bottom of the deep trench include: An oxide layer is deposited and etched back to form an ion implantation barrier layer on the sidewall of the deep trench; Ion implantation is performed to form a P-type field confinement ring around the bottom periphery of the deep trench; The oxide layer is then removed.

3. The method for manufacturing a silicon carbide device with a stepped trench structure according to claim 1, characterized in that, The steps of forming the field limiting ring contact and the source electrode include: A metal layer is formed to completely fill the trench and cover the device surface. The metal layer filling the trench serves as the field limiting ring contact, and the metal layer covering the device surface serves as the source.

4. A silicon carbide gate device with a stepped trench structure, characterized in that, From bottom to top, it includes the drain, drift region, and P-well region. Also includes: A deep trench that penetrates the P-trap region and has its bottom located in the drift region; Shallow trenches penetrate the P-well region and are located on both sides of deep trenches, wherein the depth of deep trenches is greater than the depth of shallow trenches. P-type field confinement rings are formed on the periphery of the bottom of the deep trench; P + District and N + The regions are connected to each other, forming P-well regions on both sides of the shallow trench; The gate is formed in shallow trenches on both sides and is covered by an oxide layer; The field limiting ring contact plug is formed in the middle region of the deep trench, with oxide layers formed on both sides. Its top is connected to the source electrode and its bottom is connected to the P-type field limiting ring. The source electrode, which covers the surface of the device. The P-type field limiting ring is connected to the source electrode through the field limiting ring contact bolt to achieve the same potential as the source electrode, thereby reducing the electric field in the gate oxide layer on both sides of the trench and confining the device depletion region outside the channel region on both sides of the trench under reverse bias.

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