High voltage flip chip light emitting diode and method of fabricating the same

Abstract

The application provides a high-voltage flip chip light emitting diode and a preparation method thereof. The high-voltage flip chip light emitting diode is electrically connected with the second semiconductor layer of the first side wall and the first semiconductor layer of the second side wall through the metal electrode, so that only one first electrode (i.e. one opening) is needed to realize the conduction of the high-voltage flip chip light emitting diode, the number of openings is reduced, the light emitting area of the light emitting unit occupied by the opening is reduced, and the light efficiency of the high-voltage flip chip light emitting diode is improved. The upper surfaces of the first electrode, the metal electrode, the current spreading layer and the mirror structure are flush through the planarization treatment, the risk of fracture of the second dielectric layer is reduced, and the reliability of the high-voltage flip chip light emitting diode is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light-emitting device. It has photoelectric properties such as low power consumption, small size, long life, good stability, fast response, and stable emission wavelength, making LEDs widely used in lighting, home appliances, displays, indicator lights and other fields.

[0003] In recent years, to improve the lighting quality and integration of light-emitting diodes (LEDs), luminous efficacy per unit area has become an important indicator for evaluating LEDs. Compared to traditional GaN (gallium nitride)-based conventional LEDs, high-voltage flip-chip LEDs have become a hot product to meet this development trend due to their excellent heat dissipation and current expansion capabilities. Based on this, high-voltage flip-chip LEDs, constructed by connecting high-voltage flip-chip LEDs in series, maintain high luminous efficacy per unit area while significantly reducing driver costs, making them the future trend in LED development.

[0004] Currently, high-voltage flip-chip LEDs use metal electrodes to bridge and interconnect different light-emitting units. In this interconnection method, the metal electrodes are thin layers of uniform thickness, resulting in relatively thin electrodes. Furthermore, the isolation trenches are vertical trenches with numerous and steep steps, making the thin metal electrodes prone to breakage at these steps. This can lead to reliability failures (e.g., dead LEDs) and requires sophisticated manufacturing processes, resulting in low yields. Additionally, the light absorption by the filling material in the isolation trenches (i.e., the material of the metal electrodes) reduces the luminous efficiency of the high-voltage flip-chip LED. Moreover, for GaN-based LEDs, since their substrates are generally non-conductive, multiple vias need to be etched and filled to achieve electrical connections. However, these vias occupy the light-emitting area of ​​the light-emitting units, thus reducing the brightness of the high-voltage flip-chip LED.

[0005] Therefore, providing a high-voltage flip-chip light-emitting diode that can improve the metal interconnection between different light-emitting units, thereby improving process stability, yield and reliability, as well as the scalability of the layout design and the light extraction efficiency of the high-voltage flip-chip light-emitting diode, has become an important technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] One of the objectives of this invention is to provide a high-voltage flip-chip light-emitting diode and its fabrication method, which can improve a series of problems caused by metal electrodes between different light-emitting units of the high-voltage flip-chip light-emitting diode, such as brightness loss, poor process stability, low yield, and high reliability risk.

[0007] To address the above problems, the present invention provides a high-voltage flip-chip light-emitting diode, comprising:

[0008] Substrate;

[0009] An epitaxial layer is located on the substrate, and the epitaxial layer comprises, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer;

[0010] An isolation trench is located in the epitaxial layer. The isolation trench penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units. The bottom of the isolation trench exposes the substrate. The isolation trench has a shape that is larger at the top and smaller at the bottom. The isolation trench includes a first sidewall and a second sidewall that are disposed opposite to each other.

[0011] A current spreading layer covers a portion of the upper surface of the second semiconductor layer and also covers a portion of the second semiconductor layer on the first sidewall, and the current spreading layer is spaced apart from the second sidewall.

[0012] A reflective mirror structure, wherein the reflective mirror structure covers a first semiconductor layer and a light-emitting layer on the first sidewall, and further covers a light-emitting layer and a second semiconductor layer on the second sidewall; and

[0013] A metal electrode fills the isolation trench and electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

[0014] Optionally, the angle between the first sidewall and the plane containing the substrate surface is 35° to 55°, and the angle between the second sidewall and the plane containing the substrate surface is 35° to 55°.

[0015] Optionally, the number of isolation trenches is at least one, and the isolation trenches divide the epitaxial layer into m*n arrayed light-emitting units. The total number of light-emitting units is k = m*n. Each light-emitting unit is sequentially arranged from the N-type pad to the P-type pad as the first light-emitting unit to the k-th light-emitting unit, where m ≥ 1, n ≥ 2, and m and n are both positive integers.

[0016] Furthermore, the epitaxial layer also includes an opening located in the first light-emitting unit, and the opening penetrates the second semiconductor layer and the light-emitting layer, with the bottom of the opening exposing the first semiconductor layer.

[0017] Furthermore, the current spreading layer is spaced apart from the opening of the aperture, such that the opening size of the current spreading layer at the opening of the aperture is larger than the opening size of the aperture.

[0018] Furthermore, the first sidewall is the sidewall closer to the previous light-emitting unit, and the second sidewall is the sidewall farther away from the previous light-emitting unit.

[0019] Furthermore, the mirror structure also covers the sidewalls of the opening and the upper surface of the second semiconductor layer exposed by the current spreading layer.

[0020] Furthermore, it also includes a first dielectric layer, which is located on the sidewall of the opening, on the first semiconductor layer and the light-emitting layer of the first sidewall, on the light-emitting layer and the second semiconductor layer on the second sidewall, and on the upper surface of the second semiconductor layer exposed by the current spreading layer, and the mirror structure is located on the first dielectric layer.

[0021] Furthermore, it also includes a first electrode that fills the opening, and the first electrode is separated from the epitaxial layer exposed on the sidewall of the opening by the mirror structure.

[0022] Furthermore, the upper surfaces of the first electrode, the metal electrode, the mirror structure, and the current spreading layer are flush.

[0023] Furthermore, it also includes a second dielectric layer, which covers the first electrode, the metal electrode, the mirror structure, the current spreading layer, and the exposed surface of the second semiconductor layer. A first through-hole and a second through-hole are formed in the second dielectric layer. The first through-hole penetrates the second dielectric layer and exposes the first electrode at the bottom of the trench. The second through-hole penetrates the second dielectric layer and exposes the current spreading layer of the k-th light-emitting unit at the bottom of the trench.

[0024] Furthermore, both the mirror structure and the second dielectric layer are distributed Bragg mirrors.

[0025] Furthermore, it also includes a first pad and a second pad, wherein the first pad fills the first via and covers a portion of the second dielectric layer near the opening of the first via as the N-type pad, and the second pad fills the second via and covers a portion of the second dielectric layer near the opening of the second via as the P-type pad.

[0026] On the other hand, the present invention provides a method for fabricating a high-voltage flip-chip light-emitting diode, comprising the following steps:

[0027] An epitaxial layer is formed on a substrate, the epitaxial layer comprising, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer;

[0028] An isolation trench is formed in the epitaxial layer, the isolation trench penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units, and the bottom of the isolation trench exposes the substrate. The isolation trench has a shape that is larger at the top and smaller at the bottom, and the isolation trench includes a first sidewall and a second sidewall disposed opposite to each other.

[0029] A current spreading layer is formed, which covers a portion of the upper surface of the second semiconductor layer and also covers a portion of the second semiconductor layer on the first sidewall, and the current spreading layer is spaced apart from the second sidewall.

[0030] A reflective mirror structure is formed, the reflective mirror structure covering a first semiconductor layer and a light-emitting layer on the first sidewall, and further covering a light-emitting layer and a second semiconductor layer on the second sidewall; and

[0031] A metal electrode is formed, which fills the isolation trench and electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

[0032] Optionally, the angle between the first sidewall and the plane containing the substrate surface is 35° to 55°, and the angle between the second sidewall and the plane containing the substrate surface is 35° to 55°.

[0033] Optionally, the number of isolation trenches is at least one, and the isolation trenches divide the epitaxial layer into m*n arrayed light-emitting units. The total number of light-emitting units is k = m*n. Each light-emitting unit is sequentially arranged from the N-type pad to the P-type pad as the first light-emitting unit to the k-th light-emitting unit, where m ≥ 1, n ≥ 2, and m and n are both positive integers.

[0034] Furthermore, an opening is formed in the epitaxial layer, the opening is located in the first light-emitting unit, and the opening penetrates the second semiconductor layer and the light-emitting layer, with the bottom of the opening exposing the first semiconductor layer.

[0035] Furthermore, the current spreading layer is spaced apart from the opening of the aperture, such that the opening size of the current spreading layer at the opening of the aperture is larger than the opening size of the aperture.

[0036] Furthermore, the first sidewall is the sidewall closer to the previous light-emitting unit, and the second sidewall is the sidewall farther away from the previous light-emitting unit.

[0037] Furthermore, the mirror structure also covers the sidewalls of the opening and the upper surface of the second semiconductor layer exposed by the current spreading layer.

[0038] Furthermore, before forming the mirror structure, the following steps are also included:

[0039] A first dielectric layer is formed, which is located on the sidewall of the opening, on the first semiconductor layer and the light-emitting layer of the first sidewall, on the light-emitting layer and the second semiconductor layer on the second sidewall, and on the upper surface of the second semiconductor layer exposed by the current spreading layer, and the mirror structure is located on the first dielectric layer.

[0040] Furthermore, a first electrode is formed simultaneously with the metal electrode, the first electrode fills the opening, and the first electrode is separated from the epitaxial layer exposed on the sidewall of the opening by the mirror structure.

[0041] Furthermore, the upper surfaces of the first electrode, the metal electrode, the mirror structure, and the current spreading layer are flush.

[0042] Furthermore, after forming the metal electrode, the process also includes:

[0043] A second dielectric layer is formed, which covers the first electrode, the metal electrode, the mirror structure, the current spreading layer, and the exposed surface of the second semiconductor layer. A first via and a second via are formed in the second dielectric layer. The first via penetrates the second dielectric layer and exposes the first electrode at the bottom of the trench. The second via penetrates the second dielectric layer and exposes the current spreading layer of the k-th light-emitting unit at the bottom of the trench.

[0044] Furthermore, both the mirror structure and the second dielectric layer are distributed Bragg mirrors.

[0045] Furthermore, after forming the second dielectric layer, the process also includes:

[0046] A first pad and a second pad are formed. The first pad fills the first via and covers a portion of the second dielectric layer near the opening of the first via to serve as the N-type pad. The second pad fills the second via and covers a portion of the second dielectric layer near the opening of the second via to serve as the P-type pad.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] 1. Compared with the existing technology of covering the connection of metal electrodes, the present invention reduces the risk of metal electrode breakage by filling the isolation trench with the metal electrode, while increasing the thickness of the metal electrode, thereby improving the heat dissipation capacity of the high voltage flip-chip LED, enhancing the stability of the high voltage flip-chip LED under high temperature and high current environment, and thus improving the reliability of the high voltage flip-chip LED.

[0049] 2. Compared to the existing technology where the isolation trench has a deep step that makes the second dielectric layer prone to breakage, the present invention makes the upper surfaces of the first electrode, metal electrode, current spreading layer and reflector structure flush through planarization treatment, which reduces the risk of second dielectric layer breakage and improves the reliability of high voltage flip-chip light-emitting diodes.

[0050] 3. The second semiconductor layer of the first sidewall and the first semiconductor layer of the second sidewall are electrically connected through the metal electrode, so that adjacent light-emitting units are connected in series in the isolation trench. This reduces the number of first electrodes, so that only one first electrode (i.e., one opening) is needed to enable the high-voltage flip-chip light-emitting diode to conduct. This reduces the number of openings, thereby reducing the light-emitting area of ​​the light-emitting unit occupied by the openings and improving the luminous efficiency of the high-voltage flip-chip light-emitting diode.

[0051] 4. By placing the opening in the first light-emitting unit, the central area of ​​the high-voltage flip-chip light-emitting diode is avoided. In this way, there is no opening in the central area that the ejector pin will press during the subsequent packaging process, thereby preventing failure caused by the ejector pin cracking during the packaging process.

[0052] 5. The metal electrode and the mirror structure in the isolation trench form an all-around mirror, and the first electrode and the mirror structure in the opening form an all-around mirror, which increases the reflectivity of the high-voltage flip-chip LED, reduces the light absorption of the metal in the isolation trench and the opening, and improves the brightness of the high-voltage flip-chip LED.

[0053] 6. Compared with the traditional three-stage metal interconnect process, the present invention only requires the first pad and the first electrode to be electrically connected, realizing a two-stage metal interconnect process and reducing the process flow. Attached Figure Description

[0054] Figure 1a This is a top view of an embodiment of the present invention after an epitaxial layer has been formed on a substrate;

[0055] Figure 1b for Figure 1a Cross-sectional view along line AA;

[0056] Figure 2a This is a top view of an embodiment of the present invention when forming an isolation trench;

[0057] Figure 2b for Figure 2a Cross-sectional view along line AA;

[0058] Figure 3a This is a top view of an embodiment of the present invention when an opening is formed;

[0059] Figure 3b for Figure 3a Cross-sectional view along line AA;

[0060] Figure 4a This is a top view of an embodiment of the present invention when a current spreading layer is formed;

[0061] Figure 4b for Figure 4a Cross-sectional view along line AA;

[0062] Figure 5a This is a top view of an embodiment of the present invention showing the formation of a first dielectric layer on an isolation trench between two electrically connected light-emitting units;

[0063] Figure 5b for Figure 5a Cross-sectional view along line AA;

[0064] Figure 6a This is a top view of an embodiment of the present invention when the first electrode is formed;

[0065] Figure 6b for Figure 6a Cross-sectional view along line AA;

[0066] Figure 6c After flattening Figure 6a Cross-sectional view along line AA;

[0067] Figure 7 This is a cross-sectional schematic diagram of the formation of the first through hole and the second through hole according to an embodiment of the present invention;

[0068] Figure 8 A cross-sectional schematic diagram of a high-voltage flip-chip light-emitting diode provided in an embodiment of the present invention;

[0069] Figure 9a A top view of a high-voltage flip-chip light-emitting diode provided in another embodiment of the present invention;

[0070] Figure 9b for Figure 9a Cross-sectional view along line BB;

[0071] Figure 10 This is a schematic flowchart illustrating a method for fabricating a high-voltage flip-chip light-emitting diode according to an embodiment of the present invention.

[0072] Explanation of reference numerals in the attached figures:

[0073] 11-Substrate; 12-First semiconductor layer; 13-Light-emitting layer; 14-Second semiconductor layer; 15-Isolation trench; 151-First sidewall; 152-Second sidewall; 16-Cut track; 17-Opening; 20-Current spreading layer; 30-Mirror structure; 41-First electrode; 42-Metal electrode; 50-Second dielectric layer; 51-First via; 52-Second via; 61-First pad; 62-Second pad. Detailed Implementation

[0074] The following will provide a more detailed description of a high-voltage flip-chip light-emitting diode and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0075] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0076] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0077] It should be noted that, in this embodiment, when photolithography and plasma etching (ICP) are used sequentially, the detailed process of photolithography is as follows: a patterned photoresist layer is formed through processes such as coating, exposure, and development; the plasma etching process uses the patterned photoresist layer as a mask to dry-etch away the exposed material layer to be etched. This embodiment defines... Figure 1b In the direction perpendicular to the substrate surface, the side of the epitaxial layer furthest from the substrate is designated "upper," and the side closest to the substrate is designated "lower." The components of the epitaxial layer are also defined (in words such as...). Figure 1b (Taking the second semiconductor layer as an example) The surface on the side away from the substrate is called the "top surface".

[0078] Figure 10 This is a schematic flowchart illustrating a method for fabricating a high-voltage flip-chip light-emitting diode (LED) according to this embodiment. Figure 10As shown, this embodiment provides a method for fabricating a high-voltage flip-chip light-emitting diode, including the following steps:

[0079] Step S1: An epitaxial layer is formed on the substrate, wherein the epitaxial layer comprises, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer;

[0080] Step S2: An isolation trench is formed in the epitaxial layer. The isolation trench penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units. The bottom of the isolation trench exposes the substrate. The isolation trench has a shape that is larger at the top and smaller at the bottom. The isolation trench includes a first sidewall and a second sidewall that are disposed opposite to each other.

[0081] Step S3: Form a current spreading layer, which covers a portion of the upper surface of the second semiconductor layer and also covers a portion of the second semiconductor layer on the first sidewall, and the current spreading layer is spaced apart from the second sidewall;

[0082] Step S4: Form a reflective mirror structure, the reflective mirror structure covering the first semiconductor layer and the light-emitting layer of the first sidewall, and also covering the light-emitting layer and the second semiconductor layer of the second sidewall; and

[0083] Step S5: Form a metal electrode that fills the isolation trench and electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

[0084] The following describes in detail, with reference to the accompanying drawings, a method for fabricating a high-voltage flip-chip light-emitting diode provided in this embodiment.

[0085] like Figures 1a-1b As shown, step S1 is first performed to form an epitaxial layer on the substrate 11. The epitaxial layer includes a first semiconductor layer 12, a light-emitting layer 13, and a second semiconductor layer 14 from bottom to top.

[0086] This step specifically includes the following steps:

[0087] First, a substrate 11 is provided, which may be selected from sapphire (Al2O3), silicon (Si), silicon carbide (SiC), etc. In this embodiment, the material of the substrate 11 is preferably a high-transmittance sapphire substrate, and further, the substrate 11 is a patterned sapphire substrate (PSS).

[0088] Next, an epitaxial layer is grown on the substrate 11 using metal-organic chemical vapor deposition (MOCVD). Specifically, a first semiconductor layer 12, a light-emitting layer 13, and a second semiconductor layer 14 are sequentially grown on the substrate 11 using MOCVD.

[0089] The material of the epitaxial layer is selected from any one or a combination of AlN, GaN, AlGaN, InGaN, and AlInGaN. More specifically, the main material of the epitaxial layer is GaN. More specifically, the epitaxial layer can be formed on the substrate 11 by any existing known method such as vapor deposition or evaporation.

[0090] The first semiconductor layer 12 is an N-type semiconductor layer located on the substrate 11, and the material of the first semiconductor layer 12 is, for example, GaN. The light-emitting layer 13 is located on the first semiconductor layer 12, and the light-emitting layer 13 is constructed as a multi-period quantum well layer, and the material of the quantum well layer is, for example, a GaN / InGaN superlattice multilayer structure. The second semiconductor layer 14 is a P-type semiconductor layer located on the light-emitting layer 13, and the material of the second semiconductor layer 14 is also, for example, GaN.

[0091] In this embodiment, the first semiconductor layer 12 is doped with Si ions, and the second semiconductor layer 14 is doped with Mg ions, but is not limited thereto.

[0092] like Figures 2a-2b , Figures 3a-3b as well as Figures 4a-4b As shown, step S2 is then performed to form an isolation trench 15 in the epitaxial layer. The isolation trench 15 penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units. The bottom of the isolation trench 15 exposes the substrate 11. The isolation trench 15 has a shape that is larger at the top and smaller at the bottom. The isolation trench 15 includes a first sidewall and a second sidewall that are disposed opposite to each other.

[0093] This step specifically includes the following steps:

[0094] like Figures 2a-2b As shown, firstly, dicing channels 16 are formed around the periphery of the epitaxial layer. The dicing channels 16 penetrate the epitaxial layer and expose the substrate 11. In subsequent steps, the wafer is diced through the dicing channels 16 to cut the wafer into multiple high-voltage flip-chip light-emitting diodes.

[0095] While forming the dicing channel 16, an isolation trench 15 is formed in the epitaxial layer. Specifically, the isolation trench 15 is formed in the epitaxial layer by sequentially using photolithography and plasma etching (ICP) processes. The isolation trench 15 penetrates the epitaxial layer, and the bottom of the isolation trench 15 exposes the substrate 11.

[0096] The number of isolation trenches 15 is at least one, and the isolation trenches 15 divide the epitaxial layer into m*n arrayed light-emitting units, where the total number of light-emitting units k = m*n, m ≥ 1, n ≥ 2, and m and n are both positive integers. Each light-emitting unit is sequentially designated as the first light-emitting unit, the second light-emitting unit, ..., up to the kth light-emitting unit, in a series order from the N-type pad to the P-type pad. The first sidewall 151 is the sidewall closest to the previous light-emitting unit, and the second sidewall 152 is the sidewall furthest from the previous light-emitting unit. In this embodiment, two isolation trenches 15 are formed in the epitaxial layer, and the isolation trenches 15 divide the epitaxial layer into 1*3 light-emitting units.

[0097] In this embodiment, the isolation trench 15 is shaped like an inverted trapezoid, wider at the top and narrower at the bottom. Preferably, the angle between the sidewall of the isolation trench 15 and the plane containing the surface of the substrate 11 is 35° to 55°. Specifically, the angle α between the first sidewall 151 of the isolation trench 15 and the plane containing the surface of the substrate 11 is 35° to 55°, and the angle β between the second sidewall 152 of the isolation trench 15 and the plane containing the surface of the substrate 11 is 35° to 55°. The angles α and β can be the same or different. Preferably, the angle between the sidewall of the isolation trench 15 and the plane containing the surface of the substrate 11 is 45°.

[0098] like Figures 3a-3b As shown, an opening 17 is then formed in the epitaxial layer of the first light-emitting unit. Specifically, the opening 17 is formed in the epitaxial layer of the first light-emitting unit sequentially using photolithography and plasma etching (ICP) processes. The opening 17 penetrates the second semiconductor layer 14 and the light-emitting layer 13, and the bottom of the opening 17 exposes the first semiconductor layer 12. The opening 17 in the first light-emitting unit avoids the central region of the high-voltage flip-chip LED. In this way, there is no opening in the central region that the ejector pin presses during the subsequent packaging process, thereby preventing failure caused by ejector pin cracking during the packaging process. The opening 17 can be located at any position in the first light-emitting unit. Preferably, the opening 17 is located at the center of the first light-emitting unit to improve the current spreading effect of the high-voltage flip-chip LED.

[0099] like Figures 4a-4b As shown, step S3 is then performed to form a current spreading layer 20. The current spreading layer 20 covers a portion of the upper surface of the second semiconductor layer 14 and also covers a portion of the second semiconductor layer 14 on the first sidewall 151. The current spreading layer 20 is spaced apart from the second sidewall 152.

[0100] In detail, it is first carried out using the magnetron sputtering process. Figure 3bA current spreading film layer is formed on the semiconductor structure shown. Then, the current spreading film layer is processed using photolithography and wet etching processes to form a current spreading layer 20. The current spreading layer 20 exposes the bottom and sidewalls of the dicing channel 16, as well as the sidewalls and bottom wall of the aperture 17 and the upper surface of the second semiconductor layer 14 outside the opening of the aperture 17. This is such that the current spreading layer 20 is spaced apart from the opening of the aperture 17 (i.e., the sidewall of the aperture 17), resulting in the opening size of the current spreading layer 20 at the opening of the aperture 17 being larger than the opening size of the aperture 17. The current spreading layer 20 also exposes… The second sidewall 152, the bottom wall, and the light-emitting layer, the first semiconductor layer 13, and at least a portion of the second semiconductor layer 14 of the first sidewall 151 of the isolation trench 15 are exposed, so that the current spreading layer 20 is spaced apart from the second sidewall 152. The current spreading layer 20 covers a portion of the second semiconductor layer 14 on the first sidewall 151, so that when the metal electrode 42 is subsequently formed in the isolation trench 15, the metal electrode 42 can contact the current spreading layer 20 at the first sidewall 151. This is beneficial to improving the current spreading capability of the high-voltage flip-chip light-emitting diode, and also beneficial to subsequent planarization and brightness improvement of the light-emitting unit.

[0101] Optionally, the opening size of the current spreading layer 20 at the opening of the cutting channel 16 is the same as the opening size of the cutting channel 16. For ease of manufacturing, it is preferable that the opening of the current spreading layer 20 and the opening of the cutting channel 16 are spaced apart.

[0102] In this step, the wet etching process uses a mixed solution of HCl and FeCl3.

[0103] The current spreading layer 20 is made of a transparent conductive layer (TCO), a metal conductive layer, or a composite structure thereof. Preferably, the current spreading layer 20 is made of ITO (indium tin oxide), and the thickness of the current spreading layer 20 is, for example, [missing information].

[0104] like Figures 5a-5b As shown, step S4 is then performed to form a reflector structure 30. The reflector structure covers the first semiconductor layer 12 and the light-emitting layer 13 of the first sidewall 151, and also covers the light-emitting layer 13 and the second semiconductor layer 14 of the second sidewall 152, so that when the metal electrode is subsequently formed, the metal electrode electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

[0105] In detail, Figure 4bThe semiconductor structure shown employs electron beam evaporation to deposit a mirror structure layer. Then, photolithography and plasma etching processes are used to sequentially remove portions of the mirror structure layer, so that the mirror structure 30 only covers the sidewalls of the opening 17, the light-emitting layer 13 and the first semiconductor layer 12 of the first sidewall 151, the light-emitting layer 13 and the second semiconductor layer 14 of the second sidewall 152, and the exposed upper surface of the second semiconductor layer 14 of the current spreading layer 20. The exposed upper surface of the second semiconductor layer 14 of the current spreading layer 20 includes the upper surface of the second semiconductor layer 14 at the opening of the opening 17 and the upper surface of the second semiconductor layer 14 adjacent to the second sidewall 152. In the plasma etching process of this step, CH4 is the primary etching gas.

[0106] In other embodiments, a first dielectric layer can be formed first using PECVD (Plasma Enhanced Chemical Vapor Deposition) or electron beam evaporation, and then a mirror structure layer can be formed on the first dielectric layer. The first dielectric layer covers the sidewalls of the opening 17, the light-emitting layer 13 and the first semiconductor layer 12 of the first sidewall 151, the light-emitting layer 13 and the second semiconductor layer 14 of the second sidewall 152, and the portion of the upper surface of the second semiconductor layer 14 exposed by the current spreading layer 20. The mirror structure 30 is located on the first dielectric layer. The first dielectric layer facilitates the subsequent coverage of the mirror structure 30 by the sidewalls of the isolation trench 15 and helps prevent breakage of the mirror structure 30.

[0107] In this embodiment, the reflector structure 30 is a distributed Bragg reflector (DBR), which consists of multiple periodically alternating silicon oxide and titanium oxide layers. Preferably, the DBR has 6 to 18 periods of silicon oxide and titanium oxide layers. The silicon oxide layer is made of silicon dioxide, and the titanium oxide layer is made of titanium pentoxide. The first dielectric layer is made of silicon oxide, and its thickness is [missing information].

[0108] like Figures 6a-6cAs shown, step S5 is then executed to form a metal electrode 42. The metal electrode 42 fills the isolation trench 15 and electrically connects the second semiconductor layer 14 on the first sidewall 151 and the first semiconductor layer 12 on the second sidewall 152. Specifically, the first electrode 41 and the metal electrode 42 are formed sequentially through photolithography, vapor deposition, metal lift-off, and resist removal processes. The first electrode 41 fills the opening 17, and the metal electrode 42 fills the isolation trench 15. The height of the first electrode 41 and the second electrode 42 is controlled by controlling the thickness of the metal vapor deposition. Preferably, a planarization process is performed to reduce the height difference between the first electrode 41, the metal electrode 42, and the upper surfaces of the mirror structure 30 and the current spreading layer 20 located on the second semiconductor layer 14, reducing the risk of breakage of the subsequently formed second dielectric layer and improving the reliability of the high-voltage flip-chip LED. Preferably, the first electrode 41 and the metal electrode 42 are flush with the upper surfaces of the mirror structure 30 and the current spreading layer 20 located on the second semiconductor layer 14, such as... Figure 6c As shown.

[0109] In this step, the planarization process is a chemical mechanical polishing (CMP) process; the photoresist layer used in the photolithography process is a negative photoresist; the vapor deposition process causes the first electrode 41 to fill the opening 17, and the metal electrode 42 to fill the isolation trench 15. Compared to the cover connection of the metal electrode 42 in the prior art, the metal electrode 42 filling the isolation trench 15 in this embodiment reduces the risk of metal electrode 42 breakage, while increasing the thickness of the metal electrode 42, thereby improving the heat dissipation capacity of the high-voltage flip-chip LED, enhancing the stability of the high-voltage flip-chip LED under high temperature and high current environment, and thus improving the reliability of the high-voltage flip-chip LED.

[0110] At this time, since the reflector structure 30 also acts as an insulator, the first electrode 41 does not contact the second semiconductor layer 14 and the light-emitting layer 13 on the sidewall of the opening 17, but forms an electrical connection with the first semiconductor layer 12; the metal electrode 42 does not contact the light-emitting layer 13 and the first semiconductor layer 12 at the first sidewall 151 in the isolation trench 15, and does not contact the second semiconductor layer 14 and the light-emitting layer 13 at the second sidewall 152, connecting the second semiconductor layer 14 on the first sidewall 151 and the first semiconductor layer 12 on the second sidewall 152, so that adjacent light-emitting units are connected in series in the isolation trench 15, reducing the number of first electrodes 41, so that only one first electrode 41 (i.e., one opening 17) is needed to realize the conduction of the high voltage flip-chip light-emitting diode, reducing the number of openings 17, thereby reducing the light-emitting area of ​​the light-emitting unit occupied by the opening 17, and improving the luminous efficiency of the high voltage flip-chip light-emitting diode. In addition, the metal electrode 42 is located only in the isolation trench 15, so that there is no metal electrode 42 on the upper surface of the second semiconductor layer 14, thereby reducing the light absorption of the metal electrode 42.

[0111] The first electrode 41 and the metal electrode 42 are stacked structures, which, from bottom to top, include a chromium layer, a first aluminum layer, a first titanium layer, a second aluminum layer, and a second titanium layer. The first aluminum layer increases the light reflection capability of the first electrode 41 and the metal electrode 42, so that the metal electrode 42 and the reflector structure 30 in the isolation trench 15 form an all-around reflector (ODR), and the first electrode 41 and the reflector structure 30 in the opening 17 also form an all-around reflector (ODR). This increases the reflectivity of the high-voltage flip-chip LED, reduces the light absorption of the metal in the isolation trench 15 and the opening 17, and improves the brightness of the high-voltage flip-chip LED.

[0112] like Figure 7 As shown, a second dielectric layer 50 is then formed, and a first through-hole 51 and a second through-hole 52 are formed in the second dielectric layer 50. The second dielectric layer 50 covers... Figure 6c The surface of the semiconductor structure shown (i.e., the surface where the second dielectric layer 50 covers the first electrode 41, metal electrode 42, mirror structure 30, current spreading layer 20, and the exposed surface of the second semiconductor layer 14) has a first via 51 penetrating the second dielectric layer 50 and exposing the first electrode 41 at the bottom of the trench, and a second via 52 penetrating the second dielectric layer 50 and exposing the current spreading layer 20 of the k-th light-emitting unit at the bottom of the trench. Specifically, the second dielectric layer 50 is first formed using an electron beam evaporation process; then, the first via 51 and the second via 52 penetrating the second dielectric layer 50 are sequentially formed using photolithography and ICP etching processes.

[0113] The second dielectric layer 50 has a thickness of 2 mm to 6 mm and serves as a distributed Bragg reflector (DBR). The DBR consists of multiple alternating silicon oxide and titanium oxide layers. Preferably, the DBR has 6 to 18 alternating silicon oxide and titanium oxide layers, wherein the silicon oxide layer is made of silicon dioxide and the titanium oxide layer is made of titanium pentoxide.

[0114] In this embodiment, the first electrode 41 is located in the first light-emitting unit, the first through hole 51 is located above the first light-emitting unit, the second through hole 52 is located above the kth light-emitting unit, and the bottom of the second through hole 52 exposes the current extension layer 20 of the kth light-emitting unit.

[0115] like Figure 8 As shown, the photoresist layer is then removed using photolithography, vapor deposition, metal lift-off, and photoresist removal processes to form the first pad 61 and the second pad 62.

[0116] The first pad 61 fills the first via 51 and covers a portion of the second dielectric layer 50 near the opening of the first via 51, so that the first pad 61 connects to the first electrode 41, and is connected to the first semiconductor layer 12 of the first light-emitting unit where the first electrode 41 is located, serving as the N-type pad of the high-voltage flip-chip light-emitting diode. The second pad 62 fills the second via 52 and covers a portion of the second dielectric layer 50 near the opening of the second via 52, so that the second pad 62 connects to the current spreading layer 20 at the bottom of the second via 52, and is connected to the second semiconductor layer 14 of the k-th light-emitting unit below the second via 52, serving as the P-type pad of the high-voltage flip-chip light-emitting diode. The first pad 61 and the second pad 62 do not contact each other. Compared to the prior art where three metal interconnect processes are used to form metal interconnects, this embodiment only uses two metal interconnect processes, the first pad 61 and the first electrode 41, to form metal interconnects, thereby reducing the process flow.

[0117] The first pad 61 and the second pad 62 are both metal stacks of any of the following: titanium (Ti), platinum (Pt), silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), gold (Au), and gold-tin alloy (AuSn). A welding material layer is formed on the surface of both the first pad 61 and the second pad 62. The material of the welding material layer is gold (Au) or gold-tin alloy.

[0118] Next, the substrate 11 is thinned from the side away from the epitaxial layer (i.e., the lower surface of the substrate 11), and then the substrate 11 is cut along the dicing path 16 to obtain a single high-voltage flip-chip light-emitting diode. When the high-voltage flip-chip light-emitting diode is externally powered, the current flows into the k-th light-emitting unit of the high-voltage flip-chip light-emitting diode through the second pad 62, and then flows through each light-emitting unit in the series path through the metal electrode 42 in the isolation trench 15, and finally flows into the first light-emitting unit with the first electrode 41, and then flows out through the first electrode 41 and the first pad 61, forming a series electrical connection of multiple light-emitting units, thus realizing the function of the high-voltage flip-chip light-emitting diode.

[0119] It should be noted that in the above embodiment with 1*3 light-emitting units, adjacent light-emitting units are connected in series through metal electrodes 42 filled in the isolation trench 15. In another embodiment of the present invention, as... Figures 9a-9b As shown, a structure with 2*3 light-emitting units connected in series is provided. The first to sixth light-emitting units are sequentially connected in series and labeled LED1 to LED6 respectively. Each pair of interconnected light-emitting units is electrically connected via metal electrodes 42 filled in the isolation trench 15. The structure is the same as in the embodiment with 1*3 light-emitting units and will not be described again here. For two adjacent light-emitting units that do not need to be connected in series, such as the first light-emitting unit LED1 and the fourth light-emitting unit LED4, and the third light-emitting unit LED3 and the sixth light-emitting unit LED6, the current spreading layer 20 only covers the upper surface of the second semiconductor layer 14 outside the isolation trench 15, and does not cover the second semiconductor layer 14 on the sidewall of the isolation trench 15. Simultaneously, the reflector structure 30 covers the entire sidewall and bottom wall of the isolation trench 15 to achieve isolation between adjacent light-emitting units. It is understood that there is more than one way to connect the six light-emitting units in series in this embodiment. The structure in the isolation trench 15 between two light-emitting units that do not need to be connected in series in other series configurations or other embodiments is also the same as in this embodiment and will not be described again here.

[0120] Please see Figure 8 This embodiment also provides a high-voltage flip-chip light-emitting diode (LED). The LED includes a substrate 11 and an epitaxial layer on the substrate 11. The epitaxial layer includes, from bottom to top, a first semiconductor layer 12, a light-emitting layer 13, and a second semiconductor layer 14. The epitaxial layer has an isolation trench 15, which penetrates the epitaxial layer and divides it into multiple light-emitting units. The bottom of the isolation trench 15 exposes the substrate 11. A dicing channel 16 is also provided around the periphery of the epitaxial layer, penetrating the epitaxial layer and exposing the substrate 11.

[0121] The isolation trench is shaped like an inverted trapezoid, wider at the top and narrower at the bottom. The isolation trench 15 includes a first sidewall 151 and a second sidewall 152 disposed opposite to each other. The angle α between the first sidewall 151 and the plane containing the surface of the substrate 11 is 35° to 55°, and the angle β between the second sidewall 152 and the plane containing the surface of the substrate 11 is 35° to 55°. The included angles α and β can be the same or different.

[0122] The number of isolation trenches 15 is at least one, and the isolation trenches 15 divide the epitaxial layer into m*n arrayed light-emitting units, the total number of light-emitting units k = m*n, where m ≥ 1, n ≥ 2, and m and n are both positive integers. Each light-emitting unit is sequentially designated as the first light-emitting unit, the second light-emitting unit, ..., up to the kth light-emitting unit, in a series order from the N-type pad to the P-type pad. The first sidewall 151 is the sidewall closest to the previous light-emitting unit, and the second sidewall 152 is the sidewall furthest from the previous light-emitting unit.

[0123] The epitaxial layer also includes an opening 17, which is located in the first light-emitting unit and penetrates the second semiconductor layer 14 and the light-emitting layer 13. The bottom of the opening 17 exposes the first semiconductor layer 12.

[0124] A portion of the upper surface of the second semiconductor layer 14 has a current spreading layer 20, which also covers a portion of the second semiconductor layer 14 on the first sidewall 151, and the current spreading layer 20 is spaced apart from the second sidewall 152; the current spreading layer 20 exposes the upper surface of the second semiconductor layer 14 outside the opening of the aperture 17, and the current spreading layer 20 is spaced apart from the opening of the aperture 17, such that the opening size of the current spreading layer 20 at the opening of the aperture 17 is larger than the opening size of the aperture 17.

[0125] The first sidewall 151 and the second sidewall 152 have a reflector structure 30, which covers the first semiconductor layer 12 and the light-emitting layer 13 of the first sidewall 151, the light-emitting layer 13 and the second semiconductor layer 14 of the second sidewall 152, and the upper surface of the second semiconductor layer 14 adjacent to the second sidewall 152; the sidewall of the opening 17 and the upper surface of the second semiconductor layer 14 at its opening also have a reflector structure 30.

[0126] A metal electrode 42 fills the isolation trench 15, electrically connecting the second semiconductor layer 14 on the first sidewall 151 and the first semiconductor layer 12 on the second sidewall 152. A first electrode 41 fills the opening 17 and is electrically connected to the first semiconductor layer 12 exposed by the mirror structure 30. The first electrode 41 is separated from the epitaxial layer exposed on the sidewall of the opening 17 by the mirror structure 30. Preferably, the first electrode 41, the metal electrode 42, the current spreading layer 20, and the upper surface of the mirror structure 30 are flush.

[0127] Optionally, a first dielectric layer is formed between the first sidewall 151 and the mirror structure 30, between the second sidewall 152 and the mirror structure 30, and between the sidewall of the opening 17 and the mirror structure 30. The first dielectric layer is located below the mirror structure 30, that is, the first dielectric layer is located on the sidewall of the opening 17, the light-emitting layer 13 and the first semiconductor layer 12 of the first sidewall 151, the light-emitting layer 13 and the second semiconductor layer 14 of the second sidewall 152, and the upper surface of the second semiconductor layer 14 exposed by the current spreading layer 20, and is covered by the mirror structure 30.

[0128] A second dielectric layer 50 is provided on the exposed surfaces of the current spreading layer 20, the first electrode 41, the metal electrode 42, the mirror structure 30, and the second semiconductor layer 14. The second dielectric layer 50 covers the exposed surfaces of the first electrode 41, the metal electrode 42, the mirror structure 30, the current spreading layer 20, and the second semiconductor layer 14. The second dielectric layer 50 has a first through-hole 51 and a second through-hole 52. The first through-hole 51 penetrates the second dielectric layer 50 and exposes the first electrode 41 at its bottom. The second through-hole 52 penetrates the second dielectric layer 20 and exposes the current spreading layer 20 of the k-th light-emitting unit at its bottom. Both the mirror structure 30 and the second dielectric layer 50 are distributed Bragg mirrors.

[0129] A first pad 61 and a second pad 62 are formed in the first through-hole 51, the second through-hole 52, and on the upper surface of the second dielectric layer 50. The first pad 61 fills the first through-hole 51 and covers a portion of the second dielectric layer 50 near the opening of the first through-hole 51. The second pad 62 fills the second through-hole 52 and covers a portion of the second dielectric layer 50 near the opening of the second through-hole 52. The first pad 61 is connected to the first electrode 41 and is connected to the first semiconductor layer 12 of the first light-emitting unit through the first electrode 41 as an N-type pad. The second pad 62 is connected to the current spreading layer 20 at the bottom of the second through-hole 52 and is connected to the second semiconductor layer 14 of the k-th light-emitting unit through the current spreading layer 20 as a P-type pad. The first pad 61 and the second pad 62 do not contact each other.

[0130] In summary, this invention provides a high-voltage flip-chip light-emitting diode and its fabrication method. Compared to the prior art where metal electrodes are used for covering and connecting, this invention fills the isolation trench with the metal electrode, reducing the risk of metal electrode breakage and increasing the thickness of the metal electrode, thereby improving the heat dissipation capacity of the high-voltage flip-chip light-emitting diode and enhancing its stability under high-temperature and high-current environments, thus improving the reliability of the high-voltage flip-chip light-emitting diode. Compared to the prior art where deep steps at the isolation trench easily lead to breakage when the second dielectric layer is covered, this invention uses planarization treatment to make the upper surfaces of the first electrode, metal electrode, current spreading layer, and reflector structure flush, reducing the risk of second dielectric layer breakage and improving the reliability of the high-voltage flip-chip light-emitting diode. The metal electrode electrically connects the second semiconductor layer of the first sidewall and the first semiconductor layer of the second sidewall. This design allows adjacent light-emitting units to be connected in series within the isolation trench, reducing the number of first electrodes. This means only one first electrode (i.e., one opening) is needed to enable the high-voltage flip-chip LED to conduct, reducing the number of openings and thus the light-emitting area occupied by the openings, thereby improving the luminous efficiency of the high-voltage flip-chip LED. Because the opening is located within the first light-emitting unit, it avoids the central region of the high-voltage flip-chip LED. This prevents failures caused by pin cracking during subsequent packaging, as there is no opening in the central area pressed by the ejector pin. The metal electrodes and the mirror structure in the isolation trench form an omnidirectional reflector, as do the mirror structure in the first electrode and the opening, increasing the reflectivity of the high-voltage flip-chip LED and reducing light absorption by the metal in the isolation trench and the opening, thus improving the brightness of the high-voltage flip-chip LED. Furthermore, compared to the traditional three-layer metal interconnect process, this invention only requires the first pad and the first electrode to be electrically connected, achieving a two-layer metal interconnect process and reducing the process flow.

[0131] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0132] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A high-voltage flip-chip light-emitting diode, characterized in that, include: Substrate; An epitaxial layer is located on the substrate, and the epitaxial layer comprises, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer; An isolation trench is located in the epitaxial layer. The isolation trench penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units. The bottom of the isolation trench exposes the substrate. The isolation trench has a shape that is larger at the top and smaller at the bottom. The isolation trench includes a first sidewall and a second sidewall that are disposed opposite to each other. A current spreading layer covers a portion of the upper surface of the second semiconductor layer and also covers a portion of the second semiconductor layer on the first sidewall, and the current spreading layer is spaced apart from the second sidewall. A reflective mirror structure, wherein the reflective mirror structure covers a first semiconductor layer and a light-emitting layer on the first sidewall, and further covers a light-emitting layer and a second semiconductor layer on the second sidewall; and A metal electrode fills the isolation trench and electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

2. The high-voltage flip-chip light-emitting diode as described in claim 1, characterized in that, The angle between the first sidewall and the plane containing the substrate surface is 35° to 55°, and the angle between the second sidewall and the plane containing the substrate surface is 35° to 55°.

3. The high-voltage flip-chip light-emitting diode as described in claim 1, characterized in that, The number of isolation trenches is at least one, and the isolation trenches divide the epitaxial layer into m*n arrayed light-emitting units. The total number of light-emitting units is k = m*n. Each light-emitting unit is sequentially arranged from the N-type pad to the P-type pad as the first light-emitting unit to the k-th light-emitting unit, where m ≥ 1, n ≥ 2, and m and n are both positive integers.

4. The high-voltage flip-chip light-emitting diode as described in claim 3, characterized in that, The epitaxial layer also includes an opening located in the first light-emitting unit, and the opening penetrates the second semiconductor layer and the light-emitting layer, with the bottom of the opening exposing the first semiconductor layer.

5. The high-voltage flip-chip light-emitting diode as described in claim 4, characterized in that, The current spreading layer is spaced apart from the opening of the aperture, such that the opening size of the current spreading layer at the opening of the aperture is larger than the opening size of the aperture.

6. The high-voltage flip-chip light-emitting diode as described in claim 4, characterized in that, The first sidewall is the sidewall closer to the previous light-emitting unit, and the second sidewall is the sidewall farther away from the previous light-emitting unit.

7. The high-voltage flip-chip light-emitting diode as described in claim 6, characterized in that, The mirror structure also covers the sidewalls of the opening and the portion of the upper surface of the second semiconductor layer exposed by the current spreading layer.

8. The high-voltage flip-chip light-emitting diode as described in claim 7, characterized in that, It also includes a first dielectric layer, which is located on the sidewall of the opening, on the first semiconductor layer and the light-emitting layer of the first sidewall, on the light-emitting layer and the second semiconductor layer on the second sidewall, and on the upper surface of the second semiconductor layer exposed by the current spreading layer, and the mirror structure is located on the first dielectric layer.

9. The high-voltage flip-chip light-emitting diode as described in claim 7, characterized in that, It also includes a first electrode that fills the opening, and the first electrode is separated from the epitaxial layer exposed on the sidewall of the opening by the mirror structure.

10. The high-voltage flip-chip light-emitting diode as described in claim 9, characterized in that, The upper surfaces of the first electrode, the metal electrode, the mirror structure, and the current spreading layer are flush.

11. The high-voltage flip-chip light-emitting diode as described in claim 9, characterized in that, It also includes a second dielectric layer, which covers the first electrode, the metal electrode, the mirror structure, the current spreading layer, and the exposed surface of the second semiconductor layer. A first through-hole and a second through-hole are formed in the second dielectric layer. The first through-hole penetrates the second dielectric layer and exposes the first electrode at the bottom of the trench. The second through-hole penetrates the second dielectric layer and exposes the current spreading layer of the k-th light-emitting unit at the bottom of the trench.

12. The high-voltage flip-chip light-emitting diode as described in claim 11, characterized in that, Both the mirror structure and the second dielectric layer are distributed Bragg mirrors.

13. The high-voltage flip-chip light-emitting diode as described in claim 11, characterized in that, It also includes a first pad and a second pad, wherein the first pad fills the first via and covers a portion of the second dielectric layer near the opening of the first via as the N-type pad, and the second pad fills the second via and covers a portion of the second dielectric layer near the opening of the second via as the P-type pad.

14. A method for fabricating a high-voltage flip-chip light-emitting diode, characterized in that, Includes the following steps: An epitaxial layer is formed on a substrate, the epitaxial layer comprising, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer; An isolation trench is formed in the epitaxial layer, the isolation trench penetrates the epitaxial layer and divides the epitaxial layer into multiple light-emitting units, and the bottom of the isolation trench exposes the substrate. The isolation trench has a shape that is larger at the top and smaller at the bottom, and the isolation trench includes a first sidewall and a second sidewall disposed opposite to each other. A current spreading layer is formed, which covers a portion of the upper surface of the second semiconductor layer and also covers a portion of the second semiconductor layer on the first sidewall, and the current spreading layer is spaced apart from the second sidewall. A reflective mirror structure is formed, the reflective mirror structure covering a first semiconductor layer and a light-emitting layer on the first sidewall, and further covering a light-emitting layer and a second semiconductor layer on the second sidewall; and A metal electrode is formed, which fills the isolation trench and electrically connects the second semiconductor layer on the first sidewall and the first semiconductor layer on the second sidewall.

15. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 14, characterized in that, The angle between the first sidewall and the plane containing the substrate surface is 35° to 55°, and the angle between the second sidewall and the plane containing the substrate surface is 35° to 55°.

16. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 14, characterized in that, The number of isolation trenches is at least one, and the isolation trenches divide the epitaxial layer into m*n arrayed light-emitting units. The total number of light-emitting units is k = m*n. Each light-emitting unit is sequentially arranged from the N-type pad to the P-type pad as the first light-emitting unit to the k-th light-emitting unit, where m ≥ 1, n ≥ 2, and m and n are both positive integers.

17. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 16, characterized in that, An opening is also formed in the epitaxial layer, the opening is located in the first light-emitting unit, and the opening penetrates the second semiconductor layer and the light-emitting layer, the bottom of the opening exposes the first semiconductor layer.

18. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 17, characterized in that, The current spreading layer is spaced apart from the opening of the aperture, such that the opening size of the current spreading layer at the opening of the aperture is larger than the opening size of the aperture.

19. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 17, characterized in that, The first sidewall is the sidewall closer to the previous light-emitting unit, and the second sidewall is the sidewall farther away from the previous light-emitting unit.

20. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 19, characterized in that, The mirror structure also covers the sidewalls of the opening and the portion of the upper surface of the second semiconductor layer exposed by the current spreading layer.

21. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 20, characterized in that, Before forming the mirror structure, the following steps are also included: A first dielectric layer is formed, which is located on the sidewall of the opening, on the first semiconductor layer and the light-emitting layer of the first sidewall, on the light-emitting layer and the second semiconductor layer on the second sidewall, and on the upper surface of the second semiconductor layer exposed by the current spreading layer, and the mirror structure is located on the first dielectric layer.

22. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 20, characterized in that, A first electrode is formed simultaneously with a metal electrode, the first electrode fills the opening, and the first electrode is separated from the epitaxial layer exposed on the sidewall of the opening by the mirror structure.

23. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 22, characterized in that, The upper surfaces of the first electrode, the metal electrode, the mirror structure, and the current spreading layer are flush.

24. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 22, characterized in that, After forming the metal electrode, the process also includes: A second dielectric layer is formed, which covers the first electrode, the metal electrode, the mirror structure, the current spreading layer, and the exposed surface of the second semiconductor layer. A first via and a second via are formed in the second dielectric layer. The first via penetrates the second dielectric layer and exposes the first electrode at the bottom of the trench. The second via penetrates the second dielectric layer and exposes the current spreading layer of the k-th light-emitting unit at the bottom of the trench.

25. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 24, characterized in that, Both the mirror structure and the second dielectric layer are distributed Bragg mirrors.

26. The method for fabricating a high-voltage flip-chip light-emitting diode as described in claim 24, characterized in that, After forming the second dielectric layer, the process further includes: A first pad and a second pad are formed. The first pad fills the first via and covers a portion of the second dielectric layer near the opening of the first via to serve as the N-type pad. The second pad fills the second via and covers a portion of the second dielectric layer near the opening of the second via to serve as the P-type pad.

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