A method for reducing leakage current of grid-connected inverter based on non-clamp h10 topology

Abstract

The full title of this invention is: A Method for Reducing Leakage Current in Grid-Connected Inverters Based on Non-Clamping H10 Topology. To reduce the leakage current of non-isolated photovoltaic grid-connected inverters, this invention proposes a novel non-clamping H10 topology inverter based on the traditional H6 topology. This topology operates in the same mode as the H6 topology during the active vector period, while during the zero vector period, it limits the common-mode voltage with specific switching states and isolates the grid and power supply. This method reduces the inverter's common-mode voltage by 66.7% and significantly reduces leakage current. The advantages of this invention are that it substantially reduces the inverter's common-mode voltage and cuts off the leakage current flow path, thus ensuring a reduction in leakage current. Furthermore, the control signal for the non-clamping H10 topology is generated through logic function operations based on the traditional H6 topology control signal, making the control method simple and easy to implement. Finally, simulation verification shows that compared with the traditional H6 topology and existing H10 topology inverters, this invention can significantly reduce leakage current and has good grid-connected current quality.

Description

Technical Field

[0001] This invention belongs to the field of power electronics electromagnetic compatibility, specifically relating to a method for reducing leakage current in grid-connected inverters based on a non-clamped H10 topology. Background Technology

[0002] Solar energy, as a clean and renewable energy source, is widely used in power generation. Solar photovoltaic (PV) power generation has two modes: grid-connected and stand-alone operation. In grid-connected mode, energy is directly injected into the grid without any energy storage devices, thus research on grid-connected solar PV systems has received considerable attention. Compared to systems equipped with transformers, transformerless grid-connected PV systems have advantages in size and cost; however, problems such as leakage current arise. Leakage current not only causes grid current distortion, affecting power quality, but also causes electromagnetic interference. Research shows that the magnitude of leakage current is related to the common-mode voltage variation of the inverter; specifically, the smaller the common-mode voltage variation range, the smaller the leakage current, and vice versa. Therefore, to suppress leakage current, it is necessary to study how to suppress common-mode voltage.

[0003] Using active or passive filters is a widely used method for suppressing common-mode voltage, but this increases the size and cost of the inverter system. To address this issue, pulse width modulation (PWM) methods based on control improvements to reduce common-mode voltage have been proposed, such as equivalent zero-vector PWM, adjacent three-vector PWM, and far-end three-vector PWM. These three modulation methods share the characteristic of not using a zero vector, thus significantly reducing the range of common-mode voltage variation. However, these methods suffer from drawbacks such as high harmonic content in the output phase current and bipolarity in the output line voltage. To reduce the common-mode voltage variation range while improving the quality of the output current, topology improvement has become one of the effective solutions.

[0004] Traditional three-phase two-level inverters are called H6 topologies because they have six switches. Many topology improvements are based on the H6 topology: adding a switch on the positive bus on the DC side to form the H7 topology; adding an additional switch on both the positive and negative buses to form the H8 topology. These topologies share a common characteristic: during active vectoring, the operating mode is the same as the H6 topology, while during zero vectoring, the grid and power source are isolated to limit the common-mode voltage variation during this period. Although the common-mode voltage is reduced by 33.3% for the H7 topology and 50% for the H8 topology, the range of common-mode voltage variation is still relatively large.

[0005] To further reduce the common-mode voltage variation range, many improvements based on the H8 topology have been proposed: 1. Adding three clamping capacitors and two clamping diodes to the H8 topology; 2. Replacing the two clamping diodes in 1 with a switch to form an H10 topology, etc. These two topologies reduce the common-mode voltage range by clamping the voltage during the zero-vector period; 3. Connecting additional capacitors in parallel on both sides of the switch to form an improved H8 topology that achieves zero common-mode voltage variation during the zero-vector period. These improved structures based on the H8 topology limit the common-mode voltage variation during the zero-vector period, but they also have some drawbacks: 1. The use of additional components increases system cost and power loss. 2. The power supply and grid still have an electrical connection during the zero-vector period, which creates a leakage current path, resulting in poor leakage current suppression. Therefore, to address these problems, this invention proposes a method for reducing leakage current based on a non-clamped H10 topology. Summary of the Invention

[0006] The purpose of this invention is to provide a method for reducing leakage current in grid-connected inverters based on a non-clamped H10 topology. First, a novel non-clamped H10 topology inverter is employed, which is constructed by adding four switches to the traditional H6 topology. Second, control signals for this topology are generated through logic function operations, resulting in a simple and easy-to-implement control method. This topology can achieve a 66.7% reduction in common-mode voltage and can isolate the grid and power supply during zero-vector periods, thus significantly reducing leakage current.

[0007] To achieve the above objectives, the present invention adopts the following technical solution.

[0008] A novel non-clamped H10 topology inverter structure is as follows: Figure 1 As shown. The structure is as follows: Based on the traditional H6 topology, a switch T is added to each of the positive and negative busbars after phase A. e1 and T e2 Then use switch T d1 and T d2 Connect the positive and negative bus ends to the A-phase output. Because this topology contains 10 switches and does not use any clamping elements compared to other H10 topologies that use clamping power supplies or clamping capacitors, it is called the non-clamping H10 topology (NCH10).

[0009] Combination Figure 1 The common-mode voltage of the NCH10 topology inverter is defined as: V CM =(V AO +V BO +V CO ) / 3 (1) In the formula, VCM For common-mode voltage, V AO V BO V CO These are the voltages between points A and O, B and O, and C and O, respectively. Figure 1 V in dc This is the voltage of the photovoltaic power supply.

[0010] The common-mode voltage of a conventional H6 topology inverter during the active vector period is V. dc / 3 and 2V dc / 3, while it is 0 during the zero vector "000" and V during the zero vector "111". dc Therefore, during the zero vector period, "0" and "V" dc "This significantly increases the variation range of the inverter's common-mode voltage, so common-mode voltage limiting is required for the zero vector." Figure 1 The operating characteristics of the NCH10 topology are as follows: During the active vector period, switch T e1 and T e2 Close, switch T d1 and T d2 When disconnected, the topology is the same as H6, and the operation of the other switches is also the same as H6. The main difference is during the zero vector period, where the switch states are shown in Table 1. Table 1. Switching states of the NCH10 topology during zero vector. In the table, "0" indicates that the switch is in the open state, and "1" indicates that the switch is in the closed state.

[0011] The switching state during zero vector has two functions: 1. Isolating the power grid and the power source. 2. Reducing the range of common-mode voltage variation. The range of common-mode voltage variation will be analyzed below.

[0012] In an inverter, closing a switch can be considered equivalent to a short circuit, and opening a switch can be considered equivalent to an open circuit. However, due to the presence of junction capacitance in the switch, opening the switch will be represented in terms of junction capacitance.

[0013] Because there are various scenarios where an active vector enters a zero vector—for example, "001" to "000", "100" to "000", "110" to "111", and "011" to "111"—each scenario corresponds to a different initial state of the switching junction capacitance, and therefore requires separate discussion. This invention will use "001" to "000" and "110" to "111" as examples for analysis; the others are similar.

[0014] Scenario 1: From "001" to "000"

[0015] The initial voltage state of the switching junction capacitance in "001" is: U Ca1 (0-)=U Cc2 (0-)=V dc U Ce1 (0-)=U Ca2 (0-)=U Cb2 (0-)=U Cd2 (0-)=0, from which the complex frequency domain circuit model during the zero vector “000” is derived, such as Figure 2 As shown. Where C... ** To represent the junction capacitance of the corresponding switch, write Kirchhoff's voltage and current laws for this model: I a1 +I e1 =I a2 +I c2 (6) Therefore, the common-mode voltage expression can be derived as follows:

[0016] Scenario 2: From "110" to "111"

[0017] The initial voltage state of the switching junction capacitance at "110" is: U Ca2 (0-)=U Cc1 (0-)=V dc U Ca1 (0-)=U Cb1 (0-)=U Cd1 (0-)=U Ce2 (0-)=0, from which the complex frequency domain circuit model is derived as follows: Figure 2 As shown. Where C... ** To represent the junction capacitance of the corresponding switch, write Kirchhoff's voltage and current laws for this model: I a1 +I c1 =I a2 +I e2 (13) Therefore, the common-mode voltage expression can be derived as follows:

[0018] If the junction capacitance of the switch (C) a1 -C e2 If the common-mode voltage values ​​are the same in both cases, then the common-mode voltage values ​​in the two cases are respectively V. dc / 3 and 2V dc / 3. Table 2 lists the common-mode voltage values ​​for six different scenarios. Table 2 Common-mode voltages of the NCH10 topology during zero vector.

[0019] As shown in Table 2, the common-mode voltage of the NCH10 topology during the zero-vector period is limited to V. dc / 3 to 2V dc Between / 3. This indicates that this topology can operate over a relatively small range of common-mode voltages.

[0020] The NCH10 topology is an improvement on the H6 topology; therefore, its PWM control signal can be obtained by performing logic function operations on the H6 control signal. The relationship between the control signals XYZ of the H6 topology and the control signals of the NCH10 topology is shown in Table 3. Table 3 shows the relationship between H6 topology control signals XYZ and NCH10 topology control signals. The resulting logical function is as follows:

[0021] Due to the application of the above technical solution, the present invention has the following characteristics: 1. This invention proposes a novel non-clamped H10 topology that can reduce common-mode voltage by 66.7%. 2. The present invention significantly reduces leakage current by significantly reducing the range of common-mode voltage variation and isolating the power supply and grid during zero vector period. 3. In this invention, the control of the NCH10 topology is achieved by logically modifying the control signal of the H6 topology, so the control is simple and easy to implement. Attached Figure Description

[0022] Figure 1 The non-clamped H10 topology inverter in this invention;

[0023] Figure 2 The complex frequency domain circuit model during the zero vector "000" in this invention;

[0024] Figure 3 The complex frequency domain circuit model during the zero vector "111" in this invention;

[0025] Figure 4 : Grid-connected control structure diagram of the NCH10 topology inverter in this invention;

[0026] Figure 5 Leakage current in the H6 topology of this invention;

[0027] Figure 6 Leakage current in the H10 topology of this invention;

[0028] Figure 7 Leakage current in the NCH10 topology of this invention;

[0029] Figure 8 The grid-connected current of the H6 topology in this invention;

[0030] Figure 9 The grid-connected current of the H10 topology in this invention;

[0031] Figure 10 The grid-connected current of the NCH10 topology in this invention; Detailed Implementation

[0032] The technical solution will be clearly and completely described below with reference to preferred embodiments and accompanying drawings. It should be understood that the preferred embodiments are merely illustrative of the invention and not intended to limit the scope of protection of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0033] This invention provides a method for reducing leakage current in grid-connected inverters based on a non-clamped H10 topology. The idea behind this method is that during active vectoring, this topology operates in the same mode as the H6 topology, where the common-mode voltage is limited to V. dc / 3 to 2V dc Between / 3. During zero vector, this topology also limits the common-mode voltage to V with specific switching states. dc / 3 to 2V dc The topology, which isolates the power grid and power source from each other, ultimately significantly reduces leakage current.

[0034] A grid-connected control structure diagram of one embodiment is shown below. Figure 4 As shown, the operation and implementation process of the control scheme is as follows:

[0035] Step S10: Real-time acquisition of inverter-side output current and grid voltage, coordinate transformation of the acquired voltage and current signals, and generation of phase-locked signals by phase-locked loop (PLL);

[0036] Step S20: Input the transformed voltage, current and desired current signals into the current controller, and perform coordinate inverse transformation on the output of the current controller to obtain the reference voltage signal.

[0037] Step S30: Input the reference voltage signal into the space vector pulse width modulation module (SVPWM) to generate the initial control signal XYZ.

[0038] Step S40: The initial control signals XYZ are processed by logic functions, i.e., equations (16) and (17), to finally obtain the control signals for the NCH10 topology; Simulation results

[0039] To verify the correctness of the proposed method, simulation verification was performed. The simulation parameters of the grid-connected inverter are shown in Table 1. Table 1 Simulation Parameters

[0040] A simulation module was built in MATLAB, parameters were set according to Table 1, the simulation was run, and different topologies were compared. "H6" represents a traditional inverter topology with 6 switching devices. "H10" represents an inverter topology with three clamping capacitors and 10 switching devices. "NCH10" represents the non-clamped H10 inverter topology proposed in this invention. In the simulation diagram, "RMS" represents the effective value, and "THD" represents the total harmonic distortion.

[0041] Figure 5-7 These are simulation results of the leakage current. (From...) Figure 5 As can be seen, the effective value of the leakage current of the traditional H6 topology reaches 343.2mA, which far exceeds the specified 300mA. The effective value of the leakage current of the H10 topology is 167.7mA. It can be seen that the topology improvement method can significantly reduce the leakage current value. Although this value already meets the requirement, the lower the leakage current, the better. The effective value of the leakage current of the NCH10 topology is only 105.8mA, which is less than that of the H6 and H10 topologies. Therefore, the simulation results can prove that the NCH10 topology is effective in suppressing leakage current.

[0042] Figure 8-10 These are simulation results for the grid-connected current. The purpose of this simulation is to verify the power quality of the grid-connected current in the NCH10 topology. Leakage current can overlap with the grid-connected current, thus affecting the power quality of the grid-connected current. Figure 8 The results shown are for the H6 topology, which has a grid-connected current THD of 3.25%, indicating a relatively high harmonic content. Figure 9 The current THD of the H10 topology is 1.65%, which is a significant improvement compared to the H6 topology. Figure 10 The results of the NCH10 topology in this invention are shown, which contains only 1.10% THD, and the harmonic content is significantly improved compared to the previous two. Therefore, the NCH10 topology can achieve better grid-connected current power quality.

[0043] In summary, the proposed NCH10 topology inverter can significantly reduce leakage current and has grid-connected current with fewer harmonics.

[0044] The above embodiments are merely illustrative of the technical concept and features of the present invention, intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. All equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for reducing leakage current in a grid-connected inverter based on a non-clamped H10 topology, characterized in that, First, a novel non-clamped H10 topology inverter is adopted; second, based on the traditional H6 topology control signal, the control signal for this topology is generated through logic function operations; this method can reduce the common-mode voltage by 66.7% and isolate the grid and power supply during zero vector, thereby significantly reducing leakage current. Specifically, it includes the following steps: Step 1: Adopt a new non-clamped H10 topology: This topology is constructed by adding 4 power switching transistors to the traditional H6 topology; Step 2, Signal Input: Real-time acquisition of inverter-side output current and grid voltage, coordinate transformation of the acquired voltage and current signals, and generation of phase-locked signals by phase-locked loop; Step 3: Generate reference voltage signal: Input the voltage, current and desired current signals after coordinate transformation into the current controller, and then perform inverse coordinate transformation on the output of the current controller to obtain the reference voltage signal; Step 4, Space Vector Pulse Width Modulation: Input the reference voltage signal into the SVPWM module to generate three control signals X, Y, and Z; Step 5: Control signal generation: The three control signals X, Y and Z are processed by logic functions to finally obtain the control signals for the non-clamped H10 topology, which are used to control the on and off of all power switches, thereby reducing the common-mode voltage. The novel non-clamped H10 topology inverter is described in the following structure: Based on the traditional H6 topology, a switch is added to each of the positive and negative buses after phase A, and two switches are used to connect the ends of the positive and negative buses to the output of phase A. Because this topology contains 10 switches, and compared with other H10 topologies that use clamping power supplies or clamping capacitors, this topology does not use any clamping elements. The method of generating control signals for a non-clamped H10 topology based on traditional H6 topology control signals through logic function operations is specifically implemented as follows: a. The reference voltage signal is input to the SVPWM module, which will output three control signals in the traditional H6 topology: X, Y and Z; b. The three control signals X, Y, and Z are processed by logic functions to ultimately obtain the non-clamped H10 topology control signals; the logic functions are as follows: In the formula, X, Y, and Z are the control signals of the three power switches on the traditional H6 topology output by the SVPWM module. T a1 , T a2 , T b1 , T b2 , T c1 , T c2 , T d1 , T d2 , T e1 , T e2 These are the control signals for the 10 power switches in the non-clamped H10 topology.

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