A frame synchronization error compensation method and system

Abstract

The application provides a frame synchronization error compensation processing method and system, the method comprises the following steps: measuring the PPS data width in the reference clock signal sent by the sending end, and expressing the PPS data width with the clock cycle number of the local clock generator of the receiving end; calculating the local clock cycle number and error value corresponding to the data width of the frame, half frame and time slot of the receiving end according to the PPS data width in the reference clock signal respectively, and adjusting the data width of the frame, half frame and time slot of the receiving end according to the error value respectively, so that the data time sequence of the PPS data, frame data and half frame data of the receiving end is aligned with the data time sequence of the PPS data, frame data and half frame data in the sending end. By using the technical scheme of the application, the precision of frame synchronization error compensation can be improved.

Description

Technical Field

[0001] This invention relates to the field of 5G communication, specifically to a frame synchronization error compensation processing method and system. Background Technology

[0002] In communication systems, synchronization is a crucial factor for the entire network, affecting data demodulation and normal system operation. Frame synchronization is used to align the reference clock and the local timer (wireless frame generator) to ensure that 5G (NR) data frames are transmitted as specified and that the device under test can demodulate them correctly.

[0003] Figure 1 This diagram illustrates the synchronization system between base station DU (Distributed Reference Unit) and RU (Remote Base Station Unit). The synchronization process is as follows: First, GPS clock parameters are configured in the DU and synchronized to the system clock. Then, synchronization to the RU's system clock is achieved via the PTP (Precision Time Protocol). Finally, the RU generates its own local clock signal. Because the RU's local clock may have errors compared to the GPS clock, this can lead to clock asynchrony between the RU and DU. Figure 2 As shown, DU-GPS-PPS is the PPS signal of the GPS at the DU end, DU-1588-PPS is the PPS signal generated by the DU end according to the PTP protocol and sent by the DU end, RU-1588-PPS is the PPS signal parsed by the RU end according to the PTP protocol based on the received DU-1588-PPS signal, and RU-Timer-SYNC is the synchronization signal generated by the local clock controller of the RU end based on the DU-1588-PPS signal.

[0004] To address the aforementioned issues, existing technologies typically configure the wireless frame timer register such that when a drift error is detected to exceed a program-defined threshold, the 10ms synchronization signal generated by the wireless frame timer is corrected and realigned with a reference 10ms synchronization signal. However, this existing method of setting a threshold in the wireless frame timer register to detect drift error suffers from low accuracy and insensitive error adjustment. Summary of the Invention

[0005] The purpose of this invention is to provide a frame synchronization error compensation method and system to improve the accuracy of frame synchronization error compensation.

[0006] In this embodiment of the invention, a frame synchronization error compensation method is provided, comprising:

[0007] The PPS data width in the reference clock signal emitted by the transmitter is measured and expressed as the number of clock cycles of the local clock generator at the receiver.

[0008] Based on the PPS data width in the reference clock signal, calculate the local clock cycle number and error value corresponding to the data width of the frame, half-frame and time slot at the receiving end, and adjust the data width of the frame, half-frame and time slot at the receiving end according to the error value, so that the PPS data, frame data and half-frame data at the receiving end are aligned with the PPS data, frame data and half-frame data at the transmitting end in terms of data timing.

[0009] In this embodiment of the invention, calculating the number of clock cycles and the error value of the frame data width at the receiving end includes:

[0010] Calculate the width of the frame data at the receiving end as b = a / 100 + c, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and c is the remainder if the division is not exact.

[0011] In this embodiment of the invention, adjusting the frame data width at the receiving end based on the error value includes:

[0012] Set the width of frame c in a local PPS of 100 frames to b+1, and set the width of the remaining frames to b, to ensure that the sum of the widths of the 100 frames in a local PPS is exactly the same as the width of a PPS in the reference clock signal.

[0013] In this embodiment of the invention, calculating the number of clock cycles and the error value of half-frame data width at the receiving end includes:

[0014] Calculate the width of the half-frame data at the receiving end: d = a / 200 + e, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and e is the remainder if the division is not exact.

[0015] In this embodiment of the invention, adjusting the width of half-frame data at the receiving end based on the error value includes:

[0016] Set the width of frame e in 200 half-frames of local TDD data width to d+1, and set the width of the remaining frames to d.

[0017] In this embodiment of the invention, calculating the number of clock cycles for the time slot data width at the receiving end includes:

[0018] Calculate the data width for each time slot f = a / 2000 + g, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and g is the remainder if the division is not exact.

[0019] In this embodiment of the invention, adjusting the time slot data width at the receiving end based on the error value includes:

[0020] Set the width of each local time slot to f. Calculate the error of a half-frame every ten time slots. Adjust the GP time slot of the TDD data according to the error value to ensure that the timing of the half-frame data at the receiving end and the transmitting end is aligned.

[0021] In this embodiment of the invention, the reference clock signal is a GPS clock signal.

[0022] In this embodiment of the invention, a frame synchronization error compensation system is also provided, which includes a transmitter and a receiver. When the receiver performs frame synchronization with the transmitter, the frame synchronization error compensation method is used.

[0023] Compared with existing technologies, the orthogonal error compensation processing method and system of the present invention first measures the PPS data width in the reference clock signal emitted by the transmitter and expresses it as the number of clock cycles of the local clock generator at the receiver. Then, based on the PPS data width in the reference clock signal, the number of clock cycles and error values ​​of the data width of the frame, half-frame, and time slot at the receiver are calculated respectively. Based on the error values, the data width of the frame, half-frame, and time slot at the receiver are adjusted respectively, so that the PPS data, frame data, and half-frame data at the receiver are aligned with the PPS data, frame data, and half-frame data at the transmitter. The local clock controller no longer operates with its own fixed mechanism, but determines the number of clock cycles per frame based on the number of clock cycles of each PPS. At the same time, other timing actions controlled by the local clock controller synchronously modify the number of clock cycles, thereby achieving frame synchronization between the transmitter and receiver. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the base station distributed unit and base station remote unit synchronization system.

[0025] Figure 2 This is a schematic diagram illustrating signal asynchrony between the distributed unit and the remote unit of the base station.

[0026] Figure 3 This is a flowchart illustrating the frame synchronization error compensation method according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of signal synchronization in the base station distributed unit and the base station remote unit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] The implementation of the present invention will be described in detail below with reference to specific embodiments.

[0030] like Figure 3 As shown in the figure, an embodiment of the present invention provides a frame synchronization error compensation method, which includes steps S1-S3. These are described below.

[0031] Step S1: Measure the PPS data width in the reference clock signal emitted by the transmitter and express it in terms of the number of clock cycles of the local clock generator at the receiver.

[0032] It should be noted that the embodiments of the present invention provide a method for achieving frame synchronization at the transmitting end and the receiving end, wherein the transmitting end and the receiving end can be respectively Figure 1 The base station distributed unit and base station remote unit in the 5G transceiver system can also be the transmitter and receiver in other wireless transceiver systems, and this invention does not limit them.

[0033] For 5G base station transceiver systems, the base station distributed unit uses the GPS signal as a reference clock signal. It generates a 1588 clock signal after synchronizing with the GPS signal, and then synchronizes this 1588 clock signal to the receiver via the PTP protocol. Finally, the receiver's local clock generates a clock cycle signal, which is synchronized with the GPS signal. Due to crystal oscillator instability, the clock frequency has errors. The clock cycle of the receiver's local clock signal may differ from the clock cycle of the GPS signal, resulting in inconsistent signal cycles between the receiver and transmitter, data timing misalignment, and desynchronization.

[0034] Considering this situation, in this embodiment of the invention, the width of one pps pulse interval of GPS is measured and expressed in terms of the number of local clock cycles, hereinafter referred to as a clock cycles.

[0035] Step S2: Calculate the number of clock cycles and error values ​​of the data width of the frame, half-frame and time slot at the receiving end according to the PPS data width in the reference clock signal.

[0036] It should be noted that in the 5G transmission protocol, after the DU and RU synchronize their GPS time, they are required to complete the transmission of 100 frames of data within 1 second, meaning all actions must be completed within 1pps. Therefore, the duration of each frame (10ms) is 1 / 100th of the 1pps duration. Specifically, the basic data transmission cycle is as follows:

[0037] 1 frame = 2 half frames = 10 subframes = 20 time slots.

[0038] In this embodiment of the invention, the number of clock cycles and the error value for calculating the data width of the frame, half-frame, and time slot at the receiving end are calculated as follows:

[0039] Calculate the width of the frame data at the receiving end as b = a / 100 + c, where a is the number of clock cycles of the local clock generator for the PPS data width in the reference clock signal, and c is the remainder if the division is not exact.

[0040] Calculate the width of the half-frame data at the receiving end: d = a / 200 + e, where e is the remainder if the division is not exact;

[0041] The data width of each time slot is calculated to be f = a / 2000 + g, where g is the remainder if the division is not exact.

[0042] Step S3: Adjust the data width of the frame, half-frame and time slot at the receiving end according to the error value, so that the PPS data, frame data and half-frame data at the receiving end are aligned with the PPS data, frame data and half-frame data at the transmitting end in terms of data timing.

[0043] Based on the clock cycle count and error value of the data width of the frame, half-frame, and time slot at the receiving end calculated in step S2, in this embodiment of the invention, the frame data width at the receiving end is adjusted according to the error value, including:

[0044] Set the width of frame c in a local PPS of 100 frames to b+1, and set the width of the remaining frames to b. Ensure that the sum of the widths of the 100 frames in a local PPS is exactly the same as the width of a PPS in the reference clock signal. After this adjustment, the timing synchronization of the PPS at the receiving end and the transmitting end can be achieved.

[0045] In this embodiment of the invention, adjusting the width of half-frame data at the receiving end based on the error value includes:

[0046] Set the width of frame e in one of the 200 half-frames of local TDD data width to d+1, and set the width of the remaining frames to d. After this adjustment, the timing alignment of the frame data between the receiver and transmitter can be achieved.

[0047] In this embodiment of the invention, adjusting the time slot data width at the receiving end based on the error value includes:

[0048] Set the width of each local time slot to f. Calculate the error of a half-frame every ten time slots. Adjust the GP time slot of the TDD data according to the error value to ensure that the timing of the half-frame data at the receiving end and the transmitting end is aligned.

[0049] After the above processing, the signals of RU and DU achieve frame synchronization, specifically as follows: Figure 4 As shown.

[0050] In this embodiment of the invention, a frame synchronization error compensation system is also provided, which includes a transmitter and a receiver. When the receiver performs frame synchronization with the transmitter, it adopts the above-mentioned frame synchronization error compensation method.

[0051] In summary, the orthogonal error compensation processing method and system of the present invention first measures the PPS data width in the reference clock signal emitted by the transmitter and expresses it as the number of clock cycles of the local clock generator at the receiver. Then, based on the PPS data width in the reference clock signal, the number of clock cycles and the error value of the data width of the frame, half-frame, and time slot at the receiver are calculated respectively. Based on the error value, the data width of the frame, half-frame, and time slot at the receiver are adjusted respectively, so that the PPS data, frame data, and half-frame data at the receiver are aligned with the PPS data, frame data, and half-frame data at the transmitter. The local clock controller no longer operates with its own fixed mechanism, but determines the number of clock cycles per frame based on the number of clock cycles of each PPS. At the same time, other timing actions controlled by the local clock controller synchronously modify the number of clock cycles, thereby achieving frame synchronization between the transmitter and receiver.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for compensating frame synchronization errors, characterized in that, include: The PPS data width in the reference clock signal emitted by the transmitter is measured and expressed as the number of clock cycles of the local clock generator at the receiver. Based on the PPS data width in the reference clock signal, calculate the local clock cycle number and error value corresponding to the data width of the frame, half-frame and time slot at the receiving end, and adjust the data width of the frame, half-frame and time slot at the receiving end according to the error value, so that the PPS data, frame data and half-frame data at the receiving end are aligned with the data timing of the PPS data, frame data and half-frame data at the transmitting end. Calculate the number of clock cycles and error value for the frame data width at the receiving end, including: Calculate the width of the frame data at the receiving end as b = a / 100 + c, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and c is the remainder if the division is not exact. Adjusting the frame data width at the receiving end based on the error value includes: Set the width of frame c out of 100 frames in a local PPS cycle to b+1, and set the width of the remaining frames to b, to ensure that the sum of the widths of the 100 frames in a local PPS cycle is exactly the same as the width of a PPS cycle in the reference clock signal.

2. The frame synchronization error compensation method as described in claim 1, characterized in that, Calculate the number of clock cycles and error value for the half-frame data width at the receiving end, including: Calculate the width of half-frame data at the receiving end: d = a / 200 + e, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and e is the remainder if the division is not exact.

3. The frame synchronization error compensation method as described in claim 2, characterized in that, Adjusting the width of half-frame data at the receiving end based on the error value includes: Set the width of frame e in 200 half-frames of local TDD data width to d+1, and set the width of the remaining frames to d.

4. The frame synchronization error compensation method as described in claim 1, characterized in that, The number of clock cycles required to calculate the data width of the time slot at the receiving end includes: Calculate the data width of each time slot f = a / 2000 + g, where a is the number of clock cycles of the local clock generator corresponding to the PPS data width in the reference clock signal, and g is the remainder if the division is not exact.

5. The frame synchronization error compensation method as described in claim 4, characterized in that, Adjusting the time slot data width at the receiving end based on the error value includes: Set the width of each local time slot to f. Calculate the error value of half a frame every ten time slots. Adjust the GP time slot of the TDD data according to the error value to ensure that the timing of the half-frame data at the receiving end and the transmitting end is aligned.

6. The frame synchronization error compensation method as described in claim 1, characterized in that, The reference clock signal is a GPS clock signal.

7. A frame synchronization error compensation system, characterized in that, It includes a transmitter and a receiver. When the receiver performs frame synchronization with the transmitter, it adopts the frame synchronization error compensation method as described in any one of claims 1-6.

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