Clock synchronization verification system, method, server, chip and electronic device

Abstract

The application provides a clock synchronization verification system, method, server, chip and electronic equipment, and relates to the technical field of communication. The clock synchronization verification system comprises a verification module, a measured master chip and a measured slave chip, the verification module communicates with the measured master chip and the measured slave chip; the measured master chip comprises a first time-providing module, a first sending end and a first receiving end, the measured slave chip comprises a second time-providing module, a second sending end and a second receiving end, the first sending end is connected with the second receiving end, the second sending end is connected with the first receiving end, and the verification module is used for verifying whether the clock of the measured master chip and the measured slave chip is synchronized according to the timing information and the hardware time of the measured master chip and the timing information and the hardware time of the measured slave chip. When the clock is not synchronized, the clock synchronization can be realized by adjusting the time in the measured master chip or the measured slave chip.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a clock synchronization verification system, method, server, chip, and electronic device. Background Technology

[0002] For wireless communication, clock synchronization between base stations is crucial. Currently, a commonly used clock calibration method is based on the IEEE 1588 protocol, which is a precision clock synchronization protocol standard for network measurement and control systems.

[0003] However, in communication services, when the master and slave devices transmit data, it is often necessary to process the data format of the transmitted data. Changes in the data format can cause delay jitter, affecting the precise clock synchronization of the chips in the master and slave devices, thereby reducing the data transmission efficiency between the master and slave devices. Data transmission between the master and slave devices mainly relies on data transmission between the running chips. Therefore, it is necessary to verify whether the clocks between the built-in chips of the master and slave devices are synchronized before the master and slave devices transmit data. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a clock synchronization verification system, method, server, chip and electronic device, which can specifically solve the existing chip clock synchronization verification problem.

[0005] Based on the above objectives, in a first aspect, this application proposes a clock synchronization verification system, the system comprising: a verification module, a master chip under test (DUT), and a slave chip under test (SUT), wherein the verification module communicates with the DUT and the SUT; the DUT includes a first timing module, a first transmitting end, and a first receiving end, and the SUT includes a second timing module, a second transmitting end, and a second receiving end, wherein the first transmitting end is connected to the second receiving end, and the second transmitting end is connected to the first receiving end; the first timing module is used to record when the DUT sends or receives messages. The timing information and hardware time of the tested master chip are recorded by the second timing module. The timing information and hardware time of the tested slave chip are recorded when the tested slave chip sends or receives a message. The hardware time of the tested master chip is used to calculate the link delay of the tested master chip, and the hardware time of the tested slave chip is used to calculate the link delay of the tested slave chip. The verification module is used to verify whether the clocks of the tested master chip and the tested slave chip are synchronized based on the timing information and hardware time of the tested master chip and the tested slave chip.

[0006] Optionally, the system further includes a first packet sending module, a first data acquisition module, a simulation operation module, a second packet sending module, and a second data acquisition module; the first packet sending module and the first data acquisition module are connected to the main chip under test, the second packet sending module and the second data acquisition module are connected to the slave chip under test, and the simulation operation module is connected to the first data acquisition module and the second data acquisition module respectively. The simulation operation module is used to simulate the functional execution process of the main chip under test based on the data acquired by the first data acquisition module and the second data acquisition module.

[0007] Secondly, a clock synchronization verification method is also provided, applied to the clock synchronization verification system described in the first aspect. The method includes: acquiring first data when a first message is transmitted between a master chip under test and a slave chip under test, the first message being sent by the master chip under test; obtaining, based on the first data, the time when the first message leaves the master chip under test and the time when the first message arrives at the slave chip under test; acquiring second data when a second message is transmitted between the slave chip under test and the master chip under test, the second message being sent by the slave chip under test; obtaining, based on the second data, the time when the second message leaves the slave chip under test and the time when the second message arrives at the master chip under test; obtaining a first time difference based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test; and determining the clock verification result between the master chip under test and the slave chip under test based on the first time difference.

[0008] Optionally, the first data includes the first timing information and first hardware time of the master chip under test when it sends the first message to the slave chip under test, and the second timing information, second hardware time, and first timestamp information of the slave chip under test when it receives the first message. The method includes: obtaining the link delay of the master chip under test based on the first hardware time; obtaining the time when the first message leaves the master chip under test based on the link delay and the first timing information; obtaining the link delay of the slave chip under test based on the second hardware time and the first timestamp information; and obtaining the time when the first message arrives at the slave chip under test based on the link delay and the second timing information.

[0009] Optionally, the second data includes the third timing information and third hardware time of the slave chip under test when it sends the second message to the master chip under test, and the fourth timing information, fourth hardware time, and second timestamp information of the master chip under test when it receives the second message. The method includes: obtaining the link delay of the slave chip under test based on the third hardware time; obtaining the time when the second message leaves the slave chip under test based on the link delay and the third timing information; obtaining the link delay of the master chip under test based on the fourth hardware time and the second timestamp information; and obtaining the time when the second message arrives at the master chip under test based on the link delay and the fourth timing information.

[0010] Optionally, the method includes: obtaining the simulation time of the master chip under test and the simulation time of the slave chip under test at a preset time; obtaining a second time difference based on the simulation time of the master chip under test and the simulation time of the slave chip under test; and determining the clock verification result between the master chip under test and the slave chip under test based on the deviation between the second time difference and the first time difference.

[0011] Thirdly, a clock synchronization verification server is also provided, comprising: a first data module, configured to acquire first data when a first message is transmitted between a master chip under test and a slave chip under test, wherein the first message is sent by the master chip under test; a first calculation module, configured to obtain, based on the first data, the time when the first message leaves the master chip under test and the time when the first message arrives at the slave chip under test; a second data module, configured to acquire second data when a second message is transmitted between the slave chip under test and the master chip under test, wherein the second message is sent by the slave chip under test; a second calculation module, configured to obtain, based on the second data, the time when the second message leaves the slave chip under test and the time when the second message arrives at the master chip under test; and a verification module, configured to obtain a first time difference based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test, and determine the clock verification result between the master chip under test and the slave chip under test based on the first time difference.

[0012] Fourthly, a chip is also provided, the chip including a master chip under test and a slave chip under test; the master chip under test or the slave chip under test is used to acquire time data between the master chip under test and the slave chip under test, and to obtain a clock verification result between the master chip under test and the slave chip under test based on the time data; wherein, the time data includes first timing information and first hardware time of the master chip under test when it sends a first message to the slave chip under test, second timing information, second hardware time and first timestamp information of the slave chip under test when it receives the first message; and third timing information and third hardware time of the slave chip under test when it sends a second message to the master chip under test, and fourth timing information, fourth hardware time and second timestamp information of the master chip under test when it receives the second message.

[0013] Fifthly, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the method described in the second aspect.

[0014] In a sixth aspect, a computer-readable storage medium is also provided, having a computer program stored thereon, the program being executed by a processor to implement the method described in any of the second aspects.

[0015] In summary, this application has at least the following beneficial effects:

[0016] The clock synchronization verification system provided in this embodiment constitutes a clock verification platform, providing a verification environment for chip clock verification. When the chip is in the verification environment, the timing information and hardware time of the master chip under test and the timing information and hardware time of the slave chip under test are obtained to verify whether the clocks of the master chip under test and the slave chip under test are synchronized. When the clocks are not synchronized, clock synchronization can be achieved by adjusting the internal time of the master chip under test or the slave chip under test. Attached Figure Description

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0018] Figure 1 This diagram illustrates the structure of the clock synchronization verification system of this application.

[0019] Figure 2 This diagram illustrates the clock synchronization principle of this embodiment.

[0020] Figure 3This diagram illustrates the steps of the clock synchronization verification method in this embodiment.

[0021] Figure 4 This diagram illustrates the structure of a clock synchronization verification server according to an embodiment of this application.

[0022] Figure 5 This illustration shows a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0023] Figure 6 A schematic diagram of a storage medium provided in one embodiment of this application is shown. Detailed Implementation

[0024] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Figure 1 This diagram illustrates the structure of the clock synchronization verification system of this application. In an embodiment of this application, the clock synchronization verification system 100 includes: a verification module 103, a master chip under test 101, and a slave chip under test 102. The verification module communicates with the master chip under test 101 and the slave chip under test 102.

[0027] In this embodiment, the clock synchronization verification system 100 can constitute a clock verification platform. When the master chip 101 and the slave chip 102 under test are in the verification environment, the data acquired during the verification process of the master chip 101 and the slave chip 102 under test can be used to verify whether the clocks of the master chip and the slave chip are synchronized. The verification module in this embodiment can be a processor or an integrated module with data functions. The verification module communicates with the master chip and the slave chip under test through the same Ethernet.

[0028] In this embodiment, the main chip under test 101 includes a first timing module 104, a first transmitting end tx1 and a first receiving end rx1, and the slave chip under test 102 includes a second timing module 105, a second transmitting end tx2 and a second receiving end rx2. The first transmitting end tx1 is connected to the second receiving end rx2, and the second transmitting end tx2 is connected to the first receiving end rx1.

[0029] In this embodiment, the first timing module 104 can be a PTP module, i.e., a standardized picture transfer protocol (PTP), which is a timing module inside the chip. The first timing module 104 is used to record the timing information and hardware time of the master chip under test when it sends or receives messages. Similarly, the second timing module 105 is used to record the timing information and hardware time of the slave chip under test when it sends or receives messages.

[0030] In this embodiment, the first transmitting end tx1 is used to send the data of the master chip under test to the second receiving end rx2 of the slave chip under test, and the second transmitting end tx2 is used to send the data of the slave chip under test to the first receiving end rx1 of the master chip under test, thereby enabling the master chip under test 101 and the slave chip under test 102 to be in the same network, realizing data transmission between the master chip under test and the slave chip under test, and detecting whether the clocks between the master chip and the slave chip are synchronized based on the time parameters during the data interaction process.

[0031] In this embodiment, the timing information and hardware time of the tested main chip are time information recorded using different timing methods. For example, when the tested main chip sends a 1588 message to the tested slave chip, the processing module obtains the TOD timing information and hardware time hw_time1 from the first timing module. The TOD timing information includes multiple timing unit information such as s, ns, and ns decimal information. When the ns time reaches 10 to the power of 9, the s bit will be incremented by 1, and the ns will start counting again from 0. hw_time1 contains ns information and will accumulate continuously in units of ns.

[0032] In this embodiment, hardware time is used to calculate link latency. The hardware time of the master chip under test is used to calculate the link latency of the master chip under test, and the hardware time of the slave chip under test is used to calculate the link latency of the slave chip under test. Link latency can be the time required for data transmission delay due to data format conversion or hardware configuration during data transmission within the chip.

[0033] In this embodiment, the verification module is used to verify whether the clocks of the master chip and the slave chip under test are synchronized based on the timing information and hardware time of the master chip under test, and the timing information and hardware time of the slave chip under test.

[0034] refer to Figure 1In this embodiment, the clock synchronization verification system further includes a first packet sending module, a first data acquisition module, a simulation operation module, a second packet sending module, and a second data acquisition module. The first packet sending module and the first data acquisition module are connected to the main chip under test, the second packet sending module and the second data acquisition module are connected to the slave chip under test, and the simulation operation module is connected to the first data acquisition module and the second data acquisition module respectively. The simulation operation module is used to simulate the functional execution process of the main chip under test and the main chip under test based on the data acquired by the first data acquisition module and the second data acquisition module.

[0035] In one example, both the first packet sending module and the second packet sending component include a packet sending component for sending 1588 messages from the master chip under test to the slave chip under test. The second packet sending module is used to send 1588 messages from the slave chip under test to the master chip under test. The first data acquisition module is used to acquire the input and output data of the master chip under test. The second data acquisition module is used to acquire the input and output data of the slave chip under test. The simulation operation module is used to simulate the functional execution process of the master chip under test and the slave chip under test. The simulation operation module can be a reference model (rm), which is used to simulate the executable program of the simulation simulator hardware corresponding to the chip under test.

[0036] In one example, both the master chip under test and the slave chip under test include MAC, pcs, and serdes. MAC is the protocol data interface used to receive message data packets, pcs is the physical encoding layer used for encoding, and serdes is the serializer / deserializer.

[0037] The clock synchronization verification system provided in this embodiment constitutes a clock verification platform, providing a verification environment for chip clock verification. When the chip is in the verification environment, the timing information and hardware time of the master chip under test and the timing information and hardware time of the slave chip under test are obtained to verify whether the clocks of the master chip under test and the slave chip under test are synchronized. When the clocks are not synchronized, clock synchronization can be achieved by adjusting the internal time of the master chip under test or the slave chip under test.

[0038] Figure 2 The diagram illustrates the clock synchronization principle of this embodiment. Here, delay is the link delay, delta is the time difference between the master chip and the slave chip under test, t1 is the time the packet leaves the master chip under test, t2 is the time the packet arrives at the slave chip under test, t3 is the time the packet leaves the slave chip under test, and t4 is the time the packet arrives at the master chip under test.

[0039] according to Figure 2We know that t2 = t1 + delay + delta, t4 = t3 + delay - delta. Subtracting the two equations, we get delta = ((t2 + t3) - (t1 + t4)) / 2, and thus we can obtain the time difference delta between the master chip and the slave chip under test.

[0040] based on Figure 1 The clock synchronization verification system shown and Figure 2 The clock synchronization principle shown is as follows: Figure 3 This embodiment illustrates a flowchart of the clock synchronization verification method. This embodiment also provides a clock synchronization verification method applied to… Figure 1 The clock synchronization verification system shown is referenced. Figure 3 The clock synchronization verification method includes the following steps S301 to S305:

[0041] S301. Obtain the first data when the first message is transmitted between the master chip under test and the slave chip under test.

[0042] In this embodiment, the first message is sent by the master chip under test, and the first data includes the first timing information and the first hardware time of the master chip under test when it sends the first message to the slave chip under test, and the second timing information, the second hardware time, and the first timestamp information of the slave chip under test when it receives the first message.

[0043] For example, when the master chip under test sends the first message to the slave chip under test, the master chip under test's first timing information is T1 and the first hardware time is hw_time1. T1 is stored in the message, and hw_time1 is sent to the master chip under test by the first packet sending module driver through the interface. After receiving the first message, the master chip under test calculates the link delay Δt1 of MAC, PCS, and SERDES according to the configuration of the master chip under test's internal link, and writes the delay Δt1 into the correction field of 1588. When the slave chip under test receives the first message sent by the master chip under test, it transmits the timestamp information of the first message arrival to the second data acquisition module through the interface. The second data acquisition module obtains the second timing information T2 and the second hardware time hw_time2 from the second timing module. Therefore, the first data includes the first timing information T1, the first hardware time hw_time1, the second timing information T2, the second hardware time hw_time2, and the first timestamp information timestamp1.

[0044] S302. Based on the first data, obtain the time when the first message leaves the tested master chip and the time when the first message arrives at the tested slave chip.

[0045] In this embodiment, the link delay of the tested main chip is obtained based on the first hardware time, and the time when the first message leaves the tested main chip is obtained based on the link delay of the tested main chip and the first timing information. It can be understood that, due to the existence of the link delay Δt1, the time t1 when the first message is sent from the first transmitting end of the tested main chip is t1 = T1 + Δt1, and T1 and Δt1 can be parsed from the first message.

[0046] The link delay of the slave chip under test is obtained based on the second hardware time and the first timestamp information. The arrival time of the first message at the slave chip under test is obtained based on the link delay and the second timing information. It can be understood that since the first timestamp information (timestamp1) is the hardware time of the second timing module when the first message arrives at the first receiving end, and the second hardware time (hw_time2) is the time when the second data acquisition module receives the message, the time between the message arriving at the slave chip under test and leaving the slave chip under test and being received by the second data acquisition module can be used as the link delay of the slave chip under test, denoted as (hw_time2-timestamp1). In this embodiment, the second timing information is T2, so the arrival time of the first message at the slave chip under test can be expressed as t2 = T2 - (hw_time2-timestamp1).

[0047] S303. Obtain the second data when the second message is transmitted between the slave chip under test and the master chip under test.

[0048] In this embodiment, the second message is sent by the slave chip under test. The second data includes the third timing information and third hardware time of the slave chip under test when it sends the second message to the master chip under test, and the fourth timing information, fourth hardware time, and second timestamp information of the master chip under test when it receives the second message.

[0049] For example, when the slave chip under test sends a second message to the master chip under test, the slave chip's third timing information is T3 and the third hardware time hw_time3. T3 is stored in the message, and hw_time3 is sent to the slave chip by the second packet sending module through the interface. After receiving the second message, the slave chip calculates the link delay Δt2 of MAC, PCS, and SERDES according to the configuration of the internal link of the slave chip, and writes the delay Δt2 into the correction field of 1588. When the master chip under test receives the second message from the slave chip, it transmits the timestamp information timestamp2 of the second message to the first data acquisition module through the interface. The first data acquisition module obtains the fourth timing information T4 and the fourth hardware time hw_time4 from the first timing module. Therefore, the second data includes the third timing information T3, the third hardware time hw_time3, the fourth timing information T4, the fourth hardware time hw_time4, and the second timestamp information timestamp2.

[0050] S304. Based on the second data, obtain the time when the second message leaves the tested slave chip and the time when the second message arrives at the tested master chip.

[0051] In this embodiment, the link delay of the slave chip under test is obtained based on the third hardware time, and the time when the second message leaves the slave chip under test is obtained based on the link delay of the slave chip under test and the third timing information. It can be understood that, due to the existence of the link delay Δt2, the time t3 when the second message is sent from the second transmitting end of the slave chip under test is t3 = T3 + Δt2, and T3 and Δt2 can be obtained from the second message.

[0052] The link delay of the tested main chip is obtained based on the fourth hardware time and the second timestamp information. The arrival time of the second message at the tested main chip is then obtained based on the link delay and the fourth timing information. It can be understood that since the second timestamp information (timestamp2) is the hardware time of the first timing module when the second message arrives at the second receiving end, and the fourth hardware time (hw_time4) is the time when the first data acquisition module receives the message, the time between the message arriving at the tested main chip and leaving the tested main chip and being received by the first data acquisition module can be used as the link delay of the tested main chip, denoted as (hw_time4 - timestamp2). In this embodiment, the second timing information is T4, so the arrival time of the first message at the tested slave chip can be expressed as t4 = T4 - (hw_time4 - timestamp2).

[0053] S305. Based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test, a first time difference is obtained, and the clock verification result between the master chip under test and the slave chip under test is determined based on the first time difference.

[0054] In this embodiment, the representations of t1, t2, t3, and t4 can be obtained from steps S301 to S304, combined with... Figure 2 As can be seen from the original, the first time difference between the tested master chip and the tested slave chip is:

[0055] delta_cal=((t2+t3)-(t1+t4)) / 2

[0056] The clock verification result between the tested master chip and the tested slave chip is determined based on the first time difference. This can be determined by the magnitude of the first time difference and the preset value. For example, the greater the difference between the first time difference and the preset value, the more it indicates that the time of the tested master chip and the tested slave chip is out of sync. When the first time difference is less than the preset value, it indicates that the time synchronization accuracy of the tested master chip and the tested slave chip meets the requirements.

[0057] When the clock verification result indicates that the clocks of the tested master chip and the tested slave chip are out of sync, the time difference between the two chips can be adjusted by adjusting the TOD time information of the tested master chip and the tested slave chip, that is, by adjusting the timing information of the tested master chip or the timing information of the tested slave chip.

[0058] The clock synchronization verification provided in the above embodiments is an ideal test process and adjustment method. In practical application environments, such as the UVM (Universal Verification Methodology) environment, considering that the time difference between the master chip and the slave chip under test can be directly obtained, and that the clocks of the master chip and the slave chip under test are self-provided clocks, complete frequency synchronization can be achieved. After one adjustment, the clocks of the master chip and the slave chip under test can be kept completely synchronized, and the significance of multiple tests and adjustments is not great. Therefore, this embodiment also provides a method for verifying the clock between the master chip and the slave chip under test using simulated time data, which can be used to verify the clock between the master chip and the slave chip under test in practical applications.

[0059] In this embodiment, clock synchronization verification further includes obtaining the simulation time of the master chip under test and the simulation time of the slave chip under test at a preset time; obtaining a second time difference based on the simulation time of the master chip under test and the simulation time of the slave chip under test; and determining the clock verification result between the master chip under test and the slave chip under test based on the deviation between the second time difference and the first time difference.

[0060] For example, when the TOD time of the master chip and the slave chip under test is timed to a certain point, such as 100ns, the simulation time realtime1 and realtime2 of the UVM platform are recorded respectively. Then, the second time difference delta_real = realtime1 - realtime2. At this time, delta_cal is obtained according to the clock synchronization verification method of the above embodiment. Data packets are sent in multiple rounds. The difference between delta_real and delta_cal is compared in each round of packet transmission. By repeatedly sending multiple rounds of packets, it is verified whether the clocks of the master chip and the slave chip under test are synchronized. At the same time, it can be verified whether the timestamp accuracy of the master chip and the slave chip under test can meet the expectations. When the deviation between the second time difference and the first time difference is within the preset range, it can be determined that the clocks of the master chip and the slave chip under test are synchronized. At the same time, it can also prove that the clock synchronization verification method of the above embodiment is correct.

[0061] Furthermore, the above describes the clock verification of the master chip and slave chip under test in the verification environment according to this embodiment. The time data of the master chip and slave chip under test can be acquired by the first data acquisition module or the second data acquisition module, and then processed by the processing module. However, in actual sample testing, since the time information of the master chip and slave chip under test is isolated from each other, all time information needs to be sent to the same chip for processing and calculation. For example, if all time information is sent to the slave chip under test for calculation, when the master chip under test receives a message from the slave chip under test, the slave chip under test cannot know the TOD time when the master chip under test receives the message. At this time, the master chip under test needs to send the TOD time of the master chip under test to the slave chip under test in the form of a 1588 message for calculation. That is to say, the chip under test that has not performed calculation processing needs to send a message once more. It should be noted that in actual sample testing, in order to synchronize the two clocks, the clocks of the master chip and slave chip under test need to be kept from the same source. Specifically, the master chip and the slave chip can be set on the same test circuit and connected to the same crystal oscillator to keep the clocks of the master chip and the slave chip under test from the same source.

[0062] The above describes the clock synchronization verification method provided in this embodiment. It involves acquiring first data when a first message is transmitted between the master chip under test and the slave chip under test, and obtaining the time when the first message leaves the master chip under test and the time when the first message arrives at the slave chip under test based on the first data. It also involves acquiring second data when a second message is transmitted between the slave chip under test and the master chip under test, and obtaining the time when the second message leaves the slave chip under test and the time when the second message arrives at the master chip under test based on the second data. A first time difference is then obtained based on the above data, and the clock verification result between the master chip under test and the slave chip under test is determined based on the first time difference. When the clocks of the master chip under test and the slave chip under test are not synchronized, clock synchronization can be achieved by adjusting the timing modules of the master chip under test and the slave chip under test.

[0063] Figure 4 This is a schematic diagram of a clock synchronization verification server provided in this embodiment, used to execute the clock synchronization verification method described in the above embodiment, such as... Figure 4 As shown, the clock synchronization verification server 400 includes:

[0064] The first data module 401 is used to acquire first data when the master chip under test and the slave chip under test transmit the first message, wherein the first message is sent by the master chip under test.

[0065] The first calculation module 402 is used to obtain, based on the first data, the time when the first message leaves the tested master chip and the time when the first message arrives at the tested slave chip.

[0066] The second data module 403 is used to acquire second data when the second message is transmitted between the slave chip under test and the master chip under test, wherein the second message is sent by the slave chip under test.

[0067] The second calculation module 404 is used to obtain, based on the second data, the time when the second message leaves the tested slave chip and the time when the second message arrives at the tested master chip;

[0068] The verification module 405 is used to obtain a first time difference based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test, and to determine the clock verification result between the master chip under test and the slave chip under test based on the first time difference.

[0069] In one example, the first data includes the first timing information and first hardware time of the master chip under test when it sends the first message to the slave chip under test, and the second timing information, second hardware time, and first timestamp information of the slave chip under test when it receives the first message. The first calculation module 402 is used to obtain the link delay of the master chip under test based on the first hardware time, obtain the time when the first message leaves the master chip under test based on the link delay and the first timing information, obtain the link delay of the slave chip under test based on the second hardware time and the first timestamp information, and obtain the time when the first message arrives at the slave chip under test based on the link delay and the second timing information.

[0070] In one example, the second data includes the third timing information and third hardware time of the slave chip under test when it sends the second message to the master chip under test, and the fourth timing information, fourth hardware time, and second timestamp information of the master chip under test when it receives the second message. The second calculation module 404 is used to obtain the link delay of the slave chip under test based on the third hardware time, and to obtain the time when the second message leaves the slave chip under test based on the link delay and the third timing information; to obtain the link delay of the master chip under test based on the fourth hardware time and the second timestamp information, and to obtain the time when the second message arrives at the master chip under test based on the link delay and the fourth timing information.

[0071] In one example, the verification module 405 is used to obtain the simulation time of the master chip under test and the simulation time of the slave chip under test at a preset time, obtain a second time difference based on the simulation time of the master chip under test and the simulation time of the slave chip under test, and determine the clock verification result between the master chip under test and the slave chip under test based on the deviation between the second time difference and the first time difference.

[0072] The clock synchronization verification server provided in the above embodiments of this application and the clock synchronization verification method provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the applications stored therein.

[0073] This embodiment also provides a chip, which includes a master chip and a slave chip. ，The master chip in this embodiment is the master chip under test (DUT) provided in the above embodiments, and the slave chip in this embodiment is the slave chip under test (DUT) provided in the above embodiments. The master chip or slave chip is used to acquire time data between the master chip and the slave chip, and to obtain the clock verification result between the master chip under test and the slave chip under test based on the time data. In other words, the master chip can act as the execution entity for obtaining the clock verification result between the master chip under test and the slave chip under test based on the time data, and the slave chip can also act as the execution entity for obtaining the clock verification result between the master chip under test and the slave chip under test based on the time data.

[0074] The time data includes: when the master chip under test sends a first message to the slave chip under test, the first timing information and the first hardware time of the master chip under test; when the slave chip under test receives the first message, the second timing information, the second hardware time, and the first timestamp information of the slave chip under test; and when the slave chip under test sends a second message to the master chip under test, the third timing information and the third hardware time of the slave chip under test; and when the master chip under test receives the second message, the fourth timing information, the fourth hardware time, and the second timestamp information of the master chip under test.

[0075] For example, in actual sample testing, since the time information of the master chip under test (DUT) and the slave chip under test (DUT) is isolated from each other, all time information needs to be sent to the same chip for processing and calculation. For instance, if all time information is sent to the slave chip under test for calculation, when the master chip under test receives a message from the slave chip under test, the slave chip cannot know the TOD (Time of Detail) when the master chip under test receives the message. In this case, the master chip under test needs to send its own TOD time in a 1588-message format to the slave chip under test for calculation. That is, the chip under test that hasn't yet undergone calculation needs to send an extra message. It should be noted that in actual sample testing, to synchronize the two clocks, the clocks of the master chip under test and the slave chip under test must be from the same source. Specifically, the master chip and the slave chip can be placed on the same test circuit and connected to the same crystal oscillator to ensure that their clocks are from the same source.

[0076] This application also provides an electronic device corresponding to the clock synchronization verification method provided in the foregoing embodiments, for executing the aforementioned clock synchronization verification method. This application does not limit the scope of the embodiments.

[0077] Please refer to Figure 5 This illustrates a schematic diagram of an electronic device provided by some embodiments of this application. For example... Figure 5As shown, the electronic device 20 includes: a processor 200, a memory 201, a bus 202, and a communication interface 203. The processor 200, the communication interface 203, and the memory 201 are connected via the bus 202. The memory 201 stores a computer program that can run on the processor 200. When the processor 200 runs the computer program, it executes the clock synchronization verification method provided in any of the foregoing embodiments of this application.

[0078] The memory 201 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 203 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0079] Bus 202 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs. After receiving an execution instruction, the processor 200 executes the program. The clock synchronization verification method disclosed in any of the foregoing embodiments of this application can be applied to the processor 200, or implemented by the processor 200.

[0080] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the above method.

[0081] The electronic device provided in this application embodiment and the clock synchronization verification method provided in this application embodiment are based on the same inventive concept and have the same beneficial effects as the methods they adopt, operate or implement.

[0082] This application also provides a computer-readable storage medium corresponding to the clock synchronization verification method provided in the foregoing embodiments. Please refer to... Figure 6 The computer-readable storage medium shown is an optical disc 30, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it executes the clock synchronization verification method provided in any of the foregoing embodiments.

[0083] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0084] The computer-readable storage medium provided in the above embodiments of this application and the clock synchronization verification method provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the applications stored therein.

[0085] It should be noted that:

[0086] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0087] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0088] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0089] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0090] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0091] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the virtual machine creation system according to the embodiments of this application. This application can also be implemented as a device or system program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0092] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A clock synchronization verification system, characterized in that, The system includes: a verification module, a master chip under test, and a slave chip under test, wherein the verification module communicates with the master chip under test and the slave chip under test; The tested master chip includes a first timing module, a first transmitting end and a first receiving end, and the tested slave chip includes a second timing module, a second transmitting end and a second receiving end, wherein the first transmitting end is connected to the second receiving end and the second transmitting end is connected to the first receiving end; The first timing module is used to record the timing information and hardware time of the master chip under test when it sends or receives a message. The second timing module is used to record the timing information and hardware time of the slave chip under test when it sends or receives a message. The difference between the hardware time of the master chip under test and the timestamp information recorded when the master chip under test receives a message is used to calculate the link delay of the master chip under test. The difference between the hardware time of the slave chip under test and the timestamp information recorded when the slave chip under test receives a message is used to calculate the link delay of the slave chip under test. The verification module is used to verify whether the clocks of the master chip under test and the slave chip under test are synchronized based on the timing information and hardware time of the master chip under test and the timing information and hardware time of the slave chip under test.

2. The system according to claim 1, characterized in that, The system also includes a first packet sending module, a first data acquisition module, a simulation operation module, a second packet sending module, and a second data acquisition module; The first packet sending module and the first data acquisition module are connected to the main chip under test, the second packet sending module and the second data acquisition module are connected to the slave chip under test, and the simulation operation module is connected to the first data acquisition module and the second data acquisition module respectively. The simulation operation module is used to simulate the functional execution process of the main chip under test based on the data acquired by the first data acquisition module and the second data acquisition module.

3. A clock synchronization verification method, characterized in that, The method is applied to the clock synchronization verification system according to claim 1 or 2, and the method includes: Acquire the first data when the first message is transmitted between the master chip under test and the slave chip under test, wherein the first message is sent by the master chip under test; Based on the first data, the time when the first message leaves the tested master chip and the time when the first message arrives at the tested slave chip are obtained. Acquire second data when a second message is transmitted between the slave chip under test and the master chip under test, wherein the second message is sent by the slave chip under test; Based on the second data, the time when the second message leaves the tested slave chip and the time when the second message arrives at the tested master chip are obtained. A first time difference is obtained based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test. The clock verification result between the master chip under test and the slave chip under test is determined based on the first time difference.

4. The method according to claim 3, characterized in that, The first data includes the first timing information and first hardware time of the master chip under test when it sends the first message to the slave chip under test, and the second timing information, second hardware time, and first timestamp information of the slave chip under test when it receives the first message. The first timestamp information is the hardware time of the second timing module when the first message arrives at the first receiving end. The method includes: The link delay of the tested main chip is obtained based on the first hardware time, and the time when the first packet leaves the tested main chip is obtained based on the link delay of the tested main chip and the first timing information. The link delay of the slave chip under test is obtained based on the second hardware time and the first timestamp information of the slave chip under test, and the time when the first message arrives at the slave chip under test is obtained based on the link delay and the second timing information of the slave chip under test.

5. The method according to claim 3, characterized in that, The second data includes the third timing information and third hardware time of the slave chip under test when it sends the second message to the master chip under test, and the fourth timing information, fourth hardware time, and second timestamp information of the master chip under test when it receives the second message. The second timestamp information is the hardware time of the first timing module when the second message arrives at the second receiving end. The method includes: The link delay of the tested slave chip is obtained based on the third hardware time, and the time when the second message leaves the tested slave chip is obtained based on the link delay of the tested slave chip and the third timing information. The link delay of the main chip under test is obtained based on the fourth hardware time and the second timestamp information of the main chip under test. The time when the second message arrives at the main chip under test is obtained based on the link delay of the main chip under test and the fourth timing information.

6. The method according to claim 3, characterized in that, The method includes: The simulation time of the master chip under test and the simulation time of the slave chip under test are obtained at a preset time. Based on the simulation time of the master chip under test and the simulation time of the slave chip under test, a second time difference is obtained. The clock verification result between the tested master chip and the tested slave chip is determined based on the deviation between the second time difference and the first time difference.

7. A clock synchronization verification server, characterized in that, The server is used to execute the clock synchronization verification method according to any one of claims 3-6, and the server comprises: The first data module is used to acquire first data when the first message is transmitted between the main chip under test and the slave chip under test, wherein the first message is sent by the main chip under test. The first calculation module is used to obtain, based on the first data, the time when the first message leaves the tested master chip and the time when the first message arrives at the tested slave chip; The second data module is used to acquire second data when the second message is transmitted between the slave chip under test and the master chip under test, wherein the second message is sent by the slave chip under test. The second calculation module is used to obtain, based on the second data, the time when the second message leaves the tested slave chip and the time when the second message arrives at the tested master chip; The verification module is used to obtain a first time difference based on the time when the first message leaves the master chip under test, the time when the first message arrives at the slave chip under test, the time when the second message leaves the slave chip under test, and the time when the second message arrives at the master chip under test, and to determine the clock verification result between the master chip under test and the slave chip under test based on the first time difference.

8. A chip, characterized in that, The chip includes a master chip under test and a slave chip under test; The tested master chip or the tested slave chip is used to acquire time data between the tested master chip and the tested slave chip, and to obtain clock verification results between the tested master chip and the tested slave chip based on the time data; and to verify whether the clocks of the tested master chip and the tested slave chip are synchronized based on the timing information and hardware time of the tested master chip and the timing information and hardware time of the tested slave chip. The time data includes: when the master chip under test sends a first message to the slave chip under test, the first timing information and the first hardware time of the master chip under test; when the slave chip under test receives the first message, the second timing information, the second hardware time, and the first timestamp information of the slave chip under test; and when the slave chip under test sends a second message to the master chip under test, the third timing information and the third hardware time of the slave chip under test; and when the master chip under test receives the second message, the fourth timing information, the fourth hardware time, and the second timestamp information of the master chip under test. The first timestamp information is the hardware time of the second timing module when the first message arrives at the first receiving end, and the second timestamp information is the hardware time of the first timing module when the second message arrives at the second receiving end.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 3-6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by a processor to implement the method as described in any one of claims 3-6.

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