Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes providing a substrate, the substrate including a plurality of spaced-apart active regions; forming a plurality of conductive structures, the conductive structures being spaced-apart on the substrate, with some conductive structures connected to and electrically conductive with the active regions; forming a first isolation layer, the first isolation layer being located on the top and sides of the conductive structures; and forming a first dielectric layer, the first dielectric layer being located on the top surface of the first isolation layer; wherein the conductive structures, the first isolation layer, and the first dielectric layer together form a bit line structure. Because the first dielectric layer of the bit line structure is formed outside the first isolation layer, the height of the bit line structure covered by the first isolation layer is smaller, thereby reducing the aspect ratio of the bit line structure covered by the first isolation layer. Therefore, the method for fabricating the semiconductor structure and the semiconductor structure provided by this disclosure can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] In related technologies, DRAM may include a substrate on which multiple repeating memory cells are disposed. Each memory cell may include a transistor and a capacitor, with the transistor's gate connected to a word line, its source connected to a bit line, and its drain connected to the capacitor. A voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor via the bit line, or writing data information into the capacitor for storage via the bit line.

[0004] However, the aforementioned bit lines are prone to deformation, which can affect the performance of the bit lines and DRAM. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure that can improve the performance of the semiconductor structure.

[0006] The embodiments disclosed herein provide the following technical solutions:

[0007] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0008] A substrate is provided, the substrate comprising a plurality of spaced active regions;

[0009] Multiple conductive structures are formed, and these conductive structures are arranged at intervals on the substrate. Some of the conductive structures are connected to the active region and are electrically conductive.

[0010] A first isolation layer is formed, which is located on the top and sides of the conductive structure;

[0011] A first dielectric layer is formed, and the first dielectric layer is located on the top surface of the first isolation layer;

[0012] In this structure, the conductive structure, the first isolation layer, and the first dielectric layer together form a bit line structure.

[0013] The semiconductor structure fabrication method provided in this disclosure includes: providing a substrate, the substrate including a plurality of active regions spaced apart; forming a plurality of conductive structures, the conductive structures being spaced apart on the substrate, with some conductive structures connected to and electrically conductive with the active regions; forming a first isolation layer, the first isolation layer being located on the top and side of the conductive structures; and forming a first dielectric layer, the first dielectric layer being located on the top surface of the first isolation layer; wherein the conductive structures, the first isolation layer, and the first dielectric layer together form a bit line structure. Because the first dielectric layer of the bit line structure is formed outside the first isolation layer, the height of the portion of the bit line structure covered by the first isolation layer is smaller, thereby reducing the aspect ratio of the portion of the bit line structure covered by the first isolation layer. For example, during plasma etching of the bitline structure covered by the first isolation layer, cations in the plasma, under the influence of the electric field of the ion sheath, may collide with the sidewalls of this part of the bitline structure. Because the aspect ratio of this part of the bitline structure is small, the cations are more likely to eject towards the substrate and impact the structural layers on the substrate, thus reducing the probability of cations ejecting to the bottom sidewalls of adjacent bitline structures. This can alleviate the sidewall shrinkage phenomenon at the bottom of this part of the bitline structure, reduce the deformation of this part of the bitline structure, improve the performance of the bitline structure and semiconductor structure, ensure product yield, and also alleviate the increase in resistance of the bitline structure caused by the sidewall shrinkage of the bitline metal layer in this part of the bitline structure. Furthermore, during the formation of the first isolation layer, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the stress of the first isolation layer is less likely to cause deformation of the bitline structure. In the subsequent wet etching process, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the surface tension of the liquid is also less likely to cause deformation of the bitline structure, thereby further improving the performance of the bitline structure and semiconductor structure.

[0014] In one possible implementation, the process of forming the conductive structure further includes: forming a second dielectric layer, the second dielectric layer being located between the top surface of the conductive structure and the first isolation layer; wherein the conductive structure, the second dielectric layer, the first isolation layer, and the first dielectric layer together form a bitline structure.

[0015] The second dielectric layer can reduce the damage to the conductive structure caused by the etching process, which is beneficial to ensuring the electrical performance of the bit line structure.

[0016] In one possible implementation, forming a conductive structure includes: forming a conductive material layer connected to an active region; forming a second dielectric material layer covering the conductive material layer; etching away a portion of the conductive material layer and a portion of the second dielectric material layer, leaving the conductive material layer forming the conductive structure and the remaining second dielectric material layer forming the second dielectric layer.

[0017] Simultaneous etching of part of the conductive material layer and part of the second dielectric material layer helps to simplify the fabrication process of the semiconductor structure.

[0018] In one possible implementation, forming a first dielectric layer includes: forming a sacrificial layer located between every two adjacent conductive structures and covering a first isolation layer outside the conductive structures; forming a plurality of spaced trenches in the sacrificial layer, the trenches corresponding to at least a portion of the top surface of the first isolation layer exposing the conductive structures; forming a first dielectric layer filling the trenches; and removing the sacrificial layer.

[0019] The first dielectric layer can provide protection and isolation for the bitline structure.

[0020] In one possible implementation, the substrate includes a plurality of grooves, the bottom of which exposes an active region; forming a conductive structure includes: a portion of the conductive structure being located within the groove; forming a first isolation layer includes: a portion of the first isolation layer being located within the groove and covering the groove wall and the sidewall of the conductive structure located within the groove; after forming the first isolation layer, forming a second isolation layer is included, the second isolation layer being located within the groove and covering the surface of the first isolation layer within the groove.

[0021] By simultaneously forming a first isolation layer and a second isolation layer within the groove, the isolation effect of the isolation layer located within the groove can be improved.

[0022] A second aspect of this disclosure provides a semiconductor structure including a substrate and a plurality of bit line structures. The substrate includes a plurality of spaced-apart active regions. Each bit line structure includes a conductive structure, a first isolation layer, and a first dielectric layer. The conductive structures of the plurality of bit line structures are spaced apart on the substrate, and some of the conductive structures are connected to and electrically conductive with the active regions. The first isolation layer is located on the top and side of the conductive structures. The first dielectric layer is located on the top surface of the first isolation layer.

[0023] The semiconductor structure provided in this disclosure includes a substrate and multiple bit line structures. The substrate includes multiple spaced-apart active regions. Each bit line structure includes a conductive structure, a first isolation layer, and a first dielectric layer. The conductive structures of the multiple bit line structures are spaced apart on the substrate, and some of the conductive structures are connected to and electrically conductive with the active regions. The first isolation layer is located on the top and sides of the conductive structures. The first dielectric layer is located on the top surface of the first isolation layer. Because the first dielectric layer of the bit line structure is formed outside the first isolation layer, the height of the bit line structure covered by the first isolation layer is smaller, thereby reducing the aspect ratio of the bit line structure covered by the first isolation layer. For example, during plasma etching of the bitline structure covered by the first isolation layer, cations in the plasma, under the influence of the electric field of the ion sheath, may collide with the sidewalls of this part of the bitline structure. Because the aspect ratio of this part of the bitline structure is small, the cations are more likely to eject towards the substrate and impact the structural layers on the substrate, thus reducing the probability of cations ejecting to the bottom sidewalls of adjacent bitline structures. This can alleviate the sidewall shrinkage phenomenon at the bottom of this part of the bitline structure, reduce the deformation of this part of the bitline structure, improve the performance of the bitline structure and semiconductor structure, ensure product yield, and also alleviate the increase in resistance of the bitline structure caused by the sidewall shrinkage of the bitline metal layer in this part of the bitline structure. Furthermore, during the formation of the first isolation layer, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the stress of the first isolation layer is less likely to cause deformation of the bitline structure. In the subsequent wet etching process, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the surface tension of the liquid is also less likely to cause deformation of the bitline structure, thereby further improving the performance of the bitline structure and semiconductor structure.

[0024] In one possible implementation, the bit line structure further includes a second dielectric layer located between the top surface of the conductive structure and the first isolation layer.

[0025] The second dielectric layer can reduce the damage to the conductive structure caused by the etching process, which is beneficial to ensuring the electrical performance of the bit line structure.

[0026] In one possible implementation, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer;

[0027] And / or, the ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is in the range of 6-10.

[0028] This helps reduce the aspect ratio of the bit line structure covered by the first isolation layer, thereby mitigating the deformation of that portion of the bit line structure and improving the performance of both the bit line structure and the semiconductor structure. Furthermore, a thicker first dielectric layer can enhance its protective and isolation effects on the bit line structure.

[0029] In one possible implementation, the side of the first dielectric layer is flush with the side of the first insulating layer, or the side of the first dielectric layer is recessed into the side of the first insulating layer.

[0030] There are many ways to set up the first media layer, and it can be applied to many scenarios.

[0031] In one possible implementation, the semiconductor structure further includes a second isolation layer; the substrate includes a plurality of grooves, the bottom of which exposes an active region; a portion of the conductive structure is located within the grooves, a portion of the first isolation layer is located within the grooves and covers the groove walls and the sides of the conductive structure located within the grooves; the second isolation layer is located within the grooves and covers the surface of the first isolation layer within the grooves.

[0032] By simultaneously forming a first isolation layer and a second isolation layer within the groove, the isolation effect of the isolation layer located within the groove can be improved.

[0033] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0036] Figure 2 This is a schematic diagram of the structure after providing a substrate, as provided in an embodiment of this disclosure;

[0037] Figure 3 This is a schematic diagram of the structure after forming a conductive material layer and a second dielectric material layer according to an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of the structure after forming the conductive structure and the second dielectric layer according to an embodiment of this disclosure;

[0039] Figure 5 A schematic diagram of the structure after forming the first isolation layer, the first sub-isolation material layer and the second sub-isolation material layer according to an embodiment of this disclosure;

[0040] Figure 6 This is a schematic diagram of the structure after forming the first sub-isolation layer and the second sub-isolation layer according to an embodiment of the present disclosure;

[0041] Figure 7 This is a schematic diagram of the structure after the sacrificial layer is formed, provided in an embodiment of this disclosure;

[0042] Figure 8 This is a schematic diagram of the structure after the trench is formed, provided in an embodiment of this disclosure;

[0043] Figure 9 This is a schematic diagram of the structure after the formation of the first dielectric layer provided in an embodiment of the present disclosure;

[0044] Figure 10 This is a schematic diagram of the structure after removing the sacrificial layer, provided in an embodiment of this disclosure.

[0045] Explanation of reference numerals in the attached figures:

[0046] 100: Semiconductor structure; 110: Substrate;

[0047] 111: First active region; 112: First isolation structure;

[0048] 120: Bit line structure; 130: Conductive structure;

[0049] 130a: Conductive material layer; 131: Bit line contact layer;

[0050] 131a: Bit line contact material layer; 132: Bit line barrier layer;

[0051] 132a: Bit line blocking material layer; 133: Bit line metal layer;

[0052] 133a: Bit line metal material layer; 134: Bit line contact plug;

[0053] 141: First isolation layer; 142: Second isolation layer;

[0054] 142a: Second isolation material layer; 1421: First sub-isolation layer;

[0055] 1421a: First sub-isolation material layer; 1422: Second sub-isolation layer;

[0056] 1422a: Second sub-isolation material layer; 151: First dielectric layer;

[0057] 152: Second dielectric layer; 152a: Second dielectric material layer;

[0058] 160: Sacrificial layer; 171: Trench;

[0059] 172: Groove; 173: Capacitor contact hole;

[0060] 1731: First capacitor contact hole; 1732: Second capacitor contact hole;

[0061] 180: Underlying medium layer. Detailed Implementation

[0062] In related technologies, DRAM may include multiple memory cells, word lines, and bit lines. Each memory cell may include a capacitor and a memory transistor. A word line may be connected to the gate of a memory transistor, one of the source and drain of the memory transistor may be connected to a bit line, and the other of the source and drain of the memory transistor may be connected to a capacitor.

[0063] Bit lines can include a contact layer, a barrier layer, a metal layer, and a silicon nitride (SiN) isolation layer. Plasma etching can be used to form the bit lines. Plasma can be generated by high-frequency electric or magnetic fields and can include atoms, electrons, and charged ions (such as cations). A space charge layer composed of cations, i.e., an ion sheath, will form in the plasma. Under the influence of the electric field of the ion sheath, the cations are accelerated towards the bit line material layer to be etched, bombarding the bit line material layer to achieve etching. After forming the bit lines, a silicon nitride isolation layer can be formed on the surface of the bit lines.

[0064] However, due to the large height (i.e., thickness) and small width of the bit lines, the aspect ratio is large. During plasma etching, cations in the plasma, under the influence of the electric field of the ion sheath, may collide with the sidewalls of the bit lines. This causes the cations to bounce at a certain angle onto the bottom sidewalls of adjacent bit lines, resulting in the sidewalls of those adjacent bit lines contracting inwards to form a curved surface (i.e., sidewall contraction). This reduces the bottom width of the bit lines, making them prone to deformation (e.g., collapse or bending) at the sidewall contraction point. This affects the performance of the bit lines and the DRAM, and may even impact product yield. When the sidewall contraction point is located on the metal layer of the bit line, it also increases the resistance of the metal layer.

[0065] In addition, due to the high stress of the silicon nitride isolation layer, when the aspect ratio of the bit line is large, the stress of the silicon nitride isolation layer can easily lead to bit line deformation. In the subsequent wet etching process, due to the large surface tension of the liquid, when the aspect ratio of the bit line is large, the surface tension of the liquid can easily lead to bit line deformation, thereby further affecting the performance of the bit line and DRAM.

[0066] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method for fabricating the semiconductor structure may include: providing a substrate, the substrate including a plurality of active regions spaced apart; forming a plurality of conductive structures, the conductive structures being spaced apart on the substrate, with some conductive structures connected to and electrically conductive with the active regions; forming a first isolation layer, the first isolation layer being located on the top and sides of the conductive structures; forming a first dielectric layer, the first dielectric layer being located on the top surface of the first isolation layer; wherein the conductive structures, the first isolation layer, and the first dielectric layer together form a bit line structure. Because the first dielectric layer of the bit line structure is formed outside the first isolation layer, the height of the bit line structure covered by the first isolation layer is smaller, thereby reducing the aspect ratio of the bit line structure covered by the first isolation layer. For example, during plasma etching of the bitline structure covered by the first isolation layer, cations in the plasma, under the influence of the electric field of the ion sheath, may collide with the sidewalls of this part of the bitline structure. Because the aspect ratio of this part of the bitline structure is small, the cations are more likely to eject towards the substrate and impact the structural layers on the substrate, thus reducing the probability of cations ejecting to the bottom sidewalls of adjacent bitline structures. This can alleviate the sidewall shrinkage phenomenon at the bottom of this part of the bitline structure, reduce the deformation of this part of the bitline structure, improve the performance of the bitline structure and semiconductor structure, ensure product yield, and also alleviate the increase in resistance of the bitline structure caused by the sidewall shrinkage of the bitline metal layer in this part of the bitline structure. Furthermore, during the formation of the first isolation layer, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the stress of the first isolation layer is less likely to cause deformation of the bitline structure. In the subsequent wet etching process, because the aspect ratio of the bitline structure covered by the first isolation layer is small, the surface tension of the liquid is also less likely to cause deformation of the bitline structure, thereby further improving the performance of the bitline structure and semiconductor structure.

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of the first isolation of this disclosure.

[0068] The following will combine Figures 1-10 The method for preparing the semiconductor structure 100 provided in the embodiments of this disclosure will be described.

[0069] This disclosure provides a method for fabricating a semiconductor structure 100, see [link to relevant documentation]. Figure 1 The preparation method may include:

[0070] S100: Provides a substrate, which includes a plurality of spaced active regions.

[0071] See Figure 2 First, a substrate 110 is provided. The substrate 110 may include a semiconductor material. The substrate 110 may provide a supporting base for other structural layers on the substrate 110. The substrate 110 (or semiconductor structure 100) may include an array region and a peripheral region located around the array region. Figure 2 Only the array area is shown.

[0072] The substrate 110 located in the array region may have a first isolation structure 112 and a plurality of first active regions 111. The first isolation structure 112 can be used to isolate two adjacent first active regions 111. The first active regions 111 can be used to form access transistors.

[0073] The array region provided in the embodiments of this disclosure will be described below.

[0074] See Figure 2 After providing the substrate 110, the process may include depositing an underlayer dielectric layer 180 on the substrate 110, and then etching a portion of the underlayer dielectric layer 180 and the substrate 110 to form a plurality of grooves 172 in the underlayer dielectric layer 180 and the substrate 110. The bottom of the grooves 172 exposes a first active region 111. The exposed first active region 111 can be used for electrical connection with a portion of the bit line structure 120. The remaining underlayer dielectric layer 180 can provide protection for the substrate 110 it covers.

[0075] For example, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). Other structural layers in the embodiments of this disclosure may also be formed by deposition, which will not be described in detail here.

[0076] S200: Multiple conductive structures are formed, and the multiple conductive structures are arranged at intervals on the substrate. Some of the conductive structures are connected to the active region and are electrically conductive.

[0077] See Figure 3 and Figure 4Multiple conductive structures 130 are formed at intervals on the substrate 110, and some of the conductive structures 130 can be connected to and electrically connected to the first active region 111. For example, a conductive material layer 130a can be formed on the substrate 110, and the conductive material layer 130a can be connected to the first active region 111. Then, a portion of the conductive material layer 130a is etched away, and the remaining conductive material layer 130a can form the conductive structure 130.

[0078] For example, see Figure 3 and Figure 4 The process of forming the conductive structure 130 may further include forming a second dielectric layer 152 on the top surface of the conductive structure 130. For example, forming the conductive structure 130 may include forming a conductive material layer 130a on a substrate 110, the conductive material layer 130a being connected to the first active region 111. A second dielectric material layer 152a is formed on the conductive material layer 130a. Then, a portion of the conductive material layer 130a and a portion of the second dielectric material layer 152a are etched away, the remaining conductive material layer 130a forming the conductive structure 130, and the remaining second dielectric material layer 152a forming the second dielectric layer 152. During this etching process, the second dielectric layer 152 can reduce the damage to the conductive structure 130 caused by the etching process, which is beneficial to ensuring the electrical performance of the bit line structure 120.

[0079] In an embodiment where a groove 172 and an underlying dielectric layer 180 are formed on the substrate 110, see [reference needed]. Figure 3 Forming the conductive material layer 130a may include forming the conductive material layer 130a within the groove 172 and on the top surface of the underlying dielectric layer 180. The conductive material layer 130a may fill the groove 172, and the conductive material layer 130a located within the groove 172 is electrically connected to the first active region 111. See also Figure 4 The portion of conductive structure 130 located within the groove 172 can be electrically connected to the first active region 111.

[0080] For example, see Figure 3 and Figure 4 Forming the conductive material layer 130a may include sequentially forming a bit line contact material layer 131a, a bit line blocking material layer 132a, and a bit line metal material layer 133a. Etching a portion of the conductive material layer 130a may include etching a portion of the bit line contact material layer 131a, a portion of the bit line blocking material layer 132a, and a portion of the bit line metal material layer 133a. The retained bit line contact material layer 131a may form a bit line contact layer 131, the retained bit line blocking material layer 132a may form a bit line blocking layer 132, and the retained bit line metal material layer 133a may form a bit line metal layer 133. The bit line contact layer 131, the bit line blocking layer 132, and the bit line metal layer 133 together form the conductive structure 130.

[0081] See Figure 3 and Figure 4 In an embodiment where a groove 172 and a bottom dielectric layer 180 are formed on the substrate 110, forming a bit line contact material layer 131a may include: forming a bit line contact material layer 131a within the groove 172 and on the top surface of the bottom dielectric layer 180; the bit line contact material layer 131a may fill the groove 172, and the bit line contact material layer 131a located within the groove 172 is electrically connected to the first active region 111. The bit line contact material layer 131a retained within the groove 172 may form a bit line contact plug 134, and the bit line structure 120 may be electrically connected to the first active region 111 through the bit line contact plug 134.

[0082] S300: Forming a first isolation layer, the first isolation layer being located on the top and sides of the conductive structure.

[0083] See Figure 5 and Figure 6 After forming the conductive structure 130, a first isolation layer 141 may be formed on the top and sides of the conductive structure 130. Additionally, the first isolation layer 141 may also cover the top of the substrate 110 located between two adjacent conductive structures 130. In an embodiment where a groove 172 and a bottom dielectric layer 180 are formed on the substrate 110, a portion of the conductive structure 130 is located in the groove 172. Forming the first isolation layer 141 may also cover the sidewalls of the conductive structure 130 in the groove 172, the groove walls of the groove 172, and the top surface of the bottom dielectric layer 180.

[0084] In embodiments where a second dielectric layer 152 is provided, forming a first isolation layer 141 on top of the conductive structure 130 may include forming the first isolation layer 141 on the top surface of the second dielectric layer 152.

[0085] In embodiments with groove 172, after forming the first isolation layer 141, a second isolation layer 142 may be formed within the groove 172, the second isolation layer 142 covering the surface of the first isolation layer 141 within the groove 172. By forming the first isolation layer 141 and the second isolation layer 142 within the groove 172, the isolation effect of the isolation layer within the groove 172 can be improved. For example, forming the second isolation layer 142 may include sequentially forming a first sub-isolation material layer 1421a and a second sub-isolation material layer 1422a on the first isolation layer 141, then etching away the first sub-isolation material layer 1421a and the second sub-isolation material layer 1422a outside the groove 172, retaining the first sub-isolation material layer 1421a and the second sub-isolation material layer 1422a within the groove 172, and forming the first sub-isolation layer 1421 and the second sub-isolation layer 1422 respectively. The first sub-isolation layer 1421 and the second sub-isolation layer 1422 can jointly form the second isolation layer 142, and the first sub-isolation material layer 1421a and the second sub-isolation material layer 1422a can jointly form the second isolation material layer 142a. The second isolation layer 142 can include at least one of the first sub-isolation layer 1421 and the second sub-isolation layer 1422. When the second isolation layer 142 simultaneously includes the first sub-isolation layer 1421 and the second sub-isolation layer 1422, the isolation layer located in the groove 172 is formed by the first isolation layer 141, the first sub-isolation layer 1421, and the second sub-isolation layer 1422, which can further improve the isolation effect of the isolation layer located in the groove 172.

[0086] S400: Form a first dielectric layer, which is located on the top surface of the first isolation layer.

[0087] See Figure 10After forming the first isolation layer 141, a first dielectric layer 151 may be formed on at least a portion of the top surface of the first isolation layer 141. The first dielectric layer 151 can protect and isolate the bit line structure 120. Since the first dielectric layer 151 of the bit line structure 120 is formed outside the first isolation layer 141, the height of the bit line structure 120 covered by the first isolation layer 141 is smaller, thereby reducing the aspect ratio of the bit line structure 120 covered by the first isolation layer 141. For example, during plasma etching of the bit line structure 120 covered by the first isolation layer 141, the cations in the plasma may collide with the sidewalls of the bit line structure 120 under the electric field of the ion sheath. Since the aspect ratio of the bit line structure 120 is small, the cations tend to eject towards the substrate 110 and impact the structural layer on the substrate 110 (i.e., the substrate 110 between two adjacent bit line structures 120), thereby reducing the probability of the cations ejecting to the bottom sidewalls of the adjacent bit line structure 120. This can alleviate the sidewall shrinkage phenomenon at the bottom of the bit line structure 120, reduce the deformation of the bit line structure 120, improve the performance of the bit line structure 120 and the semiconductor structure 100, ensure product yield, and also alleviate the sidewall shrinkage phenomenon of the bit line metal layer 133 in the bit line structure 120, which leads to an increase in the resistance of the bit line structure 120. In addition, when the first isolation layer 141 is formed, the bit line structure 120 covered by the first isolation layer 141 has a small aspect ratio, so the stress of the first isolation layer 141 is not likely to cause deformation of the bit line structure 120. In the subsequent wet etching process, since the bit line structure 120 covered by the first isolation layer 141 has a small aspect ratio, the surface tension of the liquid is also not likely to cause deformation of this part of the bit line structure 120, thereby further improving the performance of the bit line structure 120 and the semiconductor structure 100.

[0088] A first dielectric layer 151 can be provided without a second dielectric layer 152. In this case, the conductive structure 130, the first isolation layer 141 corresponding to the conductive structure 130, and the first dielectric layer 151 can together form a bit line structure 120. Alternatively, both the first dielectric layer 151 and the second dielectric layer 152 can be provided simultaneously, and the conductive structure 130, the second dielectric layer 152, the first isolation layer 141 corresponding to the conductive structure 130, and the first dielectric layer 151 can together form the bit line structure 120. When both the first dielectric layer 151 and the second dielectric layer 152 are provided simultaneously, the protection and isolation effect of the dielectric layer can be improved.

[0089] It is understandable that, since the first isolation layer 141 can support the part of the bit line structure 120 covered by the first isolation layer 141 and increase the width of the part of the bit line structure 120, the overall structural stability of the first isolation layer 141 and the part of the bit line structure 120 covered by the first isolation layer 141 is high, thereby alleviating the deformation of the bit line structure 120 after the formation of the first dielectric layer 151.

[0090] See Figures 7-9 Forming the first dielectric layer 151 may include forming a sacrificial layer 160 between each two adjacent conductive structures 130 and on a first isolation layer 141 outside the conductive structure 130. After forming the sacrificial layer 160, a plurality of trenches 171 spaced apart may be formed in the sacrificial layer 160, the trenches 171 potentially exposing part or all of the top surface of the first isolation layer 141 of the conductive structure 130. After forming the trenches 171, the first dielectric layer 151 may be formed in the trenches 171, the first dielectric layer 151 potentially filling the trenches 171. After forming the first dielectric layer 151, the sacrificial layer 160 may be etched away (e.g., wet etching, using hydrofluoric acid to remove the sacrificial layer 160). A capacitor contact hole 173 may be formed between two adjacent bit line structures 120. Figure 10 ).

[0091] In an embodiment where trench 171 corresponds to the entire top surface of the first insulating layer 141 exposing the conductive structure 130, the side surface of the first dielectric layer 151 can be flush with the side surface of the first insulating layer 141, thereby simplifying the shape of the capacitor contact hole 173. In an embodiment where trench 171 corresponds to a portion of the top surface of the first insulating layer 141 exposing the conductive structure 130, the side surface of the first dielectric layer 151 can be recessed into the side surface of the first insulating layer 141. The capacitor contact hole 173 may include a connection between a first capacitor contact hole 1731 and a second capacitor contact hole 1732, with the first capacitor contact hole 1731 located on the side of the second capacitor contact hole 1732 facing the substrate 110. The first capacitor contact hole 1731 may correspond to the first insulating layer 141, and the second capacitor contact hole 1732 may correspond to the first dielectric layer 151. A contact plug may be formed in the first capacitor contact hole 1731, and a contact pad may be formed in the second capacitor contact hole 1732. At this point, the area of ​​the contact pad is larger than the area of ​​the contact plug. The larger area of ​​the contact pad results in a larger contact surface between the contact pad and the contact plug, which is beneficial for achieving electrical connection between the contact pad and the contact plug.

[0092] For example, the material of the sacrificial layer 160 may have a larger etching selectivity than the materials of the first isolation layer 141 and the first dielectric layer 151, that is, the etching rate of the material of the sacrificial layer 160 is greater than the etching rate of the first isolation layer 141 and the first dielectric layer 151, thereby avoiding damage to the first isolation layer 141 and the first dielectric layer 151 when etching the sacrificial layer 160, thus ensuring that the subsequently formed first isolation layer 141 and the first dielectric layer 151 have good structural integrity. For example, the material of the sacrificial layer 160 may include photoresist or silicon dioxide. The material of at least one of the first isolation layer 141, the first dielectric layer 151, and the second dielectric layer 152 may include nitrides, such as silicon nitride, silicon carbonitride, etc. In the embodiment of dry etching of the sacrificial layer 160, the etching gas may include C4F6 / C4F8 / O2, and the etching endpoint is detected by endpoint detection mode (EPD), that is, the etching endpoint is determined by detecting the N content (e.g., when the N content suddenly increases).

[0093] For example, a method of forming the sacrificial layer 160 may include a spin coating process, for example, a silicon dioxide precursor tetraethoxysilane (Tetraethyl orthosilicone, abbreviated as TEOS) may be spin coated to form the sacrificial layer 160.

[0094] For example, after forming the sacrificial layer 160 and before forming the trench 171, the top surface of the sacrificial layer 160 may be planarized to make the top surface of the sacrificial layer 160 flatter, which can improve the consistency of etching the sacrificial layer 160 and thus improve the consistency of each trench 171. For example, the width of the trench 171 may be approximately 10 nm, and the depth of the trench 171 may be approximately 75 nm.

[0095] For example, forming the first dielectric layer 151 may include filling the trench 171 and covering the top surface of the sacrificial layer 160. After forming the first dielectric layer 151 and before removing the sacrificial layer 160, a portion of the thickness of the first dielectric layer 151 may be removed along the top surface of the sacrificial layer 160, i.e., the first dielectric layer 151 may be planarized to expose the top surface of the sacrificial layer 160.

[0096] Planarization processes may include etching or chemical-mechanical polishing (CMP). Etching in this embodiment may include dry etching or wet etching.

[0097] The peripheral area provided in the embodiments of this disclosure will be described below.

[0098] A second isolation structure and a second active region can be disposed in the substrate 110 located in the peripheral region. The second isolation structure can be used to isolate two adjacent second active regions. The second active region can be used to form a peripheral transistor. For example, a gate dielectric layer and a gate of the peripheral transistor can be formed on the channel region of the second active region, and a gate protection layer can be formed on the gate. When forming the conductive material layer 130a in the array region, the conductive material layer 130a can be formed simultaneously in the peripheral region. The conductive material layer 130a in the peripheral region can be used to form the gate of the peripheral transistor, thereby simplifying the fabrication process and reducing the fabrication cost of the semiconductor structure 100. When forming the second dielectric material layer 152a in the array region, the second dielectric material layer 152a can be formed simultaneously in the peripheral region. The second dielectric material layer 152a in the peripheral region can be used to form the gate protection layer of the peripheral transistor. The principle of the first isolation layer 141 and the first dielectric layer 151 in the peripheral region is similar to that of the second dielectric material layer 152a, and will not be described again. At least one of the second dielectric material layer 152a, the first isolation layer 141, and the first dielectric layer 151 can be used to form a gate protection layer.

[0099] The semiconductor structure 100 provided in the embodiments of this disclosure will be described below.

[0100] The semiconductor structure 100 provided in this disclosure can be fabricated using the fabrication method of the semiconductor structure 100 in the above embodiments. This semiconductor structure 100 can be applied to a memory, which may include, for example, DRAM, phase-change random access memory (PRAM), or magnetoresistive random access memory (MRAM). This disclosure describes the application of the semiconductor structure 100 to DRAM as an example.

[0101] See Figure 10 The semiconductor structure 100 may include a substrate 110, which may provide a supporting foundation for other structural layers on the substrate 110. The material of the substrate 110 may be any one or more of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, gallium arsenide compound, gallium phosphide compound, gallium sulfide compound, etc., or other materials known to those skilled in the art. The substrate 110 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.

[0102] For example, the semiconductor structure 100 may include a word line structure and a bit line structure 120. The word line structure may be connected to the gate of an access transistor, one of the drain and source of the access transistor may be connected to the bit line structure 120, and the other of the drain and source of the access transistor may be connected to a capacitor. The access transistor can act as a switching (selection) control switch, that is, the access transistor is used to control data access. The capacitor can act as a capacitor to store data, and the charge level on the capacitor determines whether the stored data information is "0" or "1". The voltage signal on the word line structure can control the access transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line structure 120, or writing data information into the capacitor for storage through the bit line structure 120, thereby realizing the access of data information.

[0103] For example, substrate 110 (or semiconductor structure 100) may include an array region and a peripheral region located around the array region. Figure 10 (Only the array region is shown in the diagram). Multiple capacitors can be disposed on the substrate 110 located in the array region. A first isolation structure 112 and multiple spaced-apart first active regions 111 can be disposed in the substrate 110 located in the array region. The first isolation structure 112 can be used to isolate two adjacent first active regions 111. The first active regions 111 can be used to form access transistors. One capacitor can be correspondingly disposed with at least one access transistor, and a corresponding capacitor and an access transistor can form a memory cell. This disclosure describes an embodiment with a one-to-one correspondence between capacitors and access transistors.

[0104] The array region provided in the embodiments of this disclosure will be described below.

[0105] See Figure 10 The top surface of the substrate 110 is covered with a bottom dielectric layer 180 for protecting the first active region 111. The bottom dielectric layer 180 can prevent the first active region 111 covered by it from being exposed to the process environment and being oxidized, which would lead to electrical degradation of the first active region 111. For example, the material of the bottom dielectric layer 180 may include silicon oxide.

[0106] See Figure 10 The substrate 110 may include a plurality of grooves 172, the bottom of which exposes the first active region 111. For example, a bottom dielectric layer 180 may be formed on the substrate 110, and then a portion of the bottom dielectric layer 180 and a portion of the substrate 110 covering the first active region 111 may be etched to form the grooves 172 that expose the first active region 111.

[0107] Multiple bit line structures 120 can be disposed on the substrate 110, and the conductive structures 130 of the multiple bit line structures 120 can be arranged at intervals on the substrate 110. For example, multiple memory cells can be arranged in an array, and the multiple memory cells can be arranged in multiple rows and columns along a first direction and a second direction. The multiple bit line structures 120 can all extend along the first direction, and the multiple bit line structures 120 can be arranged at intervals along the second direction. The first direction and the second direction can intersect, and both the first direction and the second direction can be parallel to the plane of the substrate 110. One bit line structure 120 can connect to a row (or a column) of memory cells arranged along the first direction.

[0108] For example, see Figure 10 The bit line structure 120 may include a conductive structure 130, a first isolation layer 141, and a first dielectric layer 151. A portion of the conductive structure 130 may be connected to and electrically connected to the first active region 111. For example, a portion of the conductive structure 130 may be located within a groove 172, thereby being electrically connected to the first active region 111 exposed by the groove 172.

[0109] For example, the conductive structure 130 may include a bit line contact layer 131, a bit line blocking layer 132, and a bit line metal layer 133. The material of the bit line contact layer 131 may include semiconductor materials such as polysilicon, and the material of the bit line blocking layer 132 may include metal nitrides, such as any one or more of titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), aluminum hafnium nitride (HfAlN), molybdenum nitride (MoN), and nickel aluminum nitride (NiAlN). The material of the bit line metal layer 133 may include any one or more of aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), and hafnium (Hf). A portion of the bit line contact layer 131 located within the groove 172 may form a bit line contact plug 134, and the bit line structure 120 is electrically connected to the first active region 111 through the bit line contact plug 134.

[0110] The first isolation layer 141 can be located on the top and sides of the conductive structure 130, and the first isolation layer 141 can provide some support for the portion of the bit line structure 120 covered by it. For example, the material of the first isolation layer 141 can include nitrides, such as silicon nitride (SiN). Part of the first isolation layer 141 can be located within the groove 172 and cover the groove wall of the groove 172 and the sides of the conductive structure 130 located within the groove 172.

[0111] In some embodiments, see Figure 10The semiconductor structure 100 may further include a second isolation layer 142, which may be located within a recess 172 and cover the surface of the first isolation layer 141 located within the recess 172, thereby improving the isolation effect of the isolation layers (first isolation layer 141 and second isolation layer 142) located within the recess 172. For example, the second isolation layer 142 may include a first sub-isolation layer 1421 and a second sub-isolation layer 1422. The first sub-isolation layer 1421 may cover the surface of the first isolation layer 141 located within the recess 172, and the second sub-isolation layer 1422 may cover the surface of the first sub-isolation layer 1421, so that the isolation layer located within the recess 172 is formed by the first isolation layer 141, the first sub-isolation layer 1421, and the second sub-isolation layer 1422, thereby further improving the isolation effect of the isolation layer located within the recess 172. The material of any one of the first isolation layer 141, the first sub-isolation layer 1421, and the second sub-isolation layer 1422 may include oxides, nitrides, etc. The materials of any two of the first isolation layer 141, the first sub-isolation layer 1421, and the second sub-isolation layer 1422 can be the same or different. For example, the materials of the first isolation layer 141 and the second sub-isolation layer 1422 can be nitrides (e.g., silicon nitride, silicon carbonitride, etc.). The material of the first sub-isolation layer 1421 can be an oxide (e.g., silicon oxide). In this way, an isolation layer with a nitrogen-oxygen-nitrogen (NON) structure can be formed in the groove 172, which can effectively reduce the leakage current in the bit line structure 120 and reduce the parasitic capacitance between adjacent bit line structures 120.

[0112] See Figure 10The semiconductor structure 100 may include a first dielectric layer 151, which may be located on the top surface of the first isolation layer 141 and may protect the bit line structure 120. Because the first dielectric layer 151 of the bit line structure 120 is disposed outside the first isolation layer 141, the height of the bit line structure 120 covered by the first isolation layer 141 is smaller, thereby reducing the aspect ratio of the bit line structure 120 covered by the first isolation layer 141. For example, during plasma etching of the bit line structure 120 covered by the first isolation layer 141, the cations in the plasma may collide with the sidewalls of this part of the bit line structure 120 under the electric field of the ion sheath layer. Since the aspect ratio of this part of the bit line structure 120 is small, the cations tend to be ejected towards the substrate 110 and impact the structural layer on the substrate 110, thereby reducing the probability of the cations ejecting to the bottom sidewall of the adjacent bit line structure 120. This can alleviate the sidewall shrinkage phenomenon at the bottom of this part of the bit line structure 120, reduce the deformation of this part of the bit line structure 120, improve the performance of the bit line structure 120 and the semiconductor structure 100, ensure product yield, and also alleviate the sidewall shrinkage phenomenon of the bit line metal layer 133 in this part of the bit line structure 120, which leads to an increase in the resistance of the bit line structure 120. In addition, when the first isolation layer 141 is formed, the bit line structure 120 covered by the first isolation layer 141 has a small aspect ratio, so the stress of the first isolation layer 141 is less likely to cause deformation of the bit line structure 120. In the subsequent wet etching process, since the bit line structure 120 covered by the first isolation layer 141 has a small aspect ratio, the surface tension of the liquid is also less likely to cause deformation of the bit line structure 120, thereby further improving the performance of the bit line structure 120 and the semiconductor structure 100.

[0113] For example, see Figure 10 The bitline structure 120 may further include a second dielectric layer 152, which may be located between the top surface of the conductive structure 130 and the first isolation layer 141. The second dielectric layer 152 can reduce the damage to the conductive structure 130 caused by the etching process during the etching process of forming the conductive structure 130, which is beneficial to ensuring the electrical performance of the bitline structure 120. It is understood that the bitline structure 120 may only have a first dielectric layer 151, thereby simplifying the fabrication process of the bitline structure 120. Alternatively, the bitline structure 120 may simultaneously have a first dielectric layer 151 and a second dielectric layer 152, with a large total thickness of the first dielectric layer 151 and the second dielectric layer 152, thereby providing good protection and isolation for the bitline structure 120. This embodiment of the present disclosure is illustrated by taking the simultaneous presence of a first dielectric layer 151 and a second dielectric layer 152 as an example.

[0114] For example, the thickness of the first dielectric layer 151 can be greater than the thickness of the second dielectric layer 152, thereby allowing the second dielectric layer 152 to be made thinner. This results in a smaller total height of the bit line structure 120 covered by the first isolation layer 141, which helps to reduce the aspect ratio of the bit line structure 120 covered by the first isolation layer 141, thereby alleviating the deformation of this part of the bit line structure 120 and improving the performance of the bit line structure 120 and the semiconductor structure 100. Alternatively, the first dielectric layer 151 can be made thicker, which helps to improve the protection and isolation effect of the first dielectric layer 151 on the bit line structure 120.

[0115] For example, the ratio of the thickness of the first dielectric layer 151 to the thickness of the second dielectric layer 152 can be in the range of 6-10. This avoids the ratio being too small, thus preventing the second dielectric layer 152 from being too thick and thus avoiding a large aspect ratio of the bit line structure 120 covered by the first isolation layer 141. Additionally, it avoids the ratio being too large, thus preventing the second dielectric layer 152 from being too thin and thus ensuring good protection of the conductive structure 130. For example, the ratio of the thickness of the first dielectric layer 151 to the thickness of the second dielectric layer 152 can be 6, 7, 8, 9, 10, or any value between 6 and 10. For example, the thickness of the second dielectric layer 152 can be approximately 10 nm.

[0116] For example, a capacitor contact hole 173 may be provided between two adjacent bit line structures 120. A contact plug and a contact pad may be provided in the capacitor contact hole 173. The contact pad may be located on the side of the contact plug away from the substrate 110. The capacitor may be electrically connected to the access transistor in sequence through the contact pad and the contact plug.

[0117] For example, see Figure 10 The capacitor contact hole 173 may include a first capacitor contact hole 1731 and a second capacitor contact hole 1732 that are connected. The first capacitor contact hole 1731 may be located on the side of the second capacitor contact hole 1732 facing the substrate 110. The first capacitor contact hole 1731 may correspond to the first isolation layer 141, and the second capacitor contact hole 1732 may correspond to the first dielectric layer 151. A contact plug may be disposed in the first capacitor contact hole 1731, and a contact pad may be disposed in the second capacitor contact hole 1732.

[0118] For example, see Figure 10The side of the first dielectric layer 151 can be flush with the side of the first insulating layer 141, thus making the shape of the capacitor contact hole 173 formed by the first capacitor contact hole 1731 and the second capacitor contact hole 1732 relatively simple. Alternatively, the side of the first dielectric layer 151 can be recessed into the side of the first insulating layer 141, thus making the area of ​​the second capacitor contact hole 1732 larger than the area of ​​the first capacitor contact hole 1731, and making the area of ​​the contact pad larger than the area of ​​the contact plug. That is, the area of ​​the contact pad is larger, and the contact surface between the contact pad and the contact plug is larger, which is beneficial to realizing the electrical connection between the contact pad and the contact plug.

[0119] The peripheral area provided in the embodiments of this disclosure will be described below.

[0120] A second isolation structure and multiple second active regions can be disposed in the substrate 110 located in the peripheral region. The second isolation structure can be used to isolate two adjacent second active regions. The second active regions can be used to form peripheral transistors. A gate dielectric layer and a gate of the peripheral transistor can be disposed on the channel region of the second active region, and a gate protection layer can be disposed on the gate. The gate of the peripheral transistor and at least a portion of the structural layers of the conductive structure 130 can be disposed in the same layer and with the same material, thereby simplifying the fabrication process of the semiconductor structure 100 and reducing the fabrication cost. And / or, the gate protection layer can be disposed in the same layer and with the same material as at least one of the first dielectric layer 151, the second dielectric layer 152, and the first isolation layer 141, thereby simplifying the fabrication process of the semiconductor structure 100 and reducing the fabrication cost.

[0121] "Same layer, same material" refers to a base membrane layer formed from the same material. After patterning and / or other processing of the base membrane layer, different parts of the base membrane layer are formed into various structural membrane layers. The processing techniques for the different structural membrane layers can be the same or different, and the different structural membrane layers can have the same or different thicknesses, and can be located on the same horizontal plane or different horizontal planes.

[0122] It should be noted that the numerical values ​​and ranges involved in the embodiments of this disclosure are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, the substrate comprising a plurality of spaced-apart active regions; Multiple conductive structures are formed, and the multiple conductive structures are arranged at intervals on the substrate. Some of the conductive structures are connected to the active region and are electrically conductive. A first isolation layer is formed, which is located on the top and sides of the conductive structure; A first dielectric layer is formed, wherein the first dielectric layer is located on the top surface of the first isolation layer; In the conductive structure, the first isolation layer and the first dielectric layer together form a bit line structure; The formation of the first dielectric layer includes: A sacrificial layer is formed between every two adjacent conductive structures and covers the first isolation layer outside the conductive structure; A plurality of spaced trenches are formed in the sacrificial layer, the trenches corresponding to at least a portion of the top surface of the first insulating layer that exposes the conductive structure; The first dielectric layer is formed, and the first dielectric layer fills the trench; Remove the sacrificial layer.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The process of forming the conductive structure also includes: A second dielectric layer is formed, which is located between the top surface of the conductive structure and the first isolation layer; The conductive structure, the second dielectric layer, the first isolation layer, and the first dielectric layer together form the bit line structure.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Forming the conductive structure includes: A conductive material layer is formed, and the conductive material layer is connected to the active region; A second dielectric material layer is formed, which covers the conductive material layer; Etching removes a portion of the conductive material layer and a portion of the second dielectric material layer, leaving the conductive material layer to form the conductive structure and the second dielectric material layer to form the second dielectric layer.

4. The method of producing a semiconductor structure according to any one of claims 1 to 3, wherein The substrate includes a plurality of grooves, the bottom of which exposes the active region; Forming the conductive structure includes: a portion of the conductive structure being located within the groove. Forming the first isolation layer includes: a portion of the first isolation layer being located within the groove and covering the groove wall and the side surface of the conductive structure located within the groove; After the first isolation layer is formed, the following is included: A second isolation layer is formed, which is located within the groove and covers the surface of the first isolation layer within the groove.

5. A semiconductor structure, characterized by The device includes a substrate and multiple bit line structures, wherein the substrate includes multiple spaced active regions; the bit line structures include conductive structures, a first isolation layer and a first dielectric layer. The conductive structures of the plurality of bitline structures are arranged at intervals on the substrate, and some of the conductive structures are connected to and electrically conductive with the active region; the first isolation layer is located on the top and side of the conductive structures; the first dielectric layer is located on the top surface of the first isolation layer; The bit line structure further includes a second dielectric layer, which is located between the top surface of the conductive structure and the first isolation layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer; And / or, the ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is in the range of 6-10.

6. The semiconductor structure of claim 5, wherein, The side of the first dielectric layer is flush with the side of the first isolation layer, or the side of the first dielectric layer is recessed into the side of the first isolation layer.

7. The semiconductor structure of claim 5, wherein, It also includes a second isolation layer; the substrate includes a plurality of grooves, the bottom of which exposes the active region; A portion of the conductive structure is located within the groove, and a portion of the first insulating layer is located within the groove and covers the groove wall and the side surface of the conductive structure located within the groove; The second isolation layer is located within the groove and covers the surface of the first isolation layer within the groove.

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