Display substrate and its preparation method, display device

Abstract

A display substrate, its fabrication method, and a display device are disclosed. The display substrate includes multiple circuit units, each including a pixel driving circuit and multiple signal lines. The pixel driving circuit includes a storage capacitor and a shielding electrode. The storage capacitor includes a first electrode plate and a second electrode plate. The multiple signal lines include a first scan signal line, a data signal line, a first power supply line, and an initial signal line. The initial signal line includes a first initial signal line and an initial signal connection line. The display substrate includes at least a first conductive layer, a second conductive layer, and a third conductive layer disposed on a substrate. The first scan signal line and the first electrode plate are disposed in the first conductive layer, the first initial signal line, the second electrode plate, and the shielding electrode are disposed in the second conductive layer, and the first power supply line and the initial signal connection line are disposed in the third conductive layer. The data signal line is connected to a first data fan-out line, and the data signal line and the first data fan-out line are disposed in different conductive layers.

Description

[0001] This case is a divisional application of patent application 202180002067.7. The original application was filed on July 30, 2021, with the application number 202180002067.7 and the invention title being: Display substrate and its preparation method, and display device. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate including a display area, the display area including a plurality of circuit units, each circuit unit including a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a shielding electrode, the storage capacitor including a first electrode plate and a second electrode plate, the plurality of signal lines including at least a first scan signal line extending along a first direction of the main body portion, a data signal line extending along a second direction of the main body portion, a first power line extending along the second direction of the main body portion, and an initial signal line; the initial signal line including at least a first initial signal line extending along the first direction of the main body portion and an initial signal connection line extending along the second direction of the main body portion, the first direction intersecting the second direction;

[0006] In a plane perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the first scan signal line and the first electrode plate are disposed in the first conductive layer, the first initial signal line, the second electrode plate, and the shielding electrode are disposed in the second conductive layer, the shielding electrode is disposed between the first initial signal line and the second electrode plate, the first power line and the initial signal connection line are disposed in the third conductive layer, the first power line is connected to the shielding electrode, and the initial signal connection line is connected to the first initial signal line; the data signal line is connected to a first data fan-out line extending along the first direction of the main body portion, and the data signal line and the first data fan-out line are disposed in different conductive layers.

[0007] In an exemplary embodiment, the first data fan-out line is connected to the data signal line via a via.

[0008] In an exemplary embodiment, the display substrate further includes a fourth conductive layer disposed on the side of the third conductive layer away from the substrate, the data signal line is disposed in the third conductive layer, and the first data fan-out line is disposed in the fourth conductive layer.

[0009] In an exemplary embodiment, the initial signal connection line is connected to the first initial signal line via a via.

[0010] In an exemplary embodiment, the first direction is perpendicular to the second direction.

[0011] In an exemplary embodiment, the orthographic projection of the first data fan-out line on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate.

[0012] In an exemplary embodiment, the display area further includes a second data fan-out line extending along the second direction, the second data fan-out line being connected to the first data fan-out line.

[0013] In an exemplary embodiment, the first data fan-out line and the second data fan-out line are arranged on the same layer.

[0014] In an exemplary embodiment, the orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0015] In an exemplary embodiment, at least a portion of the orthographic projection of the second data fan-out line on the substrate lies between the orthographic projection of the first power line on the substrate and the orthographic projection of the data signal line on the substrate.

[0016] In an exemplary embodiment, the orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the initial signal connection line on the substrate.

[0017] In an exemplary embodiment, the display substrate further includes an upper border, a lower border, a left border, and a right border located outside the display area, wherein the widths of the upper border, the lower border, the left border, and the right border are similar.

[0018] In an exemplary embodiment, the width of the bottom border, the left border, and the right border is less than or equal to 1.0 mm.

[0019] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0020] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate including a display area, the display area including a plurality of circuit units, the circuit units including a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a shielding electrode, the storage capacitor including a first electrode plate and a second electrode plate, the plurality of signal lines including at least a first scan signal line extending along a first direction of the main body portion, a data signal line extending along a second direction of the main body portion, a first power supply line extending along the second direction of the main body portion, and an initial signal line; the initial signal line including at least a first initial signal line extending along the first direction of the main body portion and an initial signal connection line extending along the second direction of the main body portion, the first direction intersecting the second direction; the fabrication method includes:

[0021] A first conductive layer is formed on a substrate, and the first scan signal line and the first electrode are disposed in the first conductive layer;

[0022] A second conductive layer is formed on the first conductive layer, and the first initial signal line, the second electrode plate and the shielding electrode are disposed in the second conductive layer, with the shielding electrode disposed between the first initial signal line and the second electrode plate.

[0023] A third conductive layer is formed on the second conductive layer, and the first power line and the initial signal connection line are disposed in the third conductive layer. The first power line is connected to the shielding electrode, and the initial signal connection line is connected to the first initial signal line.

[0024] The data signal line is connected to the first data fan-out line extending along the first direction of the main body, and the data signal line and the first data fan-out line are disposed in different conductive layers.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a display device;

[0028] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0030] Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0031] Figure 5 This is a timing diagram of a pixel driving circuit.

[0032] Figure 6 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0033] Figure 7 This is a schematic diagram of the structure of the data signal line and data fan-out line, which are exemplary embodiments of this disclosure;

[0034] Figure 8a and Figure 8b This is a schematic diagram of two normal areas and wiring areas, which are exemplary embodiments of this disclosure;

[0035] Figures 8c to 8j This is a schematic diagram of several compensation lines for exemplary embodiments of the present disclosure;

[0036] Figure 9 This is a schematic diagram of the structure of a driving circuit layer as an exemplary embodiment of the present disclosure;

[0037] Figure 10 This is a schematic diagram of the semiconductor layer pattern formed on the display substrate of this disclosure;

[0038] Figure 11a This is a schematic diagram of the display substrate after the first conductive layer pattern has been formed;

[0039] Figure 11b for Figure 11a A planar schematic diagram of the first conductive layer in the middle;

[0040] Figure 12aThis is a schematic diagram of the display substrate after the second conductive layer pattern has been formed;

[0041] Figure 12b for Figure 12a A schematic diagram of the second conductive layer in the middle;

[0042] Figure 13a This is a schematic diagram showing the fourth insulating layer pattern formed on the display substrate of this disclosure;

[0043] Figure 13b for Figure 13a A planar schematic diagram of multiple vias;

[0044] Figure 14a This is a schematic diagram of the display substrate after the third conductive layer pattern has been formed;

[0045] Figure 14b for Figure 14a A planar schematic diagram of the third conductive layer;

[0046] Figure 15a This is a schematic diagram showing the fifth insulating layer pattern formed on the display substrate of this disclosure;

[0047] Figure 15b for Figure 15a A planar schematic diagram of multiple vias;

[0048] Figure 16a This is a schematic diagram of the display substrate after the fourth conductive layer pattern has been formed;

[0049] Figure 16b for Figure 16a A schematic diagram of the fourth conductive layer in the middle;

[0050] Figure 17a This is a schematic diagram showing the sixth insulating layer pattern formed on the display substrate of this disclosure;

[0051] Figure 17b for Figure 17a A planar schematic diagram of multiple vias;

[0052] Figure 18a This is a schematic diagram of the display substrate after the fifth conductive layer pattern has been formed;

[0053] Figure 18b for Figure 18a A schematic diagram of the fifth conductive layer in the middle;

[0054] Figure 19a This is a schematic diagram of the display substrate after the first planarization layer pattern has been formed;

[0055] Figure 19b for Figure 19a A planar schematic diagram of multiple vias;

[0056] Figure 20a This is a schematic diagram of the display substrate after the anode pattern has been formed;

[0057] Figure 20b for Figure 20a A plan view of the intermediate anode;

[0058] Figure 21a This is a schematic diagram of another display substrate after forming a fifth insulating layer pattern;

[0059] Figure 21b for Figure 21a A planar schematic diagram of multiple vias;

[0060] Figure 22a This is a schematic diagram showing the display substrate after another fourth conductive layer pattern has been formed;

[0061] Figure 22b for Figure 22a A schematic diagram of the fourth conductive layer in the middle;

[0062] Figure 23a This is a schematic diagram of another display substrate after the formation of the fifth insulating layer pattern;

[0063] Figure 23b for Figure 23a A planar schematic diagram of multiple vias;

[0064] Figure 24a This is a schematic diagram showing the display substrate after another fourth conductive layer pattern has been formed;

[0065] Figure 24b for Figure 24a A schematic diagram of the fourth conductive layer in the middle;

[0066] Figure 25 This is a schematic diagram of the appearance of a display substrate;

[0067] Figure 26 This is a schematic diagram of the appearance of a display substrate as an exemplary embodiment of the present disclosure.

[0068] Explanation of reference numerals in the attached figures:

[0069] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0070] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0071] 17—Seventh active layer; 21—First scan signal line; 21-1—Gate block;

[0072] 22—Second scan signal line; 23—Emitting light control line; 24—First electrode plate;

[0073] 31—First initial signal line; 32—Second initial signal line; 33—Second electrode plate;

[0074] 34—Shielding electrode; 35—Opening; 41—First power supply line;

[0075] 42—Data signal line; 43—Initial signal connection line; 44—First connection electrode;

[0076] 45—Second connecting electrode; 46—Third connecting electrode; 50—Data fanout line;

[0077] 51—First data fan-out line; 52—Second data fan-out line; 53—First anode connection electrode;

[0078] 60—Lead-out wire; 61—Second anode connection electrode; 71—First compensation wire;

[0079] 72—Second compensation line; 73—Third compensation line; 74—Fourth compensation line;

[0080] 75—Fifth compensation line; 76—Sixth compensation line; 77—Seventh compensation line;

[0081] 78—Eighth compensation line; 100—Display area; 101—Substrate;

[0082] 102—Driver circuit layer; 103—Light-emitting structure layer; 104—Encapsulation layer;

[0083] 110—Normal area; 111—First routing area; 112—Second routing area;

[0084] 200—Binding area; 201—Lead wire area; 202—Bending area;

[0085] 210—Transistor; 211—Storage capacitor; 300—Border area;

[0086] 301—Anode; 302—Pixel definition layer; 303—Organic light-emitting layer;

[0087] 304—Cathode; 401—First encapsulation layer; 402—Second encapsulation layer;

[0088] 403—Third encapsulation layer. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0090] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0091] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0092] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0093] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0094] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0095] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0096] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0097] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0098] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0099] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0100] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0101] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0102] Figure 2This is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and two third sub-pixels P3 and a fourth sub-pixel P4 emitting a third color light. Each of the four sub-pixels may include a circuit unit and a light-emitting device. The circuit unit may include a scan signal line, a data signal line, a light-emitting signal line, and a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the data signal line, and the light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0103] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. In one exemplary embodiment, the four sub-pixels can be arranged in a square to form a GGRB pixel arrangement. In other exemplary embodiments, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a diamond shape, etc., and this disclosure is not limited thereto. In other exemplary embodiments, a pixel unit can include three sub-pixels, and the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure is not limited thereto.

[0104] In an exemplary embodiment, multiple sub-pixels arranged sequentially in the horizontal direction are called pixel rows, and multiple sub-pixels arranged sequentially in the vertical direction are called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array.

[0105] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels. For example... Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0106] In an exemplary embodiment, substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple signal lines and pixel driving circuitry, the pixel driving circuitry including multiple transistors and storage capacitors. Figure 3 The illustration uses only one driving transistor 210 and one storage capacitor 211 as an example. The light-emitting structure layer 103 of each sub-pixel may include multiple film layers constituting the light-emitting device. These multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of the corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0107] In an exemplary embodiment, the organic light-emitting layer 303 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer and electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer and electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layer and electron block layer of adjacent sub-pixels may have a small amount of overlap, or they may be isolated.

[0108] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 4As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is connected to 8 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD and second power supply line VSS).

[0109] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0110] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0111] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the first initial voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0112] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0113] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0114] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0115] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0116] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0117] In an exemplary embodiment, the light-emitting device may be an OLED, which includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it may be a QLED, which includes a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0118] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0119] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0120] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0121] Figure 5 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 4 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 4 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 8 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD and second power supply line VSS). All 7 transistors are P-type transistors.

[0122] In an exemplary embodiment, taking OLED as an example, the operation of the pixel driving circuit may include:

[0123] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, providing the initial voltage of the first initial signal line INIT1 to the second node N2 to initialize the storage capacitor C and clear the existing data voltage. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0124] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the second initial voltage of the second initial signal line INIT2 to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0125] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0126] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0127] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0128] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0129] With the development of OLED display technology, consumers have increasingly higher requirements for the display effect of display products. Extremely narrow bezels have become a new trend in display product development. Therefore, narrow bezels and even bezel-less designs are receiving increasing attention in OLED display product design. A display substrate typically includes a display area and a bonding area located on one side of the display area. The bonding area may include at least a first fan-out area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The first fan-out area includes at least data fan-out lines, and multiple data fan-out lines are configured to connect to the data signal lines of the display area in a fan-out routing manner. The bending area may include a composite insulating layer with grooves, configured to bend the bonding area to the back of the display area. The driver chip area may include an integrated circuit (IC), configured to connect to the multiple data fan-out lines. The bonding pin area may include bonding pads, configured to bond to an external flexible printed circuit (FPC). Typically, the width of the bonding area is smaller than the width of the display area. The signal lines of the integrated circuit and bonding pads in the bonding area need to be introduced into the wider display area through the first fan-out area. The greater the difference in width between the display area and the bonding area, the more diagonal fan-out lines there are in the fan-shaped area, and the greater the distance between the driver chip area and the display area. Therefore, the fan-shaped area occupies a large space, making it more difficult to narrow the bottom bezel design. The bottom bezel has always been maintained at around 2.0mm.

[0130] Figure 6 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6 As shown, the display substrate 10 may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of sub-pixels Pxij constituting a pixel array, a plurality of data signal lines, and a plurality of data fan-out lines. The plurality of sub-pixels Pxij are configured to display dynamic or still images, the plurality of data signal lines are configured to provide data signals to the plurality of sub-pixels Pxij, and the plurality of data fan-out lines are correspondingly connected to the plurality of data signal lines, configured such that the plurality of data signal lines are correspondingly connected to a plurality of leads in the bonding area 200 through the plurality of data fan-out lines. In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0131] In an exemplary embodiment, the display area 100 may include a plurality of pixel units arranged in a matrix. At least one pixel unit may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, a first green sub-pixel G1 emitting green light, and a second green sub-pixel G2 emitting green light. In an exemplary embodiment, the red sub-pixel R may include a red light-emitting device emitting red light and a red circuit unit connected to the red light-emitting device; the blue sub-pixel B may include a blue light-emitting device emitting blue light and a blue circuit unit connected to the blue light-emitting device; the first green sub-pixel G1 may include a first green light-emitting device emitting green light and a first green circuit unit connected to the first green light-emitting device; and the second green sub-pixel G2 may include a second green light-emitting device emitting green light and a second green circuit unit connected to the second green light-emitting device. The red circuit unit, blue circuit unit, first green circuit unit, and second green circuit unit constitute a circuit unit group, and the four circuit units in at least one circuit unit group may be arranged in a square manner. In an exemplary embodiment, the plurality of sub-pixels may form a plurality of pixel rows and a plurality of pixel columns, and the plurality of circuit units may form a plurality of circuit unit rows and a plurality of circuit unit columns. In this disclosure, a sub-pixel refers to a region divided according to a light-emitting device, and a circuit unit refers to a region divided according to a pixel driving circuit. In exemplary embodiments, the positions of sub-pixels and circuit units may correspond, or the positions of sub-pixels and circuit units may not correspond.

[0132] In an exemplary embodiment, the bonding area 200 may include a lead area 201, a bending area 202, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area 201 is connected to the display area 100, and the bending area 202 is connected to the lead area 201.

[0133] In an exemplary embodiment, the lead area 201 can be provided with multiple parallel leads extending in a direction away from the display area. One end of each lead is connected to a plurality of data fan-out lines in the display area 100, and the other end of each lead crosses the bending area 202 and connects to the integrated circuit in the driver chip area, so that the integrated circuit applies data signals to the data signal lines through the leads and data fan-out lines. Since there is no need to provide fan-shaped diagonal lines in the lead area, the vertical length of the lead area is effectively reduced, and the width of the bottom bezel is greatly reduced. This makes the widths of the top, bottom, left, and right bezels of the display device similar, all below 1.0mm, improving the screen-to-body ratio and facilitating the realization of a full-screen display.

[0134] Figure 7 This is a schematic diagram illustrating the structure of a data signal line and a data fan-out line, as exemplified by an exemplary embodiment of the present disclosure. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Multiple circuit units arranged sequentially along a first direction X are called circuit unit rows, and multiple circuit units arranged sequentially along a second direction Y are called circuit unit columns. The multiple circuit unit rows and columns constitute an array of circuit units, with the first direction X intersecting the second direction Y. In an exemplary embodiment, the first direction X may be the extension direction of the scan signal line (horizontal direction), and the second direction Y may be the extension direction of the data signal line (vertical direction). The first direction X and the second direction Y may be perpendicular to each other. Figure 7 As shown, the display area 100 may include multiple data signal lines 42 and multiple data fan-out lines 50, and the lead area 201 of the bonding area may include multiple lead-out lines 60. In an exemplary embodiment, the multiple data signal lines 42 may extend along the direction of the circuit unit column and be arranged sequentially at predetermined intervals along the direction of the circuit unit row. Each data signal line 42 is connected to the pixel driving circuit of all circuit units in a circuit unit column in the display area 100. The first end of the multiple data fan-out lines 50 is correspondingly connected to the multiple data signal lines 42, and the second end of the multiple data fan-out lines 50 is correspondingly connected to the multiple lead-out lines 60 of the lead area 201, so that the multiple data signal lines 42 in the display area 100 are correspondingly connected to the multiple lead-out lines 60 in the bonding area 200 through the multiple data fan-out lines 50 in the display area 100.

[0135] In an exemplary embodiment, the number of data fan-out lines in the display area can be the same as the number of data signal lines, with each data signal line connected to a corresponding lead through a data fan-out line. Alternatively, the number of data fan-out lines in the display area can be less than the number of data signal lines, with some data signal lines in the display area connected to corresponding leads through data fan-out lines, and other data signal lines directly connected to leads. This disclosure does not impose any limitations on this aspect.

[0136] This disclosure provides a display substrate including a driving circuit layer disposed on a substrate. The driving circuit layer includes a plurality of circuit units, each circuit unit including a pixel driving circuit, a data signal line providing data signals to the pixel driving circuit, and an initial signal line providing an initial signal. The plurality of circuit units include at least one normal circuit unit and at least one routing circuit unit. The normal circuit unit is provided with a first compensation line extending along a first direction and a second compensation line extending along a second direction. The routing circuit unit is provided with a first data fan-out line extending along the first direction or a second data fan-out line extending along the second direction. The first data fan-out line or the second data fan-out line is connected to the data signal line, and the first direction and the second direction intersect. The orthographic projection of the first compensation line in the plane of the display substrate at least partially overlaps with the orthographic projection of the initial signal line in the plane of the display substrate.

[0137] In an exemplary embodiment, the initial signal line includes a first initial signal line and a second initial signal line, the main body portions of the first initial signal line and the second initial signal line extend along the first direction, and the orthographic projection of the first compensation line in the display substrate plane at least partially overlaps with the orthographic projection of the initial signal line in the display substrate plane may include: the orthographic projection of the first compensation line in the display substrate plane at least partially overlaps with the orthographic projection of the first initial signal line in the display substrate plane, or the orthographic projection of the first compensation line in the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line in the display substrate plane.

[0138] In an exemplary embodiment, the initial signal line further includes an initial signal connection line, the main body of which extends along the second direction and is connected to the first initial signal line.

[0139] In an exemplary embodiment, the orthographic projection of the first data fan-out line in the display substrate plane at least partially overlaps with the orthographic projection of the first initial signal line in the display substrate plane, or the orthographic projection of the first data fan-out line in the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line in the display substrate plane.

[0140] In an exemplary embodiment, the circuit unit further includes a first power line that provides a power signal to the pixel driving circuit, the main body of the first power line extending along the first direction. In an exemplary embodiment, the orthographic projection of the second data fan-out line in the display substrate plane at least partially overlaps with the orthographic projection of the first power line in the display substrate plane, or at least a portion of the second data fan-out line is disposed between the first power line and the data signal line.

[0141] In an exemplary embodiment, the orthographic projection of the second data fan-out line in the plane of the display substrate at least partially overlaps with the orthographic projection of the initial signal connection line in the plane of the display substrate.

[0142] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. Insulating layers are disposed between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer. The first compensation line, the second compensation line, the first data fan-out line, and the second data fan-out line are disposed in the same layer.

[0143] In an exemplary embodiment, the data signal line is disposed in a different conductive layer from the first data fan-out line and the second data fan-out line, and the first data fan-out line or the second data fan-out line is connected to the data signal line through a via.

[0144] In an exemplary embodiment, the data signal line is disposed in the third conductive layer, and the first data fan-out line and the second data fan-out line are disposed in the fourth conductive layer; or, the data signal line is disposed in the fourth conductive layer, and the first data fan-out line and the second data fan-out line are disposed in the third conductive layer.

[0145] In an exemplary embodiment, the first initial signal line is disposed in the second conductive layer, the initial signal connection line is disposed in the third conductive layer, and the initial signal connection line is connected to the first initial signal line through a via.

[0146] In an exemplary embodiment, the data signal line and the first power line are arranged on the same layer.

[0147] Figure 8a and Figure 8b This is a schematic diagram illustrating two types of normal areas and routing areas, as exemplary embodiments of this disclosure. Figure 8a and Figure 8bAs shown, since multiple data fan-out lines 50 are set in a portion of the display area, the display area can be divided into a normal area 110 and a routing area based on whether or not data fan-out lines 50 are set. The normal area 110 can be an area without data fan-out lines 50, and the routing area can be an area with data fan-out lines 50.

[0148] In an exemplary embodiment, the normal region 110 may include a plurality of normal circuit units, and the orthographic projection of the data fan-out line 50 on the display substrate plane does not overlap with the orthographic projection of the pixel driving circuit in the normal circuit unit on the display substrate plane. The routing region may include a plurality of routing circuit units, and the orthographic projection of the data fan-out line 50 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the routing circuit unit on the display substrate plane.

[0149] In an exemplary embodiment, at least one data fan-out line 50 may include a first data fan-out line 51 extending along the direction of a circuit cell row (first direction X) and a second data fan-out line 52 extending along the direction of a circuit cell column (second direction Y). The first end of the first data fan-out line 51 is connected to a data signal line. The second end of the first data fan-out line 51 extends along the first direction X or the opposite direction of the first direction X and is connected to the first end of the second data fan-out line 52. The second end of the second data fan-out line 52 extends along the second direction Y and is connected to the lead-out line of the bonding area.

[0150] Since the data fan-out lines include a first data fan-out line 51 and a second data fan-out line 52 with different extension directions, the routing area can be divided into a first routing area 111 and a second routing area 112 according to the extension direction of the data fan-out lines. The first routing area 111 can be the area where the first data fan-out line 51 is provided, and the second routing area 112 can be the area where the second data fan-out line 52 is provided.

[0151] In an exemplary embodiment, the first trace area 111 may include a plurality of first circuit units, and the orthographic projection of the first data fan-out line 51 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the first circuit unit on the display substrate plane. In some possible exemplary embodiments, the orthographic projection of the pixel driving circuit in the first circuit unit on the display substrate plane does not overlap with the orthographic projection of the second data fan-out line 52 on the display substrate plane.

[0152] In an exemplary embodiment, the second trace region 112 may include a plurality of second circuit units, and the orthographic projection of the second data fan-out line 52 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the second circuit unit on the display substrate plane. In some possible exemplary embodiments, the orthographic projection of the pixel driving circuit in the second circuit unit on the display substrate plane does not overlap with the orthographic projection of the first data fan-out line 51 on the display substrate plane.

[0153] In an exemplary embodiment, Figure 8a and Figure 8b The division of each region shown is merely an illustrative example. Since the normal region 110, the first routing region 111, and the second routing region 112 are divided according to the presence or absence of data fan-out lines and the extension direction of the data fan-out lines, the shapes of the normal region 110, the first routing region 111, and the second routing region 112 can be regular polygons or irregular polygons. The display area can be divided into one or more normal regions 110, one or more first routing regions 111, and one or more second routing regions 112. This disclosure does not limit this.

[0154] Figure 8c This is a schematic diagram of a compensation line in a normal region, as exemplified by an embodiment of this disclosure. The normal region may include multiple normal circuit units, which do not have data fan-out lines but do have compensation lines. For example... Figure 8c As shown, in an exemplary embodiment, the compensation line in at least one normal circuit unit may include a first compensation line 71 extending along a first direction X and a second compensation line 72 extending along a second direction Y. The first compensation line 71 and the second compensation line 72 intersect each other and are an integral structure connected to each other.

[0155] In an exemplary embodiment, the first compensation line 71 can be continuously arranged in a circuit cell row, and the first compensation lines 71 in adjacent normal circuit cells in the first direction X are interconnected. The second compensation line 72 can be continuously arranged in a circuit cell column, and the second compensation lines 72 in adjacent normal circuit cells in the second direction Y are interconnected.

[0156] In one exemplary embodiment, the normal circuit unit further includes a first power line that provides a power signal to the pixel driving circuit. The main body of the first power line can extend along the second direction Y. The orthographic projection of the second compensation line 72 in the display substrate plane can at least partially overlap with the orthographic projection of the first power line in the display substrate plane. In a possible exemplary embodiment, the second compensation line 72 can be connected to the first power line via a via.

[0157] In another exemplary embodiment, the orthographic projection of the second compensation line 72 in the plane of the display substrate can be located between the orthographic projection of the first power line in the plane of the display substrate and the orthographic projection of the data signal line in the plane of the display substrate, that is, the orthographic projection of the second compensation line 72 in the plane of the display substrate does not overlap with the orthographic projection of the first power line in the plane of the display substrate.

[0158] In another exemplary embodiment, the normal circuit unit further includes an initial signal line that provides an initial signal to the pixel driving circuit. The initial signal line may include a first initial signal line, a second initial signal line, and an initial signal connection line. The main body portions of the first and second initial signal lines may extend along a first direction X, and the main body portion of the initial signal connection line may extend along a second direction Y. The initial signal connection line can be connected to the first initial signal line via a via. The orthographic projection of the first compensation line 71 in the display substrate plane may at least partially overlap with the orthographic projection of the first or second initial signal line in the display substrate plane. The orthographic projection of the second compensation line 72 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane. In a possible exemplary embodiment, the second compensation line 72 can be connected to the initial signal connection line via a via.

[0159] Figure 8d This is a schematic diagram of another compensation line in the normal region of an exemplary embodiment of this disclosure. (See diagram below.) Figure 8d As shown, in an exemplary embodiment, the compensation line in at least one normal circuit unit may include a first compensation line 71 extending along a first direction X and a second compensation line 72 extending along a second direction Y. The two second compensation lines 72 may be disposed on the side of the first compensation line 71 in the second direction Y or the opposite direction of the second direction Y, and the two second compensation lines 72 and the first compensation line 71 form an integral structure interconnected. In a possible exemplary embodiment, the two second compensation lines 72 may be interconnected by a connecting strip extending along the first direction X.

[0160] In an exemplary embodiment, the first compensation line 71 can be continuously arranged in a row of circuit cells, and the first compensation lines 71 in adjacent normal circuit cells in the first direction X are interconnected. The second compensation line 72 can be spaced out in a column of circuit cells.

[0161] In an exemplary embodiment, the orthographic projection of the first compensation line 71 onto the display substrate plane may at least partially overlap with the orthographic projection of the second initial signal line onto the display substrate plane, and the orthographic projection of the connecting strip onto the display substrate plane may at least partially overlap with the orthographic projection of the first initial signal line onto the display substrate plane. Alternatively, the orthographic projection of the first compensation line 71 onto the display substrate plane may at least partially overlap with the orthographic projection of the first initial signal line onto the display substrate plane, and the orthographic projection of the connecting strip onto the display substrate plane may at least partially overlap with the orthographic projection of the second initial signal line onto the display substrate plane.

[0162] In one exemplary embodiment, the orthographic projection of at least one second compensation line 72 in the plane of the display substrate can at least partially overlap with the orthographic projection of the first power line in the plane of the display substrate, and can be connected to the first power line through a via.

[0163] In another exemplary embodiment, the orthographic projection of at least one second compensation line 72 in the plane of the display substrate may be located between the orthographic projection of the first power line in the plane of the display substrate and the orthographic projection of the data signal line in the plane of the display substrate.

[0164] In another exemplary embodiment, the orthographic projection of at least one second compensation line 72 in the plane of the display substrate can at least partially overlap with the orthographic projection of the initial signal connection line in the plane of the display substrate, and can be connected to the initial signal connection line through a via.

[0165] Figure 8e This is a schematic diagram of a compensation line in a first routing area, as described in an exemplary embodiment of this disclosure. Figure 8e As shown, the first routing area may include multiple first circuit units, and at least one first circuit unit is provided with a first data fan-out line 51 and a third compensation line 73. In an exemplary embodiment, the first data fan-out line 51 extends along a first direction X, and the third compensation line 73 extends along a second direction Y.

[0166] In an exemplary embodiment, the first data fan-out line 51 can be continuously arranged in a circuit unit row, and the first data fan-out lines 51 in adjacent first circuit units in the first direction X are interconnected.

[0167] In an exemplary embodiment, the third compensation line 73 may be spaced out in a circuit unit column, and the third compensation line 73 may be disposed on one side or both sides of the first data fan-out line 51. A first gap L1 is formed between the edge of the first data fan-out line 51 near the third compensation line 73 and the end face of the third compensation line 73 near the first data fan-out line 51.

[0168] In an exemplary embodiment, the orthographic projection of the first data fan-out line 51 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line in the plane of the display substrate.

[0169] In an exemplary embodiment, the orthographic projection of the third compensation line 73 in the display substrate plane may at least partially overlap with the orthographic projection of the first power line in the display substrate plane; or, the orthographic projection of the third compensation line 73 in the display substrate plane may be located between the orthographic projection of the first power line in the display substrate plane and the orthographic projection of the data signal line in the display substrate plane; or, the orthographic projection of the third compensation line 73 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane.

[0170] Figure 8f This is a schematic diagram of a compensation line in the second wiring region of an exemplary embodiment of this disclosure. Figure 8f As shown, the second routing area may include multiple second circuit units, at least one of which is provided with a second data fan-out line 52 and a fourth compensation line 74. In an exemplary embodiment, the second data fan-out line 52 extends along a second direction Y, and the fourth compensation line 74 extends along a first direction X.

[0171] In an exemplary embodiment, the second data fan-out line 52 can be continuously arranged in a circuit unit column, and the second data fan-out lines 52 in adjacent second circuit units in the second direction Y are interconnected.

[0172] In an exemplary embodiment, the fourth compensation line 74 may be spaced out in a circuit cell row, and the fourth compensation line 74 may be disposed on one or both sides of the second data fan-out line 52. A second spacing L2 exists between the edge of the second data fan-out line 52 near the fourth compensation line 74 and the end face of the fourth compensation line 74 near the second data fan-out line 52.

[0173] In an exemplary embodiment, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the first power line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may be located between the orthographic projection of the first power line in the display substrate plane and the orthographic projection of the data signal line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane.

[0174] In an exemplary embodiment, the orthographic projection of the fourth compensation line 74 onto the display substrate plane may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line onto the display substrate plane. In a possible exemplary embodiment, the fourth compensation line 74 may be connected to the first initial signal line, the second initial signal line, or the initial signal connection line via a via.

[0175] Figure 8g This is a schematic diagram of another type of compensation line in the first routing area of ​​an exemplary embodiment of this disclosure. (See diagram below.) Figure 8g As shown, the first routing area may include multiple first circuit units, and at least one first circuit unit is provided with a first data fan-out line 51 and a fifth compensation line 75. In an exemplary embodiment, the first data fan-out line 51 extends along a first direction X, the fifth compensation line 75 extends along a second direction Y, the fifth compensation line 75 intersects with the first data fan-out line 51, and they are an integral structure that is interconnected.

[0176] In an exemplary embodiment, the first data fan-out line 51 can be continuously arranged in a circuit unit row, and the first data fan-out lines 51 in adjacent first circuit units in the first direction X are connected to each other. The fifth compensation line 75 can be arranged in each first circuit unit and can be located on one or both sides of the first data fan-out line 51 in the second direction Y.

[0177] In an exemplary embodiment, the orthographic projection of the first data fan-out line 51 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line in the plane of the display substrate.

[0178] In an exemplary embodiment, the orthographic projection of the fifth compensation line 75 in the display substrate plane may at least partially overlap with the orthographic projection of the first power line in the display substrate plane; or, the orthographic projection of the fifth compensation line 75 in the display substrate plane may be located between the orthographic projection of the first power line in the display substrate plane and the orthographic projection of the data signal line in the display substrate plane; or, the orthographic projection of the fifth compensation line 75 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane.

[0179] Figure 8h This is a schematic diagram of another type of compensation line in the second routing area of ​​an exemplary embodiment of this disclosure. (See diagram below.) Figure 8h As shown, the second routing area may include multiple second circuit units, and at least one second circuit unit is provided with a second data fan-out line 52 and a sixth compensation line 76. In an exemplary embodiment, the second data fan-out line 52 extends along the second direction Y, and the sixth compensation line 76 extends along the first direction X. The sixth compensation line 76 and the second data fan-out line 52 intersect each other and are an integral structure that is interconnected.

[0180] In an exemplary embodiment, the second data fan-out line 52 can be continuously arranged in a circuit unit column, and the second data fan-out lines 52 in adjacent second circuit units in the second direction Y are interconnected. The sixth compensation line 76 can be arranged in each second circuit unit, and the sixth compensation line 76 can be located on one side of the second data fan-out line 52 in the first direction X or on the opposite side of the first direction X.

[0181] In an exemplary embodiment, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the first power line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may be located between the orthographic projection of the first power line in the display substrate plane and the orthographic projection of the data signal line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane.

[0182] In an exemplary embodiment, the orthographic projection of the sixth compensation line 76 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line in the plane of the display substrate.

[0183] Figure 8i This is a schematic diagram of another type of compensation line in the first routing area of ​​an exemplary embodiment of this disclosure. (See diagram below.) Figure 8i As shown, the first routing area may include multiple first circuit units, at least one of which is provided with a first data fan-out line 51 and two seventh compensation lines 77. The two seventh compensation lines 77 may be located on one side of the first data fan-out line 51 in the second direction Y or the opposite direction of the second direction Y. In an exemplary embodiment, the two seventh compensation lines 77 may be interconnected by a connecting strip extending along the first direction X to form an "H" shaped structure.

[0184] In an exemplary embodiment, the orthographic projection of the first data fan-out line 51 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line in the plane of the display substrate.

[0185] In an exemplary embodiment, the orthographic projection of at least one seventh compensation line 77 onto the display substrate plane may at least partially overlap with the orthographic projection of the first power line onto the display substrate plane; alternatively, the orthographic projection of at least one seventh compensation line 77 onto the display substrate plane may be located between the orthographic projections of the first power line and the data signal line onto the display substrate plane; or alternatively, the orthographic projection of at least one seventh compensation line 77 onto the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line onto the display substrate plane. In an exemplary embodiment, the orthographic projection of the connecting strip connecting two seventh compensation lines 77 onto the display substrate plane may at least partially overlap with the orthographic projections of the first initial signal line or the second initial signal line onto the display substrate plane.

[0186] In an exemplary embodiment, at least one seventh compensation line 77 may be connected to the first power line via a via, or at least one seventh compensation line 77 may be connected to the initial signal connection line via a via.

[0187] Figure 8j This is a schematic diagram of yet another type of compensation line in the second routing area of ​​an exemplary embodiment of this disclosure. For example... Figure 8j As shown, the second routing area may include multiple second circuit units, and at least one second circuit unit is provided with a second data fan-out line 52 and an eighth compensation line 78. In an exemplary embodiment, the second data fan-out line 52 extends along the second direction Y, and the eighth compensation line 78 extends along the first direction X. The eighth compensation line 78 and the second data fan-out line 52 intersect each other and are an integral structure connected to each other.

[0188] In an exemplary embodiment, the second data fan-out line 52 can be continuously arranged in a circuit unit column, and the second data fan-out lines 52 in adjacent second circuit units in the second direction Y are interconnected. The eighth compensation line 78 can be arranged in each second circuit unit, and the eighth compensation line 78 can be located on one side of the second data fan-out line 52 in the first direction X and on the side opposite to the first direction X.

[0189] In an exemplary embodiment, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the first power line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may be located between the orthographic projection of the first power line in the display substrate plane and the orthographic projection of the data signal line in the display substrate plane; or, the orthographic projection of the second data fan-out line 52 in the display substrate plane may at least partially overlap with the orthographic projection of the initial signal connection line in the display substrate plane.

[0190] In an exemplary embodiment, the orthographic projection of the eighth compensation line 78 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line or the second initial signal line in the plane of the display substrate.

[0191] like Figures 8a to 8j As shown, in a normal circuit unit, the first compensation line 71 has a first compensation width C1, and the second compensation line 72 has a second compensation width C2. In the first circuit unit, the first data fan-out line 51 may have a first fan-out width B1, and the third compensation line 73, the fifth compensation line 75, and the seventh compensation line 77 may each have a third compensation width C3. In the second circuit unit, the second data fan-out line 52 may have a second fan-out width B2, and the fourth compensation line 74, the sixth compensation line 76, and the eighth compensation line 78 may have a fourth compensation width C4. Wherein, the first compensation width C1, the first fan-out width B1, and the fourth compensation width C4 can be dimensions in the second direction Y, and the second compensation width C2, the third compensation width C3, and the second fan-out width B2 can be dimensions in the first direction X.

[0192] In an exemplary embodiment, the first compensation width C1 and the first fan-out width B1 may be the same, and the fourth compensation width C4 and the first fan-out width B1 may be the same.

[0193] In an exemplary embodiment, the second compensation width C2 and the second fan-out width B2 can be the same, and the third compensation width C3 and the second fan-out width B2 can be the same.

[0194] In an exemplary embodiment, the first spacing L1 and the first fan-out width B1 can be the same, and the second spacing L2 and the second fan-out width B2 can be the same.

[0195] Figure 9 This is a schematic diagram of a driving circuit layer as an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two circuit units in rows and four circuit units in columns) in a normal region. For example... Figure 9 As shown, in a plane parallel to the display substrate, at least one circuit unit may include: a first scan signal line 21, a second scan signal line 22, a light emission signal line 23, a first initial signal line 31, a second initial signal line 32, a first power supply line 41, a data signal line 42, an initial signal connection line 43, a first compensation line 71, a second compensation line 72, and a pixel driving circuit. The pixel driving circuit may include a storage capacitor and seven transistors. The seven transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The third transistor may be a driving transistor.

[0196] In an exemplary embodiment, the main body portions of the first scan signal line 21, the second scan signal line 22, the light emission signal line 23, the first initial signal line 31, the second initial signal line 32, and the first compensation line 71 may extend along the first direction X, and the main body portions of the first power line 41, the data signal line 42, the initial signal connection line 43, and the second compensation line 72 may extend along the second direction Y.

[0197] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include at least a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. In an exemplary embodiment, the semiconductor layer may include an active layer of multiple transistors; the first conductive layer may include a first scan signal line 21, a second scan signal line 22, the gate electrodes of the multiple transistors, and the first electrode of a storage capacitor; the second conductive layer may include a first initial signal line 31, a second initial signal line 32, and the second electrode of a storage capacitor; the third conductive layer may include a first power supply line 41, a data signal line 42, an initial signal connection line 43, and the first and second electrodes of the multiple transistors; and the fourth conductive layer may include a first compensation line 71 and a second compensation line 72.

[0198] In an exemplary embodiment, the initial signal connection line 43 located in the third conductive layer can be connected to the first initial signal line 31 located in the second conductive layer through a via, such that the first initial signal line 31 extending along the first direction X of the main body and the initial signal connection line 43 extending along the second direction Y of the main body form a grid, and the first initial signal line 31 in the multiple circuit unit rows and multiple circuit unit columns have the same potential.

[0199] In an exemplary embodiment, the driving circuit layer may include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is disposed between the substrate and the semiconductor layer, the second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.

[0200] In an exemplary embodiment, the orthographic projection of the first compensation line 71 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line 31 or the second initial signal line 32 in the plane of the display substrate.

[0201] In one exemplary embodiment, the orthographic projection of the second compensation line 72 in the plane of the display substrate at least partially overlaps with the orthographic projection of the first power line 41 in the plane of the display substrate, and the second compensation line 72 can be connected to the first power line 41 through a via.

[0202] In another exemplary embodiment, the orthographic projection of the second compensation line 72 in the plane of the display substrate can be located between the orthographic projection of the first power line 41 in the plane of the display substrate and the orthographic projection of the data signal line 42 in the plane of the display substrate.

[0203] In another exemplary embodiment, the orthographic projection of the second compensation line 72 in the plane of the display substrate at least partially overlaps with the orthographic projection of the initial signal connection line 43 in the plane of the display substrate, and the second compensation line 72 can be connected to the initial signal connection line 43 through a via.

[0204] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0205] Figures 10 to 20b The fabrication process of a normal area in a display substrate is illustrated using an example of eight circuit units (two circuit units in a row and four circuit units in a column). In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0206] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 10 As shown.

[0207] In an exemplary embodiment, the semiconductor layer of each circuit unit may include a first active layer 11 of the first transistor T1 to a seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 are an interconnected integrated structure. In each circuit unit column, the sixth active layer 16 of the M-th row circuit unit and the seventh active layer 17 of the (M+1)-th row circuit unit are connected to each other, that is, the semiconductor layers of adjacent circuit units in each circuit unit column are an interconnected integrated structure.

[0208] In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14 and the seventh active layer 17 in the M-th row circuit unit are located on a side of the third active layer 13 of the current circuit unit away from the (M+1)-th row circuit unit, the first active layer 11 and the seventh active layer 17 are located on a side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13, and the fifth active layer 15 and the sixth active layer 16 in the M-th row circuit unit are located on a side of the third active layer 13 close to the (M+1)-th row circuit unit.

[0209] In an exemplary embodiment, the first active layer 11 may be n-shaped, the second active layer 12 may be 7-shaped, the third active layer 13 may be inverted Ω-shaped, the fourth active layer 14 and the seventh active layer 17 may be 1-shaped, and the fifth active layer 15 and the sixth active layer 16 may be L-shaped.

[0210] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 may be separately provided. The second region of the first active layer 11 simultaneously serves as the first region of the second active layer 12, and both are connected to point a (the second node N2); the first region of the third active layer 13 simultaneously serves as the second region of the fourth active layer 14 and the second region of the fifth active layer 15, and all three are connected to point b (the first node N1); the second region of the third active layer 13 simultaneously serves as the second region of the second active layer 12 and the first region of the sixth active layer 16, and all three are connected to point c (the third node N3); the second region of the sixth active layer 16 simultaneously serves as the second region of the seventh active layer 17, and both are connected to point d.

[0211] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern includes at least: a first scan signal line 21, a second scan signal line 22, a light emission control line 23, and a first electrode 24, such as... Figure 11a and Figure 11b As shown, Figure 11b for Figure 11a A schematic planar view of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE 1) layer.

[0212] Combination Figures 10 to 11b As shown, the main body portions of the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 can extend along the first direction X. The first scan signal line 21 and the second scan signal line 22 in the Mth row of the circuit unit can be located on the side of the first electrode plate 24 of this circuit unit away from the (M+1)th row of the circuit unit. The second scan signal line 22 is located on the side of the first scan signal line 21 of this circuit unit away from the first electrode plate 24. The light emission control line 23 can be located on the side of the first electrode plate 24 of this circuit unit closer to the (M+1)th row of the circuit unit.

[0213] In an exemplary embodiment, the first electrode 24 may be rectangular, with chamfered corners. The orthographic projection of the first electrode 24 onto the substrate overlaps with the orthographic projection of the third active layer 13 of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode 24 may simultaneously serve as an electrode of a storage capacitor and a gate electrode of the third transistor T3.

[0214] In an exemplary embodiment, the region where the first scan signal line 21 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2. The first scan signal line 21 is provided with a gate block 21-1 protruding towards the second scan signal line 22. The orthographic projection of the gate block 21-1 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate, forming a dual-gate structure second transistor T2. The region where the first scan signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The region where the second scan signal line 22 overlaps with the first active layer 11 serves as the gate electrode of the dual-gate structure first transistor T1. The region where the second scan signal line 22 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7. The region where the light-emitting control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5. The region where the light-emitting control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.

[0215] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the seventh active layer are both conducted.

[0216] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern includes at least: a first initial signal line 31, a second initial signal line 32, a second electrode 33, and a shielding electrode 34, such as... Figure 12a and Figure 12b As shown, Figure 12b for Figure 12a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE 2) layer.

[0217] Combination Figures 10 to 12b As shown, the main body portions of the first initial signal line 31 and the second initial signal line 32 can extend along the first direction X. The first initial signal line 31 in the Mth row of the circuit unit can be located between the first scan signal line 21 and the second scan signal line 22 of this circuit unit, and the second initial signal line 32 can be located on the side of the second scan signal line 22 of this circuit unit away from the first scan signal line 21. The second electrode 33, as the other electrode of the storage capacitor, is located between the first scan signal line 21 and the light emission control line 23 of this circuit unit. The shielding electrode 34 is located between the first scan signal line 21 (excluding the main body portion of the gate block 21-1) and the second initial signal line 32 of this circuit unit. The shielding electrode 34 is configured to shield the influence of data voltage jumps on critical nodes, avoid data voltage jumps affecting the potential of critical nodes in the pixel driving circuit, and improve the display effect.

[0218] In an exemplary embodiment, the outline of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 33 on the substrate overlaps with the orthographic projection of the first electrode plate 24 on the substrate. The first electrode plate 24 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit. An opening 35 is provided on the second electrode plate 33, and the opening 35 can be located in the middle of the second electrode plate 33. The opening 35 can be rectangular, so that the second electrode plate 33 forms a ring structure. The opening 35 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 35 on the substrate. In an exemplary embodiment, the opening 35 is configured to accommodate a subsequently formed first via, the first via being located within the opening 35 and exposing the first electrode plate 24, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode plate 24.

[0219] In an exemplary embodiment, the second plates 33 of adjacent circuit units in the first direction X or the opposite direction of the first direction X can be connected by plate connecting lines. The first end of the plate connecting line is connected to the second plate 33 of the circuit unit, and the second end extends along the first direction X or the opposite direction of the first direction X and is connected to the second plate 33 of the adjacent circuit unit. That is, the plate connecting lines are configured to connect the second plates 33 of adjacent circuit units in a circuit unit row to each other. In an exemplary embodiment, the plate connecting lines can form an integrated structure where the second plates of multiple circuit units in a circuit unit row are interconnected. The integrated structure of the second plates can be reused as power signal connecting lines, ensuring that multiple second plates in a circuit unit row have the same potential. This helps improve the uniformity of the panel, avoids display defects in the display substrate, and ensures the display effect of the display substrate.

[0220] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with a plurality of vias, the plurality of vias including at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eleventh via V11, a ninth via V9, a tenth via V10, and an eleventh via V11, such as... Figure 13a and Figure 13b As shown, Figure 13b for Figure 13a A planar schematic diagram of multiple vias.

[0221] Combination Figures 10 to 13bAs shown, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the opening 35 of the second electrode plate 33 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 24. The first via V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 via this via.

[0222] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the range of the orthographic projection of the second electrode plate 33 onto the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 33. The second via V2 is configured to allow a subsequently formed first power line to connect to the second electrode plate 33 through the via. In an exemplary embodiment, multiple second vias V2 may be included as power vias, and these multiple second vias V2 may be arranged sequentially along the second direction Y to increase the reliability of the connection between the first power line and the second electrode plate 33.

[0223] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the range of the orthographic projection of the fifth active layer onto the substrate. The fourth, third, and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow a subsequently formed first power line to connect to the fifth active layer through the via.

[0224] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the sixth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fourth via V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via.

[0225] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the range of the orthographic projection of the fourth active layer onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to allow subsequently formed data signal lines to connect to the fourth active layer through this via; the fifth via V5 is referred to as a data write via.

[0226] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the second active layer onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer). The sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first active layer through the via, and to connect the first electrode of the subsequently formed second transistor T2 to the second active layer through the via.

[0227] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the range of the orthographic projection of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer. The seventh via V7 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the seventh active layer through the via.

[0228] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the range of the orthographic projection of the first active layer onto the substrate. The fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the first active layer. The eighth via V8 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first active layer through the via.

[0229] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the first initial signal line 31 onto the substrate. The fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the first initial signal line 31. The ninth via V9 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first initial signal line 31 through the via.

[0230] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the range of the orthographic projection of the second initial signal line 32 onto the substrate. The fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the second initial signal line 32. The tenth via V10 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the second initial signal line 32 through the via.

[0231] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the shielding electrode 34 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the shielding electrode 34. The eleventh via V11 is configured to allow a subsequently formed first power line to connect to the shielding electrode 34 through the via.

[0232] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a third conductive layer disposed on a fourth insulating layer, the third conductive layer including at least: a first power line 41, a data signal line 42, an initial signal connection line 43, a first connection electrode 44, a second connection electrode 45, and a third connection electrode 46, such as Figure 14a and Figure 14b As shown, Figure 14b for Figure 14a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0233] Combination Figures 10 to 14b As shown, the main body of the first power line 41 can extend along the second direction Y. The first power line 41 is connected to the second electrode plate 33 through the second via V2, connected to the fifth active layer through the third via V3, and connected to the shielding electrode 34 through the eleventh via V11, so that the shielding electrode 34 and the second electrode plate 33 have the same potential as the first power line 41. Since the shielding electrode 34 is connected to the first power line 41, and at least a portion of the shielding electrode 34 (such as the vertical part on the right side of the shielding electrode 34) is located between the first connecting electrode 44 (which serves as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, i.e., the second node N2) and the data signal line 42, the influence of data voltage jumps on key nodes in the pixel driving circuit can be effectively shielded, avoiding the impact of data voltage jumps on the potential of key nodes in the pixel driving circuit, thus improving the display effect.

[0234] In an exemplary embodiment, the main body of the data signal line 42 may extend along the second direction Y, and the data signal line 42 is connected to the first region of the fourth active layer through the fifth via V5, thereby enabling the data signal line 42 to write the data signal to the fourth transistor T4.

[0235] In an exemplary embodiment, the initial signal connection line 43 can be a zigzag shape extending along the second direction Y. In each circuit unit, the initial signal connection line 43 is connected to the first initial signal line 31 through the ninth via V9 on one hand, and to the first region of the first active layer through the eighth via V8 on the other hand. The initial signal connection line 43 can serve as the first pole of the first transistor T1, thus enabling the first initial signal line 31 to write the first initial signal into the first transistor T1.

[0236] In an exemplary embodiment, the initial signal connection line 43 may include a first line segment 43-1 and a second line segment 43-2 that are connected to each other. The first line segment 43-1 may be a straight line segment extending along the second direction Y, and the second line segment 43-2 may be a broken line segment.

[0237] In an exemplary embodiment, the second line segment 43-2 may include a first sub-line segment 43-2A and a third sub-line segment 43-2C extending along the first direction X of the main body portion, and a second sub-line segment 43-2B extending along the second direction Y of the main body portion. In a circuit unit column, the first end of the first sub-line segment 43-2A of the Mth circuit unit is connected to the first line segment 43-1 of the (M-1)th circuit unit, and the second end extends along the first direction X and is connected to the first end of the second sub-line segment 43-2B. The second end of the second sub-line segment 43-2B extends along the second direction Y and is connected to the first end of the third sub-line segment 43-2C. The second end of the third sub-line segment 43-2C extends in the opposite direction of the first direction X and is connected to the first line segment 43-1 of the circuit unit.

[0238] In an exemplary embodiment, the initial signal connection line 43 of the Mth row circuit unit in each circuit unit column is interconnected with the initial signal connection line 43 of the (M+1)th row circuit unit, meaning that the initial signal connection lines 43 of adjacent circuit units in each circuit unit column are interconnected as an integral structure. Since the initial signal connection line 43 is connected to the first initial signal line 31 through the ninth via V9, the integral structure of the initial signal connection line 43 can be reused as a vertical initial signal line. The first initial signal line 31 extending along the first direction X and the initial signal connection line 43 extending along the second direction Y of the main body form a mesh. This disclosure, by connecting the initial signal connection line to the first initial signal line, enables the first initial signal line to form a mesh structure. Multiple first initial signal lines 31 in multiple circuit unit rows and multiple circuit unit columns have the same potential, effectively reducing the resistance of the first initial signal line and decreasing the voltage drop of the first initial voltage. Furthermore, it effectively improves the uniformity of the first initial voltage in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0239] In an exemplary embodiment, there is an overlap between the orthographic projection of the initial signal connection line 43 on the substrate and the orthographic projection of the shielding electrode 34 on the substrate.

[0240] In an exemplary embodiment, the first connecting electrode 44 can be a straight line extending along the second direction Y. Its first end is connected to the second region of the first active layer (which is also the first region of the second active layer) through a sixth via V6, and its second end is connected to the first electrode plate 24 through a first via V1, so that the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connecting electrode 44 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0241] In an exemplary embodiment, the second connection electrode 45 can be a straight line extending along the second direction Y, with its first end connected to the second initial signal line 32 through the tenth via V10 and its second end connected to the first region of the seventh active layer through the seventh via V7. The second connection electrode 45 can serve as the first electrode of the seventh transistor T7, thus enabling the second initial signal line 32 to write the second initial signal into the seventh transistor T7.

[0242] In an exemplary embodiment, the third connection electrode 46 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4, such that the second terminals of the sixth transistor T6 and the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 46 can serve as the second terminal of both the sixth transistor T6 and the seventh transistor T7. In an exemplary embodiment, the third connection electrode 46 is configured to connect to a subsequently formed first anode connection electrode.

[0243] In an exemplary embodiment, the first power line 41 of each circuit unit can be designed with non-uniform width. The non-uniform width design of the first power line 41 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0244] In an exemplary embodiment, the shapes of the first power line 41, data signal line 42, initial signal connection line 43, first connection electrode 44, second connection electrode 45 and third connection electrode 46 of each circuit unit may be the same or different, and this disclosure does not limit them.

[0245] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, the plurality of vias including at least a twelfth via V12 and a twenty-first via V21, such as... Figure 15a and Figure 15b As shown, Figure 15b for Figure 15a A planar schematic diagram of multiple vias.

[0246] Combination Figures 10 to 15b As shown, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the third connecting electrode 46 on the substrate. The fifth insulating layer inside the twelfth via V12 is removed, exposing the surface of the third connecting electrode 46. The twelfth via V12 is configured to allow the subsequently formed first anode connecting electrode to be connected to the third connecting electrode 46 through the via.

[0247] The orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate. The fifth insulating layer inside the 21st via V21 is removed, exposing the surface of the first power line 41. The 21st via V21 is configured to allow the subsequently formed second compensation line to be connected to the first power line 41 through the via.

[0248] In an exemplary embodiment, the twenty-first via V21 may include multiple vias, and the multiple twenty-first vias V21 may be arranged sequentially along the second direction Y to increase the connection reliability between the first power line and the second compensation line.

[0249] In an exemplary embodiment, the positions of the twelfth via V12 and the twenty-first via V21 in each circuit unit may be the same or different, and this disclosure does not limit this.

[0250] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, the fourth conductive layer including at least: a first compensation line 71, a second compensation line 72, and a first anode connection electrode 53, such as Figure 16a and Figure 16b As shown, Figure 16b for Figure 16a A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0251] Combination Figures 10 to 16b As shown, in an exemplary embodiment, the first compensation line 71 can be a straight line extending along the first direction X of the main body, and the second compensation line 72 can be a straight line extending along the second direction Y of the main body. The first compensation line 71 and the second compensation line 72 intersect each other and are connected to each other in an integral structure.

[0252] In an exemplary embodiment, the orthographic projection of the first compensation line 71 onto the display substrate plane may at least partially overlap with the orthographic projection of the second initial signal line 32 onto the display substrate plane. In another exemplary embodiment, the orthographic projection of the first compensation line 71 onto the display substrate plane may at least partially overlap with the orthographic projection of the first initial signal line 31 onto the display substrate plane.

[0253] In one exemplary embodiment, the orthographic projection of the second compensation line 72 on the substrate at least partially overlaps with the orthographic projection of the first power line 41 on the substrate, and the second compensation line 72 is connected to the first power line 41 through at least one twenty-first via V21. In another possible exemplary embodiment, the orthographic projection of the second compensation line 72 on the substrate is located within the range of the orthographic projection of the first power line 41 on the substrate.

[0254] In another exemplary embodiment, the orthographic projection of the second compensation line 72 on the substrate may be located between the orthographic projection of the first power line 41 on the substrate and the orthographic projection of the data signal line 42 in the plane of the display substrate.

[0255] In another exemplary embodiment, the orthographic projection of the second compensation line 72 in the plane of the display substrate can at least partially overlap with the orthographic projection of the initial signal connection line 43 in the plane of the display substrate, and the second compensation line 72 can be connected to the initial signal connection line 43 through a via.

[0256] In an exemplary embodiment, a first anode connection electrode 53 may be disposed in each circuit unit. The first anode connection electrode 53 is connected to a third connection electrode 46 via a twelfth via V12. Since the third connection electrode 46 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via a fourth via V4, the first anode connection electrode 53 is thus connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the third connection electrode 46. In an exemplary embodiment, the first anode connection electrode 53 is configured to be connected to a subsequently formed second anode connection electrode.

[0257] In an exemplary embodiment, the shape of the first anode connection electrode in the Nth column of circuit units may be the same as the shape of the first anode connection electrode in the N+2th column of circuit units, and the shape of the first anode connection electrode in the N+1th column of circuit units may be the same as the shape of the first anode connection electrode in the N+3th column of circuit units. The shape of the first anode connection electrode may be rectangular.

[0258] In a display substrate, the display area includes a trace area with data fan-out lines and a normal area without data fan-out lines. Because the data fan-out lines in the trace area have high reflectivity under external light, while the other metal lines in the normal area have weak reflectivity, the appearance of the normal area differs significantly from that of the trace area, resulting in an appearance defect in the display substrate, especially noticeable when the screen is off or in low grayscale display. An exemplary embodiment of this disclosure provides compensation lines in the normal area. These compensation lines are disposed on the same layer as the data fan-out lines and formed simultaneously through the same patterning process. This makes the reflectivity of the compensation lines in the normal area substantially similar to that of the data fan-out lines in the trace area, eliminating the appearance difference between the normal area and the trace area and avoiding an appearance defect in the display substrate.

[0259] Figure 16a and Figure 16b China only Figure 8c The first compensation line 71 and the second compensation line 72 shown are illustrated by way of example. In other exemplary embodiments, Figure 16a and Figure 16b It can be adopted in China Figure 8d The structure of the first compensation line 71 and the second compensation line 72 shown is not limited in this disclosure.

[0260] (18) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering a fourth conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, and the plurality of vias includes at least a thirteenth via V13, such as... Figure 17a and Figure 17b As shown, Figure 17b for Figure 17a A planar schematic diagram of multiple vias.

[0261] Combination Figures 10 to 17b As shown, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the first anode connection electrode 53 on the substrate. The sixth insulating layer inside the thirteenth via V13 is removed, exposing the surface of the first anode connection electrode 53. The thirteenth via V13 is configured to allow the subsequently formed second anode connection electrode to be connected to the first anode connection electrode 53 through the via.

[0262] In an exemplary embodiment, the positions of the thirteenth via V13 in each circuit unit may be the same or different, and this disclosure does not limit this.

[0263] (19) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a sixth insulating layer, the fifth conductive layer including at least: a second anode connection electrode 61, such as... Figure 18a and Figure 18b As shown, Figure 18b for Figure 18a A planar schematic diagram of the fifth conductive layer.

[0264] Combination Figures 10 to 18b As shown, in an exemplary embodiment, a second anode connection electrode 61 may be provided in each circuit unit. The second anode connection electrode 61 is connected to the first anode connection electrode 53 via a thirteenth via V13. Since the first anode connection electrode 53 is connected to the third connection electrode 46 via a twelfth via V12, and the third connection electrode 46 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via a fourth via V4, the second anode connection electrode 61 is thus connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the first anode connection electrode 53 and the third connection electrode 46. In an exemplary embodiment, the second anode connection electrode 61 is configured to connect to a subsequently formed anode.

[0265] In an exemplary embodiment, the shape of the anode connection electrode in the circuit unit in row M and column N can be the same as the shape of the second anode connection electrode in the circuit unit in row M+1 and column N+2, the shape of the second anode connection electrode in the circuit unit in row M+1 and column N can be the same as the shape of the second anode connection electrode in the circuit unit in row M and column N+2, the shape of the second anode connection electrode in the circuit unit in column N+1 can be the same as the shape of the second anode connection electrode in the circuit unit in column N+3, and the shape of the second anode connection electrode can be rectangular.

[0266] (110) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, patterning the first planarization film using a patterning process to form a first planarization layer covering a fifth conductive layer, wherein a fourteenth via V14 is provided on the first planarization layer, such as... Figure 19a and Figure 19b As shown, Figure 19b for Figure 19a A planar schematic diagram of multiple vias.

[0267] Combination Figures 10 to 19bAs shown, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the second anode connection electrode 61 on the substrate. The first planarization layer inside the fourteenth via V14 is removed, exposing the surface of the second anode connection electrode 61. The fourteenth via V14 is configured to allow the subsequently formed anode to be connected to the second anode connection electrode 61 through the via.

[0268] At this point, the driving circuit layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a light emission control line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In an exemplary embodiment, at least one circuit unit may include a first data fan-out line and / or a second data fan-out line. The first data fan-out line is disposed between the first power line and the data signal line, and the orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the initial signal connection line on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, and a first planarization layer, sequentially stacked on the substrate. The first data fan-out line and / or the second data fan-out line may be disposed in the fourth conductive layer.

[0269] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0270] (111) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include: depositing a sixth conductive film on a substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process to form an anode pattern disposed on a first planarization layer, wherein the anodes are arranged in a square manner to form a GGRB pixel arrangement, such as... Figure 20a and Figure 20b As shown, Figure 20b for Figure 20a A planar schematic diagram of the intermediate anode.

[0271] Combination Figures 10 to 20bAs shown, the anode pattern may include a red anode 301R of a red light-emitting device, a blue anode 301B of a blue light-emitting device, a first green anode 301G1 of a first green light-emitting device, and a second green anode 301G2 of a second green light-emitting device. The area where the red anode 301R is located can form a red sub-pixel R that emits red light, the area where the blue anode 301B is located can form a blue sub-pixel B that emits blue light, the area where the first green anode 301G1 is located can form a first green sub-pixel G1 that emits green light, and the area where the second green anode 301G2 is located can form a second green sub-pixel G2 that emits green light. The red sub-pixel R and the blue sub-pixel B are arranged sequentially along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are arranged sequentially along the second direction Y. The first green sub-pixel G1 and the second green sub-pixel G2 are respectively located on one side of the red sub-pixel R and the blue sub-pixel B in the first direction X. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a square-arranged pixel unit.

[0272] In an exemplary embodiment, in a pixel unit, the red anode 301R is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the Mth row and Nth column, the blue anode 301B is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and Nth column, the first green anode 301G1 is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the Mth row and N+1th column, and the second green anode 301G2 is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and N+1th column. In another pixel unit, the red anode 301R is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and (N+2)th column. The blue anode 301B is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M)th row and (N+2)th column. The first green anode 301G1 is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and (N+3)th column. The second green anode 301G2 is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M)th row and (N+3)th column.

[0273] In an exemplary embodiment, since each anode is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the second anode connection electrode, the first anode connection electrode and the third connection electrode 46 in a circuit unit, the four anodes in a pixel unit are respectively connected to the pixel driving circuits of the four circuit units in a circuit unit group, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0274] In an exemplary embodiment, the two red anodes 301R connected to the pixel driving circuits in the M-th row, N-th column circuit unit and the (M+1)-th row, N+2-th column circuit unit, respectively, have the same shape and position. The two blue anodes 301B connected to the pixel driving circuits in the (M+1)-th row, N-th column circuit unit and the (M+1)-th row, N+3-th column circuit unit, respectively, have the same shape and position. The two first green anodes 301G1 connected to the pixel driving circuits in the M-th row, N+1-th column circuit unit and the (M+1)-th row, N+3-th column circuit unit, respectively, have the same shape and position. The two second green anodes 301G2 connected to the pixel driving circuits in the (M+1)-th row, N+1-th column circuit unit and the (M+3)-th column circuit unit, respectively, have the same shape and position. In an exemplary embodiment, the shapes and areas of the red anodes 301R, blue anodes 301B, first green anodes 301G1, and second green anodes 301G2 in a single pixel unit are all different.

[0275] In an exemplary embodiment, the anode shape and area of ​​the four sub-pixels in a pixel unit may be the same or different. The positional relationship between the four sub-pixels of a pixel unit and the four circuit units in a circuit unit group may be the same or different. The shape and position of the red anode 301R, blue anode 301B, first green anode 301G1 and second green anode 301G2 in different pixel units may be the same or different. This disclosure does not limit this.

[0276] In an exemplary embodiment, subsequent fabrication processes may include: first, forming a pixel definition layer pattern, which may include a red pixel opening exposing a red anode, a blue pixel opening exposing a blue anode, a first green opening exposing a first green anode, and a second green opening exposing a second green anode. Then, an organic light-emitting layer is formed using vapor deposition or inkjet printing. The organic light-emitting layer is connected to the anode through corresponding pixel openings. A cathode is formed on the organic light-emitting layer and connected to the organic light-emitting layer. An encapsulation layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0277] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0278] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The sixth conductive layer may be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer, and sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth and sixth insulating layers are called passivation (PVX) layers. The first planarization layer can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0279] Figures 21a to 22b The fabrication process of the first wiring region in the display substrate is illustrated using eight circuit units (two circuit units in a row and four circuit units in a column) as an example. In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0280] In the exemplary embodiment, the process of forming the semiconductor layer, the first conductive layer, the second conductive layer, the fourth insulating layer and the third conductive layer pattern in this exemplary embodiment can be substantially the same as in the foregoing embodiments (11) to (15), and will not be repeated here.

[0281] (26) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, the plurality of vias including at least a twelfth via V12 and a twenty-second via V22, such as... Figure 21a and Figure 21b As shown, Figure 21b for Figure 21a A planar schematic diagram of multiple vias.

[0282] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the third connecting electrode 46 onto the substrate. The fifth insulating layer within the twelfth via V12 is removed, exposing the surface of the third connecting electrode 46. The twelfth via V12 is configured to allow a subsequently formed first anode connecting electrode to be connected to the third connecting electrode 46 through the via.

[0283] The orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate. The fifth insulating layer inside the 22nd via V22 is removed, exposing the surface of the first power line 41. The 22nd via V22 is configured to allow the subsequently formed third compensation line to be connected to the first power line 41 through the via.

[0284] In an exemplary embodiment, the second 22 via V22 may include multiple vias, and the multiple second 22 vias V22 may be arranged sequentially along the second direction Y to increase the connection reliability between the first power line and the third compensation line.

[0285] In an exemplary embodiment, the positions of the twelfth via V12 and the twelfth via V22 in each circuit unit may be the same or different, and this disclosure does not limit this.

[0286] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, the fourth conductive layer including at least: a first data fan-out line 51, a first anode connection electrode 53, and a third compensation line 73, such as Figure 22a and Figure 22bAs shown, Figure 22b for Figure 22a A planar schematic diagram of the fourth conductive layer.

[0287] In an exemplary embodiment, the first data fan-out line 51 can be a straight line extending along a first direction X, and the third compensation line 73 can be a straight line extending along a second direction Y. The first data fan-out line 51 can be continuously arranged in a circuit cell row, and the first data fan-out lines 51 in adjacent first circuit cells in the first direction X are interconnected. The third compensation line 73 can be spaced out in a circuit cell column, and the third compensation line 73 can be arranged on both sides of the first data fan-out line 51 in the second direction Y. There is a first gap between the edge of the first data fan-out line 51 near the third compensation line 73 and the end face of the third compensation line 73 near the first data fan-out line 51.

[0288] In an exemplary embodiment, the orthographic projection of the first data fan-out line 51 onto the display substrate plane may at least partially overlap with the orthographic projection of the second initial signal line 32 onto the display substrate plane. In another exemplary embodiment, the orthographic projection of the first data fan-out line 51 onto the display substrate plane may at least partially overlap with the orthographic projection of the first initial signal line 31 onto the display substrate plane.

[0289] In one exemplary embodiment, the orthographic projection of the third compensation line 73 on the substrate at least partially overlaps with the orthographic projection of the first power line 41 on the substrate, and the third compensation line 73 is connected to the first power line 41 through at least one twenty-second via V22. In another possible exemplary embodiment, the orthographic projection of the third compensation line 73 on the substrate is located within the range of the orthographic projection of the first power line 41 on the substrate.

[0290] In another exemplary embodiment, the orthographic projection of the third compensation line 73 on the substrate may be located between the orthographic projection of the first power line 41 on the substrate and the orthographic projection of the data signal line 42 in the plane of the display substrate.

[0291] In another exemplary embodiment, the orthographic projection of the third compensation line 73 in the plane of the display substrate can at least partially overlap with the orthographic projection of the initial signal connection line 43 in the plane of the display substrate, and the third compensation line 73 can be connected to the initial signal connection line 43 through a via.

[0292] Figure 22a and Figure 22b China only Figure 8e The third compensation line 73 shown is an example illustration; in other exemplary embodiments, Figure 22a and Figure 22b It can be adopted in China Figure 8g The structure of the fifth compensation line shown or Figure 8iThe structure of the seventh compensation line shown is not limited in this disclosure.

[0293] In an exemplary embodiment, the structure of the first anode connecting electrode 53 is similar to that of the aforementioned embodiment, and will not be described again here.

[0294] In an exemplary embodiment, the process of forming the sixth insulating layer, the fifth conductive layer, the first planarization layer and the anode pattern can be substantially the same as that in the foregoing embodiments (18) to (111), and will not be repeated here.

[0295] Figures 23a to 24b The fabrication process of the second wiring region in the display substrate is illustrated using an example of eight circuit units (two circuit units in a row and four circuit units in a column). In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0296] In the exemplary embodiment, the process of forming the semiconductor layer, the first conductive layer, the second conductive layer, the fourth insulating layer and the third conductive layer pattern in this exemplary embodiment can be substantially the same as in the foregoing embodiments (11) to (15), and will not be repeated here.

[0297] (36) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, the plurality of vias including at least a twelfth via V12 and a twenty-third via V23, such as... Figure 23a and Figure 23b As shown, Figure 23b for Figure 23a A planar schematic diagram of multiple vias.

[0298] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the third connecting electrode 46 onto the substrate. The fifth insulating layer within the twelfth via V12 is removed, exposing the surface of the third connecting electrode 46. The twelfth via V12 is configured to allow a subsequently formed first anode connecting electrode to be connected to the third connecting electrode 46 through the via.

[0299] The orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the initial signal connection line 43 on the substrate. The fifth insulating layer of the 23rd via V23 is removed, exposing the surface of the initial signal connection line 43. The 23rd via V23 is configured to allow the subsequently formed fourth compensation line to be connected to the initial signal connection line 43 through the via.

[0300] (37) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, the fourth conductive layer including at least: a second data fan-out line 52, a first anode connection electrode 53, and a fourth compensation line 74, such as Figure 24a and Figure 24b As shown, Figure 24b for Figure 24a A planar schematic diagram of the fourth conductive layer.

[0301] In an exemplary embodiment, the second data fan-out line 52 can be a straight line extending along the second direction Y, and the fourth compensation line 74 can be a straight line extending along the first direction X. The fourth compensation line 74 is connected to the initial signal connection line 43 via the twenty-third via V23. The second data fan-out lines 52 can be continuously arranged in a circuit cell column, and the second data fan-out lines 52 in adjacent first circuit cells in the second direction Y are interconnected. The fourth compensation lines 74 can be spaced apart in a circuit cell row, and can be arranged on both sides of the second data fan-out line 52 in the first direction X. A second gap exists between the edge of the second data fan-out line 52 near the fourth compensation line 74 and the end face of the fourth compensation line 74 near the second data fan-out line 52.

[0302] In an exemplary embodiment, the orthographic projection of the second data fan-out line 52 onto the substrate at least partially overlaps with the orthographic projection of the first power line 41 onto the substrate. In a possible exemplary embodiment, the orthographic projection of the second data fan-out line 52 onto the substrate lies within the range of the orthographic projection of the first power line 41 onto the substrate.

[0303] In another exemplary embodiment, the orthographic projection of the second data fan-out line 52 on the substrate may be located between the orthographic projection of the first power line 41 on the substrate and the orthographic projection of the data signal line 42 in the plane of the display substrate.

[0304] In yet another exemplary embodiment, the orthographic projection of the second data fan-out line 52 in the plane of the display substrate may at least partially overlap with the orthographic projection of the initial signal connection line 43 in the plane of the display substrate.

[0305] In an exemplary embodiment, the orthographic projection of the fourth compensation line 74 in the plane of the display substrate may at least partially overlap with the orthographic projection of the first initial signal line 31 or the second initial signal line 32 in the plane of the display substrate.

[0306] In an exemplary embodiment, the fourth compensation line 74 can be connected to the first power line 41 via a via, or the fourth compensation line 74 can be connected to the initial signal connection line 43 via a via.

[0307] Figure 24a and Figure 24b China only Figure 8f The fourth compensation line 74 shown is an example illustration; in other exemplary embodiments, Figure 24a and Figure 24b It can be adopted in China Figure 8h The structure of the sixth compensation line shown or Figure 8j The structure of the eighth compensation line shown is not limited in this disclosure.

[0308] In an exemplary embodiment, the structure of the first anode connecting electrode 53 is similar to that of the aforementioned embodiment, and will not be described again here.

[0309] In an exemplary embodiment, the process of forming the sixth insulating layer, the fifth conductive layer, the first planarization layer and the anode pattern can be substantially the same as that in the foregoing embodiments (18) to (111), and will not be repeated here.

[0310] In a display substrate, the display area includes a trace area with data fan-out lines and a normal area without data fan-out lines. The trace area includes a first data fan-out line and a second data fan-out line with different extension directions. Since the normal area has weak reflectivity and the trace area has strong reflectivity, and the reflectivity of the first data fan-out line is different from that of the second data fan-out line, the appearance of the normal area and the trace area are significantly different. The appearance of the first trace area with the first data fan-out line and the appearance of the second trace area with the second data fan-out line are different, resulting in a defective appearance of the display substrate, which is more obvious when the screen is off or when displaying at low grayscale. The exemplary embodiments of this disclosure provide compensation lines in the normal area, the first trace area, and the second trace area. The compensation lines are disposed on the same layer as the data fan-out lines and formed simultaneously by the same patterning process. The normal area is provided with a first compensation line extending along the first direction X and a second compensation line extending along the second direction Y. The first trace area is provided with a third compensation line extending along the second direction Y, and the second trace area is provided with a fourth compensation line extending along the first direction X. This makes the reflectivity of the first and second compensation lines in the normal area, the first data fan-out lines and the third compensation line in the first trace area, and the second data fan-out lines and the fourth compensation line in the second trace area substantially similar, eliminating the difference in appearance between the normal area, the first trace area, and the second trace area, and avoiding poor appearance of the display substrate.

[0311] As can be seen from the above description of the display substrate structure and fabrication process, this disclosure, by setting data fan-out lines within the display area, connects the lead lines of the bonding area to the data signal lines through the data fan-out lines. This eliminates the need for fan-shaped diagonal lines in the lead area, effectively reducing the vertical length of the lead area and significantly shortening the bottom bezel width. This results in the top, bottom, left, and right bezels of the display device having similar widths, all below 1.0mm, thus increasing the screen-to-body ratio and facilitating full-screen display. Furthermore, by setting initial signal connection lines extending along the second direction in the main body, and connecting these initial signal connection lines to the first initial signal lines through vias, this disclosure creates a mesh structure between the initial signal connection lines and the first initial signal lines. This not only effectively reduces the resistance of the first initial signal lines and decreases the voltage drop of the first initial voltage, but also effectively improves the uniformity of the first initial voltage in the display substrate, thereby enhancing display uniformity, display quality, and overall display performance. This disclosure eliminates the difference in appearance between the normal area, the first routing area, and the second routing area by setting compensation lines in the same layer as the data fan-out lines and forming them simultaneously in the same patterning process, thus avoiding appearance defects of the display substrate. This disclosure also avoids electrical defects caused by the floating of the compensation lines by connecting them to the first power line or the initial signal connection line, improving operational reliability and display effect. The fabrication process of this disclosure is highly compatible with existing fabrication processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield.

[0312] This disclosure effectively reduces parasitic capacitance between the first data fan-out line and the first power line by placing the first data fan-out line between the first power line and the data signal line, thereby effectively reducing crosstalk.

[0313] The structure and its preparation process described above are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be modified or reduced according to actual needs. For example, Figure 15a and Figure 15b The twenty-first via in the diagram exposes the surface of the initial signal connection line. Figure 16a and Figure 16b The second compensation line can at least partially overlap with the initial signal connection line, and the second compensation line is connected to the initial signal connection line through the twenty-first via. For example, Figure 21a and Figure 21b The 22nd via in the diagram can expose the surface of the initial signal connection line. Figure 22a and Figure 22bThe third compensation line can at least partially overlap with the initial signal connection line, and the third compensation line is connected to the initial signal connection line through the twenty-second via. For example, Figure 23a and Figure 23b The 23rd via in the diagram can expose the surface of the first power line. Figure 24a and Figure 24b The fourth compensation line 74 can be connected to the first power line through the twenty-third via, and the second data fan-out line can at least partially overlap with the initial signal connection line. Alternatively, the fan-out line and compensation line can be disposed in the third conductive layer, and the first power line and data signal line can be disposed in the fourth conductive layer. Alternatively, the first power line and data signal line can be disposed in the fourth conductive layer, and the fan-out line and compensation line can be disposed in the fifth conductive layer. Alternatively, the first power line and data signal line can be disposed in different film layers. Alternatively, the display substrate can also include a second power line VSS extending along the second direction, and the orthographic projections of the data fan-out line and compensation line extending along the second direction in the plane of the display substrate can at least partially overlap with the orthographic projections of the second power line VSS in the plane of the display substrate, etc., which are not limited herein.

[0314] Figure 25 This is a schematic diagram of the appearance of a display substrate. Figure 26 This is a schematic diagram of the appearance of a display substrate according to an exemplary embodiment of the present disclosure. In one display substrate, the display area includes a trace area with data fan-out lines and a normal area without data fan-out lines. The trace area includes a first data fan-out line and a second data fan-out line with different extending directions. Because the normal area has weak reflectivity, while the data fan-out lines in the trace area have strong reflectivity, and because the reflectivity of the first data fan-out line differs from that of the second data fan-out line, the appearance of the normal area and the trace area are significantly different. The appearance of the first trace area with the first data fan-out line differs from that of the second trace area with the second data fan-out line, resulting in an appearance defect in the display substrate. Figure 25 As shown in the exemplary embodiment of this disclosure, by providing compensation lines in the normal area, the first trace area, and the second trace area, with the normal area having a first compensation line and a second compensation line, the first trace area having a third compensation line, and the second trace area having a fourth compensation line, the reflection conditions of the normal area, the first trace area, and the second trace area are made substantially similar, eliminating the difference in appearance between the normal area, the first trace area, and the second trace area, and avoiding defects in the appearance of the display substrate, such as... Figure 26 As shown.

[0315] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0316] This disclosure also provides a method for fabricating a display substrate to produce the display substrate provided in the above embodiments. In an exemplary embodiment, the fabrication method may include:

[0317] A driving circuit layer is formed on a substrate; the driving circuit layer includes a plurality of circuit units, each circuit unit including a pixel driving circuit and a data signal line providing data signals to the pixel driving circuit and an initial signal line providing an initial signal; the plurality of circuit units include at least one normal circuit unit and at least one routing circuit unit, the normal circuit unit being provided with a first compensation line extending along a first direction and a second compensation line extending along a second direction, the routing circuit unit being provided with a first data fan-out line extending along the first direction or a second data fan-out line extending along the second direction, the first direction intersecting the second direction; the orthographic projection of the first compensation line in the plane of the display substrate at least partially overlaps with the orthographic projection of the initial signal line in the plane of the display substrate.

[0318] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0319] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The display area includes a display region comprising multiple circuit units, each circuit unit including a pixel driving circuit and multiple signal lines connected to the pixel driving circuit. The pixel driving circuit includes at least a storage capacitor and a shielding electrode. The storage capacitor includes a first electrode and a second electrode. The multiple signal lines include at least a first scan signal line extending along a first direction, a data signal line extending along a second direction, a first power line extending along the second direction, and an initial signal line. The initial signal line includes at least a first initial signal line extending along the first direction and an initial signal connection line extending along the second direction, the first direction intersecting the second direction. In a plane perpendicular to the display substrate, the display substrate includes at least a first signal line disposed on a substrate. The system comprises a conductive layer, a second conductive layer disposed on the side of the first conductive layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; a first scan signal line and a first electrode plate are disposed in the first conductive layer; a first initial signal line, a second electrode plate, and a shielding electrode are disposed in the second conductive layer; the shielding electrode is disposed between the first initial signal line and the second electrode plate; a first power line and an initial signal connection line are disposed in the third conductive layer; the first power line is connected to the shielding electrode; and the initial signal connection line is connected to the first initial signal line; a data signal line is connected to a first data fan-out line extending along the first direction of the main body portion; and the data signal line and the first data fan-out line are disposed in different conductive layers.

2. The display substrate according to claim 1, characterized in that, The first data fan-out line is connected to the data signal line through a via.

3. The display substrate according to claim 1, characterized in that, The display substrate further includes a fourth conductive layer disposed on the side of the third conductive layer away from the substrate, the data signal line is disposed in the third conductive layer, and the first data fan-out line is disposed in the fourth conductive layer.

4. The display substrate according to claim 1, characterized in that, The initial signal connection line is connected to the first initial signal line through a via.

5. The display substrate according to claim 1, characterized in that, The first direction is perpendicular to the second direction.

6. The display substrate according to claim 1, characterized in that, The orthographic projection of the first data fan-out line on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate.

7. The display substrate according to claim 1, characterized in that, The display area also includes a second data fan-out line extending along the second direction, the second data fan-out line being connected to the first data fan-out line.

8. The display substrate according to claim 7, characterized in that, The first data fan-out line and the second data fan-out line are set on the same layer.

9. The display substrate according to claim 7, characterized in that, The orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

10. The display substrate according to claim 7, characterized in that, At least a portion of the second data fan-out line's orthographic projection on the substrate lies between the orthographic projection of the first power line on the substrate and the orthographic projection of the data signal line on the substrate.

11. The display substrate according to claim 7, characterized in that, The orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the initial signal connection line on the substrate.

12. The display substrate according to any one of claims 1 to 11, characterized in that, The display substrate also includes an upper border, a lower border, a left border, and a right border located outside the display area, wherein the widths of the upper border, the lower border, the left border, and the right border are similar.

13. The display substrate according to claim 12, characterized in that, The width of the top border, the bottom border, the left border, and the right border is less than or equal to 1.0 mm.

14. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 13.

15. A method for preparing a display substrate, characterized in that, The display substrate includes a display area, which includes multiple circuit units. Each circuit unit includes a pixel driving circuit and multiple signal lines connected to the pixel driving circuit. The pixel driving circuit includes at least a storage capacitor and a shielding electrode. The storage capacitor includes a first electrode plate and a second electrode plate. The multiple signal lines include at least a first scan signal line extending along a first direction, a data signal line extending along a second direction, a first power line extending along the second direction, and an initial signal line. The initial signal line includes at least a first initial signal line extending along the first direction and an initial signal connection line extending along the second direction, wherein the first direction intersects the second direction. The fabrication method includes: A first conductive layer is formed on a substrate, and the first scan signal line and the first electrode are disposed in the first conductive layer; A second conductive layer is formed on the first conductive layer, and the first initial signal line, the second electrode plate and the shielding electrode are disposed in the second conductive layer, with the shielding electrode disposed between the first initial signal line and the second electrode plate. A third conductive layer is formed on the second conductive layer, and the first power line and the initial signal connection line are disposed in the third conductive layer. The first power line is connected to the shielding electrode, and the initial signal connection line is connected to the first initial signal line. The data signal line is connected to the first data fan-out line extending along the first direction of the main body, and the data signal line and the first data fan-out line are disposed in different conductive layers.

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