A method and apparatus for verifying a time delay parameter

Abstract

The application discloses a method and device for checking a time delay parameter. The method comprises the following steps: obtaining a first group of parameters and a second group of parameters, wherein the first group of parameters comprises time delay parameters of a message transmitted in at least one module of a register transfer level (RTL) circuit, and the second group of parameters comprises time delay parameters of the at least one module when the message is transmitted in an electronic system level (ESL) model; checking whether the first group of parameters matches the second group of parameters; if not, determining that the second group of parameters has an error, calibrating the second group of parameters to obtain a third group of parameters, and using the third group of parameters to evaluate the time delay of the message transmission, so that the error caused by the developer sampling the RTL time delay parameter can be avoided, and the accuracy of evaluating the time delay of the message transmission by using the ESL model is improved, and the requirements of high accuracy and low time delay are met.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a method and apparatus for verifying the delay parameters of an ESL model. Background Technology

[0002] The transmission latency of messages in a switch is a key indicator for testing switch performance. With the rapid development of communication services, the latency performance of switch chips is becoming increasingly important. Large-scale and highly complex chip designs are common in switch chips, requiring designers to continuously evaluate and monitor latency performance throughout the development process. If the chip's latency performance fails to meet the design specifications, the designer must quickly adjust the chip architecture to ensure compliance, thereby guaranteeing the chip's competitiveness upon final tape-out.

[0003] For switch chip designers, there are two main methods for evaluating message transmission latency during chip development: one is through Electronic Design Automation (EDA) verification; the other is through Electronic System Level (ESL) chip modeling. For large-scale and highly complex switch chip designs, designers typically use ESL chip models instead of actual Register Transfer Level (RTL) latency evaluation.

[0004] ESL models use high-level languages ​​like C and C++ to model chips, resulting in code complexity and scale far less than RTL code. This allows for efficient support of chip performance evaluation, including latency assessment. However, an ESL model is just a model and not equivalent to RTL code. To ensure the accuracy of latency evaluation by the ESL model, all latency-related parameters in the RTL circuit need to be back-annotated into the ESL chip model. This is essential to guarantee the accuracy and effectiveness of the latency performance metrics evaluated by the ESL chip model.

[0005] Currently, the method for back-annotating delay parameters from an RTL circuit to an ESL chip model relies on chip designers sampling the delay parameters of the RTL circuit. For example, code developers obtain the delay parameters by reading the RTL code. However, differences in understanding of the RTL code among different developers, or oversights in their understanding, can lead to significant errors in the obtained RTL delay parameters, resulting in low accuracy when back-annotating the delay parameters from the RTL circuit to the ESL chip model. In actual project testing, the error in message transmission delay data evaluated by the ESL model after back-annotating delay parameters in the above way can reach 1 microsecond (μs), while the industry requirement for the overall delay performance of switches is no more than 0.4μs. Therefore, it still does not meet the requirements for high accuracy and low latency. Summary of the Invention

[0006] This application provides a method and apparatus for verifying delay parameters, used to detect the accuracy of obtained ESL circuit delay parameters, thereby improving the accuracy of evaluating message transmission delay using ESL models. Specifically, this application discloses the following technical solutions:

[0007] In a first aspect, this application provides a method for verifying latency parameters. This method can be applied to a network device, which may be a server or a functional module integrated into a server. The method includes:

[0008] Obtain a first set of parameters and a second set of parameters, wherein the first set of parameters includes the delay parameters of the message transmission in at least one module of the register transfer layer RTL circuit; the second set of parameters includes the delay parameters of the at least one module as statistically analyzed when the message is transmitted in the electronic system-level design ESL model.

[0009] If the first set of parameters does not match the second set of parameters, it is determined that the second set of parameters has an error. The second set of parameters is then calibrated to obtain the third set of parameters, and the message transmission delay is evaluated using the third set of parameters.

[0010] The method provided in this paper calibrates the obtained ESL model delay parameters when errors are detected, and uses the calibrated parameters to evaluate message delay. This avoids errors caused by developers sampling RTL delay parameters. This method improves the accuracy of evaluating message transmission delay using the ESL model, while meeting the requirements of high precision and low latency, thus ensuring the competitiveness of chip project development.

[0011] In addition, this method breaks down end-to-end latency data into numerous small-granularity latency metrics, namely the transmission latency parameters corresponding to each module. Latency data is evaluated in each small-granularity latency parameter metric, making the evaluation results more refined and accurate.

[0012] In conjunction with the first aspect, in one possible implementation of the first aspect, the at least one module includes a first module, and the acquisition of the first set of parameters includes: acquiring the time difference between the time point when the message arrives at the input interface of the first module and the time point when it arrives at the output interface.

[0013] In conjunction with the first aspect, in another possible implementation of the first aspect, before obtaining the first set of parameters, the method further includes: determining whether the data transmitted by the message in the RTL circuit chip is real data; if so, obtaining the first set of parameters.

[0014] In conjunction with the first aspect, in another possible implementation of the first aspect, determining whether the data transmitted in the RTL circuit chip by the message is real data includes: determining whether the indicator flag carried in the message start portion is "1".

[0015] In conjunction with the first aspect, in another possible implementation of the first aspect, when the message is a first message set, the first message set includes N messages of different lengths, N≥2, and N is a positive integer, then obtaining the first set of parameters includes: obtaining the weighted average of the delay parameters of the N messages transmitted in the same module. This implementation calculates the weighted average of the N messages as the RTL circuit delay parameters, which is more accurate than obtaining the first set of parameters from a single message.

[0016] In conjunction with the first aspect, in another possible implementation of the first aspect, obtaining the first set of parameters includes: obtaining the first set of parameters from the chip delay accuracy verification table CLAT, wherein the CLAT table includes the delay parameters transmitted by each of the at least one module.

[0017] In conjunction with the first aspect, in another possible implementation of the first aspect, obtaining the second set of parameters includes: obtaining the transmission delay parameters of at least one module in the ESL model based on ESL modeling and ESL simulation technology.

[0018] Secondly, this application also provides a device for verifying time delay parameters, the device comprising:

[0019] The acquisition unit is used to acquire a first set of parameters and a second set of parameters. The first set of parameters includes the delay parameters of the message transmission in at least one module of the register transfer layer RTL circuit, and the second set of parameters includes the delay parameters of the at least one module statistically analyzed when the message is transmitted in the electronic system level design ESL model.

[0020] The processing unit is used to verify that when the first set of parameters does not match the second set of parameters, it determines that there is an error in the second set of parameters, calibrates the second set of parameters to obtain a third set of parameters, and uses the third set of parameters to evaluate the message transmission delay.

[0021] In conjunction with the second aspect, in one possible implementation of the second aspect, the at least one module includes a first module, and the acquisition unit is further configured to acquire the time difference between the time point when the message arrives at the input interface of the first module and the time point when it arrives at the output interface.

[0022] In conjunction with the second aspect, in another possible implementation of the second aspect, the processing unit is further configured to determine whether the data transmitted in the RTL circuit chip by the message is real data before the acquisition unit acquires the first set of parameters, and if so, acquire the first set of parameters.

[0023] Furthermore, the processing unit is also configured to determine that the data is real data when the indicator flag carried in the message start portion of the message is "1".

[0024] In conjunction with the second aspect, in another possible implementation of the second aspect, when the message is a first message set, the first message set includes N messages of different lengths, N≥2, and N is a positive integer, the acquisition unit is further used to acquire the weighted average of the delay parameters of the N messages transmitted in the same module.

[0025] In conjunction with the second aspect, another possible implementation of the second aspect further includes a storage unit for storing a chip latency accuracy verification table (CLAT), which includes latency parameters transmitted by each of the at least one module; the acquisition unit is further configured to acquire the first set of parameters from the CLAT of the storage unit.

[0026] In conjunction with the second aspect, in another possible implementation of the second aspect, the acquisition unit is further configured to acquire the latency parameters of at least one module of the message transmission in the ESL model based on ESL modeling and ESL simulation technology.

[0027] Thirdly, this application also provides a detection device, which includes at least one processor and an interface circuit, wherein the interface circuit is used to provide instructions and / or data to the at least one processor; the at least one processor is used to execute the instructions to implement the methods in the first aspect and various implementations thereof.

[0028] In addition, the device also includes a memory for storing the instructions and / or data.

[0029] Optionally, the at least one processor and the interface circuit can be integrated into a single processing chip or chip circuit.

[0030] Optionally, the detection device is a network device, which includes, but is not limited to, a server and a controller.

[0031] Fourthly, this application also provides a computer-readable storage medium storing instructions that, when executed on a computer or processor, can be used to perform the methods described in the first aspect and various implementations thereof.

[0032] In addition, this application also provides a computer program product including computer instructions that, when executed by a computer or processor, can implement the methods in the first aspect and various implementations of the first aspect.

[0033] Fifthly, this application also provides a server, including the apparatus of the second aspect and various implementations thereof, or including the apparatus of the third aspect thereof, for implementing the method of the first aspect and various implementations thereof.

[0034] It should be noted that the beneficial effects of the various implementation methods of the second to fifth aspects mentioned above are the same as those of the first aspect and its various implementation methods. For details, please refer to the description of the beneficial effects in the first aspect and its various implementation methods, which will not be repeated here. Attached Figure Description

[0035] Figure 1 An architecture diagram of a wireless communication system provided in this application embodiment;

[0036] Figure 2 A schematic diagram of the structure of an RTL circuit chip model provided in an embodiment of this application;

[0037] Figure 3 A flowchart of a delay parameter verification method provided in an embodiment of this application;

[0038] Figure 4 A flowchart illustrating another delay parameter verification method provided in this application embodiment;

[0039] Figure 5 A schematic diagram of a time delay parameter verification device provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the structure of a detection device provided in an embodiment of this application. Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. Before describing the technical solutions in the embodiments of this application, the application scenarios of the technical solutions in this application will first be described.

[0042] The technical solution of this application can be applied to a testing device that can be used to evaluate the transmission latency of a chip during the chip testing phase of a switch or router. The testing device is integrated as a functional module, such as an Android application package (APK), into a third-party device, including but not limited to network devices such as servers and controllers.

[0043] The switch or router is a device in a wireless communication system, such as in a Wireless Local Area Network (WLAN). Figure 1 As shown, it includes at least one server, switch, base station (Node B or eNB), and terminal equipment. The terminal equipment includes user equipment (UE), smartphone, smart screen TV, laptop, tablet, personal computer (PC), personal digital assistant (PDA), foldable terminal, wearable device with wireless communication function (such as smartwatch or bracelet), etc.

[0044] Furthermore, the switch or router can also be used in other communication systems, such as wired transmission systems. This embodiment does not limit the chip structure and composition of the switch or router.

[0045] The following section introduces the terminology that may be used during chip testing.

[0046] (1) Electronic System Level (ESL) Design: ESL is a design methodology for chip simulators. Common simulators include functional simulation, performance simulation, and instruction simulation. The industry also offers many simulator design platforms and tools, such as Coware, Carbon, and Mentor. ESL is a methodology for developing, optimizing, and verifying complex system-on-chip (SoC) architectures and embedded software in a tightly coupled manner. It provides a verification foundation for downstream register-transfer level (RTL) implementations. Furthermore, ESL utilizes high-level languages ​​such as C / C++ to simulate hardware behavior through software models, providing various levels of software simulation platforms for SoC systems. This provides a runnable verification environment for SoC system architecture verification and embedded software development, effectively supporting the iterative development of SoC systems.

[0047] (2) Register Transfer Level (RTL), also known as "register transfer level circuit". In integrated circuit design, RTL is used to describe the abstract level of synchronous digital circuit operation.

[0048] (3) Electronic Design Automation (EDA): EDA technology uses computers as tools, allowing designers to automatically design electronic products by integrating the latest achievements in electronic technology, computer technology, information processing, and intelligent technology on an EDA software platform. The emergence of EDA technology has greatly improved the efficiency and operability of circuit design.

[0049] (4) LIFO and FIFO. Based on message forwarding characteristics, the following message forwarding delay types can be included:

[0050] First-In-First-Out (LIFO) and Last-In-First-Out (FIFO) are two methods for measuring transmission delay. In the FIFO method, the time interval between the last bit of a frame entering the switch port and the first bit of the frame being forwarded from that port is defined as the time required for the switch to perform table lookups, buffer scheduling, and forwarding after fully receiving the message.

[0051] The FIFO method refers to the time interval between the first bit of a frame entering the device port and the first bit of the frame being forwarded from the device port. In cut-through mode, forwarding begins as soon as the packet header arrives at the switch, and the packet is not buffered. This method can more accurately measure any storage or processing time encountered by the data packet / message when passing through the switch. Therefore, this embodiment uses the FIFO method to obtain the packet transmission delay.

[0052] The technical solution of this application will be described in detail below.

[0053] This application provides a method for verifying delay parameters to improve the accuracy of sampling parameters in ESL chip models. The method comprises three stages: a sampling stage, a comparison stage, and a calibration stage. The implementation process of these three stages is described below.

[0054] I. Sampling Phase

[0055] This embodiment uses a detection device as an example of the execution subject. In the "I. Sampling Stage", the detection device needs to acquire two sets of parameters. The first set of parameters is the RTL circuit delay parameter, and the second set of parameters is the delay parameter obtained using the ESL model. First, the process of acquiring the first set of parameters, namely the RTL circuit delay parameter, will be introduced.

[0056] See Figure 2 This embodiment provides a schematic diagram of an RTL circuit chip model, which simplifies numerous complex circuit structures into individual modules (blocks). This embodiment does not limit the circuit structure contained in each module. Figure 2 The RTL circuit chip shown contains three blocks, labeled block 0, block 1, and block 2, where "0", "1", and "2" are the block identifiers, and each block has a different identifier. Furthermore, the circuit chip may contain more or fewer other modules; this embodiment does not impose any limitations on this.

[0057] In the RTL circuit chip model, each block contains at least one input interface and one output interface. For example, the input interface of block 0 is set to 'a' and the output interface to 'b'; the input interface of block 1 is set to 'b' and the output interface to 'c'; and the input interface of block 2 is set to 'c' and the output interface to 'd'. By marking the input / output interfaces of each block, it is easy to record the transmission latency of messages or data in each block. Specifically, when the first message passes through any block, the transmission latency in that block can be characterized as: the time difference Δt between the time when the message header of the first message arrives at the input interface of that block and the time when it arrives at the output interface, that is: transmission latency = time when it arrives at the output interface – time when it arrives at the input interface.

[0058] See Figure 3 The method for obtaining the delay parameters of the RTL circuit mentioned above includes:

[0059] Step 101: Obtain the first set of parameters, which includes the delay parameters of at least one message being transmitted in at least one module of the RTL circuit.

[0060] Specifically, when sampling the delay parameters of the RTL circuit, it is first necessary to determine whether the transmission of one or more messages within the RTL circuit chip meets preset conditions. If the preset conditions are met, the delay parameters of at least one block during the current message transmission are obtained. If the preset conditions are not met, the sampling fails and resampling is required.

[0061] The determination of whether the preset conditions are met includes: detecting whether the received message data is real data. If "yes", it is determined that the message transmission meets the preset conditions; if the determination result is "no", it is determined that the preset conditions are not met. For example, taking the received message as a first message as an example, it is determined whether the indicator flag carried in the start-of-packet (SOP) of the first message is "1"; if it is "1", it is determined that the data transmitted in the first message is real data, that is, the preset conditions are met; if the SOP indicator flag is "0", then the transmitted data is not real data, that is, the preset conditions are not met.

[0062] In addition, when the detection device receives the first message, it also simultaneously acquires the first signal. The first signal's flag is valid, for example, indicated as "1" in the first signal's flag. The first signal and / or the first message can be transmitted on the interface bus and will pass through at least one block during transmission.

[0063] In chip circuit logic, to indicate that a real message has been transmitted through the chip interface, the chip circuit typically transmits a 1-bit valid signal on the interface bus to detect whether a valid message transmission exists at the current moment. This process can be called "valid signal marking". If the content carried in the preset field of this signal is "1", it indicates that the signal is valid, and the data on the interface bus is valid data. If the content indicated by the signal mark is "0", it indicates that the signal is invalid, that is, no data message has been received from the RTL circuit chip, and therefore the first set of parameters cannot be obtained.

[0064] Furthermore, determining whether the data transmitted in the first message is real data can be achieved through the SOP indicator flag. Since the interface bus has a limited bus width, longer messages need to be segmented into multiple bus-width units during transmission. Each bus-width unit can be called a message fragment unit, and each fragment unit is used to transmit real, valid data. During the "sampling phase," the delay is calculated using the FIFO method, and only the timing of the initial fragment (SOP flag) of the message is obtained.

[0065] For example, taking block 0 as an example, the transmission delay of the first message through block 0 can be represented as latency_ab. The sampling point of input interface a can be represented by the start point, and the sampling point of output interface b can be represented by the end point. Then, Δt(latency_ab) = t(end point) - t(start point). Similarly, the transmission delay of the first message in block 1 is latency_bc, and the transmission delay in block 2 is latency_cd.

[0066] Optionally, the latency parameters of each block in the RTL circuit chip model can be represented by the "Chip Latency Accuracy Verification Table" (CLAT), as shown in Table 1 below.

[0067] Table 1, CLAT Table

[0068]

[0069] In Table 1, "block" represents a module, and "LatencyName" is the transmission delay name, which is unique within the same module. "Start point" indicates the starting position of the transmission delay sampling point, which can be used to mark the valid signal on the chip interface bus; "end point" indicates the ending position of the transmission delay sampling point, which can also be used to mark the valid signal on the chip interface bus.

[0070] It should be understood that the aforementioned CLAT table can be pre-configured and stored in the detection device. Furthermore, it should be noted that the parameters in the aforementioned CLAT table can be freely set by the chip developer, i.e., determining which latency parameters need to be collected and compared. The parameter setting process in this embodiment is not restricted.

[0071] In the "first sampling stage", the detection device uses the interface signal monitoring function provided by EDA technology to add the input / output interface signal of each block to the EDA verification environment. At the beginning, it sends the first message to the input interface of block 0 in the RTL circuit chip, and then samples the timestamp of the sampling point position of the first message in each block in the EDA verification environment.

[0072] Specifically, in step 101 above, for each block, for module block 0, the first set of parameters is obtained as the delay parameter Δt(latency_ab, delay between ab interfaces); for module block 1, the first set of parameters is obtained as the delay parameter Δt(latency_bc, delay between bc interfaces); for module block 2, the first set of parameters is obtained as the delay parameter Δt(latency_cd, delay between cd interfaces); for the chip circuit module composed of modules block 0, block 1 and block 2, the obtained first set of parameters includes delay parameters Δt(latency_ab), Δt(latency_bc) and Δt(latency_cd).

[0073] Optionally, to improve sampling accuracy, the first set of parameters can also be a weighted average of the delay parameters of N messages transmitted in the same module, where N is a positive integer and N≥2. For example, in one message sampling method, the chip circuit transmits a first message set to the interface bus. The first message set includes N standard-length messages, for example, N=5, and the standard lengths of these 5 messages are: 64 bytes, 256 bytes, 1518 bytes, 4096 bytes, 9600 bytes, etc. For each message length, sampling data (i.e., transmission delay parameters) is obtained in the RTL circuit model, and then the average value of this set of data is calculated to obtain the corresponding first set of parameters.

[0074] For example, taking block 0 as an example, each packet in the first packet set is transmitted to block 0. Under the aforementioned preset conditions, the timestamp of each packet's input / output interface in block 0 is obtained. Then, the delay parameters of each packet in block 0 are calculated. Corresponding to the five packets 64B, 256B, 1518B, 4096B, and 9600B in the first packet set, five delay parameters are obtained: Δt1, Δt2, Δt3, Δt4, and Δt5. The weighted average value (Δt average) from Δt1 to Δt5 is calculated, resulting in the first set of parameters for block 0, which is the Δt average. Similarly, for blocks 1 and 2, the first set of parameters for each block is obtained using the same weighted average method. For an RTL circuit chip model containing three blocks, the obtained first set of parameters includes three Δt averages. For example, Δt0 average, Δt1 average, and Δt2 average correspond to block 0, block 1, and block 2, respectively.

[0075] This method, by reusing the EDA verification monitor (the interface signal monitoring function provided by EDA technology), defines a standard method for sampling circuit delay parameters: that is, the valid signal and sop signal of the input / output interface of each block are added to the EDA verification environment. One or more messages are input at the input interface of the first module of the chip. The EDA verification environment will sample according to the changes of the valid signal and sop signal on the input interface to obtain the timestamp of the message at the corresponding input / output interface. In this way, the RTL circuit delay parameters of each block can be accurately calculated, providing a basis for the subsequent parameter comparison stage.

[0076] Step 102: Use the ESL model to obtain the second set of parameters, which includes the latency parameters of at least one module statistically analyzed by the ESL model.

[0077] The process of obtaining the second set of parameters is similar to step 101 above. It also involves obtaining the transmission delay of a message in each block of the ESL model, or obtaining the weighted average of the transmission delays of multiple messages of different lengths in the same block.

[0078] It should be understood that the transmission of the first message or the first message set {64Byte, 256B, 1518B, 4096B, 9600B} in the second set of parameters is the same as the message transmitted by the interface bus in the aforementioned RTL circuit chip model. The process of obtaining the transmission delay parameters of the ESL model is not described in detail in this embodiment.

[0079] Optionally, both the first and second sets of parameters can be recorded in the CLAT table, and the statistical results are shown in Table 2. Optionally, the method further includes storing Table 2 in the storage unit of the detection device.

[0080] Table 2, CLAT Table

[0081]

[0082] In one example, referring to Table 2, the first and second sets of parameters for block 0 are calculated to be 10 and 10 respectively, in microseconds (μs); the first and second sets of parameters for block 1 are 8 and 8 respectively; and the first and second sets of parameters for block 2 are 12 and 10 respectively.

[0083] II. Comparison Phase

[0084] 103: Determine whether the first set of parameters and the second set of parameters match, that is, determine whether the delay parameters of the RTL circuit are the same as the delay parameters statistically obtained by the ESL model.

[0085] Specifically, the comparison is performed on a block-by-block basis. If the first set of parameters is the transmission delay Δt(latency_ab) of the first message through block 0, then the second set of parameters is the transmission delay of the first message in block 0 obtained in the ESL model, for example, denoted as Δt'(latency_ab). The comparison is made to determine whether Δt(latency_ab) and Δt'(latency_ab) are the same, or whether the difference between them is within an acceptable range.

[0086] Similarly, if the RTL circuit module being tested contains 3 blocks, then the first set of parameters and the second set of parameters corresponding to each block are compared to see if they are the same, or if the difference in delay between each set of parameters is within the allowable range.

[0087] 104: If not, that is, the first set of parameters and the second set of parameters do not match or are not the same, then it is determined that there is an error in the second set of parameters (the time delay parameters statistically obtained by the ESL model).

[0088] 105: If so, that is, the first set of parameters and the second set of parameters match or are the same, then it is determined that there is no error in the second set of parameters. Then, the detection device uses the second set of parameters to evaluate the message transmission delay, that is, it uses the delay parameters statistically obtained by the ESL model to evaluate the chip transmission delay performance index, and can obtain accurate evaluation results.

[0089] For example, in the two sets of parameters in Table 2 above, for block 0, the first set of parameters Δt(latency_ab) = 10 and the second set of parameters Δt'(latency_ab) = 10, that is, Δt(latency_ab) = Δt'(latency_ab), then it is determined that the sampling of the second set of parameters Δt'(latency_ab) is accurate.

[0090] Similarly, for block 1, the first set of parameters Δt(latency_bc) = 8, and the second set of parameters Δt'(latency_bc) = 8, meaning Δt(latency_bc) = Δt'(latency_bc), thus determining that the sampling value of the second set of parameters Δt'(latency_ab) is accurate. For block 2, the first set of parameters Δt(latency_cd) = 12, and the second set of parameters Δt'(latency_cd) = 10, meaning Δt(latency_cd) > Δt'(latency_cd), thus determining that the sampling value of the second set of parameters Δt'(latency_cd) is inaccurate.

[0091] Furthermore, for the entire ESL circuit model comprising three blocks, if one or more of the comparison results in "mismatch," then the sampling result for determining the second set of parameters is inaccurate for the entire ESL circuit. In other words, the sampling result of the entire ESL circuit model is accurate only if the sampling results of all block comparisons are "accurate."

[0092] It should be noted that, in the data statistics in Table 1 or Table 2 above, testers can call the timestamp corresponding to the input / output interface of the module they want to detect the transmission latency of, and then calculate the first set of parameters and the second set of parameters mentioned above.

[0093] III. Calibration Phase

[0094] When it is determined in step 103 that there is an error in the second set of parameters, following step 104, the method further includes:

[0095] 106: The second set of parameters is calibrated to obtain the third set of parameters, and the third set of parameters is used to evaluate the message transmission delay.

[0096] One possible implementation is to use the first set of parameters as input to calibrate the ESL model parameters, correct the time delay parameters of the ESL model statistics (i.e., the second set of parameters), and obtain the third set of parameters. The third set of parameters matches the first set of parameters.

[0097] In this embodiment, when an error is detected in the sampled ESL model delay parameter, the ESL model delay parameter is calibrated, and the calibrated parameter is used to evaluate the message delay. This avoids the error caused by the developer sampling the RTL delay parameter. This method improves the accuracy of evaluating message transmission delay using the ESL model, while meeting the requirements of high precision and low latency, thus ensuring the competitiveness of chip project development.

[0098] Optionally, the method flow of this embodiment can be... Figure 4 As shown, see Figure 4 The method comprises three parts. Part ①, "Delay Parameter Collection," serves as the preparation phase. Specifically, in Part ①, "Delay Parameter Collection," the relevant functionality is achieved by developing a custom delay evaluation form, such as the CLAT table. Using the CLAT table, chip developers confirm the relevant delay parameters and their corresponding names for the input and output interfaces of each block in the RTL circuit.

[0099] Part ② is the "delay parameter sampling" process, which corresponds to "I. Sampling stage" in the aforementioned embodiment. In the "delay parameter sampling" process of Part ②, the delay parameter sampling includes: RTL circuit delay parameter sampling (first set of parameters) and ESL model delay parameter sampling (second set of parameters).

[0100] The RTL circuit delay parameters are sampled by recording the start and end points of the interface sampling points for each block in the CLAT table. The signal from each interface sampling point is then added to the EDA verification environment monitor component to obtain the RTL circuit delay parameters. For example, the RTL circuit transmission delay Δt (latency) for any block is t(end point) - t(start point). Conversely, the ESL model delay parameters are obtained by recording interface signal information in the CLAT table. For instance, the corresponding interface modeling characteristics are found in the ESL model, and the delay parameter data for any block in the ESL model is obtained based on ESL modeling and ESL simulation techniques.

[0101] Part ③ is "Time Delay Parameter Comparison and Calibration," which corresponds to "Part Two, Comparison Stage" and "Part Three, Calibration Stage" in the aforementioned embodiments. During Part ③, "Time Delay Parameter Comparison and Calibration," the specific values ​​of the RTL circuit time delay parameters and the ESL model time delay parameters are compared based on the CLAT table. If the two sets of parameters are the same or match, it indicates that the ESL model time delay parameters are accurate; otherwise, it is determined that the ESL model time delay parameters are inaccurate.

[0102] Furthermore, if it is determined that the delay parameters statistically obtained from the ESL model are inaccurate, the delay parameters of the ESL model are calibrated. For example, the delay parameters of the RTL circuit are used as input to calibrate the ESL model, the delay parameters of the ESL model are corrected to obtain the corrected delay parameters, and then the corrected delay parameters are used to evaluate the message transmission delay.

[0103] It should be noted that if RTL circuit delay parameters are used to evaluate message transmission delay, it is not feasible for large-scale, complex chips due to the extremely high implementation cost. Therefore, in order to measure delay in large-scale chips and avoid the high cost of evaluating messages using RTL circuit delay parameters, this application uses high-order ESL model delay parameters in C language to evaluate message delay. In this case, it is necessary to use RTL circuit delay parameters to calibrate the erroneous ESL model delay parameters to obtain corrected ESL delay parameters.

[0104] This method addresses the issue of insufficient accuracy in switch chip latency assessment. It rapidly marks RTL circuit parameters affecting chip latency into the ESL model, evaluates the accuracy of ESL model latency parameters using a high-precision chip ESL model, corrects inaccurate ESL model latency parameters, and finally evaluates packet transmission latency using the corrected ESL model latency parameters to obtain accurate latency results. This method improves the efficiency and accuracy of aligning ESL model latency parameters.

[0105] In addition, in this embodiment, the end-to-end latency data is further broken down into numerous small-granularity latency metrics, namely the transmission latency parameters corresponding to each block. The latency data is evaluated in each small-granularity latency parameter metric, making the evaluation results more refined and accurate.

[0106] It should be noted that this method can provide not only end-to-end transmission latency data of the chip, but also transmission latency parameter data of arbitrary length (which is less than the chip end-to-end latency) according to the needs of chip developers, providing convenience for chip developers to evaluate the latency indicators of different modules and subsystems inside the chip.

[0107] The following describes the apparatus embodiments corresponding to the above method embodiments.

[0108] Figure 5 This is a schematic diagram of a delay parameter verification device provided in an embodiment of this application. The device can be the aforementioned detection device, or a third-party device that includes the functions of the detection device and can implement the delay parameter verification method in the aforementioned embodiments.

[0109] Specifically, such as Figure 5 As shown, the device may include an acquisition unit 501 and a processing unit 502. Furthermore, the device may also include a storage unit (the storage unit is located in...). Figure 5 Other units or modules (not shown in the figure) are not limited in this embodiment.

[0110] The acquisition unit 501 is used to acquire a first set of parameters and a second set of parameters. The first set of parameters includes the delay parameters of the message transmission in at least one module of the RTL circuit. The second set of parameters includes the delay parameters of the at least one module when the message is transmitted in the ESL model. The RTL circuit and ESL circuit being detected are pre-divided into at least one module (block), and each module includes a signal input interface and an output interface.

[0111] The processing unit 502 is used to verify that when the first set of parameters does not match the second set of parameters, it determines that there is an error in the second set of parameters, calibrates the second set of parameters to obtain a third set of parameters, and uses the third set of parameters to evaluate the message transmission delay.

[0112] Optionally, in one specific implementation, if the at least one module includes a first module, the acquisition unit 501 is further configured to acquire the time difference between the time point when the message arrives at the input interface of the first module and the time point when it arrives at the output interface.

[0113] Furthermore, the acquisition unit 501 is also used to acquire the first set of parameters by reusing the EDA verification monitor or by using the interface signal monitoring function provided by EDA technology.

[0114] Optionally, in another specific embodiment, the processing unit 502 is further configured to determine whether the data transmitted in the RTL circuit chip by the message is real data before the acquisition unit 501 acquires the first set of parameters, and if so, acquire the first set of parameters.

[0115] Furthermore, when the indicator flag carried in the start of message (SOP) of the message is determined to be "1", it is determined that the data transmitted in the message is real data.

[0116] Optionally, in another specific implementation, when the message is a first message set, the first message set includes N messages of different lengths, N≥2, and N is a positive integer, the acquisition unit 501 is further used to acquire the weighted average of the delay parameters of the N messages transmitted in the same module.

[0117] Optionally, in another specific embodiment, the storage unit is used to store a CLAT table, which includes latency parameters transmitted by each of the at least one module. The acquisition unit 501 is further configured to acquire the first set of parameters from the CLAT stored in the storage unit.

[0118] Optionally, the CLAT table also stores the second set of parameters, as well as the comparison result of the first set of parameters and the second set of parameters.

[0119] Optionally, in another specific embodiment, the acquisition unit 501 is further configured to acquire the latency parameters of the transmission of the message in at least one module of the ESL model based on ESL modeling and ESL simulation technology.

[0120] This device combines EDA verification technology and ESL model technology to quickly mark RTL circuit parameters into the ESL model, ensuring that accurate delay data can be obtained at any time during chip development, thus improving the efficiency of obtaining chip transmission delay parameters.

[0121] In another hardware implementation, this application embodiment also provides a detection device, which can be a chip circuit or a functional module integrated into a third-party device, such as an APK package. Furthermore, the detection device may also include the aforementioned delay parameter verification device.

[0122] Figure 6A schematic diagram of the detection device is shown, including at least one processor 110 and an interface circuit 120, wherein the at least one processor 110 and the interface circuit 120 are coupled via a bus. Optionally, it may also include other modules or units such as a memory 130 and at least one pin.

[0123] At least one processor 110 serves as the control center for the chip circuit and can be used to perform methods such as the time delay parameter verification described in the aforementioned embodiments.

[0124] Furthermore, at least one processor 110 may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor may include a central processing unit (CPU) or a digital signal processor (DSP).

[0125] Furthermore, at least one processor 110 may also include a hardware chip, which may be a logic circuit, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0126] The memory 130 is used to store and exchange various types of data or signals, including a first message, a first message set, a first set of parameters, a second set of parameters, or a CLAT table. In addition, the memory 130 may store computer programs or code.

[0127] Specifically, memory 130 may include volatile memory, such as random access memory (RAM); it may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 130 may also include combinations of the above types of memory.

[0128] Optionally, the memory 130 can be integrated into at least one processor 110 as a storage medium, or it can be configured outside the processor; this embodiment does not limit this.

[0129] The memory 130 is used to store information such as the first set of parameters, the second set of parameters, the received messages, and the CLAT table.

[0130] The interface circuit 120 includes at least one input interface and one output interface, and can use any transceiver-like device. For example, the interface circuit 120 is connected to an RTL circuit chip to obtain the delay parameters of the RTL circuit, i.e., the aforementioned first set of parameters. In addition, the interface circuit 120 is also used to obtain the delay parameters of at least one module of the ESL model statistics, i.e., the aforementioned second set of parameters.

[0131] It should be understood that the interface circuit 120 is also used to communicate with other internal or external devices, such as Ethernet, WLAN, etc.

[0132] Furthermore, when the aforementioned detection device is used as a third-party device, such as a server or controller, the third-party device may also include a mobile communication module, a wireless communication module, etc. The mobile communication module includes modules with wireless communication capabilities, such as 2G / 3G / 4G / 5G communication modules. It may also include filters, switches, power amplifiers, low-noise amplifiers (LNAs), etc. In addition, the wireless communication module can provide wireless communication solutions for applications on servers or controllers, including WLAN, Bluetooth (BT), Global Navigation Satellite System (GNSS), etc.

[0133] It should be understood that the above-described detection device may include more or fewer other components, and the structure illustrated in the embodiments of this application does not constitute a specific limitation on its structure. Figure 6 The components shown can be implemented in hardware, software, firmware, or any combination thereof.

[0134] When implemented using software, it can be implemented entirely or partially as a computer program product. For example, in the aforementioned... Figure 5 In the device shown, the functions of the acquisition unit 501 and the processing unit 502 can be implemented by at least one processor 110 and interface circuit 120, and the function of the storage unit can be implemented by the memory 130.

[0135] Furthermore, embodiments of this application also provide a wireless communication system, such as... Figure 1 As shown, the system includes at least one server, a switch, a UE, and an eNB. The architecture of each device in the system can be similar to... Figure 6 The structures shown may be the same or different.

[0136] When using Figure 6 In the illustrated configuration, at least one processor 110 uses interface circuit 120 to acquire the first set of parameters and the second set of parameters. The first set of parameters includes latency parameters for message transmission in at least one module of the RTL circuit, and the second set of parameters includes latency parameters of the at least one module statistically analyzed during message transmission in the ESL model. Furthermore, at least one processor 110 is also configured to determine whether the first set of parameters matches the second set of parameters. If not, it determines that the second set of parameters has an error, calibrates the second set of parameters to obtain a third set of parameters, and uses the third set of parameters to evaluate message transmission latency.

[0137] The system provided in this system calibrates the ESL model delay parameters when an error is detected in the sampled ESL model delay parameters, and uses the calibrated parameters to evaluate the message delay. This avoids the errors caused by developers sampling RTL delay parameters. This method improves the accuracy of evaluating message transmission delay using the ESL model, while meeting the requirements of high precision and low latency, ensuring the competitiveness of chip project development.

[0138] In addition, this application also provides a computer program product comprising one or more computer program instructions. When a computer loads and executes the computer program instructions, all or part of the processes or functions described in the above embodiments are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0139] The computer program instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one network node, computer, server, or data center to another node via wired or wireless means.

[0140] Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. Additionally, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0141] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A method for verifying time delay parameters, characterized in that, The method includes: Obtain a first set of parameters, which includes the delay parameters of the message transmission in at least one module of the register transfer layer RTL circuit. Obtain a second set of parameters, which includes the latency parameters of at least one module as statistically analyzed during the transmission of the message in the electronic system-level design ESL model; If the first set of parameters does not match the second set of parameters, it is determined that the second set of parameters has an error. The second set of parameters is then calibrated to obtain the third set of parameters, and the message transmission delay is evaluated using the third set of parameters.

2. The method of claim 1, wherein, The at least one module includes a first module, wherein obtaining the first set of parameters includes: The time difference between the time the message arrives at the input interface of the first module and the time it arrives at the output interface is obtained.

3. The method according to claim 1 or 2, characterized in that, Before obtaining the first set of parameters, the process also includes: Determine whether the data transmitted in the message within the RTL circuit chip is real data; if so, obtain the first set of parameters.

4. The method according to claim 3, characterized in that, Determining whether the data transmitted in the message within the RTL circuit chip is real data includes: Determine whether the indicator flag carried in the beginning part of the message is "1".

5. The method according to claim 1, characterized in that, When the message is a first message set, and the first message set includes N messages of different lengths, N≥2, and N is a positive integer, then obtaining the first set of parameters includes: Obtain the weighted average of the latency parameters of the N messages transmitted in the same module.

6. The method according to claim 1, characterized in that, The process of obtaining the first set of parameters includes: The first set of parameters is obtained from the chip delay accuracy verification table CLAT, which includes the delay parameters transmitted by each of the at least one module.

7. The method according to claim 1, characterized in that, The process of obtaining the second set of parameters includes: Based on ESL modeling and ESL simulation techniques, the latency parameters of the message transmission in at least one module of the ESL model are obtained.

8. A device for testing time delay parameters, characterized in that, The device includes: The acquisition unit is used to acquire a first set of parameters and a second set of parameters. The first set of parameters includes the delay parameters of the message transmission in at least one module of the register transfer layer RTL circuit, and the second set of parameters includes the delay parameters of the at least one module statistically analyzed when the message is transmitted in the electronic system level design ESL model. The processing unit is used to verify that when the first set of parameters does not match the second set of parameters, it determines that there is an error in the second set of parameters, calibrates the second set of parameters to obtain a third set of parameters, and uses the third set of parameters to evaluate the message transmission delay.

9. The apparatus according to claim 8, characterized in that, The at least one module includes a first module. The acquisition unit is further configured to acquire the time difference between the time point when the message arrives at the input interface of the first module and the time point when it arrives at the output interface.

10. The apparatus according to claim 8 or 9, characterized in that, The processing unit is further configured to determine whether the data transmitted in the RTL circuit chip by the message is real data before the acquisition unit acquires the first set of parameters; if so, the first set of parameters is acquired.

11. The apparatus according to claim 10, characterized in that, The processing unit is further configured to determine that the data is real data when the indicator flag carried in the message start portion of the message is "1".

12. The apparatus according to claim 8, characterized in that, When the message is a first message set, the first message set includes N messages of different lengths, N≥2, and N is a positive integer. The acquisition unit is also used to acquire the weighted average value of the delay parameters of the N messages transmitted in the same module.

13. The apparatus according to claim 8, characterized in that, It also includes storage units, The storage unit is used to store a chip latency accuracy verification table (CLAT), which includes latency parameters transmitted by each of the at least one module. The acquisition unit is further configured to acquire the first set of parameters from the CLAT of the storage unit.

14. The apparatus according to claim 8, characterized in that, The acquisition unit is also used to acquire the latency parameters of the transmission of the message in at least one module of the ESL model based on ESL modeling and ESL simulation technology.

15. A detection device, characterized in that, include: At least one processor and interface circuit, The interface circuit is used to provide instructions and / or data to the at least one processor; The at least one processor is configured to execute the instructions to implement the method as described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed, implement the method as described in any one of claims 1 to 7.

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