Offset embedded ground plane cutout

Abstract

An embedded ground plane cutout is proposed for generating an offset in a qubit device to facilitate frequency tuning of the qubit device. The qubit device may include a first substrate and a second substrate in a flip-chip assembly. The qubit chip assembly may include a qubit component fabricated on the first substrate. The qubit component may include a Josephson junction (JJ) circuit that can be offset from the center point of the qubit component. The qubit chip assembly may include an embedded ground plane located on the surface of the qubit chip assembly. The cutout portion may be formed in the ground plane and positioned above the JJ circuit. The cutout portion may enable access to the JJ circuit for optical signals or magnetic flux. The frequency of the qubit component can be tuned based on the application of optical signals or magnetic flux to the JJ circuit.

Description

Technical Field

[0001] This disclosure relates to quantum circuits, and more specifically, to offset embedded ground plane cutouts. Summary of the Invention

[0002] The following overview is presented to provide a basic understanding of one or more embodiments of the disclosed subject matter. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, apparatuses, structures, methods, devices, and / or computer program products are provided that can facilitate the creation, design, and / or utilization of offset circuitry systems and embedded ground plane cutouts for qubit devices to facilitate frequency tuning of such qubit devices.

[0003] According to an embodiment, the system may include a qubit chip assembly. The qubit chip assembly may include a qubit component fabricated on a substrate, wherein the qubit component includes a Josephson junction circuit offset from a defined distance from the center point of the qubit component. The qubit chip assembly may further include a ground plane located on the surface of the qubit chip assembly, wherein a cutout portion is formed in the ground plane and defined by the remainder of the ground plane, and is positioned on the Josephson junction circuit.

[0004] Another embodiment relates to a method that may include forming a qubit assembly including a Josephson junction circuit on a substrate, wherein the Josephson junction circuit is offset from a defined distance from a center point of the qubit assembly. The method may further include forming a ground plane on a surface of a qubit chip package including the qubit assembly, wherein a cutout portion is formed in the ground plane and defined by the remainder of the ground plane, and positioned above the Josephson junction circuit.

[0005] Another embodiment relates to a qubit device that may include a qubit chip package. The qubit chip package may include a qubit component formed on a substrate assembly, wherein the qubit component includes a Josephson junction component offset by a defined amount from the central region of the qubit component. The qubit chip package may further include a ground plane component located on a surface of the qubit chip package, wherein a cutout portion is formed in the ground plane component and defined by the remainder of the ground plane component and located on the Josephson junction component.

[0006] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0007] This patent or application document contains at least one color drawing. A copy of this patent or application disclosure with color drawings will be provided by the office upon request and payment of the necessary fees.

[0008] Figure 1 Illustrations of exemplary, non-limiting devices are shown based on different aspects and embodiments of the disclosed subject matter. These devices may include offset circuitry and offset ground plane cutouts to facilitate tuning of the frequency of one or more qubits of the device.

[0009] Figure 2 The illustration depicts top and side views of example portions of a first chip (e.g., a qubit chip) according to different aspects and embodiments of the disclosed subject matter. The first chip may include a qubit component having an offset Josephson junction circuit and an offset cutout portion in an embedded ground plane to facilitate laser tuning of the Josephson junction circuit of the qubit component.

[0010] Figure 3 The illustration shows top and side views of example portions of a first chip (e.g., a qubit chip) according to different aspects and embodiments of the subject matter of this disclosure. The first chip may include a qubit component having an offset Josephson junction circuit, including a superconducting quantum interference device (SQUID) component, and an offset cutout portion in an embedded ground plane to facilitate the tuning of the flux of the qubit component.

[0011] Figure 4 The diagram depicts a top view of an example portion of a first chip (e.g., a qubit chip) according to various aspects and embodiments of the disclosed subject matter, wherein flux coils may be placed over an offset cutout portion in the embedded ground plane of the qubit chip to facilitate flux tuning of the qubit assembly.

[0012] Figure 5 Illustrations of example, non-limiting devices are shown based on different aspects and embodiments of the disclosed subject matter. These devices may include offset Josephson junction circuitry, offset embedded ground plane cutouts, and interpolator ground plane cutouts that may combine frequency enhancement of one or more flux-tunable qubits of the device with mutual inductance of the magnetic field generated by the coil assembly and facilitate ideal tuning of the frequency of one or more flux-tunable qubits of the device.

[0013] Figure 6The illustration shows an example X-mon qubit assembly according to different aspects and embodiments of the subject matter of this disclosure. The qubit assembly may include an offset Josephson junction circuit and may be associated with an offset ground plane cutout portion to facilitate desired tuning of the qubits of the qubit device.

[0014] Figure 7 The illustration depicts an example of a transmon qubit assembly according to different aspects and embodiments of the disclosed subject matter. The qubit assembly may include an offset Josephson junction circuit and may be associated with an offset ground plane cutout portion to facilitate desired tuning of the qubits of the qubit device.

[0015] Figure 8 An example graph illustrating the operator coupling dependency relative to ground plane cutoff offset, based on various aspects and embodiments of the disclosed subject matter, is presented.

[0016] Figure 9 The charts depict example graphs illustrating the dependence of magnetic fields and qubit manipulator transmission on different aspects and embodiments of the disclosed subject matter.

[0017] Figure 10 A diagram illustrating the frequency dependence of an operator coupled with a ground plane cut-off offset according to various aspects and embodiments of the disclosed subject matter is shown.

[0018] Figure 11 A diagram illustrating an example of how qubit crosstalk can cause a ground plane cutoff offset, based on various aspects and embodiments of the disclosed subject matter.

[0019] Figure 12 An example graphical transmission S as a function of frequency is shown according to various aspects and embodiments of the disclosed subject matter. 21 A diagram illustrating (e.g., qubit-to-qubit crosstalk).

[0020] Figure 13 Block diagrams are depicted of example systems based on different aspects and embodiments of the disclosed subject matter, which can be used to create, form, or design a qubit device including offset Josephson junction circuitry, offset embedded ground plane cutout portions, and / or offset interpolator ground plane cutout portions.

[0021] Figure 14 Flowcharts of exemplary, non-limiting methods are shown based on different aspects and embodiments of the disclosed subject matter, which can form an offset circuit system and a ground plane cutout to facilitate the tuning of the frequency of one or more qubits of a qubit device.

[0022] Figure 15A flowchart of another example, non-limiting method is depicted based on various aspects and embodiments of the disclosed subject matter, which may form an offset circuit and a ground plane cutout to facilitate tuning of the frequency of one or more qubits of a qubit device.

[0023] Figure 16 A flowchart of an example, non-limiting method for tuning the frequency of a qubit component in a qubit device according to different aspects and embodiments of the disclosed subject matter is shown, wherein the qubit device includes an offset cutout portion in an embedded ground plane and / or the qubit device includes a plurality of offset Josephson junction circuits.

[0024] Figure 17 A block diagram is shown that illustrates an example non-limiting operating environment that may facilitate one or more embodiments described herein.

[0025] Figure 18 Schematic diagrams depicting example qubit devices, which may include multi-layered packaging, based on various aspects and embodiments of the disclosed subject matter. Detailed Implementation

[0026] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding background or overview or detailed description sections.

[0027] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0028] Frequency-tunable qubit devices can be useful and desirable in many quantum computing architectures. For example, frequency-tunable qubit devices can be used for parameter computation or as tunable coupling devices. Frequency-tunable qubit devices based on Josephson junction circuits can exist, where the qubit device can be tuned by applying an optical signal (e.g., a laser signal) to the Josephson junction circuit. Multiple frequency-tunable qubit devices based on superconducting quantum interference devices (SQUIDs) can also exist, where the qubit device can be tuned by applying a magnetic flux to the SQUID loop.

[0029] Multilayer packaging can be used to scale up multi-qubit devices (e.g., devices including multiple qubit components). This multilayer package can include a chip that may include multiple qubits and associated circuitry, which can be intercalated into a larger component (e.g., a qubit chip assembly), wherein the qubit chip and intercalator chip include grounding via through-silicon vias (TSVs) to desirablely suppress chip patterns. See also Figure 18 , Figure 18 This is an illustration of an example qubit device 1800, which may include a multilayer package, based on different aspects and embodiments of the disclosed subject matter. The example qubit device 1800 may include a qubit chip 1802 and an interpolator chip 1804. Each of the qubit chip 1802 and the interpolator chip 1804 may have desired dimensions (e.g., length, width, and height). A handler chip 1806 may be associated with the qubit chip 1802, wherein the handler chip 1806 may have desired dimensions. Another handler chip 1808 may be associated with the interpolator chip 1804, wherein the handler chip 1808 may have desired dimensions.

[0030] The qubit chip 1802 may include an embedded ground plane 1810, which may be associated with (e.g., adjacent to or attached to) the operator wafer 1806, wherein the embedded ground plane 1810 may be formed of a desired conductive material, such as a desired superconducting material. A metallization layer 1812 (e.g., qubit metallization) may be formed or deposited on the outer or top surface of the qubit chip 1802, wherein the metallization layer 1812 may include a conductive material, such as a desired superconducting material. The metallization layer 1812 may be processed (e.g., chemically etched) to form qubits, such as qubits 1814 and 1816, and a ground plane 1818 (e.g., a qubit ground plane). A set of TSVs, such as TSV1820 and TSV1822, can be formed in the qubit chip 1802 (e.g., they can be formed in the qubit chip structure material of the qubit chip 1802, wherein the qubit chip structure material may be located between the embedded ground plane 1810 and the ground plane 1818 and the qubits 1814 and 1816).

[0031] Further relating to the interpolator chip 1804, the interpolator chip 1804 may include an embedded ground plane 1824, which may be associated with (e.g., adjacent to or attached to) the operator wafer 1808, wherein the embedded ground plane 1824 may be formed of a desired conductive material (e.g., a desired superconducting material). A ground plane 1826 (e.g., an interpolator ground plane) may be formed or deposited on the outer or top surface of the interpolator chip 1804, wherein the ground plane 1826 may include a conductive material, such as, for example, a desired superconducting material. A set of TSVs, such as TSV 1828 and TSV 1830, may be formed in the interpolator chip 1804 (e.g., may be formed in the interpolator chip structure material of the interpolator chip 1804, wherein the interpolator chip structure material may be located between the embedded ground plane 1824 and the ground plane 1826).

[0032] For example, near the location of the TSV, a set of raised joints, such as raised joints 1832 and 1834, can be formed between the ground plane 1818 of the qubit chip 1802 and the ground plane 1826 of the interpolator chip 1804. This set of raised joints can connect components on the qubit chip 1802 to components on the interpolator chip 1804.

[0033] It may be desirable to tune (e.g., adjust) the frequency of the qubits in a qubit device to avoid unwanted frequency conflicts, which could negatively impact the performance of a quantum computer. Qubit frequency tuning can typically be performed after the qubit device has been fabricated. Techniques for tuning the qubit frequency can include laser tuning or flux tuning. With laser tuning, a laser device can apply a pulse of light (e.g., a laser pulse) to the Josephson junction of the qubit device to adjust the frequency of the qubits. With flux tuning, a coil assembly (e.g., an electric coil) can generate a magnetic field, and the magnetic flux generated by this magnetic field can be applied to the SQUID loop associated with the qubits of a flux-frequency-tunable qubit device to adjust the frequency of those qubits.

[0034] Utilizing a multilayer package with a flip-chip structure, where the operator wafer associated with the qubit chip and interpolator chip of the qubit device can be located on an external region of the qubit device, and where the qubits can be located in an internal region of the qubit device, adjusting the frequency of these qubits using laser tuning or flux tuning techniques may be infeasible, impractical, or impossible due to the presence of a continuous ground plane on top of the qubit chip. This continuous ground plane (e.g., a continuous superconducting ground plane) can prevent or suppress optical signals or magnetic flux from penetrating the ground plane and reaching the qubits to achieve tuning of these qubits.

[0035] It is desirable to have frequency-tunable devices that do not suffer from these and / or other defects. For example, it may be desirable to create, implement, or develop a frequency-tunable qubit device that can be tuned in an efficient, practical, and useful manner (e.g., post-tuning) that will undesirably (e.g., negatively or excessively) affect the performance of the qubit device.

[0036] Therefore, the various embodiments described herein relate to techniques for designing, creating, and / or utilizing offset circuitry systems and embedded ground plane cutouts to facilitate frequency tuning of the qubit device. The qubit device may include a first substrate assembly (e.g., a first processor wafer) and a second substrate assembly (e.g., a second processor wafer) in a flip-chip assembly. The qubit chip assembly may include a qubit component formed (e.g., fabricated) on the first substrate assembly (e.g., on the first substrate assembly of the qubit chip). The qubit component may include a Josephson junction circuit that may be offset from a distance defined by a center point of the qubit component. In some embodiments, the Josephson junction circuit may include a SQUID loop. The qubit chip assembly may also include an embedded ground plane that may be located on the surface of the qubit chip assembly, wherein the embedded ground plane may be located on the opposite side of the qubit chip to the qubit ground plane, and wherein the embedded ground plane may be associated with, formed on, or located on the first substrate assembly (e.g., the operator wafer assembly of the qubit chip). A cutout portion can be formed in the embedded ground plane and can be positioned above or at least partially above the Josephson junction circuit. The cutout portion can have a desired shape and size, as described herein. In some embodiments, the cutout portion enables access to the Josephson junction circuit for an optical signal (e.g., an optical signal including a laser pulse), wherein an optical signal generator device can generate the optical signal, and wherein the frequency of the qubit component can be tuned at least partially based on the application of the optical signal to the Josephson junction circuit (e.g., laser tuning). In other embodiments, the cutout portion enables access to the Josephson junction circuit for magnetic flux, wherein a coil component can generate a magnetic field to produce the magnetic flux, and wherein the frequency of the qubit component can be tuned at least partially based on the application of the magnetic flux to the Josephson junction circuit including the SQUID loop (e.g., flux tuning).

[0037] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the accompanying drawings.

[0038] Figure 1Illustrations of an example, non-limiting device 100 are shown based on various aspects and embodiments of the disclosed subject matter. This device may include offset circuitry and an offset ground plane cutout to facilitate tuning the frequency of one or more qubits of the device 100. The device 100 may include a system of different components and circuitry that may be arranged to perform one or more desired functions. In some embodiments, the device 100 may be or may include a qubit device (e.g., a frequency-tunable qubit device). In some embodiments, the device 100 may be a transport subqubit device.

[0039] The device 100 may include a first chip 102 (e.g., a qubit chip) and a second chip 104 (e.g., an interpolator chip). In some embodiments, the first chip 102 and the second chip 104 may be arranged relative to each other to form a multilayer flip-chip package, wherein the second chip 104 may be flipped (e.g., inverted) such that its top surface (on which various components and circuits are formed) can face and be relatively adjacent to the top surface of the first chip 102, on which various other components and circuits may be formed. The first chip 102 and the second chip 104 may each have desired dimensions (e.g., length, width, and height), wherein at least some dimensions of the second chip 104 (e.g., length, width, and / or height) may be the same as or correspond to at least some dimensions of the first chip 102 (e.g., length, width, and / or height). Device 100 (e.g., a qubit device, or a multi-qubit device or package) may have varying dimensions, wherein the length of device 100 may range from, for example, millimeters to tens of millimeters, the width of device 100 may range from, for example, millimeters to tens of millimeters, and the thickness may range from, for example, about 1 millimeter (mm) to about 3 mm. It should be appreciated and understood that these dimensions of device 100 are exemplary, and according to other embodiments, device 100 may have dimensions different from the exemplary dimensions described herein (e.g., smaller or larger).

[0040] A first substrate assembly 106 (also referred to herein as a first actuator wafer) may be associated with a first chip 102, wherein the first substrate assembly 106 may have a desired size, and wherein at least some dimensions of the first substrate assembly 106 (e.g., length and / or width) may be the same as or correspond to at least some dimensions of the first chip 102 (e.g., length and / or width). The first substrate assembly 106 may provide physical support for the first chip 102 and may provide areas or surfaces thereon on which different components and circuits of the first chip 102 may be formed, as described herein. A second substrate assembly 108 (also referred to herein as a second actuator wafer) may be associated with a second chip 104, wherein the second substrate assembly 108 may have a desired size, and wherein at least some dimensions of the second substrate assembly 108 (e.g., length and / or width) may be the same as or correspond to at least some dimensions of the second chip 104 (e.g., length and / or width). The second substrate assembly 108 may provide physical support for the second chip 104 and may provide areas or surfaces thereon on which different components and circuits of the second chip 104 may be formed, as described herein. The first substrate assembly 106 and the second substrate assembly 108 may include desired silicon-based materials (e.g., silicon-type dielectric substrates).

[0041] The first chip 102 may include an embedded ground plane 110, which may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the first substrate assembly 106, wherein the embedded ground plane 110 may be formed of a desired conductive material, such as a desired superconducting material (e.g., a niobium-based superconducting material or other superconducting materials). The first chip 102 and / or the first substrate assembly 106 may have variable dimensions, wherein the length of the first chip 102 and / or the first substrate assembly 106 may range, for example, from millimeters to tens of millimeters, the width may range, for example, from millimeters to tens of millimeters, and the thickness may range, for example, from about 100 micrometers (m) to about 1000 μm. It should be understood and appreciated that these dimensions of the first chip 102 and / or the first substrate assembly 106 are exemplary, and according to other embodiments, the first chip 102 and / or the first substrate assembly 106 may have dimensions different from the example dimensions described herein (e.g., smaller or larger). On the outer or top surface of the first chip 102, a metallize layer 112 (e.g., qubit metallization) may be formed or deposited, wherein the metallize layer 112 may include a conductive material, such as, for example, a desired superconducting material. The metallize layer 112 may be processed (e.g., chemically etched) to form a set of qubit components, including, for example, qubit components 114 and 116, and a ground plane 118 (e.g., a qubit ground plane), as described more fully herein. The qubit components (e.g., 114 or 116) may have varying dimensions, wherein the length of the qubit components may range, for example, from about 50 μm to about 500 μm, the width of the qubit components may range, for example, from about 50 μm to about 500 μm, and the thickness of the qubit components may range, for example, from about 50 nanometers (nm) to about 500 nm. It should be understood and appreciated that these dimensions of the qubit assembly (e.g., 114 or 116) are exemplary, and according to other embodiments, the qubit assembly may have different dimensions (e.g., smaller or larger) than the examples described herein.

[0042] A first set of TSVs, including TSVs 120 and 122, can be formed in the first chip 102. For example, the first set of TSVs (e.g., 120, 122) can be formed in a structural material (e.g., a qubit chip structural material) of the first chip 102, wherein the structural material can be located between embedded ground planes 110 and 118 and qubits 114 and 116, wherein a portion of the structural material retained after the formation of the TSVs (e.g., 120, 122) can surround the TSVs and define the shape and size of the TSVs, and wherein the TSVs can have desired dimensions (e.g., width and / or height). According to various embodiments, the structural material of the first chip 102 can be or may include the same or similar material as the substrate material of the first substrate assembly 106. The first set of TSVs (e.g., 120, 122) can be used to suppress or promote the suppression of chip patterns of the first chip 102. Corresponding qubit assemblies (e.g., 114, 116) can typically be positioned between corresponding TSVs (e.g., 120, 122).

[0043] Further concerning the second chip 104, the second chip 104 may include an embedded ground plane 124, which may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the second substrate assembly 108, wherein the embedded ground plane 124 may be formed of a desired conductive material, such as a desired superconducting material. The second chip 104 and / or the second substrate assembly 108 may have variable dimensions, wherein the length of the second chip 104 and / or the second substrate assembly 108 may range, for example, from millimeters to tens of millimeters, the width may range, for example, from millimeters to tens of millimeters, and the thickness may range, for example, from about 100 μm to about 1000 μm. It should be understood and appreciated that these dimensions of the second chip 104 and / or the second substrate assembly 108 are exemplary, and according to other embodiments, the second chip 104 and / or the second substrate assembly 108 may have dimensions different from the example dimensions described herein (e.g., smaller or larger). On the outer or top surface of the second chip 104, a ground plane 126 (e.g., an interpolator ground plane) may be formed or deposited, wherein the ground plane 126 may include a conductive material, such as a desired superconducting material.

[0044] A second set of TSVs, including TSVs 128 and 130, can be formed in the second chip 104. For example, the second set of TSVs (e.g., 128, 130) can be formed in a structural material (e.g., an interpolator chip structural material) of the second chip 104, wherein such structural material can be located between an embedded ground plane 124 and a ground plane 126, wherein a portion of the remaining structural material after the formation of the TSVs (e.g., 128, 130) can surround the TSVs and define their shape and size, and wherein the TSVs can have desired dimensions (e.g., width and / or height). According to different embodiments, the structural material of the second chip 104 can be or may include the same or similar material as the substrate material of the second substrate assembly 108. The second set of TSVs (e.g., 128, 130) can be used to suppress or facilitate the suppression of chip patterns of the second chip 104.

[0045] In some embodiments, a set of bump bonding components (BBs) may be formed between the ground plane 118 of the first chip 102 and the ground plane 126 of the second chip 104, near the locations of the respective TSVs of the first group of TSVs (e.g., TSV120, TSV122, and / or other TSVs) and the second group of TSVs (e.g., TSV128, TSV130, and / or other TSVs). This set of bump bonding components (e.g., 132, 134) may connect or facilitate connections between components on the first chip 102 and components on the second chip 104.

[0046] The frequency of device 100 may need to be tuned (e.g., adjusted or modified). It may be desirable to be able to tune one or more qubit components of the qubit device after its fabrication. In some embodiments, laser tuning can be performed by having a laser device apply an optical signal having a desired wavelength (e.g., a laser or an optical signal including a laser or optical pulse) to the Josephson junction circuit (e.g., a Josephson junction component) of the one or more qubit components of the qubit device, and the frequency of the one or more qubit components can be tuned (e.g., adjusted or modified) to the desired frequency at least in part based on applying the optical signal to the Josephson junction circuit of the one or more qubit components. For example, the optical signal may include infrared or other invisible lasers or optical pulses, which may have wavelengths in the infrared or invisible spectrum. In other embodiments, the Josephson junction circuit of the one or more qubit components of the qubit device (e.g., flux-tunable qubits) may include a SQUID component (e.g., a SQUID loop) of a coupler component (e.g., a qubit / coupler device). Flux coils can apply a desired amount of magnetic flux to the SQUID component and can tune (e.g., adjust or modify) the frequency of the qubit component based at least in part on the amount of magnetic flux applied to the SQUID component. Laser tuning or flux tuning of qubit devices can desirablely reduce frequency conflicts in packaged multi-qubit devices and can alleviate precision constraints (e.g., specifications or requirements) for targeting qubit frequencies, which can be particularly challenging to meet (e.g., comply with requirements) when the number of qubits on a multi-qubit device is increased. In conventional multilayer qubit packaging structures, because a continuous ground plane (e.g., an embedded ground plane) exists on top of the qubit chip (e.g., this continuous superconducting ground plane can prevent the optical signal or magnetic flux from penetrating such a ground plane to enable the application of the optical signal or magnetic flux to the Josephson junction circuit of the qubit), the qubit cannot be frequency-tuned, or at least cannot be ideally (e.g., appropriately, adequately, or optimally) tuned, by laser tuning or flux tuning techniques.

[0047] According to various embodiments, the disclosed subject matter (e.g., using device-formed components, as described herein) may be formed in the embedded ground plane 110 of the first chip 102 (e.g., by removing a portion of the conductive material of the embedded ground plane 110) with cutouts (e.g., open segments or regions) to enable (e.g., allow) the light access of an optical signal or the penetration of magnetic flux to the Josephson junction circuit of the qubit components (e.g., 114, 116) of the device 100 to facilitate tuning of the qubit components of the device 100 (e.g., laser tuning or flux tuning). However, it should be noted that if the cutouts in the embedded ground plane 110 and other features of the qubit device are not properly structured, forming cutouts in the embedded ground plane of the qubit chip may potentially undesirably provide an alternative path for energy, thereby undesirably leaking from the qubits to the operator wafer, and / or potentially causing undesirable crosstalk between the qubits in the device (e.g., a multi-qubit device). The transmission of electromagnetic energy from the qubit to the operator chip (e.g., S21) can be undesirably amplified (e.g., increased) at frequencies corresponding to the chip mode in the operator chip of the qubit chip, and can increase with increasing cut-out size in the embedded ground plane, which can saturate for cut-out sizes greater than approximately 200 μm. While reducing the size of the cut-out in the embedded ground plane to below 200 μm can attenuate the transmission from the qubit to the operator, reducing the cut-out size can undesirably reduce the optical access efficiency on the Josephson junction circuit that applies the optical signal to the qubit and can undesirably reduce the mutual inductance from the flux coil to the qubit device.

[0048] According to various embodiments, the disclosed subject matter may be desirablely (e.g., suitably, appropriately, or optimally) formed and structured cutout portions (e.g., offset cutout portions), such as cutout portions 136 and 138, in the embedded ground plane 110 and other features of the qubit device to enable desirable tuning of the qubit components (e.g., 114, 116) of the qubit device while mitigating (e.g., reducing or minimizing) undesirable transmission of electromagnetic energy from the qubit to the operator wafer and undesirable crosstalk between qubits. The disclosed subject matter can also offset the Josephson junction circuits (e.g., Josephson junction components or SQUID components (e.g., SQUID loops)) of these qubit components (e.g., 114, 116), along with the cutouts (e.g., 136, 138) positioned above the offset Josephson junction circuit for each qubit component (e.g., 114, 116), enabling ideal tuning of the qubit components (e.g., 114, 116) of device 100 while mitigating (e.g., reducing or minimizing) undesirable electromagnetic energy transfer from the qubit to the processing wafer and undesirable crosstalk between qubits, as described more fully herein.

[0049] It should be recognized and understood that although only two cutout portions are depicted in device 100, including cutout portions 136 and 138 formed in the embedded ground plane 110, the subject matter disclosed is not limited thereto, and according to different embodiments, device 100 may include a desired number of cutout portions formed in the embedded ground plane 110, for example, to correspond to and be associated with corresponding qubit components formed on device 100.

[0050] See Figure 2 (together) Figure 1 ), Figure 2 The illustration depicts top-view (e.g., top cross-sectional view) and side-view (e.g., side cross-sectional view) views of example portions of a first chip 200 (e.g., a qubit chip) according to different aspects and embodiments of the disclosed subject matter. The first chip may include a qubit assembly having an offset Josephson junction circuit and an offset cutout portion in an embedded ground plane to facilitate laser tuning of the Josephson junction circuit of the qubit assembly. For reasons of brevity and clarity, Figure 2 Only some components and features of the qubit chip and qubit assembly are shown in the image. Figure 2 A top view 202 and a side view 204 of this portion of the first chip 200 are presented.

[0051] A first chip 200 (e.g., a portion of the first chip 200) may include a qubit component 206, which may be formed in a ground plane pocket 208, which may be formed in a ground plane 210 of the first chip 200 (e.g., a portion of the qubit ground plane). The qubit component 206, the ground plane pocket 208, and the ground plane 210 may be formed on and / or by a metallization layer, which may be formed and processed (e.g., etched) on or associated with a first substrate assembly 212 (e.g., a first processing wafer). The metallization layer, as well as the qubit component 206 (partially) and the ground plane 210, may be formed of a desired conductive material, such as a desired superconducting material. The first substrate assembly 212 may be made of a desired silicon-based material. The ground plane pouch 208 may have desired dimensions (e.g., length, width, and / or depth), spanning an area on the order of micrometers, larger than the size of the qubit assembly 206, and may surround the qubit assembly 206 to facilitate the desired formation of the qubit assembly 206 and the desired isolation of the qubit assembly 206 from other components of the qubit device. The first chip 200 may be connected to... Figure 1 The first chip 102 is substantially the same, except as described and modified herein, in order to enable tuning (e.g., laser tuning) of the qubits of the qubit device (e.g., qubit assembly 206).

[0052] The qubit assembly 206 may include a capacitor assembly (C) 214 (e.g., a qubit capacitor) that may include or be associated with capacitor paddle assemblies 216 and 218, which may have desired dimensions (e.g., length, width, and height). Capacitor paddle assemblies 216 and 218 may be separated from each other, with a desired amount of space between them (e.g., on the micrometer scale). The qubit assembly 206 may also include a Josephson junction circuit that may include a Josephson junction assembly 220, wherein the ends (e.g., corresponding terminals) of the Josephson junction assembly 220 may be correspondingly associated with (e.g., electrically connected to) these capacitor paddle assemblies 216 and 218. Conventionally, the Josephson junction may be located (e.g., positioned) in the central region of the capacitor paddles of the qubit capacitor (e.g., the Josephson junction may be located halfway along the length of these capacitor paddles). In some embodiments, the disclosed subject matter (e.g., employing a device forming component) can form a Josephson junction circuit including a Josephson junction component 220, which is desirablely offset from the center of capacitor paddle components 216 and 218 by a defined distance (d), such that the Josephson junction circuit including the Josephson junction component 220 can be positioned (e.g., located) on or near the ends of capacitor paddle components 216 and 218 on one side of defined qubit device forming parameters. According to various embodiments, the defined offset distance (d) can range, for example, from about 200 μm to 800 μm. For example, the desired defined offset distance (d) could be about 300 μm. In some embodiments, the Josephson junction circuit can be a capacitively shunt Josephson junction circuit. According to the defined qubit device formation criteria, the disclosed subject matter can be desirablely positioned further away from the center of qubit assembly 206 (e.g., the qubit center) and the center of capacitor paddle assemblies 216 and 218 by offsetting the Josephson junction circuit, including the Josephson junction assembly 220, from the center of qubit assembly 206 (e.g., the qubit center) and the center of capacitor paddle assemblies 216 and 218, and along the length of capacitor paddle assemblies 216 and 218.

[0053] The first chip 200 may further include an embedded ground plane 222, which may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the first substrate assembly 212, wherein the embedded ground plane 222 may be formed of a desired conductive material, such as a desired superconducting material. The embedded ground plane 222 may be a surface (e.g., an embedded surface) of a qubit chip assembly (also referred to as a qubit chip package) of a qubit device. The qubit assembly (including qubit assembly 206 and ground plane 210 formed by a metallization layer) may be located on opposite surfaces of the qubit chip assembly. A structural material 224 (e.g., a qubit chip structural material) that may include the same or similar material as the first substrate assembly 212 may be located between the embedded ground plane 222 and the qubit assembly 206, the ground plane pouch 208, and the ground plane 210. Therefore, the embedded ground plane 222 may be located (e.g., embedded) between the structural material 224 and the first substrate assembly 212.

[0054] In some embodiments, the disclosed subject matter (e.g., using a device forming component) may form a cutout 226 in an embedded ground plane 222, wherein the cutout 226 may have desired dimensions (e.g., length and width) according to defined qubit device forming criteria. In some embodiments, the disclosed subject matter (e.g., using a device forming component) may form the cutout 226 to have a desired length that may be greater than approximately 200 μm, according to defined qubit device forming criteria. When forming the cutout 226, the disclosed subject matter (e.g., using a device forming component) may desirablely offset the cutout 226 relative to the position of the qubit component 206, and particularly relative to the position of the capacitor component 214, by a desired distance, such that the cutout 226 may be positioned over (e.g., positioned over at least a portion of) a Josephson junction circuit including the offset of the Josephson junction component 220. For example, the disclosed subject matter can offset the position of the cutout portion 226 in the embedded ground plane 222 and can offset the position of the Josephson junction circuit, including the Josephson junction assembly 220, relative to the position of the qubit assembly 206, and particularly relative to the position of the capacitor assembly 214, such that the capacitor assembly 214 is exposed, the capacitor paddle assemblies 216 and 218, and / or other components of the qubit assembly 206 to the cutout portion 226 and the first substrate assembly 212 (e.g., the first operator wafer) can be desirously reduced or minimized, which can reduce or minimize the amount of energy leaking from the qubit assembly 206 to the first substrate assembly 212 and / or can reduce or minimize the interaction between the qubit assembly 206 and another qubit assembly in the qubit device (e.g., a multi-qubit device). Figure 2Crosstalk between qubit components (not shown in the diagram). For example, the remainder of the embedded ground plane 222 may be positioned over and / or cover a desired portion (e.g., a majority) of the capacitor assembly 214, including the desired portions (e.g., a majority) of the capacitor paddle assemblies 216 and 218. This may desirably reduce or minimize the amount of energy leaking from the qubit component 206 to the first substrate assembly 212 and / or reduce or minimize crosstalk between the qubit component 206 and one or more other qubit components of the qubit device. Thus, qubit operator coupling may be desirablely suppressed (e.g., reduced or minimized). Moreover, crosstalk between qubit components (e.g., qubit component 206 and adjacent qubit components) may be ideally suppressed (e.g., reduced or minimized) to substantially the same level as when no cut-off portion exists (e.g., when a continuous embedded ground plane is present). In some embodiments, the cutout portion 226 may be offset relative to the Josephson junction circuit, including offset relative to the Josephson junction assembly 220, such that a portion of the cutout portion 226 on one side (e.g., the edge) of the cutout portion 226 can be positioned on the Josephson junction circuit (e.g., the Josephson junction assembly 220), wherein another portion (e.g., a relatively larger portion) of the cutout portion 226 is positioned on a ground plane bag 208 adjacent to the qubit assembly 206.

[0055] In some embodiments, a laser device 228 may be utilized to facilitate tuning the frequency of the qubit assembly 206. The laser device 228 may generate and emit an optical signal 230 (e.g., a laser beam or an optical signal comprising a laser beam or optical pulse), which may have a desired wavelength, as described herein. The laser device 228 may apply the optical signal 230 to the Josephson junction circuit (including the Josephson junction assembly 220) via optical access accessible through a cutout 226 in the embedded ground plane 222. For example, the optical signal 230 may pass through the first substrate assembly 212, the cutout 226 in the embedded ground plane 222, and the structural material 224 between the embedded ground plane 222 and the ground plane 210, and may be applied to the Josephson junction circuit (including the Josephson junction assembly 220). The frequency of the qubit assembly 206 may be desired (e.g., suitably or optimally) at least partially tuned or adjusted based on the optical signal 230 applied to the Josephson junction circuit (including the Josephson junction assembly 220).

[0056] Turn Figure 3 (together) Figure 1 ), Figure 3Illustrations showing top-view (e.g., top cross-sectional view) and side-view (e.g., side cross-sectional view) views of example portions of a first chip 300 (e.g., a qubit chip) according to different aspects and embodiments of the disclosed subject matter, the first chip may include a qubit component having an offset Josephson junction circuit including a SQUID component, and an offset cutout portion in an embedded ground plane to facilitate flux tuning of the qubit component. For reasons of simplicity and clarity, Figure 3 Only some components and features of the qubit chip and qubit assembly are shown in the image. Figure 3 A top view 302 and a side view 304 of this portion of the first chip 300 are presented.

[0057] A first chip 300 (e.g., a portion of the first chip 300) may include a qubit component 306, which may be formed in a ground plane pouch 308, which may be formed in a ground plane 310 of the first chip 300 (e.g., a portion of the qubit ground plane). The qubit component 306, the ground plane pouch 308, and the ground plane 310 may be formed on and / or formed by a metallization layer, which may be formed and processed (e.g., chemically etched) on or associated with a first substrate assembly 312 of the first chip 300 (e.g., a first actuator wafer). The metallization layer, the qubit component 306 (partially), and the ground plane 310 may be formed of a desired conductive material, such as a desired superconducting material. The first substrate assembly 312 may be made of a desired silicon-based material. The ground plane pouch 308 may have desired dimensions (e.g., length, width, and / or depth), spanning an area on the order of micrometers, larger than the size of the qubit assembly 306, and may surround the qubit assembly 306 to facilitate desired isolation of the qubit assembly 306 from other components of the qubit device. An instance portion of the first chip 300 may substantially be connected to... Figure 1 The first chip 102 and Figure 2 This portion of the first chip 200 is the same, except as described and modified herein, including, for example, that portion of the first chip 300 may include a SQUID component (e.g., a SQUID circuit) and may preferably enable tuning (e.g., flux tuning) of the qubit device's qubits (e.g., qubit component 306).

[0058] The qubit assembly 306 may include a capacitor assembly 314 (e.g., a qubit capacitor) that may include or be associated with capacitor paddle assemblies 316 and 318, which may have desired dimensions (e.g., length, width, and height). The capacitor paddle assemblies 316 and 318 may be separated from each other, with a desired amount of space between them (e.g., on the micrometer scale). The qubit assembly 306 may also include a Josephson junction circuit that may include a SQUID assembly (S) 320 (e.g., a SQUID loop), wherein the SQUID assembly 320 may include at least two Josephson junction assemblies, including Josephson junction assembly (JJ) 322 and Josephson junction assembly 324, and wherein the ends (e.g., corresponding terminals) of the SQUID assembly 320 may be correspondingly associated with (e.g., electrically connected thereto) the capacitor paddle assemblies 316 and 318. Traditionally, Josephson junction circuits including SQUID loops can be located (e.g., positioned) in the central region of the capacitor paddles of a qubit capacitor (e.g., the SQUID loop can be located halfway along the length of these capacitor paddles). In some embodiments, the disclosed subject matter (e.g., employing a device forming assembly) can be formed to include a Josephson junction circuit including a SQUID component 320, which is desirablely offset from the center of capacitor paddle components 316 and 318 by a defined distance (d), such that the Josephson junction circuit including the SQUID component 320 can be positioned (e.g., located) on one side of the capacitor paddle components 316 and 318 at or near the ends of the capacitor paddle components 316 and 318, according to defined qubit device forming parameters. According to the defined qubit device formation criteria, the disclosed subject matter can be desirablely positioned further away from the center of qubit component 314 and other components of qubit component 306 by offsetting the Josephson junction circuit, including SQUID component 320, from the center of qubit component 306 (e.g., qubit center) and the center of capacitor paddle components 316 and 318 by a desired distance, and along the length of capacitor paddle components 316 and 318.

[0059] The first chip 300 may further include an embedded ground plane 326, which may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the first substrate assembly 312, wherein the embedded ground plane 326 may be formed of a desired conductive material, such as a desired superconducting material. The embedded ground plane 326 may be a surface (e.g., an embedded surface) of a qubit chip assembly or a qubit chip package of a qubit device. A qubit assembly (including qubit assembly 306 and a ground plane 310 formed by a metallization layer) may be located on the opposite surface of the qubit chip assembly or the qubit chip package. A structural material 328 (e.g., a qubit chip structural material) that may include the same or similar material as the first substrate assembly 312 may be located between the embedded ground plane 326 and the qubit assembly 306, the ground plane pouch 308, and the ground plane 310. Therefore, the embedded ground plane 326 may be located (e.g., embedded) between the structural material 328 and the first substrate assembly 312.

[0060] In some embodiments, the disclosed subject matter (e.g., using a device forming component) may form a cutout portion 330 in an embedded ground plane 326, wherein the cutout portion 330 may have desired dimensions (e.g., length and width) according to defined qubit device forming criteria. In some embodiments, the disclosed subject matter (e.g., using a device forming component) may form the cutout portion 330 to have a desired length that may be greater than approximately 200 μm, according to defined qubit device forming criteria. When forming the cutout portion 330, the disclosed subject matter (e.g., using a device forming component) may desirablely offset the cutout portion 330 relative to the position of the qubit component 306, and particularly relative to the position of the capacitor component 314, by a desired distance, such that the cutout portion 330 can be positioned above (e.g., centered or substantially centered thereon) the offset Josephson junction circuit (including the SQUID component 320). For example, the disclosed subject matter can offset the position of the cutout portion 330 in the embedded ground plane 326 and can offset the position of the Josephson junction circuit, including the SQUID component 320, relative to the position of the qubit component 306 (e.g., relative to the central region of the qubit component 306), and particularly relative to the position of the capacitor component 314, such that the exposure of the capacitor component 314, the capacitor paddle components 316 and 318, and / or other components of the qubit component 306 to the cutout portion 330 and the first substrate component 312 (e.g., the first operator wafer) can be desirously reduced or minimized. This can reduce or minimize the amount of energy leaking from the qubit component 306 to the first substrate component 312 and / or can reduce or minimize the interaction between the qubit component 306 and another(s) qubit component(s) of the qubit device (e.g., a multi-qubit device). Figure 3 Crosstalk between qubit components (not shown in the diagram). For example, the remainder of the embedded ground plane 326 may be positioned over and / or cover a desired portion (e.g., a majority) of the capacitor assembly 314, including the desired portions (e.g., a majority) of the capacitor paddle assemblies 316 and 318. This may desirablely reduce or minimize the amount of energy leaking from the qubit assembly 306 to the first substrate assembly 312 and / or reduce or minimize crosstalk between the qubit assembly 306 and one or more other qubit components of the qubit device. Thus, qubit operator coupling may be desirablely suppressed (e.g., reduced or minimized). Moreover, crosstalk between qubit components (e.g., qubit assembly 306 and adjacent qubit components) may be ideally suppressed (e.g., reduced or minimized) to substantially the same level as when there is no cutout portion (e.g., when a continuous embedded ground plane is present). In some embodiments, the cutout portion 330 formed in the embedded ground plane 326 may be offset with respect to the Josephson junction circuit (e.g., relative to the Josephson junction circuit), including being offset with respect to the SQUID component 320, such that a portion of the cutout portion 330 on one side (e.g., the edge) of the cutout portion 330 can be positioned in the Josephson junction circuit (e.g., the SQUID component 320), wherein another portion (e.g., the relatively larger portion) of the cutout portion 330 is located on the ground plane pouch 308 adjacent to the qubit component 306.

[0061] In some embodiments, a coil assembly 332 (e.g., a flux coil) can be utilized to facilitate tuning the frequency of the qubit assembly 306. The coil assembly 332 can generate and emit a desired amount of magnetic flux 334. This magnetic flux 334 can be applied to the Josephson junction circuit (including the SQUID assembly 320) via flux access obtained through a cutout 330 formed in the embedded ground plane 326. For example, the magnetic flux 334 can pass through (e.g., penetrate) the first substrate assembly 312, the cutout 330 formed in the embedded ground plane 326, and the structural material 328 between the embedded ground plane 326 and the ground plane 310, and thereby be applied to the Josephson junction circuit, including the SQUID assembly 320. The frequency of the qubit assembly 306 can be desired (e.g., suitably or optimally) at least partially based on the application of the magnetic flux 334 to the Josephson junction circuit (including the SQUID assembly 320) for tuning or adjustment.

[0062] See Figure 4 (as well as Figure 1 and 3 ), Figure 4An illustration depicts a top view 400 (e.g., a top cross-sectional view) of an example portion of a first chip 300 (e.g., a qubit chip) according to various aspects and embodiments of the disclosed subject matter, wherein flux coils can be placed over an offset cutout portion in the embedded ground plane of the qubit chip to facilitate flux tuning of the qubit assembly. For reasons of simplicity and clarity, Figure 4 Only some components and features of the qubit chip and qubit assembly are shown in the image.

[0063] In some embodiments, the coil assembly 332 (e.g., an external coil assembly) may include a flux coil 402 centered above a cutout 330 formed in an embedded ground plane 326. For example, the flux coil 402 may be a concentric flux coil concentric with the cutout 330 formed in the embedded ground plane 326, wherein the coil assembly 332 can generate a desired magnetic flux 334 and apply that magnetic flux 334 to the SQUID assembly 320 (e.g., a SQUID loop). By employing the flux coil 402, which is concentric with the cutout 330 formed in the embedded ground plane 326 and positioned above the SQUID assembly 320 (e.g., an offset SQUID loop), the flux coil 402 can generate a desired (e.g., enhanced, optimal, or maximum) mutual inductance with the SQUID assembly 320.

[0064] See Figure 5 , Figure 5 Illustrations of an example, non-limiting device 500 are shown based on various aspects and embodiments of the disclosed subject matter. This device may include an offset Josephson junction circuit, an offset embedded ground plane cutout, and an interpolator ground plane cutout, which may combine with the frequency enhancement of one or more flux-tunable qubits of device 500 from the mutual inductance of the magnetic field generated by the coil assembly and facilitate ideal tuning of the frequency of one or more flux-tunable qubits of device 500. Device 500 may include a system of different components and circuitry that may be arranged to perform one or more desired functions. In some embodiments, device 500 may be or may include a qubit device (e.g., a frequency-tunable qubit device). Device 500 may be substantially the same as device 100 (e.g., may be configured to be substantially the same as device 100), except as described and modified herein (e.g., to include an interpolator ground plane cutout).

[0065] The device 500 may include a first chip 502 (e.g., a qubit chip) and a second chip 504 (e.g., an interpolator chip) that can be arranged relative to each other to form a multilayer flip-chip package. The second chip 504 may be flipped (e.g., inverted) such that its top surface (on which different components and circuitry are formed) faces and is relatively close to the top surface of the first chip 502, on which different other components and circuitry can be formed. The device 500 may include a first substrate assembly 506 (also referred to herein as a first actuator wafer) that can be associated with the first chip 502, and a second substrate assembly 508 (also referred to herein as a second actuator wafer) that can be associated with the second chip 504. The first chip 502 may include an embedded ground plane 510 that may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the first substrate assembly 506. A metallization layer 512 (e.g., qubit metallization) may be formed or deposited on the outer or top surface of the first chip 502, wherein the metallization layer 512 may include a conductive material, such as a desired superconducting material. The metallization layer 512 can be processed (e.g., chemically etched) to form a set of qubit components, including, for example, qubit components 514 and 516, and a ground plane 518 (e.g., a qubit ground plane). A first set of TSVs including TSVs 520 and 522 can be formed in the first chip 502. For example, the first set of TSVs (e.g., 520, 522) can be formed in a structural material (e.g., a qubit chip structural material) of the first chip 502, wherein the structural material can be located between the embedded ground plane 510 and the ground plane 518 and the qubits 514 and 516, wherein a portion of the structural material retained after the formation of the TSVs (e.g., 520, 522) can surround the TSVs and define the shape and size of the TSVs, and wherein the TSVs can have desired dimensions (e.g., width and / or height). According to various embodiments, the structural material can be or can include a material that is the same as or similar to the substrate material of the first substrate component 506.

[0066] Further relating to the second chip 504, the second chip 504 may include an embedded ground plane 524, which may be associated with (e.g., adjacent to or attached to) and / or formed thereon with the second substrate assembly 508. A ground plane 526 (e.g., an interposer ground plane) may be formed or deposited on the outer or top surface of the second chip 504, wherein the ground plane 526 may include a conductive material, such as, for example, a desired superconducting material. A second set of TSVs, including TSVs 528 and TSV 530, may be formed in the second chip 504. For example, the second set of TSVs (e.g., 528, 530) may be formed in the structural material interposer chip structural material of the second chip 504, wherein such structural material may be located between the embedded ground plane 524 and the ground plane 526, wherein a portion of such structural material remaining after the formation of the TSVs (e.g., 528, 530) may surround and define the shape and size of the TSVs, and wherein the TSVs may have desired dimensions (e.g., width and / or height). According to different embodiments, the structural material of the second chip 504 may be or may include the same or similar material as the substrate material of the second substrate assembly 508.

[0067] In some embodiments, a set of raised engagement components may be formed between the ground plane 518 of the first chip 502 and the ground plane 526 of the second chip 504 near the locations of the respective TSVs of the first group of TSVs (e.g., TSV520, TSV522 and / or other TSVs) and the second group of TSVs (e.g., TSV528, TSV530 and / or other TSVs). This set of raised engagement components includes, for example, raised engagement component 532 and raised engagement component 534. This set of raised engagement components (e.g., 532, 534) may connect or facilitate connections between components on the first chip 502 and components on the second chip 504.

[0068] In some embodiments, the disclosed subject matter may be desirablely (e.g., appropriately, suitably, or optimally) formed and structured cutout portions (e.g., offset cutout portions), such as cutout portion 536, in the embedded ground plane 510 and other features of the device 500 to enable desirable tuning of the qubit components of the device 500 (e.g., qubit component 514) while mitigating (e.g., reducing or minimizing) undesirable transmission of electromagnetic energy from the qubits to the operator wafer and undesirable crosstalk between qubits. The disclosed subject matter can also offset the Josephson junction circuits (e.g., SQUID components (e.g., SQUID loops)) of these qubit components (e.g., 514), which, together with the cutout portion (e.g., 536) positioned above the offset Josephson junction circuit, can enable these qubit components (e.g., 514) of the device 500 to be desiredly tuned while mitigating (e.g., reducing or minimizing) undesirable transmission of electromagnetic energy from the qubit to the operator chip and undesirable crosstalk between qubits, as described more fully herein.

[0069] In some embodiments, in addition to including the offset Josephson junction circuit (e.g., the offset SQUID loop) and the offset embedded ground plane cutout portion (e.g., cutout portion 536) formed in the embedded ground plane 510 on the first chip 502 (e.g., the qubit chip), an interpolator ground plane cutout portion 538 may also be included. This interpolator ground plane cutout portion may be formed in the ground plane 526 (e.g., the interpolator ground plane) of the second chip 504 (e.g., the interpolator chip), close to the offset Josephson junction circuit (e.g., the offset SQUID loop) of the qubit assembly 514. The coil assembly 540 can apply a desired magnetic flux to the offset SQUID component of the qubit assembly 514 through the cutout portion 536 formed in the embedded ground plane 510, wherein the magnetic flux can also pass (e.g., permeate) between TSV520 and TSV522 through the first substrate assembly 506 and the structural material (e.g., the qubit chip structural material). In some embodiments, the interpolator ground plane cutout portion 538 may be offset by a defined distance relative to the center (e.g., qubit center) and / or the associated offset SQUID component of the qubit assembly 514 in the same or similar manner as the cutout portion 536 formed in the embedded ground plane 510 on the first chip 502. Additional cutout portions formed in the ground plane 526 (e.g., the interpolator ground plane cutout portion 538) may enhance (e.g., increase or decrease) the amount of mutual inductance generated by the magnetic field produced by the coil assembly 540, which may further enhance and make the process of tuning the frequency of one or more flux-tunable qubits of the tuning device 500 more efficient.

[0070] It should be recognized and understood that although only two cutout portions are described in device 500, including cutout portion 536 formed in embedded ground plane 510 and cutout portion 538 formed in ground plane 526, the subject matter disclosed is not limited thereto, and according to various embodiments, device 500 may include a desired number of cutout portions formed in embedded ground plane 510 and a desired number of cutout portions formed in ground plane 526, for example, corresponding to and associated with corresponding qubit components formed on device 500.

[0071] Further information regarding qubits and related capacitors, in addition to what is discussed here... Figure 1-5 Beyond the qubits and related capacitor designs described herein, the disclosed topics can be presented in a manner similar to those discussed here. Figure 1-5 The similar approach described relates to various other types of qubits and associated capacitors, employing and implementing offset Josephson junction circuits and offset ground plane cutouts. For this purpose, see briefly... Figure 6 , Figure 6 Illustrations show an example X-mon qubit assembly 600 according to different aspects and embodiments of the disclosed subject matter. This qubit assembly may include an offset Josephson junction circuit and may be associated with an offset ground plane cutout portion to facilitate desired tuning of the qubits of the qubit device. The X-mon qubit assembly 600 may include a cross-shaped qubit capacitor assembly 602, which may include a first electrode assembly 604 and a second electrode assembly 606, the first electrode assembly being configured in a cross-like form.

[0072] The X-mon qubit assembly 600 may include a Josephson junction circuit offset by a desired distance from the center point of the X-mon qubit assembly 600 toward one end and / or near one of the electrode assemblies (e.g., the first electrode assembly 604). In some embodiments, the Josephson junction circuit may include a SQUID assembly 608 (e.g., a SQUID loop) (as depicted), which may include at least two Josephson junction assemblies, including Josephson junction assemblies 610 and 612. In other embodiments, other types of Josephson junction circuits may be used with the X-mon qubit assembly 600. In some embodiments, one of the electrode assemblies (e.g., the second electrode assembly 606) may be part of the ground plane of the qubit device (e.g., a qubit ground plane). The first electrode assembly 604, the second electrode assembly 606, and the Josephson junction circuit (e.g., the SQUID assembly 608) may be formed of a desired conductive material (e.g., a desired superconducting material).

[0073] In the same or similar manner as described more fully herein, a cutout 614 may be formed in the embedded ground plane 616 of the qubit chip in the qubit device. The cutout 614 may be formed in the embedded ground plane such that it can be offset from the center point of the qubit by a desired distance (e.g., from the center or intersection point of the cross-shaped qubit capacitor assembly 602), and / or from the center point of the Josephson junction circuit (e.g., SQUID assembly 608), wherein at least a portion of the cutout 614 may be positioned over the Josephson junction circuit.

[0074] Briefly turn Figure 7 , Figure 7 An illustration depicts an exemplary transport sub-qubit assembly 700 according to different aspects and embodiments of the disclosed subject matter. This qubit assembly may include an offset Josephson junction circuit and may be associated with an offset ground plane cutout portion to facilitate desired tuning of the qubits of the qubit device. The transport sub-qubit assembly 700 may include a capacitor assembly 702, which may include a first capacitor island assembly 704 and a second capacitor island assembly 706 that may be separated from each other by a desired gap 708 (e.g., space). In some embodiments, the first capacitor island assembly 704 and the second capacitor island assembly 706 may be shaped and arranged relative to each other such that the gap 708 may behave in a snake-like manner.

[0075] The transport qubit assembly 700 may include a Josephson junction circuit that can be offset by a desired distance from the center point of the transport qubit assembly 700 toward and / or near the end of the capacitor assembly 702 (e.g., near the corresponding or associated ends of the first capacitor island assembly 704 and the second capacitor island assembly 706). In some embodiments, the Josephson junction circuit may include a SQUID assembly 710 (e.g., a SQUID loop) (as depicted), which may include at least two Josephson junction assemblies, including Josephson junction assemblies 712 and 714. In other embodiments, other types of Josephson junction circuits may be used with the transport qubit assembly 700. The first capacitor island assembly 704, the second capacitor island assembly 706, and the Josephson junction circuit (e.g., SQUID assembly 710) may be formed of a desired conductive material (e.g., a desired superconducting material).

[0076] In the same or similar manner as described more fully herein, a cutout 716 may be formed in the embedded ground plane 718 of the qubit chip in the qubit device. The cutout 716 may be formed in the embedded ground plane 718 such that it may be offset by a desired distance from the center point of the qubit (e.g., the center point of the transport qubit assembly 700), and / or may be offset by a desired distance from the center point of the Josephson junction circuit (e.g., the SQUID assembly 710), wherein at least a portion of the cutout 716 may be positioned over the Josephson junction circuit.

[0077] The disclosed subject matter, by desirablely offsetting the Josephson junction circuit, creating one or more cutouts in the embedded ground plane of the qubit chip, offsetting the one or more cutouts in the embedded ground plane of the qubit chip, creating cutouts in the interpolator ground plane of the interpolator chip, and / or offsetting the cutouts in the interpolator ground plane of the interpolator chip, enables the desired mitigation or reduction of frequency conflicts in multi-qubit devices by enabling tuning of qubit frequencies after fabrication of a multi-layer qubit device using magnetic fields and / or laser tuning. The disclosed subject matter can also reduce the challenges that may be faced during the fabrication of multi-qubit devices regarding achieving precise target qubit frequencies in multi-qubit devices. The disclosed subject matter can also be added to the knowledge base of device structures for mitigating crosstalk and chip-mode coupling. The disclosed subject matter can also significantly and faster facilitate (e.g., enable) the production of larger multi-qubit devices.

[0078] Brief Reference Figure 8 , Figure 8 An example graph 800 illustrating the operator coupling dependency relative to a ground plane cutoff offset, based on various aspects and embodiments of the disclosed subject matter, is presented. Example graph 800 includes graph 802, which may represent the transmission S measured in decibels (dB) at 2.5 GHz (e.g., the lowest frequency chip mode of a qubit device). 21 (For example, from a qubit to an operator chip), as a function of the ground plane cutoff offset in μm. Example graph 800 may also include graph 804, which presents the percentage of qubit electric field participation as a function of the ground plane cutoff offset in μm. In graphs 802 and 804, a 0-cutoff offset can correspond to the original case where the ground plane cutoff portion, coil, and qubit ground plane pouch are all concentric. As can be observed in graphs 802 and 804, a ground plane cutoff portion offset of 600 μm x 600 μm can desirably reduce the amount of coupling between the qubit and the operator chip, and can desirably reduce the percentage of qubit electric field participation in the operator chip.

[0079] Figure 9 A diagram illustrating example graph 900, representing different aspects and embodiments of the disclosed subject matter, can demonstrate the dependence of magnetic fields and qubit manipulator transmission. Example graph 900 may include graph 902, which may present transmission speed S measured in decibels (dB) at 2.5 GHz (e.g., in the lowest frequency chip mode of the qubit device). 21 (For example, from a qubit to an operator chip), as a function of the ground plane cutoff offset in μm. Example graph 900 may also include graph 904, which presents the mutual inductance (Ф0 / mA) based on the ground plane cutoff x displacement position (μm). Regarding the data presented in graphs 902 and 904, this data is based on a coil concentric with the center of the ground plane cutoff.

[0080] As can be observed in graphs 902 and 904, maximum mutual inductance may occur when the coil, the cut-out portion, and the SQUID are all centered at an offset of approximately 250 μm from the ground plane cut-out portion. As can also be observed in graphs 902 and 904, for a 500 μm offset from the ground plane cut-out portion, an attenuation of approximately 34 dB (e.g., SQUID) can be obtained using sufficient flux coupling (e.g., 0.22Ф0 / mA). 21 (50x variation of amplitude). As can be further observed in graphs 902 and 904, an attenuation of approximately 56 dB (S) can be obtained even when the qubit device is largely covered by an embedded ground plane (e.g., a 600 μm cutout in the ground plane). 21 (The change is 630x), and there can still be a mutual inductance of about 0.1Ф0 / mA.

[0081] Brief reference Figure 10 , Figure 10 A graph 1000 illustrating the frequency dependence of an operator coupled to a ground plane cutout offset according to various aspects and embodiments of the disclosed subject matter is shown. Graph 1000 displays the transmission S in dB. 21 (e.g., from qubit to operator chip), as a function of frequency (f) in GHz, where there is no offset of the ground plane cutout portion (as indicated by reference numeral 1002) and has an offset of 500 μm of the ground plane cutout portion (as indicated by reference numeral 1004). As can be observed from graph 1000, including the corresponding data points (e.g., corresponding graph lines) indicated at reference numerals 1002 and 1004, the suppressed coupling to the operator chip of the qubit device can preferably be broadband, with an offset of the ground plane cutout portion, including at the operator mode frequency.

[0082] Brief Turn Figure 11 and Figure 12 , Figure 11 An example graph 1100 illustrating qubit crosstalk versus ground plane cutoff offset based on different aspects and embodiments of the disclosed subject matter is shown, and Figure 12 Figure 1200 shows an example curve in dB of the transmission S as a function of frequency (f) in GHz. 21 (For example, a diagram illustrating qubit-to-qubit crosstalk via an operator chip mode). Graph 1100 can represent the transmission S. 21 (e.g., qubit-to-qubit crosstalk via operator chip mode), in dB, as a function of the cutoff offset (in μm) of the ground plane cutoff portion in the embedded ground plane of the qubit device, relative to crosstalk at the operator mode frequency of 2.5 GHz, and having a qubit-to-qubit distance of 2 mm (as indicated by the data point at reference numeral 1102). When there is a closed (e.g., no cutoff portion) embedded ground plane in the qubit device, the transmission S 21 Indicated at reference number 1104.

[0083] Graph 1200 can show the transmission S as a function of frequency. 21 The embedded ground plane of the qubit device has an offset without a ground plane cutout (as indicated by the data point at reference numeral 1202), an offset with a ground plane cutout (as indicated by the data point at reference numeral 1204), and a closed (e.g., without a cutout therein) embedded ground plane (as indicated by the data point at reference numeral 1206). As can be observed in graphs 1100 and 1200, in the case of an offset of the ground plane cutout in the embedded ground plane of the qubit device (e.g., for |cutout offset|>500μm), crosstalk between qubits (e.g., adjacent qubits) can be desirablely suppressed, and the amount of crosstalk between qubits with cutout offsets in the embedded ground plane can be at substantially the same level as the amount of crosstalk between qubits when there is no cutout in the embedded ground plane of the qubit device (e.g., when these qubits can be turned off from the operator wafer of the qubit device). Therefore, the curve at reference numeral 1204 (e.g., for cutout offset) substantially overlaps the curve at reference numeral 1206 (for enclosing the embedded ground plane).

[0084] Figure 13A block diagram of an example system 1300, illustrating different aspects and embodiments of the disclosed subject matter, is depicted. This example system can be used to create, form, or design a qubit device including offset Josephson junction circuitry, offset embedded ground plane cutout portions, and / or offset interpolator ground plane cutout portions. System 1300 may include a device forming assembly 1302, a processor assembly 1304, and a data storage 1306. The device forming assembly 1302 can be used to create, form, or design different components of or associated with the qubit device 1308, and the frequencies of the qubit components of the qubit device 1308 can be tuned (e.g., by laser tuning or flux tuning), as described more fully herein. For example, the device forming assembly 1302 can be used to create, form, or design different components that can be formed or located on a first chip 1310 (e.g., a qubit chip) and different components that can be formed or located on a second chip 1312 (e.g., an interpolator chip). These different components may include, for example, a qubit component 1314, a coupler component 1316 (which may include or be associated with a capacitor component), a Josephson junction (JJ) circuit 1318 (e.g., an offset Josephson junction circuit), which in some embodiments may include a SQUID component (SQUID COMP.) 1320 (e.g., a SQUID loop), an embedded ground plane 1322, an interpolator ground plane 1324, multiple cutouts 1326 (e.g., multiple offset cutouts in the embedded ground plane and / or the interpolator ground plane), a TSV 1328, a bump engagement component 1330, and associated circuitry 1332. The device forming assembly 1302 may also employ and / or control the operation of the laser device or coil assembly to tune the frequency of the qubit component 1314 of the qubit device 1308 (e.g., after manufacturing the qubit device 1308).

[0085] As part of the qubit device 1308 or to facilitate the creation, formation, or design of various components associated with the qubit device 1308, the device forming assembly 1302 may form or process substrate assemblies, such as a first substrate assembly that may be part of a first chip 1310 and a second substrate assembly that may be part of a second chip 1312. Furthermore, as part of the qubit device 1308 or to facilitate the creation, formation, or design of the qubit device or various components associated with the qubit device, the device forming assembly 1302 may also form, deposit, or process one or more metallization layers on the first and second substrate assemblies, wherein these metallization layers may be formed of one or more desired metals or conductive materials, which may be or include one or more desired superconducting materials (e.g., niobium-type superconductors), and wherein the metallization layers may have a desired thickness or height. In some embodiments, the device forming assembly 1302 may remove (e.g., selectively remove) corresponding portions of the metallization layers to facilitate the creation or formation of corresponding components or circuitry of the qubit device 1308. For example, the device forming component 1302 may employ and / or control various processes, including microfabrication processes, nanofabrication processes, mask or photoresist processes, photolithography processes, chemical etching processes, other etching or removal processes, or other desired processes, to desirablely process the metallization layer and remove corresponding portions of the metallization layer in order to facilitate the generation or formation of corresponding components or circuits of the qubit device 1308.

[0086] Processor component 1304 may work in conjunction with other components (e.g., device forming component 1302, data storage 1306, or another component) to facilitate the execution of various functions of system 1300. Processor component 1304 may employ one or more processors, microprocessors, or controllers that can process data, such as information related to: qubit devices, qubit components, coupler components, SQUID loops, Josephson junction components, capacitor components, inductor components, embedded ground planes, interpolation ground planes, cutouts in embedded ground planes and / or interpolation ground planes, TSVs, bump junction components, circuit design standards, circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information, to facilitate the operation of system 1300, as more fully disclosed herein, and to control the data flow between system 1300 and other components associated with (e.g., connected to system 1300) system 1300 (e.g., computer components, computers, laptop computers, other computing or communication devices, or network devices).

[0087] Data storage 1306 may store data structures (e.g., user data, metadata), code structures (e.g., modules, objects, hashes, classes, programs) or instructions, information relating to qubit devices, qubit components, coupler components, SQUID loops, Josephson junction components, capacitor components, inductor components, embedded ground planes, interpolation ground planes, cutouts in embedded ground planes and / or interpolation ground planes, TSVs, bump junction components, circuit design standards, circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information to facilitate control of operations associated with system 1300. In one aspect, processor component 1304 may be functionally coupled (e.g., via a memory bus) to data storage 1306 to store and retrieve information intended to operate and / or at least partially contribute to functional aspects of device forming component 1302, data storage 1306, or other components and / or system 1300, and substantially any other operational aspect.

[0088] It should be understood that the data storage 1306 described herein may include volatile memory and / or non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which may serve as external cache memory. By way of example, and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory intent of the disclosed aspects includes, but is not limited to, these and other suitable types of memory.

[0089] These systems and / or devices have been (or will be) described herein with respect to the interaction between several components. It should be understood that such systems and components may include those components or sub-components specified herein, some of the specified components or sub-components, and / or additional components. Sub-components may also be implemented as components communicatively coupled to other components, rather than being included within a parent component. Furthermore, one or more components and / or sub-components may be combined into a single component that provides aggregate functionality. These components may also interact with one or more other components, which are not specifically described herein for the sake of brevity but are known to those skilled in the art.

[0090] Figure 14Flowcharts of an example, non-limiting method 1400 are shown based on different aspects and embodiments of the disclosed subject matter. This method can form an offset circuit system and a ground plane cutout to facilitate tuning the frequency of one or more qubits in a qubit device. For example, method 1400 can be performed by a system (e.g., a computer system) including or operatively coupled to device forming components, processor components, and memory. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted or may be omitted.

[0091] At 1402, a qubit assembly including a Josephson junction circuit can be formed on the substrate assembly, wherein the Josephson junction circuit can be offset from the center point of the qubit assembly by a defined distance. The device forming assembly can form a qubit assembly including a Josephson junction circuit on the substrate assembly (e.g., the substrate assembly on the qubit chip), wherein the Josephson junction circuit can be offset from the center point of the qubit assembly by a defined distance.

[0092] At 1404, a ground plane can be formed, wherein the ground plane may be located on the surface of a qubit chip package including qubit components, and wherein a cutout portion may be formed in and defined by the remainder of the ground plane, and may be positioned over the Josephson junction circuit. A device forming assembly can form a ground plane (e.g., an embedded ground plane on the qubit chip), wherein the ground plane may be located on the surface of a qubit chip package including qubit components, and wherein a cutout portion (e.g., an offset cutout portion) may be formed in and defined by the remainder of the ground plane, and may be positioned over the Josephson junction circuit.

[0093] Figure 15 A flowchart of another example, non-limiting method 1500, is depicted based on different aspects and embodiments of the disclosed subject matter. This method may form an offset circuit system and a ground plane cutout to facilitate tuning the frequency of one or more qubits of a qubit device. Method 1500 may be performed by a system (e.g., a computer system) including, for example, device-forming components, processor components, and memory operatively coupled to them. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted.

[0094] At 1502, an embedded ground plane may be formed on the first substrate assembly, wherein the embedded ground plane may be located on a first surface of a qubit chip package that may be formed on the first substrate assembly. A device forming assembly may form the embedded ground plane on the first substrate assembly (e.g., the first substrate of the qubit chip or an operator wafer), wherein the embedded ground plane may be located on a first surface of a qubit chip package that may be formed on the first substrate assembly.

[0095] In 1504, a qubit ground plane can be formed on the second surface of the qubit chip package. Device forming components can form the qubit ground plane on the second surface (e.g., a metallization layer) of the qubit chip package.

[0096] At 1506, qubit components can be formed on the second surface of the qubit chip package. Device forming components can be formed on the second surface (e.g., a metallization layer) of the qubit chip package.

[0097] At 1508, in conjunction with forming the qubit component, the Josephson junction circuit associated with the qubit component can be offset from the center point of the qubit component by a defined distance. In conjunction with forming the qubit component, the device forming component can offset the Josephson junction circuit associated with the qubit component from the center point of the qubit component by a defined distance. In some embodiments, the Josephson junction circuit may include a SQUID loop, which may include two or more Josephson junction components.

[0098] At 1510, an interpolator chip package including an interpolator ground plane may be formed on a second substrate assembly. A device forming assembly may form an interpolator chip package including an interpolator ground plane on the second substrate assembly (e.g., a second substrate of the interpolator chip or an operator wafer).

[0099] At 1512, TSVs can be formed in both qubit chip packages and interpolator chip packages. Device forming components can form TSVs at desired locations in both qubit chip packages (e.g., qubit chip assemblies) and interpolator chip packages (e.g., interpolator chip assemblies), as described more fully herein.

[0100] At 1514, a bump bonding assembly can be formed to connect the qubit chip package to the interpolator chip package. The device forming assembly can form a bump bonding assembly to connect the qubit chip package to the interpolator chip package (e.g., connecting a component of the qubit chip package to a component of the interpolator chip package).

[0101] At 1516, a capacitor assembly can be formed, wherein the capacitor assembly can be associated with the Josephson junction circuit and can be part of the qubit assembly. The device forming assembly can form a capacitor assembly, wherein the capacitor assembly can be associated with the Josephson junction circuit (e.g., an offset Josephson junction circuit) and can be part of the qubit assembly.

[0102] In 1518, an offset cutout portion may be formed in the embedded ground plane, wherein the offset cutout portion may be defined by the remainder of the embedded ground plane and may be positioned above the Josephson junction circuit, and wherein the remainder of the embedded ground plane may be positioned above a portion (e.g., a majority) of the capacitor assembly. The device forming assembly may form an offset cutout portion in the embedded ground plane, wherein the offset cutout portion may be defined by the remainder of the embedded ground plane and may be positioned above the Josephson junction circuit, and wherein the remainder of the embedded ground plane may be positioned above a portion (e.g., a majority) of the capacitor assembly. In some embodiments, the device forming assembly may form an offset cutout portion in the embedded ground plane such that the cutout portion may be offset by a desired distance relative to the center point of the qubit assembly and / or relative to the center point of the Josephson junction circuit, as described more fully herein.

[0103] Figure 16 A flowchart of an example, non-limiting method 1600, illustrating a qubit device capable of tuning the frequency of its qubit components according to different aspects and embodiments of the disclosed subject matter, is shown, wherein the qubit device includes an offset cutout portion in an embedded ground plane and / or the qubit device includes an offset Josephson junction circuit. Method 1600 can be performed by a system (e.g., a computer system) including or operatively coupled to device forming components, processor components, and memory. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted.

[0104] At 1602, a determination can be made regarding whether the qubit components of the qubit device are laser-tunable or flux-tunable, wherein the qubit device includes an offset cutout portion in an embedded ground plane and / or the qubit device includes an offset Josephson junction circuit. At 1604, if it is determined that the qubit component is laser-tunable, an optical signal can be applied to the offset Josephson junction circuit through the offset cutout portion in the embedded ground plane of the qubit device. At 1606, the frequency of the qubit component can be adjusted (e.g., tuned) at least in part based on the application of an optical signal to the offset Josephson junction circuit. If it is determined that the qubit component is laser-tunable, then the device forming components can employ a laser device to generate an optical signal of the desired wavelength (e.g., a laser or an optical signal including a laser or optical pulse) and apply the optical signal to the offset Josephson junction circuit through the offset cutout portion in the embedded ground plane of the qubit device. The apparatus for employing or controlling the laser device can form components that adjust or tune the frequency of the qubit component, at least in part, based on applying the optical signal to the offset Josephson junction circuit.

[0105] Referring again to Figure 1602, if it is determined at 1602 that the qubit component is flux-tunable, then at 1608, magnetic flux can be applied to the offset Josephson junction circuit (e.g., an offset SQUID loop) through an offset cutout portion in the embedded ground plane of the qubit device. At 1610, the frequency of the qubit component can be adjusted (e.g., tuned) at least in part based on the application of magnetic flux to the offset Josephson junction circuit. If it is determined that the qubit component is flux-tunable, then the device forming assembly can employ a coil assembly (e.g., a flux coil) to generate the desired magnetic flux and apply that magnetic flux to the offset Josephson junction circuit (e.g., an offset SQUID loop) through an offset cutout portion in the embedded ground plane of the qubit device. The device forming assembly employing or controlling the coil assembly can adjust or tune the frequency of the qubit component at least in part based on the application of magnetic flux to the offset Josephson junction circuit. It should be recognized and understood that, in some embodiments, laser tuning and flux tuning can be performed on the Josephson junction circuit if and as desired (e.g., laser tuning and flux tuning can be performed on the Josephson junction component of the SQUID loop).

[0106] For the sake of simplicity, these methods and / or computer-implemented methods are depicted and described as a series of actions. It should be understood and appreciated that the disclosed subject matter is not limited to the actions and / or the order of the actions shown; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented and described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented methods according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that computer-implemented methods may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented methods disclosed below and throughout this specification can be stored on an article of art to facilitate the transfer and assignment of such computer-implemented methods to a computer. As used herein, the term "article of art" is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0107] In order to provide context for the various aspects of the disclosed subject, Figure 17 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 17 A block diagram illustrating an example, non-limiting operating environment that may facilitate one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted. References Figure 17A suitable operating environment 1700 for implementing various aspects of this disclosure may also include a computer 1712. The computer 1712 may further include a processing unit 1714, system memory 1716, and a system bus 1718. The system bus 1718 couples system components (including, but not limited to, system memory 1716) to the processing unit 1714. The processing unit 1714 may be any of the various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1714. The system bus 1718 may be any of several types of bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of the various available bus architectures, including (but not limited to) Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI). System memory 1716 may also include volatile memory 1720 and non-volatile memory 1722. A basic input / output system (BIOS) containing basic routines such as those for transferring information between components within computer 1712 during startup is stored in non-volatile memory 1722. By way of example and not limitation, non-volatile memory 1722 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 1720 may also include random access memory (RAM) that acts as an external cache memory. As an illustration and not a limitation, RAM can be obtained in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0108] Computer 1712 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 17Disk storage 1724 is shown. Disk storage 1724 may also include (but is not limited to) means such as disk drives, floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage 1724 may also include storage media, alone or in combination with other storage media, including but not limited to optical disc drives, such as compact disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital universal disc ROM drives (DVD-ROM). To facilitate connection between disk storage 1724 and system bus 1718, removable or non-removable interfaces, such as interface 1726, are typically used. Figure 17 Software acting as an intermediary between the user and the basic computer resources described in the suitable operating environment 1700 is also described. This software may also include, for example, an operating system 1728. The operating system 1728, which may be stored on disk storage 1724, is used to control and allocate the resources of computer 1712. System application 1730 utilizes the operating system 1728 to manage resources through program modules 1732 and program data 1734, for example, stored in system memory 1716 or on disk storage 1724. It should be understood that this disclosure can be implemented using different operating systems or combinations of operating systems. The user inputs commands or information into computer 1712 through input devices 1736. Input devices 1736 include, but are not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, gamepad, disc satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to processing unit 1714 via interface port 1738 through system bus 1718. Interface port 1738 includes, for example, a serial port, a parallel port, a gaming port, and a Universal Serial Bus (USB). Output device 1740 uses some of the same type of ports as input device 1736. Thus, for example, a USB port can be used to provide input to computer 1712 and to output information from computer 1712 to output device 1740. Output adapter 1742 is provided to illustrate that, in addition to other output devices 1740 that require special adapters, there are other output devices 1740 such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1742 includes video and sound cards that provide a method of connection between output device 1740 and system bus 1718. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1744.

[0109] Computer 1712 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computers 1744). Remote computer 1744 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other public network node, and typically may also include many or all of the elements described relative to computer 1712. For simplicity, memory storage device 1746 is described using only remote computer 1744 as an example. Remote computer 1744 is logically connected to computer 1712 via network interface 1748 and then physically connected via communication connection 1750. Network interface 1748 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and their variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1750 refers to the hardware / software used to connect network interface 1748 to system bus 1718. Although communication connection 1750 is shown inside computer 1712 for clarity, it can also be external to computer 1712. For illustrative purposes only, the hardware / software used to connect to network interface 1748 may also include internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0110] One or more embodiments may be systems, methods, apparatuses, and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of one or more embodiments. A computer-readable storage medium may be a tangible means for retaining and storing instructions for use by an instruction execution apparatus. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may include: portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), SRAM, portable CD-ROMs, digital universal disks (DVDs), memory sticks, floppy disks, mechanical encoding devices such as punch cards, or protrusions in recesses having instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0111] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device. The computer-readable program instructions used to perform operations on the disclosed subject matter may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the disclosed subject matter.

[0112] Aspects of the disclosed subject matter are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create a method for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0113] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of the disclosed subject matter. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a non-linear order. For example, depending on the functions involved, two consecutively shown blocks may be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0114] While the subject matter has been described above in the general context of computer-executable instructions running on a computer and / or a computer program product on a computer, those skilled in the art will recognize that this disclosure can also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer-implemented methods disclosed herein can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic devices, etc. The aspects shown can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the invention can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0115] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. As an illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another instance, a corresponding component may execute from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by a mechanical component operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other methods to execute software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0116] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "an" as used in the subject matter specification and figures should generally be interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an instance, example, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as superior to or better than other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0117] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "memory," "data storage," "data memory," "database," and substantially any other information storage component, as used in relation to the operation and function of a component, are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include ROM, PROM, EPROM, EEPROM, flash memory, or non-volatile RAM (e.g., FeRAM). Volatile memory may include, for example, RAM that can act as an external cache memory. By way of illustration and not limitation, RAM may be available in many forms, such as SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, DRRAM, DRDRAM, and RDRAM. Furthermore, the memory components of the systems or computer-implemented methods disclosed herein inherently include (but are not limited to) these and any other suitable types of memory.

[0118] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the use of terms such as “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings is intended to be inclusive in a manner similar to the term “including,” as “including” is interpreted when used as a transitional word in a claim. Various embodiments have been described for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A qubit system, comprising: Quantum bit chip assembly, the quantum bit chip assembly comprising: A qubit assembly fabricated on a substrate, wherein the qubit assembly includes a Josephson junction circuit offset from the center point of the qubit assembly by a defined distance; and A ground plane located on the surface of the qubit chip assembly, wherein a cutout portion is formed in the ground plane and defined by the remainder of the ground plane and positioned above the Josephson junction circuit.

2. The qubit system of claim 1, wherein, The cut-out portion of the ground plane is at least partially positioned above the Josephson junction circuit and offset from the center point of the qubit assembly.

3. The qubit system of claim 1, wherein, The cutout portion of the ground plane enables optical access of the Josephson junction circuit to the optical signal, and wherein the frequency of the qubit component is tuned based on the application of the optical signal to the Josephson junction circuit.

4. The qubit system of claim 1, wherein, The Josephson junction circuit includes a superconducting quantum interference device (SQU) loop, wherein the cutout portion of the ground plane enables magnetic flux access to the SQU loop, and wherein the frequency of the qubit assembly is tuned based on applying the magnetic flux to the SQU loop.

5. The qubit system according to claim 4, further comprising: A coil assembly concentric with the cutout portion of the ground plane, wherein the coil assembly generates the magnetic flux and applies the magnetic flux to the circuit of the superconducting quantum interference device.

6. The qubit system of claim 5, wherein, The cut-out portion of the ground plane is a first cut-out portion of a first ground plane, wherein the second ground plane is part of an interpolator chip assembly associated with the qubit chip assembly, wherein the second cut-out portion is formed in the second ground plane and located near the Josephson junction circuit, and wherein the second cut-out portion promotes an increase in mutual inductance caused by the magnetic field generated by the coil assembly.

7. The qubit system of any one of claims 1 to 5, wherein, The qubit assembly is associated with a first ground plane located on a first surface of the qubit chip assembly, wherein the ground plane located on the surface of the qubit chip assembly is a second ground plane located on a second surface of the qubit chip assembly, wherein the second ground plane is embedded in the substrate, and wherein the second ground plane is on the side of the qubit chip assembly opposite to the first ground plane.

8. The qubit system according to claim 7, further comprising: A capacitor assembly associated with a portion of the Josephson junction circuit and the qubit assembly, wherein the remaining portion of the second ground plane is positioned on at least a portion of the capacitor assembly.

9. The qubit system of claim 7, wherein, The substrate is a first substrate that provides physical support to the qubit chip assembly, wherein the qubit chip assembly includes a first set of through-holes, and wherein the system further includes: An interpolation assembly including a second set of through-holes, wherein the interpolation assembly is electrically connected to the qubit chip assembly via a set of vias; and A second substrate that provides physical support for the interpolator assembly.

10. The qubit system of claim 8, wherein, The substrate is a first substrate that provides physical support to the qubit chip assembly, wherein the qubit chip assembly includes a first set of through-holes, and wherein the system further includes: An interpolation assembly including a second set of through-holes, wherein the interpolation assembly is electrically connected to the qubit chip assembly via a set of vias; and A second substrate that provides physical support for the interpolator assembly.

11. A method for fabricating a qubit system, comprising: A qubit assembly including a Josephson junction circuit is formed on a substrate, wherein the Josephson junction circuit is offset from the center point of the qubit assembly by a defined distance; and A ground plane is formed on the surface of a qubit chip package, the qubit chip package including the qubit assembly, wherein a cutout portion is formed in the ground plane and defined by the remainder of the ground plane and positioned above the Josephson junction circuit.

12. The method of claim 11, wherein, The cutout portion of the ground plane enables access of optical signals to the Josephson junction circuit, wherein the frequency of the qubit component is adjustable based on applying the optical signal to the Josephson junction circuit.

13. The method of claim 11, further comprising: The Josephson junction circuit forms a superconducting quantum interference device (SQU) circuit, wherein the cutout portion of the ground plane enables magnetic flux access to the SQU circuit, and wherein the frequency of the qubit assembly is adjustable based on applying the magnetic flux to the SQU circuit via a coil device.

14. The method of any one of claims 11 to 13, wherein, The qubit component is associated with a first ground plane located on a first surface of the qubit chip package, wherein the ground plane located on the surface of the qubit chip package is a second ground plane located on a second surface of the qubit chip package, wherein the second ground plane is embedded in the substrate, and wherein the second surface is on the side of the qubit chip package opposite to the first surface.

15. The method of claim 14, further comprising: A capacitor assembly is formed, which is associated with the Josephson junction circuit and is part of the qubit assembly, wherein the remainder of the second ground plane is positioned on at least a portion of the capacitor assembly.

16. The method of claim 14, wherein, The substrate is a first substrate that provides support for the qubit chip package, and the method further includes: A first set of through-holes is formed in the quantum bit chip package; Forming an interpolator assembly, the interpolator assembly including a second set of through-holes and associated with a second substrate providing support to the interpolator assembly; and A set of bumps are formed to connect the interpolator assembly to the qubit chip package.

17. The method of claim 15, wherein, The substrate is a first substrate that provides support for the qubit chip package, and the method further includes: A first set of through-holes is formed in the quantum bit chip package; Forming an interpolator assembly, the interpolator assembly including a second set of through-holes and associated with a second substrate providing support to the interpolator assembly; and A set of bumps are formed to connect the interpolator assembly to the qubit chip package.

18. A qubit device, comprising: Quantum bit chip packaging includes: A qubit assembly formed on a substrate assembly, wherein the qubit assembly includes a Josephson junction assembly offset from a central region of the qubit assembly by a defined amount; and A ground plane assembly located on the surface of the qubit chip package, wherein a cutout portion is formed in the ground plane assembly and defined by the remainder of the ground plane assembly and located on the Josephson junction assembly.

19. The qubit device of claim 18, wherein the notched portion of the ground plane assembly enables access of an optical signal to the Josephson junction assembly to facilitate modulation of the frequency of the qubit assembly based on the application of the optical signal to the Josephson junction assembly.

20. The qubit apparatus of claim 18, wherein the Josephson junction assembly comprises a superconducting quantum interference device loop, and wherein, The cutout portion of the ground plane assembly enables access to the superconducting quantum interference device (SQI) circuitry to facilitate frequency modulation of the qubit assembly based on applying the magnetic flux to the SQI circuitry via the coil assembly.

21. The qubit device according to any one of claims 18 to 20, wherein the qubit component is associated with a first ground plane component located on a first surface of the qubit chip package, wherein the ground plane component located on the surface of the qubit chip package is a second ground plane component located on a second surface of the qubit chip package, wherein the second ground plane component is embedded in the substrate component, and wherein the second surface is on the side of the qubit chip package opposite to the first surface.

22. The qubit device of claim 21, wherein, The substrate assembly is a first actuator assembly providing support for the qubit chip package, wherein the qubit chip package includes a first set of through-holes, and wherein the qubit device further includes: A capacitor assembly, which is associated with the Josephson junction assembly and is part of the qubit assembly, wherein the remaining portion of the second ground plane assembly is located on at least a portion of the capacitor assembly; An interposer assembly including a second set of through-holes, wherein the interposer assembly is connected to the qubit chip package via a set of bump-engagement connectors; and A second operator component provides support for the interpolator assembly.

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