Voltage conversion device

Abstract

A voltage conversion device (D1, B) includes a magnetic coupling interleaved chopper circuit (D1) and a control unit (B) that controls the magnetic coupling interleaved chopper circuit (D1). The control unit (B) includes a switching frequency setting unit (14) that sets a switching frequency of the magnetic coupling interleaved chopper circuit (D1) based on a state quantity that indicates an operating state of the magnetic coupling interleaved chopper circuit (D1), and generates a voltage conversion gate signal at the switching frequency set by the switching frequency setting unit (14) and outputs the voltage conversion gate signal to the magnetic coupling interleaved chopper circuit (D1).

Description

Technical Field

[0001] This invention relates to a transformer.

[0002] This application claims priority based on Japan Patent Application No. 2020-216358, filed on December 25, 2020, the contents of which are incorporated herein by reference. Background Technology

[0003] Patent Document 1 discloses a DC / DC converter. This DC / DC converter includes: a DC voltage source; a first inductor, one end of which is connected to the positive terminal of the DC voltage source; a second inductor, one end of which is connected to the positive terminal of the DC voltage source and connected in parallel with the first inductor; a capacitor connected between the other ends of the first inductor and the second inductor; a first diode, the anode terminal of which is connected to the common connection point of the first inductor and the capacitor; and a second diode, the anode terminal of which is connected to the common connection point of the second inductor and the capacitor. The DC / DC converter includes: a first switching device connected between the common junction of the second inductor and the capacitor and the negative terminal of the DC voltage source; a second switching device connected between the common junction of the capacitor and the first diode and the negative terminal of the DC voltage source; and an output capacitor connected to the cathode terminals of the first and second diodes. The DC / DC converter uses a coupling inductor that is coupled in a direction that eliminates the DC flux linked to the first and second inductors.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-097287 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The aforementioned DC / DC converter, also known as a magnetically coupled interleaved chopper circuit, reduces the pulsating current flowing to the input / output capacitors (condensers) and reactors by switching the first and second switching devices with a 180° phase offset.

[0009] Furthermore, the purpose of this DC / DC converter is to reduce the switching losses and surge voltage of the first and second switching devices. To achieve this, a capacitor is placed between the other end of the first inductor and the other end of the second inductor. That is, this DC / DC converter focuses on the switching losses of the first and second switching devices as circuit losses.

[0010] However, the aforementioned DC / DC converter operates the first and second switching devices at a preset switching frequency, which is a fixed value. Therefore, depending on the operating state of the DC / DC converter, it may not be possible to sufficiently reduce switching losses. That is, by setting the switching frequency of the magnetically coupled interleaved chopper circuit to a fixed value, it may not be possible to improve performance regarding circuit losses, etc.

[0011] The present invention was made in view of the above circumstances, and its object is to provide a transformer device that can more reliably improve the performance of a magnetically coupled interleaved chopper circuit according to the operating state.

[0012] Methods for solving problems

[0013] According to a first aspect of the present invention, a transformer device includes: a magnetically coupled interleaved chopper circuit; and a control unit that controls the magnetically coupled interleaved chopper circuit, wherein the control unit includes a switching frequency setting unit that sets the switching frequency of the magnetically coupled interleaved chopper circuit based on a state quantity representing the operating state of the magnetically coupled interleaved chopper circuit, and generates a transformer gate signal for the switching frequency set by the switching frequency setting unit and outputs it to the magnetically coupled interleaved chopper circuit.

[0014] According to a second aspect of the present invention, in the first aspect described above, the switching frequency setting unit sets the switching frequency to minimize the circuit loss of the magnetically coupled interleaved chopper circuit.

[0015] According to a third aspect of the present invention, in the second aspect described above, the switching frequency setting unit sets the switching frequency of the magnetically coupled interleaved chopper circuit in an operating state where the boost ratio is twice to a lower frequency than the switching frequency in the operating state before and after the boost ratio of the magnetically coupled interleaved chopper circuit is twice.

[0016] According to a fourth aspect of the present invention, in any of the first to third aspects described above, the state quantity includes a reactor current flowing to the magnetically coupled interleaved chopper circuit, and in the event that the reactor current is an abnormal value, the switching frequency setting unit increases the switching frequency.

[0017] According to a fifth aspect of the present invention, in any one of the first to fourth aspects described above, the switching frequency setting unit includes a frequency map that registers a plurality of frequency values ​​corresponding to the state quantity as the switching frequency, and retrieves the frequency map based on the state quantity to generate the transformer gate signal.

[0018] The effects of the invention

[0019] According to the present invention, a transformer device can be provided that can more reliably improve the performance of a magnetically coupled interleaved chopper circuit based on the operating state. Attached Figure Description

[0020] Figure 1 This is a circuit diagram illustrating the overall structure of the control device A according to one embodiment of the present invention.

[0021] Figure 2 This is a block diagram illustrating the structure of a transformer gate signal generation unit in one embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram illustrating the structure of a carrier frequency mapping diagram in one embodiment of the present invention.

[0023] Figure 4 This is a flowchart illustrating the operation of a transformer device according to one embodiment of the present invention.

[0024] Figure 5 This is a timing diagram illustrating the operation of a transformer device according to one embodiment of the present invention.

[0025] Figure 6 This is a characteristic graph showing the relationship between the circuit efficiency and switching frequency of a boost / buck converter in one embodiment of the present invention. Detailed Implementation

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the control device A in this embodiment includes a PCU (Power Control Unit) 1, a gate driver 2, and an ECU (Electronic Control Unit) 3.

[0028] Furthermore, as shown in the figure, PCU1 includes three power conversion circuits: a boost / buck converter D1, a drive inverter D2, and a power generation inverter D3. Additionally, as shown in the figure, the gate driver 2 includes three gate signal generation units for transformer operation: a gate signal generation unit 2a for transformer operation, a gate signal generation unit 2b for drive operation, and a gate signal generation unit 2c for power generation.

[0029] Furthermore, the boost / buck converter D1 of PCU1 includes a first capacitor (condenser) 4, a transformer 5, four IGBTs (Insulated Gate Bipolar Transistors) 6a to 6d for transformer operation, and a second capacitor (condenser) 7. Similarly, the drive inverter D2 of PCU1 includes six drive IGBTs 8a to 8f, and the power generation inverter D3 includes six power generation IGBTs 9a to 9f. In addition, this boost / buck converter D1 is a component of the magnetically coupled interleaved chopper circuit involved in this invention.

[0030] As shown in the figure, a battery P, a three-phase motor M (electric motor), and a generator G are connected to such a control device A. That is, the control device A has a pair of battery terminals E1 and E2 for connecting the battery P, three motor terminals Fu, Fv, and Fw for connecting the three-phase motor M, and three generator terminals Hu, Hv, and Hw for connecting the generator G as external connection terminals.

[0031] Such a control device A is an electrical device found in electric vehicles such as hybrid electric vehicles and electric vehicles. It controls a three-phase motor M, which acts as a rotating motor, and controls the charging of battery P by AC power generated by generator G. That is, the control device A performs drive control of the three-phase motor M based on the output of battery P (battery power) and charging control of battery P based on the output power of generator G (generated power).

[0032] As shown in the figure, the positive electrode of the battery P is connected to the positive battery terminal E1, and the negative electrode is connected to the negative battery terminal E2. This battery P is a secondary battery such as a lithium-ion battery, and it discharges to and is charged by the DC power supplied by the control device A.

[0033] The three-phase motor M is a three-phase electric motor with "3" phases, serving as the load for the drive inverter D2. The U-phase input terminal of this three-phase motor M is connected to the U-phase motor terminal Fu, the V-phase input terminal is connected to the V-phase motor terminal Fv, and the W-phase input terminal is connected to the W-phase motor terminal Fw. The rotating shaft (drive shaft) of this three-phase motor M is connected to the wheel of the electric vehicle, driving the wheel to rotate by applying rotational power to it.

[0034] Generator G is a three-phase generator. Its U-phase output terminal is connected to the U-phase generator terminal Hu, its V-phase output terminal is connected to the V-phase generator terminal Hv, and its W-phase output terminal is connected to the W-phase generator terminal Hw. This generator G is connected to the output shaft of a power source such as an engine mounted on an electric vehicle, and outputs three-phase AC power to the control device A.

[0035] The boost / buck converter D1 is a power circuit known as a magnetically coupled interleaved chopper circuit. This boost / buck converter D1 selectively performs the following operations: boosting the DC power input from battery P via a pair of battery terminals E1, E2 and outputting it to the drive inverter D2; and bucking the DC power input from the drive inverter D2 or the generator inverter D3 and outputting it to battery P via the same pair of battery terminals E1, E2. In other words, the boost / buck converter D1 is a power conversion circuit that bidirectionally inputs / outputs DC power between battery P and the drive inverter D2 or the generator inverter D3.

[0036] The drive inverter D2 has three (or more) switching legs (U-phase drive switching leg, V-phase drive switching leg, and W-phase drive switching leg) configured to correspond to the number of phases (three (or more)) of the three-phase motor M (motor). This drive inverter D2 is a power conversion circuit that selectively performs traction and regenerative braking operations.

[0037] That is, the drive inverter D2 selectively performs the following operations: a traction operation where the DC power input from the boost / buck converter D1 is converted into three-phase AC power and output to the three-phase motor M via the three motor terminals Fu, Fv, and Fw; and a regenerative operation where the three-phase AC power input from the three-phase motor M via the three motor terminals Fu, Fv, and Fw is converted into DC power and output to the boost / buck converter D1. This drive inverter D2 is a power circuit that converts DC power and three-phase AC power between the boost / buck converter D1 and the three-phase motor M.

[0038] The generator inverter D3 is a power conversion circuit that converts the three-phase AC power input from the generator G via the three generator terminals Hu, Hv, and Hw into DC power and outputs it to the boost / buck converter D1. In other words, the generator inverter D3 is a power circuit that converts DC power and three-phase AC power between the boost / buck converter D1 and the generator G.

[0039] The structure of the boost / buck converter D1, drive inverter D2, and power generation inverter D3 of PCU1 will be described in detail below. Initially, in the boost / buck converter D1, one end of the first capacitor (condenser) 4 is connected to the first DC input / output terminal E1 and the transformer 5, and the other end is connected to the second DC input / output terminal E2. The two ends of this first capacitor (condenser) 4 are the primary-side input / output terminals of the boost / buck converter D1.

[0040] That is, the first capacitor (condenser) 4 is connected in parallel with the battery P to remove high-frequency noise contained in the DC power (battery power) input from the battery P to the boost / buck converter D1. In addition, the first capacitor (condenser) 4 smooths the pulsations contained in the DC power (charging power) input from the transformer 5.

[0041] The transformer 5 includes a primary winding 5a and a secondary winding 5b. One end of the primary winding 5a and one end of the secondary winding 5b are connected to the first DC input / output terminal E1 and one end of the first capacitor (condenser) 4. Furthermore, the other end of the primary winding 5a is connected to the emitter terminal of the first transformer IGBT 6a and the collector terminal of the second transformer IGBT 6b, and the other end of the secondary winding 5b is connected to the emitter terminal of the third transformer IGBT 6c and the collector terminal of the fourth transformer IGBT 6d.

[0042] In such a transformer 5, the primary winding 5a and the secondary winding 5b are electromagnetically coupled with a predetermined coupling coefficient k. That is, the primary winding 5a has a predetermined first self-inductance La corresponding to its number of turns, and the secondary winding 5b has a predetermined second self-inductance Lb corresponding to its number of turns. Furthermore, the primary winding 5a and the secondary winding 5b have a mutual inductance M based on the aforementioned first self-inductance La, second self-inductance Lb, and coupling coefficient k.

[0043] The first transformer IGBT 6a and the second transformer IGBT 6b of the four transformer IGBTs 6a to 6d constitute the A-phase transformer switching branch in the boost / buck converter D1. Furthermore, the third transformer IGBT 6c and the fourth transformer IGBT 6d constitute the B-phase transformer switching branch in the boost / buck converter D1.

[0044] The collector terminal of the first transformer IGBT 6a is connected to the collector terminal of the third transformer IGBT 6c and one end of the second capacitor (condenser) 7. The emitter terminal is connected to the other end of the primary winding 5a and the collector terminal of the second transformer IGBT 6b. The gate terminal is connected to the first output terminal of the boost / buck converter D1 in the gate driver 2. This first transformer IGBT 6a is a semiconductor switching element whose on / off operation is controlled based on the first transformer gate signal input from the gate driver 2.

[0045] The collector terminal of the second transformer IGBT 6b is connected to the other end of the primary winding 5a and the emitter terminal of the first transformer IGBT 6a. The emitter terminal is connected to the emitter terminal of the fourth transformer IGBT 6d, the other end of the first capacitor (condenser) 4, and the other end of the second capacitor (condenser) 7. The gate terminal is connected to the second output terminal of the boost / buck converter D1 in the gate driver 2. This second transformer IGBT 6b is a semiconductor switching element whose on / off operation is controlled based on the second transformer gate signal input from the gate driver 2.

[0046] The collector terminal of the third transformer IGBT 6c is connected to the collector terminal of the first transformer IGBT 6a and one end of the second capacitor (condenser) 7. The emitter terminal is connected to the other end of the secondary winding 5b and the collector terminal of the fourth transformer IGBT 6d. The gate terminal is connected to the third output terminal of the boost / buck converter D1 in the gate driver 2. This third transformer IGBT 6c is a semiconductor switching element whose on / off operation is controlled based on the third transformer gate signal input from the gate driver 2.

[0047] The collector terminal of the fourth transformer IGBT 6d is connected to the other end of the secondary winding 5b and the emitter terminal of the third transformer IGBT 6c. The emitter terminal is connected to the emitter terminal of the second transformer IGBT 6b, the other end of the first capacitor (condenser) 4, and the other end of the second capacitor (condenser) 7. The gate terminal is connected to the fourth output terminal of the boost / buck converter D1 in the gate driver 2. This fourth transformer IGBT 6d is a semiconductor switching element whose on / off operation is controlled based on the fourth transformer gate signal input from the gate driver 2.

[0048] Furthermore, one end of the second capacitor (condenser) 7 is connected to the collector terminal of the first transformer IGBT 6a and the collector terminal of the third transformer IGBT 6c, while the other end is connected to the emitter terminal of the second transformer IGBT 6b, the emitter terminal of the fourth transformer IGBT 6d, the other end of the first capacitor (condenser) 4, and the second DC input / output terminal E2. The two ends of this second capacitor (condenser) 7 are the secondary-side input / output terminals in the boost / buck converter D1.

[0049] This second capacitor (condenser) 7 smooths out the pulsations contained in the DC power (boost power) input from the A-phase transformer switch branch and the B-phase transformer switch branch. Furthermore, this second capacitor (condenser) 7 smooths out the pulsations contained in the DC power (regenerative power) input from the drive inverter D2 and the DC power (charging power) input from the generator inverter D3.

[0050] Although not illustrated, the boost / buck converter D1 includes a primary-side voltage sensor, a secondary-side voltage sensor, and a reactor current sensor as detectors to measure state variables indicating the operating status of the boost / buck converter D1. The primary-side voltage sensor detects the primary-side voltage V1 of the boost / buck converter D1, i.e., the primary-side voltage of the battery P side, and outputs the state variable of the boost / buck converter D1, i.e., the primary-side voltage V1, to the ECU3.

[0051] The secondary-side voltage sensor is a voltage sensor that detects the secondary-side voltage V2 of the boost / buck converter D1, i.e., the drive inverter D2 side (generator inverter D3 side). It outputs the status value of the boost / buck converter D1, i.e., the secondary-side voltage V2, to the ECU3. Furthermore, this secondary-side voltage V2 also serves as the primary-side voltage of the drive inverter D2 and the secondary-side voltage of the generator inverter D3.

[0052] Furthermore, the reactor current sensor detects the total current of the primary current flowing to the primary winding 5a of transformer 5 and the secondary current flowing to the secondary winding 5b as the reactor current I, and outputs the state quantity of the boost / buck converter D1, i.e., the reactor current I, to ECU3. This reactor current I is equivalent to the traction current flowing from the primary side to the secondary side of the boost / buck converter D1, or the regenerative current or charging current flowing from the secondary side to the primary side.

[0053] Next, among the six drive IGBTs 8a to 8f that constitute the drive inverter D2, the first drive IGBT 8a and the second drive IGBT 8b constitute the U-phase drive switching branch, the third drive IGBT 8c and the fourth drive IGBT 8d constitute the V-phase drive switching branch, and the fifth drive IGBT 8e and the sixth drive IGBT 8f constitute the W-phase drive switching branch.

[0054] In the first driving IGBT 8a and the second driving IGBT 8b, the collector terminal of the first driving IGBT 8a is connected to the collector terminal of the third driving IGBT 8c and the collector terminal of the fifth driving IGBT 8e, and the emitter terminal is connected to the collector terminal of the second driving IGBT 8b and the U-phase motor terminal Fu.

[0055] Furthermore, the gate terminal of this first drive IGBT 8a is connected to the first output terminal of the drive inverter D2 in the gate driver 2. This first drive IGBT 8a is a semiconductor switching element whose on / off operation is controlled based on the first drive gate signal input from the gate driver 2.

[0056] The collector terminal of the second driving IGBT 8b is connected to the emitter terminal of the first driving IGBT 8a and the U-phase motor terminal Fu, and the emitter terminal is connected to the emitter terminal of the fourth driving IGBT 8d and the emitter terminal of the sixth driving IGBT 8f.

[0057] Furthermore, the gate terminal of this second drive IGBT 8b is connected to the second output terminal of the drive inverter D2 in the gate driver 2. This second drive IGBT 8b is a semiconductor switching element whose on / off operation is controlled based on the second drive gate signal input from the gate driver 2.

[0058] The collector terminal of the third driving IGBT 8c is connected to the collector terminal of the first driving IGBT 8a and the collector terminal of the fifth driving IGBT 8e, and the emitter terminal is connected to the collector terminal of the fourth driving IGBT 8d and the V-phase motor terminal Fv.

[0059] Furthermore, the gate terminal of this third drive IGBT 8c is connected to the second output terminal of the drive inverter D2 in the gate driver 2. This third drive IGBT 8c is a semiconductor switching element whose on / off operation is controlled based on the third drive gate signal input from the gate driver 2.

[0060] The collector terminal of the fourth driving IGBT 8d is connected to the emitter terminal of the third driving IGBT 8c and the V-phase motor terminal Fv, and the emitter terminal is connected to the emitter terminal of the second driving IGBT 8b and the emitter terminal of the sixth driving IGBT 8f.

[0061] Furthermore, the gate terminal of this fourth drive IGBT 8d is connected to the fourth output terminal of the drive inverter D2 in the gate driver 2. This fourth drive IGBT 8d is a semiconductor switching element whose on / off operation is controlled based on the fourth drive gate signal input from the gate driver 2.

[0062] The collector terminal of the 5th drive IGBT 8e is connected to the collector terminal of the 1st drive IGBT 8a and the collector terminal of the 3rd drive IGBT 8c, and the emitter terminal is connected to the collector terminal of the 6th drive IGBT 8f and the W-phase motor terminal Fw.

[0063] Furthermore, the gate terminal of this fifth drive IGBT 8e is connected to the fifth output terminal of the drive inverter D2 in the gate driver 2. This fifth drive IGBT 8e is a semiconductor switching element whose on / off operation is controlled based on the fifth drive gate signal input from the gate driver 2.

[0064] The collector terminal of the 6th drive IGBT 8f is connected to the emitter terminal of the 5th drive IGBT 8e and the W-phase motor terminal Fw. The emitter terminal is connected to the emitter terminal of the 2nd drive IGBT 8b and the emitter terminal of the 4th drive IGBT 8d.

[0065] Furthermore, the gate terminal of this sixth drive IGBT 8f is connected to the sixth output terminal of the drive inverter D2 in the gate driver 2. This sixth drive IGBT 8f is a semiconductor switching element whose on / off operation is controlled based on the sixth drive gate signal input from the gate driver 2.

[0066] In such a drive inverter D2, the two ends of the three interconnected switching branches, namely the U-phase drive switching branch, the V-phase drive switching branch, and the W-phase drive switching branch, namely the collector terminals of the first drive IGBT 8a, the third drive IGBT 8c, and the fifth drive IGBT 8e, and the emitter terminals of the second drive IGBT 8b, the fourth drive IGBT 8d, and the sixth drive IGBT 8f, are the primary-side input / output terminals of the drive inverter D2. In addition, the three midpoints of the U-phase drive switch branch, the V-phase drive switch branch, and the W-phase drive switch branch, namely the connection point between the emitter terminal of the first drive IGBT 8a and the collector terminal of the second drive IGBT 8b, the connection point between the emitter terminal of the third drive IGBT 8c and the collector terminal of the fourth drive IGBT 8d, and the connection point between the emitter terminal of the fifth drive IGBT 8e and the collector terminal of the sixth drive IGBT 8f, are the secondary side input / output terminals of the drive inverter D2.

[0067] That is, the connection point between the emitter terminal of the first drive IGBT 8a and the collector terminal of the second drive IGBT 8b, the connection point between the emitter terminal of the third drive IGBT 8c and the collector terminal of the fourth drive IGBT 8d, and the connection point between the emitter terminal of the fifth drive IGBT 8e and the collector terminal of the sixth drive IGBT 8f are the secondary side input / output terminals of the drive inverter D2.

[0068] Furthermore, one of the primary side input / output terminals of the drive inverter D2, namely the collector terminal of the first drive IGBT 8a, the collector terminal of the third drive IGBT 8c, and the collector terminal of the fifth drive IGBT 8e, is connected to one of the secondary side input / output terminals of the boost / buck converter D1, namely one end of the second capacitor (condenser) 7, the collector terminal of the first transformer IGBT 6a, and the collector terminal of the third transformer IGBT 6c.

[0069] Furthermore, the other side of the primary input / output terminal of the drive inverter D2, namely the emitter terminal of the second drive IGBT 8b, the emitter terminal of the fourth drive IGBT 8d, and the emitter terminal of the sixth drive IGBT 8f, is connected to the other side of the secondary input / output terminal of the boost / buck converter D1, namely the other end of the first and second capacitors (condensers) 4 and 7, the emitter terminal of the second transformer IGBT 6b, and the emitter terminal of the fourth transformer IGBT 6d.

[0070] Next, among the six power generation IGBTs 9a to 9f that constitute the power generation inverter D3, the first power generation IGBT 9a and the second power generation IGBT 9b constitute the U-phase power generation switching branch, the third power generation IGBT 9c and the fourth power generation IGBT 9d constitute the V-phase power generation switching branch, and the fifth power generation IGBT 9e and the sixth power generation IGBT 9f constitute the W-phase power generation switching branch.

[0071] In the first power generation IGBT 9a and the second power generation IGBT 9b, the collector terminal of the first power generation IGBT 9a is connected to the collector terminal of the third power generation IGBT 9c and the collector terminal of the fifth power generation IGBT 9e, and the emitter terminal is connected to the collector terminal of the second power generation IGBT 9b and the U-phase generator terminal Hu.

[0072] Furthermore, the gate terminal of this first power generation IGBT 9a is connected to the first output terminal of the power generation inverter D3 in the gate driver 2. This first power generation IGBT 9a is a semiconductor switching element whose on / off operation is controlled based on the first power generation gate signal input from the gate driver 2.

[0073] The collector terminal of the second power generation IGBT 9b is connected to the emitter terminal of the first power generation IGBT 9a and the U-phase generator terminal Hu, and the emitter terminal is connected to the emitter terminal of the fourth power generation IGBT 9d and the emitter terminal of the sixth power generation IGBT 9f.

[0074] Furthermore, the gate terminal of this second power generation IGBT 9b is connected to the second output terminal of the power generation inverter D3 in the gate driver 2. This second power generation IGBT 9b is a semiconductor switching element whose on / off operation is controlled based on the second power generation gate signal input from the gate driver 2.

[0075] The collector terminal of the third power generation IGBT 9c is connected to the collector terminal of the first power generation IGBT 9a and the collector terminal of the fifth power generation IGBT 9e, and the emitter terminal is connected to the collector terminal of the fourth power generation IGBT 9d and the V-phase generator terminal Hv.

[0076] Furthermore, the gate terminal of this third power generation IGBT 9c is connected to the third output terminal of the power generation inverter D3 in the gate driver 2. This third power generation IGBT 9c is a semiconductor switching element whose on / off operation is controlled based on the third power generation gate signal input from the gate driver 2.

[0077] The collector terminal of the fourth power generation IGBT 9d is connected to the emitter terminal of the third power generation IGBT 9c and the V-phase generator terminal Hv. The emitter terminal is connected to the emitter terminal of the second power generation IGBT 9b and the emitter terminal of the sixth power generation IGBT 9f.

[0078] Furthermore, the gate terminal of this fourth power generation IGBT 9d is connected to the fourth output terminal of the power generation inverter D3 in the gate driver 2. This fourth power generation IGBT 9d is a semiconductor switching element whose on / off operation is controlled based on the fourth power generation gate signal input from the gate driver 2.

[0079] The collector terminal of the 5th power generation IGBT 9e is connected to the collector terminal of the 1st power generation IGBT 9a and the collector terminal of the 3rd power generation IGBT 9c, and the emitter terminal is connected to the collector terminal of the 6th power generation IGBT 9f and the W-phase generator terminal Hw.

[0080] Furthermore, the gate terminal of this fifth power generation IGBT 9e is connected to the fifth output terminal of the power generation inverter D3 in the gate driver 2. This fifth power generation IGBT 9e is a semiconductor switching element whose on / off operation is controlled based on the fifth power generation gate signal input from the gate driver 2.

[0081] The collector terminal of the 6th power generation IGBT 9f is connected to the emitter terminal of the 5th power generation IGBT 9e and the W-phase generator terminal Hw. The emitter terminal is connected to the emitter terminal of the 2nd power generation IGBT 9b and the emitter terminal of the 4th power generation IGBT 9d.

[0082] Furthermore, the gate terminal of this sixth power generation IGBT 9f is connected to the sixth output terminal of the power generation inverter D3 in the gate driver 2. This sixth power generation IGBT 9f is a semiconductor switching element whose on / off operation is controlled based on the sixth power generation gate signal input from the gate driver 2.

[0083] In such a power generation inverter D3, the three midpoints of the U-phase power generation switch branch, the V-phase power generation switch branch, and the W-phase power generation switch branch, namely the connection point of the emitter terminal of the first power generation IGBT 9a and the collector terminal of the second power generation IGBT 9b, the connection point of the emitter terminal of the third power generation IGBT 9c and the collector terminal of the fourth power generation IGBT 9d, and the connection point of the emitter terminal of the fifth power generation IGBT 9e and the collector terminal of the sixth power generation IGBT 9f, are the primary side input / output terminals of the power generation inverter D3.

[0084] In such a power generation inverter D3, among the three primary-side input / output terminals, the midpoint of the U-phase power generation switch branch is connected to the U-phase generator terminal Hu, the midpoint of the V-phase power generation switch is connected to the V-phase generator terminal Hv, and the midpoint of the W-phase power generation switch is connected to the W-phase generator terminal Hv.

[0085] Furthermore, the two ends of the U-phase power generation switch branch, V-phase power generation switch branch, and W-phase power generation switch branch that are interconnected in the power generation inverter D3, namely the collector terminals of the first power generation IGBT 9a, the collector terminals of the third power generation IGBT 9c, the collector terminals of the fifth power generation IGBT 9e, the emitter terminals of the second power generation IGBT 9b, the emitter terminals of the fourth power generation IGBT 9d, and the emitter terminals of the sixth power generation IGBT 9f, are the secondary side input / output terminals of the power generation inverter D3.

[0086] As shown in the figure, the secondary input / output terminals of this power generation inverter D3 are connected to the secondary input / output terminals of the boost / buck converter D1 and the primary input / output terminals of the drive inverter D2. That is, the boost / buck converter D1 provides input / output of DC power to and from the drive inverter D2 and / or the power generation inverter D3 between the battery P.

[0087] As shown in the figure, the aforementioned transformer IGBTs 6a to 6d, driver IGBTs 8a to 8f, and generator IGBTs 9a to 9f each include a freewheeling diode. Specifically, for each IGBT, the cathode terminal of this freewheeling diode is connected to the collector terminal, and the anode terminal is connected to the emitter terminal. When the IGBT is in the OFF state, this freewheeling diode allows the freewheeling current to flow from the anode terminal to the cathode terminal.

[0088] Next, the gate driver 2 includes a transformer gate signal generation unit 2a, a drive gate signal generation unit 2b, and a power generation gate signal generation unit 2c. It is a circuit that generates the first to fourth transformer gate signals, the first to sixth drive gate signals, and the first to sixth power generation gate signals based on various duty cycle command values ​​(transformer duty cycle command value, drive duty cycle command value, and power generation duty cycle command value) input from the ECU3.

[0089] The transformer gate signal generation unit 2a corresponds to the boost / buck converter D1 and generates the first to fourth transformer gate signals based on the transformer duty cycle command value input from the ECU3 and the transformer carrier frequency. That is, the transformer gate signal generation unit 2a generates PWM (Pulse Width Modulation) signals with a repetition frequency (repetition period) and duty cycle corresponding to the transformer carrier frequency and the transformer duty cycle command value as the first to fourth transformer gate signals by comparing the transformer duty cycle command value with a carrier wave (triangular wave) with a period corresponding to the transformer carrier frequency and the transformer duty cycle command value.

[0090] The transformer gate signal generation unit 2a outputs the first transformer gate signal to the gate terminal of the first transformer IGBT 6a of the boost / buck converter D1, the second transformer gate signal to the gate terminal of the second transformer IGBT 6b of the boost / buck converter D1, the third transformer gate signal to the third transformer IGBT 6c of the boost / buck converter D1, and the fourth transformer gate signal to the fourth transformer IGBT 6d of the boost / buck converter D1.

[0091] The drive gate signal generation unit 2b corresponds to the drive inverter D2 and generates the first to sixth drive gate signals based on the drive duty cycle command value input from the ECU3 and the drive carrier frequency. That is, the drive gate signal generation unit 2b generates PWM signals with a repetition frequency (repetition period) and duty cycle corresponding to the drive carrier frequency and the drive duty cycle command value as the first to sixth drive gate signals by comparing the drive duty cycle command value with a carrier wave (triangular wave) with a period corresponding to the drive carrier frequency and the drive duty cycle command value.

[0092] The drive gate signal generation unit 2b outputs a first drive gate signal to the gate terminal of the first drive IGBT 8a of the drive inverter D2, a second drive gate signal to the gate terminal of the second drive IGBT 8b of the drive inverter D2, a third drive gate signal to the gate terminal of the third drive IGBT 8c of the drive inverter D2, a fourth drive gate signal to the gate terminal of the fourth drive IGBT 8d of the drive inverter D2, a fifth drive gate signal to the gate terminal of the fifth drive IGBT 8e of the drive inverter D2, and a sixth drive gate signal to the gate terminal of the sixth drive IGBT 8f of the drive inverter D2.

[0093] The generator gate signal generation unit 2c corresponds to the generator inverter D3 and generates the first to sixth generator gate signals based on the generator duty cycle command value input from the ECU3 and the generator carrier frequency. That is, the generator gate signal generation unit 2c generates the first to sixth generator gate signals by comparing the generator duty cycle command value with a carrier wave (triangular wave) with a period corresponding to the generator carrier frequency.

[0094] The gate signal generation unit 2c outputs the first gate signal to the gate terminal of the first IGBT 9a of the inverter D3, the second gate signal to the gate terminal of the second IGBT 9b of the inverter D3, the third gate signal to the gate terminal of the third IGBT 9c of the inverter D3, the fourth gate signal to the gate terminal of the fourth IGBT 9d of the inverter D3, the fifth gate signal to the gate terminal of the fifth IGBT 9e of the inverter D3, and the sixth gate signal to the gate terminal of the sixth IGBT 9f of the inverter D3.

[0095] ECU3 is a control circuit that performs prescribed control processing based on a pre-stored control program. ECU3 outputs various duty cycle command values ​​(transformer duty cycle command value, drive duty cycle command value, and generator duty cycle command value) generated based on the above control processing to gate driver 2.

[0096] This ECU3, via PCU1 and gate driver 2, performs drive control of the three-phase motor M and charge control of the battery P. Specifically, based on the detection values ​​(voltage detection values) and current detection values ​​(current detection values) of the voltage sensors (voltage sensors) and the current sensors (current sensors) incidentally installed in the boost / buck converter D1, drive inverter D2, and generator inverter D3, as well as operating information of the electric vehicle, the ECU3 generates various duty cycle command values ​​(transformer duty cycle command value, drive duty cycle command value, and generator duty cycle command value) related to the boost / buck converter D1, drive inverter D2, and generator inverter D3.

[0097] The ECU3 generates the first to fourth transformer gate signals, the first to sixth drive gate signals, and the first to sixth generator gate signals by providing the gate driver 2 with the aforementioned various duty cycle command values ​​(transformer duty cycle command value, drive duty cycle command value, and generator duty cycle command value). The first to fourth transformer gate signals control the boost / buck converter D1, the first to sixth drive gate signals control the drive inverter D2, and the first to sixth generator gate signals control the generator inverter D3.

[0098] Next, refer to Figure 2 The structure of the transformer control unit B, which controls the aforementioned boost / buck converter D1, will be described in detail.

[0099] The transformer control unit B is composed of some functional components of the transformer gate signal generation unit 2a and ECU3, and is a control component that specializes in controlling the boost / buck converter D1. For example... Figure 2 As shown, the transformer control unit B includes a target value setting unit 10, a current control unit 11, a voltage control unit 12, a duty cycle control unit 13, a carrier frequency setting unit 14, and a transformer gate signal generation unit 2a.

[0100] The target value setting unit 10 is a functional component that sets the transformer control target value X0 based on the operating parameters of the electric vehicle, etc. This transformer control target value X0 is a target value for the boost ratio when the boost / buck converter D1 is performing boost operation, or a target value for the buck ratio when the boost / buck converter D1 is performing buck operation. The target value setting unit 10 outputs this transformer control target value X0 to the current control unit 11. Furthermore, the aforementioned boost ratio or buck ratio is the ratio between the primary side voltage V1 and the secondary side voltage V2.

[0101] The current control unit 11 is a calculation unit that calculates the current command value X1 based on the aforementioned transformer control target value X0, and based on the primary side voltage V1 input from the primary side voltage sensor, the secondary side voltage V2 input from the secondary side voltage sensor, and the reactor current I input from the reactor current sensor. The current control unit 11 outputs the current command value X1 to the voltage control unit 12.

[0102] The voltage control unit 12 is an arithmetic unit that calculates the voltage command value X2 based on the current command value X1 and the reactor current I. The voltage control unit 12 outputs the voltage command value X2 to the duty cycle control unit 13. The duty cycle control unit 13 is an arithmetic unit that calculates the duty cycle of the gate signals (PWM signals) for the first to fourth transformers based on the voltage command value X2.

[0103] In this embodiment, the boost / buck converter D1 has a magnetically coupled primary winding 5a and a secondary winding 5b, and a magnetically coupled interleaved chopper circuit with an A-phase transformer switching branch and a B-phase switching branch. The A-phase transformer switching branch and the B-phase switching branch are controlled by the first and second transformer gate signals and the third and fourth transformer gate signals, which are 180° out of phase.

[0104] To accommodate this boost / buck converter D1, the aforementioned duty cycle command values ​​X3 and X4 are composed of duty cycle command value X3 for phase A and duty cycle command value X4 for phase B. That is, duty cycle command value X3 for phase A is used to specify the duty cycle of the gate signals for the first and second transformers, and duty cycle command value X4 for phase B is used to specify the duty cycle of the gate signals for the third and fourth transformers.

[0105] The carrier frequency setting unit 14 is a functional component that sets the repetition frequency (carrier frequency fc) of the gate signals for the first to fourth transformers based on the primary side voltage V1, the secondary side voltage V2, and the reactor current I. This carrier frequency fc is a power generation carrier frequency that corresponds to the frequency of the carrier (triangular wave) used by the transformer gate signal generation unit 2a in generating the gate signals for the first to fourth transformers.

[0106] The carrier frequency setting unit 14 is a functional component equivalent to the switching frequency setting unit of the present invention, and the carrier frequency fc is a physical quantity used to specify the switching frequency of the first to fourth transformer IGBTs 6a to 6d constituting the boost / buck converter D1. That is, the carrier frequency setting unit 14 sets the carrier frequency fc of the boost / buck converter D1 (magnetically coupled interleaved chopper circuit) based on the primary side voltage V1, the secondary side voltage V2, and the reactor current I (state quantity) representing the operating state of the boost / buck converter D1 (magnetically coupled interleaved chopper circuit).

[0107] The carrier frequency setting unit 14 sets the frequency value X5 of the carrier frequency fc by using the carrier frequency mapping diagram 15 pre-stored in the ECU3. For example... Figure 3 As shown, the above-mentioned carrier frequency mapping diagram 15 is a two-dimensional table that registers the frequency values ​​X5 of the carrier frequency fc corresponding to the discrete multiple values ​​related to the secondary side voltage V2 and the reactor current I, which are over a specified range.

[0108] That is, such as Figure 3As shown, the carrier frequency mapping diagram 15 is a two-dimensional table related to the case where the primary side voltage V1 is 220V (volts), the voltage values ​​of the carrier frequency fc are recorded for a total of 11 points in the range of 220V to 700V for the secondary side voltage V2, and the current values ​​of the carrier frequency fc are recorded for a total of 41 points in the range of -200A (amperes) to +200A for the reactor current I.

[0109] In this carrier frequency mapping diagram 15, the values ​​of the three physical quantities representing the operating state of the boost / buck converter D1—primary-side voltage V1, secondary-side voltage V2, and reactor current I—are recorded at the frequency value X5 that minimizes the overall circuit loss of the boost / buck converter D1. Additionally, regarding... Figure 3 The polarity of the reactor current I is defined as follows: when the reactor current I flows from the primary side to the secondary side of the boost / buck converter D1, it is set to + (positive); when it flows from the secondary side to the primary side, it is set to - (negative).

[0110] The frequency values ​​X5 in such a carrier frequency mapping diagram 15 were found, for example, as values ​​that minimize the overall circuit loss of the boost / buck converter D1 in a prior experiment related to the performance of the boost / buck converter D1 before the PCU1 was mounted on an electric vehicle.

[0111] For example, a carrier frequency range is defined, with the upper limit set to meet the thermal requirements of the IGBT and the lower limit set to meet the noise and vibration requirements of the device. Thus, a mapping diagram is established for the primary-side voltage V1, secondary-side voltage V2, and reactor current I within this carrier frequency range, deriving a frequency value X5 that minimizes the overall circuit loss of the boost / buck converter D1. Therefore, the optimal carrier frequency for the device can be set.

[0112] Among them, Figure 3 The document describes, for example, the frequency values ​​X5 corresponding to the secondary voltage V2 and reactor current I when the primary voltage V1 is 220V. For a secondary voltage V2 of 450V and reactor current I of -20A, the carrier frequency fc is 12kHz. That is, when the primary voltage V1 is 220V, the secondary voltage V2 is 450V, and the reactor current I is -20A, the condition for minimizing the overall circuit loss of the boost / buck converter D1 is setting the carrier frequency fc to X5 at 12kHz.

[0113] In addition, such as Figure 3As shown, when the boost ratio of the boost / buck converter D1 is approximately 2, i.e., the secondary side voltage V2 is 450V, the frequency value X5 in the carrier frequency mapping diagram 15 is set lower than the frequency value X5 in the boost ratio before and after. That is, the frequency value X5 in the operating state where the boost ratio of the boost / buck converter D1 is 2 is set lower than the frequency value X5 in the operating state before and after the boost ratio of the boost / buck converter D1 is 2. Figure 3 Specific examples will be described below.

[0114] For example, when the secondary voltage V2 is 450V and the reactor current I is -30A, the frequency value X5 is 9kHz, but when the secondary voltage V2 is 400V and the reactor current I is -30A, the frequency value X5 is 11kHz, and when the secondary voltage V2 is 500V and the reactor current I is -30A, the frequency value X5 is 12kHz.

[0115] Furthermore, when the secondary side voltage V2 is 450V and the reactor current I is 20A, the frequency value X5 is 11kHz, but when the secondary side voltage V2 is 400V and the reactor current I is 20A, the frequency value X5 is 12kHz, and when the secondary side voltage V2 is 500V and the reactor current I is 20A, the frequency value X5 is 12kHz.

[0116] In the boost / buck converter D1, which is configured as a magnetically coupled interleaved chopper circuit, there is the following feature: when the boost ratio is 2 times, the magnetic flux generated by the reactor current Ia flowing to the primary winding 5a of the transformer 5 and the magnetic flux generated by the reactor current Ib flowing to the secondary winding 5b cancel each other out, and the core loss is minimized.

[0117] Therefore, in this embodiment, when the boost ratio is 2, in order to reduce the switching losses in the A-phase switch branch and the B-phase switch branch, i.e. the switching losses of the IGBTs 6a to 6d used for the first to fourth transformers, and thus minimize the overall circuit loss of the boost / buck converter D1, the carrier frequency fc is reduced to be lower than the carrier frequency fc in other boost ratios.

[0118] In the carrier frequency mapping diagram 15, a carrier frequency fc frequency value X5 is extracted by specifying the values ​​of the primary side voltage V1, the secondary side voltage V2, and the reactor current I. That is, the carrier frequency setting unit 14 retrieves the carrier frequency fc frequency value X5 corresponding to each value of the primary side voltage V1, the secondary side voltage V2, and the reactor current I input from the external source from the carrier frequency mapping diagram 15, and outputs the frequency value X5 as the result of this retrieval to the transformer gate signal generation unit 2a.

[0119] Among the components constituting the transformer control unit B, the target value setting unit 10, current control unit 11, voltage control unit 12, and duty cycle control unit 13 are the same as those in a known gate signal generation device. That is, among the components of the transformer control unit B, the most characteristic component in this embodiment is the carrier frequency setting unit 14.

[0120] The transformer control unit B, together with the boost / buck converter D1, constitutes the transformer device according to this embodiment. That is, the transformer device according to this embodiment consists of a magnetically coupled interleaved chopper circuit (boost / buck converter D1) and a control unit (transformer control unit B) that controls the magnetically coupled interleaved chopper circuit.

[0121] Next, refer to Figures 4 to 6 The operation of an important component of the control device A involved in this embodiment, namely the control operation of the transformer control unit B, will be described in detail.

[0122] In this transformer control unit B, initially, the carrier frequency setting unit 14 acquires the frequency value X5 of the carrier frequency fc corresponding to the values ​​of the primary side voltage V1, secondary side voltage V2 and reactor current I acquired from the primary side voltage sensor, secondary side voltage sensor and reactor current sensor of the boost / buck converter D1 (step S1).

[0123] That is, the carrier frequency setting unit 14 retrieves the carrier frequency mapping diagram 15 based on the values ​​of the primary side voltage V1, the secondary side voltage V2, and the reactor current I, thereby obtaining a frequency value X5. Then, the carrier frequency setting unit 14 outputs the frequency value X5 as the retrieval result to the transformer gate signal generation unit 2a.

[0124] On the other hand, in the transformer control unit B, the target value setting unit 10 sets the transformer control target value X0 based on the operating amount of the electric vehicle, etc. (step S2). Then, the target value setting unit 10 outputs the transformer control target value X0 to the current control unit 11.

[0125] Then, in addition to the transformer control target value X0, the current control unit 11 calculates the current command value X1 based on the values ​​of the primary side voltage V1, the secondary side voltage V2, and the reactor current I (step S3). Then, the current control unit 11 outputs the current command value X1 to the voltage control unit 12.

[0126] Then, in addition to the current command value X1 mentioned above, the voltage control unit 12 also calculates the voltage command value X2 based on the reactor current I (step S4). Then, the voltage control unit 12 outputs the voltage command value X2 to the duty cycle control unit 13.

[0127] Then, based on the voltage command value X2, the duty cycle control unit 13 calculates the A-phase duty cycle command value X3 for the A-phase switching branch and the B-phase duty cycle command value X4 for the B-phase switching branch in the boost / buck converter D1 (step S5). Then, the duty cycle control unit 13 outputs the A-phase duty cycle command value X3 and the B-phase duty cycle command value X4 to the transformer gate signal generation unit 2a.

[0128] Then, the transformer gate signal generation unit 2a generates the first to fourth transformer gate signals based on the duty cycle command value X3 for phase A and the duty cycle command value X4 for phase B (step S6). The transformer gate signal generation unit 2a then outputs the first to fourth transformer gate signals to the gate terminals of the first to fourth transformer IGBTs 6a to 6d that constitute the boost / buck converter D1. As a result, the boost / buck converter D1 performs transformer operation at the transformer ratio (boost ratio or buck ratio) specified by the transformer control target value X0.

[0129] in, Figure 5 An example of the gate signals for the first to fourth transformers during the boost operation of the boost / buck converter D1 is shown. During this boost operation, the gate signals for the first and second transformers cause high and low potentials to repeat at a fixed period to synchronize and turn on / off the first and second transformer IGBTs 6a and 6b. The gate signals for the third and fourth transformers become inverse signals of the gate signals for the first and second transformers, causing high and low potentials to repeat at a fixed period to synchronize and turn on / off the third and fourth transformer IGBTs 6c and 6d.

[0130] Furthermore, the gate signals for controlling the third and fourth transformers (6c and 6d) constituting the B-phase switch branch are 180° out of phase with respect to the gate signals for controlling the first and second transformers (6a and 6b) constituting the A-phase switch branch. As a result, the pulsating currents of the reactor current (A-phase reactor current Ia) connected to the primary winding 5a of the A-phase switch branch and the reactor current (B-phase reactor current Ib) connected to the secondary winding 5b of the B-phase switch branch are 180° out of phase.

[0131] The phase A reactor current Ia flows to the second capacitor (condenser) 7 via the freewheeling diode installed in the first transformer IGBT 6a, and the phase B reactor current Ib flows to the second capacitor (condenser) 7 via the freewheeling diode installed in the third transformer IGBT 6c. That is, the combined current of the phase A reactor current Ia and the phase B reactor current Ib flows to the second capacitor (condenser) 7, but because the phase A reactor current Ia and the phase B reactor current Ib are 180° out of phase, the amplitude of the combined current is extremely small.

[0132] The boost / buck converter D1 is a magnetically coupled interleaved chopper circuit consisting of two phases, A and B. Compared with a conventional chopper circuit with a single-phase structure, it can significantly reduce output current ripple.

[0133] Furthermore, according to this embodiment, the repetition frequency (repetition period) of the gate signals for the first to fourth transformers is set according to the values ​​of the primary side voltage V1, the secondary side voltage V2, and the reactor current I, so as to minimize the overall circuit loss of the boost / buck converter D1. Therefore, the overall circuit loss is minimized throughout the entire operating range (entire transformer ratio) of the boost / buck converter D1.

[0134] Therefore, according to this embodiment, based on the values ​​of the primary side voltage V1 and the secondary side voltage V2, which indicate the operating state of the boost / buck converter D1, and the reactor current I, one of the performance characteristics of the boost / buck converter D1, namely its performance with respect to circuit losses, can be reliably improved.

[0135] Furthermore, according to this embodiment, the carrier frequency fc (switching frequency) of the boost / buck converter D1 (magnetically coupled interleaved chopper circuit) in the operating state where the boost ratio is twice is set to be lower than the carrier frequency fc (switching frequency) in the boost ratios before and after. According to this embodiment, not only can the inductor losses in transformer 5 be reduced, but also the switching losses of IGBTs 6a to 6d used in the first to fourth transformers can be reduced.

[0136] Furthermore, according to this embodiment, a carrier frequency mapping diagram 15 (frequency mapping diagram) is provided, which registers multiple frequency values ​​corresponding to the values ​​of the primary side voltage V1, the secondary side voltage V2 and the reactor current I as carrier frequencies fc (switching frequencies) as state quantities. The carrier frequency mapping diagram 15 is retrieved based on the aforementioned state quantities to generate gate signals for the first to fourth transformers.

[0137] According to this embodiment, the carrier frequency fc corresponding to the values ​​of the primary side voltage V1, the secondary side voltage V2, and the reactor current I (state quantity) can be acquired in a relatively short time. As a result, the gate signals for the first to fourth transformers can be generated in a relatively short time.

[0138] Furthermore, the present invention is not limited to the above-described embodiments; for example, the following variations are considered.

[0139] (1) In the above embodiment, a magnetically coupled interleaved chopper circuit with a two-phase structure of boost / buck converter D1, i.e., phase A and phase B, has been described, but the present invention is not limited thereto. That is, the present invention can also be applied to magnetically coupled interleaved chopper circuits with a structure of three or more phases.

[0140] (2) In the above embodiment, the carrier frequency fc is set based on the carrier frequency mapping diagram 15, but the present invention is not limited thereto. For example, in the case where the reactor current I represents an abnormal value, such as Figure 6 As shown, the carrier frequency fc (switching frequency) can also be increased in an emergency to avoid disaster.

[0141] In Figure 6 The diagram illustrates the state where the reactor current I exceeds a current threshold R as the transformer control unit B sequentially decreases the carrier frequency fc as the reactor current I increases. This current threshold R, which is pre-stored in the transformer control unit B as control data, is the current value that divides the normal current region and the abnormal current region of the boost / buck converter D1.

[0142] Thus, when the operating state of the boost / buck converter D1 shifts from the normal current region to the abnormal current region, the IGBTs 6a to 6d of the first to fourth transformers may be damaged due to the abnormal current. However, by increasing the carrier frequency fc, the peak current of the reactor current I can be suppressed to a lower level.

[0143] According to this modified example, since the switching load of the first to fourth transformer IGBTs 6a to 6d can be reduced, damage to the first to fourth transformer IGBTs 6a to 6d caused by abnormal current can be effectively avoided. Furthermore, such abnormal currents can occur in situations such as slippage in electric vehicles.

[0144] (3) In the above embodiment, the carrier frequency fc is set using the carrier frequency mapping diagram 15, but the present invention is not limited thereto. For example, the function can also be set based on the frequency value obtained through prior experiments, and the state quantity can be substituted into the function to obtain the frequency value X5 of the carrier frequency fc.

[0145] (4) In the above embodiments, the following were adopted: Figure 3The carrier frequency mapping diagram 15 illustrates the logic structure, but the invention is not limited thereto. For example, the ranges of each physical quantity in the carrier frequency mapping diagram 15 (e.g., the ranges of primary-side voltage V1, secondary-side voltage V2, and reactor current I) should be appropriately set based on the operating range of the boost / buck converter D1 (magnetically coupled interleaved chopper circuit). Therefore, the ranges of each physical quantity are not limited to... Figure 3 .

[0146] also, Figure 3 The carrier frequency mapping diagram in Figure 15 is related to the case where the primary-side voltage V1 is 220V, but the primary-side voltage V1 is not limited to 220V. That is, the primary-side voltage V1 can also be specified by the output voltage of battery P, therefore, it should be set appropriately according to the output voltage of battery P.

[0147] (5) In the above embodiment, PCU1 using IGBT was described as a semiconductor switching element, but the present invention is not limited thereto. For example, MOSFET may also be used as a semiconductor switching element.

[0148] Industrial availability

[0149] According to the present invention, a transformer device can be provided that can more reliably improve the performance of a magnetically coupled interleaved chopper circuit based on the operating state.

[0150] Label Explanation

[0151] A. Control device; B. Transformer control unit; D1. Boost / buck converter (magnetically coupled interleaved chopper circuit); D2. Drive inverter; D3. Generator inverter; E1, E2. Battery terminals; Fu, Fv, Fw. Motor terminals; G. Generator; Hu, Hv, Hw. Generator terminals; P. Battery; M. Three-phase motor; 1. PCU (Power Control Unit); 2. Gate driver; 2a. Transformer gate signal generation unit; 2b. Drive gate signal generation unit; 2c. Generator gate signal generation unit; 3. ECU; 4. First capacitor (condenser); 5. Transformer; 5a. Primary winding; 5b. Secondary winding; 6a to 6d. Transformer IGBTs; 7. Second capacitor (condenser); 8a to 8f. Drive IGBTs; 9a to 9f. Generator IGBTs; 10. Target value setting unit; 11. Current control unit; 12. Voltage control unit; 13. Duty cycle control unit; 14. Carrier frequency setting unit (switch frequency setting unit); 15 Carrier frequency mapping diagram (frequency mapping diagram).

Claims

1. A transformer device comprising: a magnetically coupled interleaved chopper circuit; and a control unit for controlling the magnetically coupled interleaved chopper circuit, wherein, The control unit includes a switching frequency setting unit that sets the switching frequency of the magnetically coupled interleaved chopper circuit based on the primary-side voltage, secondary-side voltage, and reactor current, which indicate the operating state of the circuit. The control unit generates a transformer gate signal for the switching frequency set by the switching frequency setting unit and outputs it to the magnetically coupled interleaved chopper circuit. The switching frequency setting unit sets the switching frequency to minimize the circuit loss of the magnetically coupled interleaved chopper circuit. The switching frequency setting unit sets the switching frequency of the magnetically coupled interleaved chopper circuit in the operating state where the boost ratio is 2 times to a lower value than the switching frequency in the operating state before and after the boost ratio of the magnetically coupled interleaved chopper circuit is 2 times.

2. The transformer device as described in claim 1, wherein, When the reactor current is abnormal, the switching frequency setting unit increases the switching frequency.

3. The transformer device as described in claim 1 or 2, wherein, The switching frequency setting unit has a frequency mapping map that registers multiple frequency values ​​corresponding to the primary side voltage, the secondary side voltage, and the reactor current as the switching frequency, and retrieves the frequency mapping map based on the primary side voltage, the secondary side voltage, and the reactor current to generate the transformer gate signal.

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