Method and apparatus for low complexity mode dependent lookup table pre-compensation

Abstract

Methods and systems are disclosed for pre-correcting a transmission signal comprising a sequence of symbols using a Pattern Dependent Look-up Table (PDLUT) comprising one or more distortion correction values. When accessing a distortion correction value for a symbol in the sequence of symbols from the PDLUT, the accessed distortion correction value is quantized into one or more quantized values according to one or more quantizations, thereby reducing the bit-width of the distortion correction value. Linear correction compensation can be applied to the transmission signal and the distortion correction value having the lower bit-width, for example by finite impulse response (FIR) filters independent of each other, wherein the one or more quantized correction values having the lower bit-width reduce the number of computational steps performed during the linear correction compensation, thereby saving power consumption. The linearly compensated quantized values and the linearly compensated signal are combined into a pre-corrected signal.

Description

[0001] Cross-referencing related applications

[0002] This application claims the benefit and priority of U.S. nonprovisional patent application No. 17 / 157,691, filed January 25, 2021, entitled “METHOD AND APPARATUS OF LOW-COMPLEXITY PATTERN DEPENDENT LOOKUP TABLE PRE-COMPENSATION”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to communication technology, and more particularly to a method and apparatus for precompensating signals using lookup tables during digital signal processing. Background Technology

[0004] Communication signals transmitted via wireless, wired, or optical channels are susceptible to various impairments, especially at high baud rates (or high baud rates), including nonlinear inter-symbol interference or mode-dependent distortion introduced by transmitter components such as digital-to-analog converters (DACs), radio frequency (RF) amplifiers, and Mach-Zehnder modulators. Specifically, the nonlinear effects of each transmitter component interact with the frequency response of each individual component, and when combined, they result in nonlinear distortion with a memory length, leading to nonlinear degradation of amplitude and phase based on the symbol sequence in the signal received by the receiver in the optical communication system. This type of nonlinear distortion has been considered one of the major impairments limiting transceiver performance, especially for high-order modulation formats at high baud rates. Nonlinear distortion is typically strongly dependent on data patterns with considerable memory lengths.

[0005] Nonlinear digital pre-distortion (DPD) algorithms, typically based on adaptive Volterra finite impulse response (FIR) filters or machine learning-based artificial neural networks (ANNs), can be used to mitigate or compensate for nonlinear distortion in transmitters. However, these methods can significantly increase the implementation complexity and power consumption of application-specific integrated circuit (ASIC) digital signal processing (DSP) processors.

[0006] A trade-off is struck between performance and implementation to achieve nonlinear compensation for the transmitter. Specifically, before electro-optical conversion and transmission using the optical link of the communication system, the input communication signal is processed (or pre-compensated) in the electrical domain to compensate for signal distortion introduced by nonlinearity before transmission. For example, a compensation module is used to digitally process the electrical input signal to generate a pre-compensated (or pre-corrected) electrical signal; the corresponding pre-compensated electrical signal is then used to modulate the light source to generate a pre-compensated optical signal transmitted in the optical communication system.

[0007] A lookup table can be generated by calculating the distortion correction value corresponding to each symbol sequence in a preset sequence of N symbols and storing each calculated distortion correction value along with an associated lookup table (LUT) index. The distortion correction value is related to a specific pattern of the symbol sequence, so the resulting LUT is also called a Pattern Dependent Lookup Table (PDLUT).

[0008] Traditional PDLUT distortion correction values ​​are typically long-bit resolution (i.e., 8 bits or longer). To maintain accurate distortion correction values, the bit resolution required by the FIR filter used to receive the distortion correction values ​​is increased to accommodate the long-bit input. This not only increases the computational complexity of the FIR filter but also significantly increases the power consumption of the DSP processor. For ultra-high-speed (i.e., 800Gbps and above) short-range and data center interconnect (DCI) applications, the power consumption of the transceiver module must meet stringent standards, posing a challenge to DSP algorithms. Therefore, there is an urgent need for an improved PDLUT with lower complexity and power consumption to address the nonlinear distortion problem of the transmitter.

[0009] Therefore, there is a need for an improved PDLUT pre-compensation method and apparatus that is more efficient and consumes less power. Summary of the Invention

[0010] This disclosure provides a low-power, efficient, and low-complexity PDLUT pre-compensation method and apparatus for pre-compensating a transmitted signal comprising a symbol sequence, wherein the symbol sequence is used to generate an index value, the index value being used to access distortion correction values ​​stored in the PDLUT. The distortion correction values ​​accessed from the PDLUT are quantized into one or more quantized values ​​according to one or more quantizations. Each of the quantized values ​​and the original transmitted signal are received by a corresponding FIR filter for linear compensation. Each FIR filter has multiple input levels (also called quantization levels) that reduce the number of computational steps performed by the FIR filter, thereby reducing power consumption. The linearly compensated quantized distortion correction values ​​can be applied to the linearly compensated original transmitted signal to provide a pre-compensated signal for transmission.

[0011] According to one aspect, a method is provided for pre-correcting a signal comprising a symbol sequence using a Pattern Dependent Look-up Table (PDLUT) containing one or more distortion correction values, the method comprising: accessing distortion correction values ​​of symbols in the symbol sequence from the PDLUT; quantizing the accessed distortion correction values ​​into one or more quantized values ​​according to one or more quantizations to reduce the bit width of the distortion correction values; applying linear correction compensation to the one or more quantized values ​​and the signal respectively, wherein the one or more quantized correction values ​​having a lower bit width reduce the number of computation steps performed during the linear correction compensation; and combining the linearly compensated quantized values ​​and the linearly compensated signal into a pre-corrected signal.

[0012] According to another aspect, a digital signal processor (DSP) for a transmitter is provided, comprising: a processor configured to: access distortion correction values ​​of symbols in a symbol sequence to be transmitted by the transmitter in a PDLUT; quantize the accessed distortion correction values ​​into one or more quantized values ​​according to one or more quantizations to reduce the bit width of the distortion correction values; one or more FIR filters configured to: apply linear correction compensation to the one or more quantized values ​​and the symbol sequence, wherein the one or more quantized correction values ​​having a lower bit width reduce the number of computation steps performed during the linear correction compensation; and an adder configured to: combine the linearly compensated quantized values ​​and the linearly compensated symbol sequence into a pre-corrected signal.

[0013] In any of the foregoing aspects, the quantization may further include: quantizing the distortion correction value of the access into a first quantized value according to the first quantization; and quantizing a second portion of the distortion correction value into a second quantized value according to the second quantization; wherein the second portion of the distortion correction value is the difference between the distortion correction value of the access and the first quantized value.

[0014] In any of the foregoing aspects, the application may further include: providing the first quantized value to a first finite impulse response (FIR) filter having a first plurality of input levels; providing the second quantized value to a second FIR filter having a second plurality of input levels; and providing the signal to a third FIR filter.

[0015] In any of the foregoing aspects, the access may further include: for each symbol in the foregoing symbol sequence, selecting the number of consecutive symbols centered on each symbol; forming an index based on the number of symbols; and retrieving the distortion correction value from the foregoing PDLUT using the index.

[0016] In any of the above aspects, the one or more quantized values ​​of the one or more distortion correction values ​​can be pre-calculated and stored in the PDLUT, and the pre-calculated quantized values ​​can be accessed and directly applied to the signal.

[0017] In any of the foregoing aspects, the quantization may include a quantization where linear compensation is applied by an FIR filter having an odd number of input levels, and the quantization may further include determining a scaling factor representing the difference in distortion correction values ​​between adjacent input levels of the FIR filter. ,in, It is the maximum distortion correction value. It is the minimum distortion correction value. These are the odd number of input levels of the aforementioned FIR filter; the aforementioned quantization values ​​( ) determined as Where ROUND is the rounding function. This is the distortion correction value for the above access.

[0018] In any of the foregoing aspects, the quantization may include a quantization where linear compensation is applied by an FIR filter having an even number of input levels, and the quantization may further include determining a scaling factor representing the difference in distortion correction values ​​between adjacent input levels of the FIR filter. ,in, It is the maximum distortion correction value. It is the minimum distortion correction value. It is the even number of input levels mentioned above; the above quantization values ​​( ) determined as Where ROUND is the rounding function. This is the distortion correction value for the above access.

[0019] In any of the foregoing aspects, the first portion of quantizing the distortion correction value may include: determining a first scaling factor representing the difference in distortion correction values ​​between adjacent quantization levels of the first quantization. ,in, It is the maximum distortion correction value. It is the minimum distortion correction value. It is the first plurality of quantization levels of the first quantization mentioned above; the first quantization value ( ) determined as Where ROUND is the rounding function. This is the distortion correction value for the above access.

[0020] In either of the above aspects, the first plurality of quantization levels can be an even number or an odd number of levels.

[0021] In any of the foregoing aspects, the second portion of quantizing the aforementioned distortion correction value may include: determining a second scaling factor representing the difference in distortion correction values ​​between adjacent quantization levels of the second quantization. ,in, It is the second or more quantization levels of the second quantization mentioned above; the above distortion correction value is determined as The second quantization value mentioned above is determined as follows: , where ROUND is the rounding function.

[0022] In either of the above aspects, the second plurality of quantization levels can be an odd number of levels.

[0023] In any of the above aspects, the second plurality of quantization levels may include a 0 quantization level, and the remaining levels in the second plurality of quantization levels are symmetrically distributed around the 0 quantization level.

[0024] In any of the foregoing aspects, the second portion of quantizing the aforementioned distortion correction value may include: determining a second scaling factor representing the difference in distortion correction values ​​between adjacent quantization levels of the second quantization. ,in, It is the second or more quantization levels of the second quantization mentioned above; the above distortion correction value is determined as The second quantization value mentioned above is determined as follows: , where ROUND is the rounding function.

[0025] In either of the above aspects, the second plurality of quantization levels can be an even number of levels.

[0026] In any of the foregoing aspects, the quantization step may include three or more quantizations, wherein the quantization level of each of the three or more quantizations may be determined as follows: ,in, It refers to multiple quantization levels of a single quantization. It is the number of quantization levels of the nth quantization in the above three or more quantizations.

[0027] In either of the above aspects, the single quantization and the multiple quantizations mentioned above can achieve the same precision.

[0028] In any of the foregoing aspects, the processor may also be configured to: quantize a first portion of the distortion correction value into a first quantized value according to a first quantization; and quantize a second portion of the distortion correction value into a second quantized value according to a second quantization; wherein the second portion of the distortion correction value is the difference between the accessed distortion correction value and the first quantized value.

[0029] In any of the foregoing aspects, the one or more FIR filters may include: a first FIR filter having a first plurality of input levels for receiving the first quantized value; and a second FIR filter having a second plurality of input levels for receiving the second quantized value.

[0030] In any of the above aspects, the adder can be any one of a half adder, a full adder, a ripple carry adder, a carry-lookahead adder, a Brent-Kung adder, a Kogge-Stone adder, a carry-save adder, a carry-select adder, and a carry-skip adder.

[0031] At least some of the above aspects can advantageously allow for a reduction in the bit width of the distortion correction value, thereby reducing computational complexity and power consumption when applied to an FIR filter for linear compensation. This allows the transmitter DSP circuitry to perform pre-correction of the transmitted signal with lower power consumption and higher efficiency. Attached Figure Description

[0032] The accompanying drawings, by way of example, illustrate exemplary embodiments of this application, wherein:

[0033] Figure 1 A schematic block diagram of the optical communication system provided in this disclosure is shown;

[0034] Figure 2A A schematic block diagram of signal propagation in the traditional PDLUT compensation method is shown;

[0035] Figure 2B A schematic block diagram of a conventional PDLUT pre-calibration system is shown.

[0036] Figure 3A block diagram of the two-level PDLUT module provided in this disclosure is shown;

[0037] Figure 4 A flowchart of a single-step PDLUT compensation method provided by an exemplary embodiment of this disclosure is shown;

[0038] Figure 5A A graph showing the PDLUT distortion correction values ​​based on single-step quantization with 15 quantization levels and the corresponding quantization values ​​provided by an exemplary embodiment of the present disclosure is shown.

[0039] Figure 5B It shows Figure 5A The amplified portion;

[0040] Figure 6 A graph showing the bit error rate (BER) of a one-step quantized PDLUT versus an unquantized PDLUT is presented, where BER is a function of the number of quantization levels.

[0041] Figure 7 A flowchart illustrating a two-level PDLUT compensation method provided by an exemplary embodiment of this disclosure is shown;

[0042] Figure 8A and Figure 8B This disclosure illustrates the result processing of a two-step PDLUT quantization method provided in this disclosure. Figure 5A The same set of PDLUT distortion correction values;

[0043] Figure 9 It shows Figure 1 A block diagram of an exemplary hardware architecture for the Tx DSP 18.

[0044] Similar reference numerals can be used to denote similar components in different accompanying drawings. Detailed Implementation

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those known to one of ordinary skill in the art to which the described embodiments pertain.

[0046] Figure 1A schematic block diagram of an optical communication system 10 is shown. As shown, system 10 includes a transmitter 12 and a receiver 14. The transmitter 12 also includes a transmitter (Tx) DSP 18, a digital-to-analog converter (DAC) 20, a driver 22, an in-phase quadrature modulator (IQM) 24, and a first laser 26. The coherent system 10 also includes a communication link (e.g., an optical fiber link) 16 interconnecting the transmitter 12 and the receiver 14. The receiver 14 includes a coherent receiver (e.g., an integrated coherent receiver (ICR) 28), a second laser 30, an analog-to-digital converter (ADC) 32, and a receiver (Rx) DSP 34. It should be understood that other components may be present, but for simplicity, they are not shown in this figure.

[0047] The Tx DSP 18 is configured to receive digital signals and perform upsampling and pre-compensation on the received digital signals, including pre-compensation performed by the PDLUT module 100. As used herein, "module" can refer to a combination of hardware processing circuitry and machine-readable instructions (software and / or firmware) executable on that hardware processing circuitry. Hardware processing circuitry can include any or some combinations of a microprocessor, the core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a system-on-a-chip (SoC) or other hardware processing circuitry.

[0048] DAC 20 is configured to convert an upsampled and pre-compensated digital signal into an analog signal. This analog signal is amplified by driver 22. The amplified analog signal is then modulated by IQM 24 to the output of the first laser 26 to convert the amplified analog signal into an optical signal with X-polarization and Y-polarization channels.

[0049] The X-polarization channel and Y-polarization channel of the optical signal are transmitted through communication link 16. It should be understood that although communication link 16 can be used to transmit optical signals, in other embodiments, communication link 16 can also transmit the analog signal in the form of radio frequency signals in a wireless medium.

[0050] The X-polarized and Y-polarized channels of the optical signal are detected by the ICR 28 using a local oscillator including the second laser 30. Thus, the ICR 28 converts the optical signal into X-polarized and Y-polarized electrical signal channels. The ADC 32 is configured to convert the X-polarized and Y-polarized analog electrical signal channels into X-polarized and Y-polarized digital signal channels. These X-polarized and Y-polarized digital signal channels are then forwarded to the Rx DSP 34 for various digital signal processing operations. It should be understood that other components may be present, but for simplicity, they are not shown in this figure.

[0051] Figure 2A A schematic block diagram of signal propagation in a conventional PDLUT compensation method, which can be implemented at the PDLUT compensation module 100, is shown. For coherent communication, the Tx signal may include four sets of symbol sequences: XI, XQ, YI, and YQ, each set of symbol sequences corresponding to in-phase and quadrature X-polarization and in-phase and quadrature Y-polarization, respectively. Figure 2A For simplicity, the Tx signal is shown as including the XI component. As shown, the Tx signal, including the symbol sequence (XI), is first passed to the PDLUT module 100, which generates a mode-related nonlinear distortion correction value (Δ), discussed in more detail below, and applies it to the Tx signal to derive a pre-corrected signal. This pre-corrected symbol (XI+Δ) is then passed through an FIR filter for linear compensation. The output of this FIR filter can be further processed in the Tx DSP 18 before being transmitted to other components (e.g., the DAC 20 in the illustrated embodiment).

[0052] Figure 2B A schematic block diagram of a conventional PDLUT pre-calibration system 50, typically implemented at the PDLUT module 100, is shown. PDLUT distortion correction values ​​can be obtained according to the calibration process by comparing the symbol sequence received after the Rx DSP with the original transmitted symbol sequence from the Tx DSP. As an example, for an undercorrected symbol with index k, a continuous sequence of symbols S(kn:k+n) of memory length 2n+1 centered at symbol k is used to generate or access the corresponding distortion correction value for symbol k. For conventional PDLUTs, the memory length is typically an odd number (i.e., 2n+1), such as... Figure 2BAs shown. However, it should be understood that a symbol sequence can have an even number of symbols. Continuing the example, the corresponding symbol sequence received after all Rx DSP processing can be defined as A(kn:k+n), which may contain some mode-related distortion. The difference (or error) between S(kn:k+n) and A(kn:k+n) in symbol-wise resolution can be determined as ΔS(k). The PDLUT (also known as the LUT) contains the nonlinear correction error value for the center symbol within each symbol sequence S(kn:k+n). The LUT amplitude correction can be initialized to all zeros. A sliding window is used to identify consecutive symbol sequences to form the index value of the LUT (i.e., index(ii)). As the window traverses forward through the received symbol sequence, the correction error value ΔS(k) is incremented at the corresponding LUT index for each occurrence of the symbol sequence. A LUT counter (C) is used to track the number of updates for each specific entry, incrementing by 1 each time (i.e., C(ii) = C(ii) + 1). The average correction error value, determined as ΔS(ii) = LUT(ii) / C(ii), is applied to the actually received sequence A(kn:k+n) to produce the predistorted output amplitude. In practice, the LUT correction can be pre-calculated or determined in real time, depending on the trade-offs between performance and implementation complexity. However, the value of ΔS(k) is typically expressed as a decimal value, which is smaller than the value of each individual symbol. Therefore, the value of ΔS(k) must be represented using additional bits, which requires more bit-wise operations in all subsequent steps, resulting in longer computation time.

[0053] Figure 3 A block diagram of a two-stage PDLUT module 100 provided in this disclosure is shown. The PDLUT module 100 includes a PDLUT 102, FIR filters 104, 106 and 108, and an adder 110.

[0054] PDLUT module 100 receives a signal (XI) comprising a sequence of N symbols as input. The input signal XI is converted into an index value for accessing PDLUT 102. In some embodiments, each distinct sequence of N symbols corresponds to an index (or address), and the correction for a particular sequence is stored under that index. The total number of indices is L^N, corresponding to the LUT size. L is the possible number of each symbol; for example, L=2 for QPSK; L=4 for 16QAM; and L=8 for 64QAM. N is the number of symbols in the sequence of N symbols corresponding to the memory length. When N is odd, the center symbol is the (N+1) / 2th symbol in the symbol sequence; when N is even, the center symbol is either the N / 2th symbol or the N / 2+1th symbol in the symbol sequence. The index value generated based on the sequence of N symbols is then used to access the corresponding register in lookup table 102 to read the nonlinear correction error value stored in that register.

[0055] PDLUT 102 is configured to maintain a connection similar to a binding. Figure 2B The calibration process described generates multiple distortion correction values.

[0056] FIR filters 104 and 106 are each configured to receive a first quantized value and a second quantized value, respectively. FIR filter 108 is configured to receive an input signal (XI). In some embodiments, FIR filters 104, 106, and 108 perform linear compensation independently of each of the first quantized value, the second quantized value, and the input signal XI. For each of FIR filters 104, 106, and 108, the input signal passes through a series of delay latches. The junction at the output of each latch is called a tap. Each tap (except the last tap) is fed to the next latch in the series of latches and to the input of a multiplier. As the sampled digital signal data is fed to the series of delay latches, the tap contains a series of consecutive samples of the input signal. The corresponding multiplier multiplies each of these samples by its corresponding tap weight, which is stored in a corresponding weight register. Consecutive tap weights can be selected to obtain certain desired filtering characteristics, such as overcoming bandwidth limitations imposed by components on the data path, performing Nyquist pulse shaping to improve spectral efficiency, or compensating for impairments such as time skew and power imbalance. The products of the multipliers are then sent to an accumulator array, which adds these outputs to provide the final output of the FIR filter. After each multiplication and addition step, the digital signal data stored in each latch is sequentially moved to the next latch, and a new digital signal sample is latched into the first latch.

[0057] Adder 110 can combine the outputs of FIR filters 104, 106, and 108 into a pre-calibrated signal, which can be forwarded to other components of transmitter 12 before being transmitted to receiver 14. Adder 110 can be implemented in the processor's arithmetic logic unit (ALU). Adder 110 can be implemented as a half adder, full adder, ripple carry adder, carry-lookahead adder, Brent-Kung adder, Kogge-Stone adder, carry-hold adder, carry-select adder, carry-skip adder, or any other type of adder.

[0058] It should be understood that although a two-step PDLUT module 100 is shown, as can be clearly seen from this disclosure, module 100 can be extended to a single-step or multi-step PDLUT module 100.

[0059] Figure 4 A flowchart of a single-step PDLUT compensation method 400 provided by an exemplary embodiment of the present disclosure is shown. Method 400 can be implemented via hardware, software, or a combination of hardware and software means at the PDLUT compensation module 100.

[0060] In step 402, the input transmission signal sequence is fed into PDLUT 102. For each symbol in the transmission signal, a sequence of N consecutive symbols is used to generate an index that accesses a pre-correction error value stored in PDLUT 102, where each symbol serves as the center symbol in the symbol sequence. When N is odd, the center symbol is the (N+1) / 2th symbol in the symbol sequence; when N is even, the center symbol is either the N / 2th or N / 2+1th symbol in the symbol sequence. As a non-limiting illustrative example, for a sequence of three symbols (S1, S2, and S3) in a transmission signal with 16 QAM, each symbol has four possibilities (XI, XQ, YI, and YQ). Then, the index can be calculated as... ,in, Then, the generated index is used to access the corresponding register of PDLUT 102 to read the nonlinear correction error value.

[0061] In 404, the distortion correction value accessed from PDLUT 102 is quantized to a quantized value according to the quantization, so as to reduce the bit width of the distortion correction value.

[0062] FIR filter input level (N) levelThis is also called the corresponding quantization level. In some embodiments, the number of FIR filter input levels is odd. This input level is symmetrically distributed around the 0 level. The scaling factor representing the incremental increase in distortion correction value between adjacent quantization levels can be determined according to equation (1):

[0063]

[0064] in, It is the maximum distortion correction value stored in PDLUT 102. It is the minimum distortion correction value stored in PDLUT102. This is the number of input levels (also called quantization levels) of the FIR filter configured to receive quantized values. This quantization value can be determined according to equation (2):

[0065]

[0066] in, This is the distortion correction value accessed from PDLUT 102. "ROUND" is a function that rounds the value to the nearest integer. This is the quantization value. It should be understood that other rounding methods can be used, such as rounding to near powers of 2 for simple bit shifting, and any other rounding method. The maximum quantization error (or rounding error) is less than this scaling factor.

[0067] In some other embodiments, the FIR filter may have an even number of input levels (N). level In this case, the scaling factor and the quantification value can be determined as follows:

[0068]

[0069]

[0070] As a non-restrictive example, Figure 5A The PDLUT distortion correction value 502 is shown, which is plotted using its corresponding quantization value 504 based on single-step quantization using the corresponding FIR filter with 16 input levels. Figure 5B It shows Figure 5A The amplification portion, especially for PDLUT indexes with distortion correction values ​​ranging from 0 to 100, between 0.4 and -0.4.

[0071] It should be understood that the quantization method in step 404 is an exemplary embodiment of this disclosure, and other quantization methods are also possible.

[0072] Return to reference Figure 4In 406, linear compensation is applied to the quantized value and the Tx signal respectively using an FIR filter. It is well known that the speed of an FIR filter, and therefore its associated electronics, is typically limited by the speed of the tapped multiplier. As the resolution of the input signal to the FIR filter increases, the bit width of the signal increases, leading to increased multiplication complexity and significant power consumption.

[0073] The quantized values ​​read from the PDLUT 102 and the transmitted signal can be input to a separate FIR filter. The FIR filter can divide the arithmetic calculations into smaller numbers, thereby achieving faster computation time and power savings.

[0074] Then, in step 410, the linearly compensated quantized value and the linearly compensated signal are combined by an adder or the like to form a pre-corrected signal for transmission. This combined signal can then be forwarded to one or more components of transmitter 12 for transmission to receiver 14.

[0075] The rounding performed in step 404 results in quantization error. This quantization error worsens as the range of distortion correction values ​​increases, leading to an increase in the incremental distortion correction value between the scaling factor or quantization levels. Figure 6 A graph showing the bit error rate (BER) of one-step quantization versus unquantized PDLUT is presented, where BER is the number of input levels (N) to the FIR filter. level The function of ). Figure 6 It can be observed that the fewer the number of FIR filter input levels, the higher the BER. As the number of FIR filter input levels increases, the resulting quantized value is closer to the original PDLUT distortion correction value, and the rounding error during quantization is minimized, thereby improving the BER. However, increasing the number of FIR filter input levels leads to computational complexity and increased power consumption. Furthermore, increasing the number of FIR filter input levels provides a diminishing return on the BER improvement. Therefore, in some embodiments of this disclosure, a multi-step quantization method is implemented to provide the same accuracy performance (i.e., BER or root mean square (RMS) or error value) while using an FIR filter with a relatively low number of input levels.

[0076] Figure 7 A flowchart of a two-level PDLUT compensation method 700 provided by an exemplary embodiment of the present disclosure is shown. In the exemplary method 700, total quantization is divided into two quantization steps, each quantization having a smaller number of quantization levels while maintaining accuracy performance.

[0077] In step 702, the input transmission signal sequence is input into PDLUT 102. A similar process to step 402 of method 400 is used to generate an index for accessing the corresponding register of PDLUT 102 to read the nonlinear correction error value; for the sake of brevity, this will not be described further.

[0078] In 704, the distortion correction value will be accessed from PDLUT 102 according to the first quantization. The first part of the quantization is the first quantization value.

[0079] The first scaling factor, representing the increase in the distortion correction value between adjacent quantization levels of the first quantization, can be determined according to equation (5):

[0080]

[0081] in, It is the maximum distortion correction value stored in PDLUT 102. It is the minimum distortion correction value stored in PDLUT102. This is the number of input levels of a first FIR filter configured to receive a first quantization value or a first quantization level. In some embodiments, the first number of FIR input levels can be even or odd, and does not need to be set symmetrically around the 0 level.

[0082] The first quantization value can be determined according to equation (6):

[0083]

[0084] in, This is the distortion correction value accessed from PDLUT 102. "ROUND" is a function that rounds the value to the nearest integer. This is the first quantized value. Other rounding methods can be used, such as rounding to a power of 2 to achieve simple bit shifting.

[0085] In 706, according to the second quantization, the distortion correction value ( The second part of ) is quantized into a second quantized value ( In some embodiments, the second portion of the distortion correction value is defined as the residual distortion correction value ( The residual distortion correction value can be determined according to equation (7) as the difference between the distortion correction value accessed from PDLUT 102 and the first quantization value:

[0086]

[0087] Conceptually, this residual distortion correction value represents the quantization error of the first quantization, which can be significant, especially for large distortion correction ranges and low numbers of first quantization levels.

[0088] The second scaling factor, representing the increment of the distortion correction value between adjacent quantization levels in the second quantization, can be determined according to equation (8) as follows:

[0089]

[0090] Among them, the first proportional factor ( ) represents the residual distortion correction value of peak to peak (i.e., maximum value). ), It is the number of input levels of the second FIR filter configured to receive the second quantized value or the second quantized level. The second quantized value ( ) can be determined according to equation (9). It is determined to be:

[0091]

[0092] Here, "ROUND" is a function that rounds to the nearest integer value. It should be understood that other rounding methods can be used, such as rounding to near powers of 2, to achieve simple bit shifting. Due to the randomness of the first quantization (i.e., rounding down or up to each quantization level), the residual distortion correction value is statistically less than the mean. Symmetry. Therefore, in some embodiments, to ensure improved resolution and efficiency, the second FIR filter is configured with a symmetrical input level distribution, wherein the second number of FIR input levels includes an odd number of levels ( One of the input levels is 0, and the remaining input levels are evenly distributed around the 0 level, which can be determined using equations (4) and (5).

[0093] In some other embodiments, the second FIR filter may be configured with an even number of input levels, which may not include a zero input level. Internally symmetrical distribution. In this case, the second scaling factor can be determined as follows:

[0094]

[0095] Then, the second quantization value can be determined according to equation (11):

[0096]

[0097] Effectively, the first quantification step 704 is based on The distortion correction value is quantized at a relatively coarse scale. Because the resolution of the first quantization is less precise, the error derived from the rounding value (i.e., quantization error) in the first quantization step 704 is captured by the residual distortion correction value, which is quantized at a more precise scale (i.e., ...). It is equal to the first quantization ratio. Further quantization. In one respect, the second quantization reduces the quantization error of the first quantization in a quantization manner in order to ensure the computational efficiency of the FIR filter.

[0098] It should be understood that the quantization methods in steps 704 and 706 are exemplary embodiments of this disclosure, and other quantization methods are also possible.

[0099] In 708, linear compensation is applied to the first quantized value, the second quantized value, and the Tx signal independently of each other using separate FIR filters.

[0100] Then, in 710, the linearly compensated quantized value and the linearly compensated signal are combined by an adder, etc., to form a pre-corrected signal for transmission. Compared with the FIR filter, the power consumption of the adder is negligible, so its introduction does not significantly affect the power consumption of the overall system. The combined signal can then be forwarded to one or more components of the transmitter 12 for transmission to the receiver 14.

[0101] It should be understood that although a two-step PDLUT quantization is shown, method 700 can be adapted to a quantization method with three or more quantizations after making the necessary modifications.

[0102] Figure 8A and Figure 8B The results of the two-step PDLUT quantization method (i.e., method 700) provided in this disclosure are shown. Figure 4 The same set of PDLUT distortion correction values ​​for A. Figure 8A The first FIR filter with four (4) input levels is shown, which are asymmetrically distributed around the 0 level (i.e., two levels above and one level below). Figure 8B A second FIR filter with five (5) input levels is shown. From Figure 8B It can be seen that the residual correction value of each first quantization level ranges from 0.15 to -0.15, and these values ​​are symmetrically distributed around the intermediate value of 0. Figure 8B The root mean square (RMS) value of the residual correction value of the second quantization shown is... Figure 5A The quantization value in each step is the same, i.e., 0.0176. Therefore, the relationship between the number of quantization levels in the single-step PDLUT quantization and multi-step PDLUT quantization provided in this disclosure can be determined as follows:

[0103]

[0104] in, It refers to the number of quantization levels in single-step quantization. It refers to the number of quantization levels in multi-step quantization. This represents the total number of quantizations; +1 indicates a 0 input level. Figure 5A , Figure 5B , Figure 8A and Figure 8B In the example shown, 16-level single-step quantization corresponds to the product of the number of input levels according to the two-level quantization method of equation (12) (i.e., 16 = (4-1)(5) + 1). As another example, 19-level single-stage PDLUT quantization can be converted into 3-stage quantization, where each of the first, second, and third quantizations has 3 corresponding FIR filters with input levels of 3, 3, and 3 respectively, such that 19 = (3-1)(3)(3) + 1.

[0105] The number of FIR filter input levels can be selected based on the severity of the inherent nonlinear distortion in the system. For larger peak-to-peak (i.e., maximum to minimum) nonlinear distortion values, more FIR filter input levels may be required to minimize rounding errors caused by the quantization process. Alternatively, for smaller peak-to-peak nonlinear distortion, fewer FIR filter input levels may be needed. Therefore, in some embodiments, the total number of FIR filter input levels may depend on the error range and the desired performance metric. Once the total number of FIR filter input levels is determined, it can be converted to multi-step quantization according to equation (6). For example, 18-level single-step quantization may not be feasible, and the nearest possible single-step quantization level, i.e., 18, may be required to achieve the multi-step quantization provided in this disclosure. In some embodiments, 19-level single-step quantization may not have a corresponding two-step quantization available due to the availability of FIR filters, and may need to be converted to three-step quantization with a first FIR filter with 3 input levels, a second FIR filter with 3 input levels, and a third FIR filter with 3 input levels (i.e., 19 = (3-1)(3)(3)+1). If the power consumption of 3-level quantization is undesirable, then 16-level two-stage quantization can be considered (i.e., a first FIR filter with 4 input levels and a second FIR filter with 5 input levels).

[0106] For the two-step PDLUT quantization method, since the number of input levels (m) of the first plurality of FIR filter input levels and the number of input levels (n) of the second plurality of FIR filter input levels are equal to or greater than 3, then (m-1)+n < (m-1)n, and the minimum value of (m-1)n is 6. Therefore, in some embodiments, for a one-step PDLUT quantization with more than 6 FIR filter input levels, the corresponding two-step PDLUT quantization can achieve the same performance in terms of accuracy, while reducing the resolution of the FIR filters and thus saving power.

[0107] By employing multi-step quantization, the input level of the FIR filter corresponding to each quantization is reduced, thereby reducing the multiplier operations within the corresponding FIR filter and thus reducing power consumption without compromising performance.

[0108] Figure 9 A block diagram of an exemplary hardware structure of a Tx DSP 18 in which a PDLUT module 100 is implemented is shown. Other computing systems suitable for implementing the embodiments described in this disclosure may be used, which may include components different from those discussed below. In some examples, the Tx DSP 18 may be implemented across multiple physical hardware units, such as in parallel computing, distributed computing, virtual server, or cloud computing configurations. Although Figure 9 A single instance of each component is shown, but in TxDSP 18, each component may have multiple instances.

[0109] exist Figure 9 In this Tx DSP 18, there is a processing unit 902, an input / output (I / O) interface 904, and a memory 910.

[0110] Tx DSP 18 may include one or more processing devices 902, such as a central processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), neural processing unit (NPU), microprocessor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), dedicated logic circuit, dedicated artificial intelligence processor unit, or a combination thereof.

[0111] The Tx DSP 18 may also include one or more input / output (I / O) interfaces 904, which allow the Tx DSP 18 to receive input digital signals 906 and Rx feedback signals 35 from signal sources such as signal generators (not shown) during calibration. The I / O interfaces 904 may also transmit processed digital signals 908, such as compensated transmission signals, for further processing in system 10.

[0112] Memory 910 may include volatile memory or non-volatile memory. Examples of non-transitory computer-readable media include random access memory (RAM), read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, compact disc ROM (CD-ROM), or other portable storage. Non-transitory memory 910 may store instructions for execution by processing unit 902, such as performing the methods or procedures described in the examples of this disclosure. Memory 910 may include other software instructions, such as software instructions for implementing an operating system and other applications / functions.

[0113] In the Tx DSP 18, the PDLUT module 100 can be implemented by the processing unit 902 and the memory 910, among other components.

[0114] Bus 912 provides a communication channel between the components of the Tx DSP 18, including processing unit 902, I / O interface 904, and / or memory 910. Bus 912 can be any suitable bus architecture, including, for example, a memory bus or a peripheral bus.

[0115] In some embodiments, to further reduce power consumption, the quantization value of each distortion correction value in the PDLUT can be pre-calculated. For example, in some embodiments, the distortion correction value can be converted into its corresponding quantization value during the calibration phase and stored in the PDLUT. Therefore, during pre-calibration, the quantization value stored in PDLUT 102 can be accessed using the index value generated from each signal, and no computational power is required to calculate the quantization value.

[0116] Although this disclosure describes methods and processes by means of steps performed in a certain order, one or more steps in the methods and processes may be omitted or changed as appropriate. Where appropriate, one or more steps may be performed in an order different from that described in this disclosure.

[0117] Although this disclosure describes at least part of the methodological aspects, those skilled in the art will understand that this disclosure also relates to various components, whether hardware components, software, or any combination thereof, for performing at least some aspects and features of the method. Accordingly, the technical solutions of this disclosure can be embodied in the form of a software product. Suitable software products can be stored in pre-recorded storage devices or other similar non-volatile or non-transitory computer-readable media, including DVDs, CD-ROMs, USB flash drives, removable hard drives, or other storage media. The software product includes instructions tangibly stored thereon that enable a processor device (e.g., a personal computer, server, or network device) to perform examples of the methods disclosed herein.

[0118] This disclosure may be implemented in other specific forms without departing from the subject matter of the claims. The exemplary embodiments described are merely illustrative in all respects and not restrictive. Features selected from one or more of the foregoing embodiments may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations will be understood within the scope of this disclosure.

[0119] All values ​​and sub-ranges within the scope of the disclosure are also disclosed. Furthermore, although the systems, devices, and processes disclosed and illustrated herein may include a specific number of elements / components, modifications may be made to include more or fewer such elements / components. For example, although any element / component disclosed may be referred to as the singular, embodiments disclosed herein may be modified to include multiple such elements / components. The subject matter described herein is intended to cover and encompass all appropriate technical changes.

[0120] Certain adaptations and modifications can be made to the described embodiments. Therefore, the embodiments discussed above are considered illustrative rather than limiting.

Claims

1. A method for pre-correcting a signal comprising a symbol sequence using a Pattern Correlation Lookup Table (PDLUT) containing one or more distortion correction values, characterized in that, The method includes: Access the nonlinear distortion correction values ​​of the symbols in the symbol sequence from the PDLUT; The accessed nonlinear distortion correction value is quantized into one or more quantized values ​​according to one or more quantization steps to reduce the bit width of the nonlinear distortion correction value; Linear correction compensation is applied to the one or more quantized values ​​and the signal respectively, wherein the one or more quantized correction values ​​with a lower bit width reduce the number of computation steps performed during the linear correction compensation; The quantized value and the linearly compensated signal are combined to form the pre-corrected signal.

2. The method according to claim 1, characterized in that, The step of proceeding according to one or more quantization steps further includes: According to the first quantization step, the first portion of the accessed nonlinear distortion correction value is quantized into a first quantized value; According to the second quantization step, the second part of the nonlinear distortion correction value is quantized into a second quantized value. The second part of the nonlinear distortion correction value is the difference between the accessed nonlinear distortion correction value and the first quantization value.

3. The method according to claim 2, characterized in that, The application also includes: The first quantized value is provided to a first finite impulse response (FIR) filter having a first plurality of input levels; The second quantized value is provided to a second FIR filter having a second plurality of input levels; The signal is then provided to the third FIR filter.

4. The method according to any one of claims 1 to 3, characterized in that, The access also includes: For each symbol in the symbol sequence, select the number of consecutive symbols centered on each symbol; An index is formed based on the number of symbols; Use the index to retrieve the nonlinear distortion correction value from the PDLUT.

5. The method according to any one of claims 1 to 3, characterized in that, The pre-calculated one or more quantized values ​​of the one or more nonlinear distortion correction values ​​are stored in the PDLUT, the pre-calculated quantized values ​​are accessed, and the pre-calculated quantized values ​​are directly applied to the signal.

6. The method according to any one of claims 1 to 3, characterized in that, The quantization includes a quantization process where linear compensation is applied by an FIR filter with an odd number of input levels, and the quantization also includes: The scaling factor representing the difference in nonlinear distortion correction values ​​between adjacent input levels of the FIR filter is determined as follows: ,in, It is the maximum nonlinear distortion correction value. It is the minimum nonlinear distortion correction value. These are the odd number of input levels of the FIR filter; The quantized value ( ) determined as Where ROUND is the rounding function. It is the nonlinear distortion correction value of the access.

7. The method according to any one of claims 1 to 3, characterized in that, The quantization includes a quantization process where linear compensation is applied by an FIR filter with an even number of input levels, and the quantization also includes: The scaling factor representing the difference in nonlinear distortion correction values ​​between adjacent input levels of the FIR filter is determined as follows: ,in, It is the maximum nonlinear distortion correction value. It is the minimum nonlinear distortion correction value. It is the even number of input levels; The quantized value ( ) determined as Where ROUND is the rounding function. It is the nonlinear distortion correction value of the access.

8. The method according to claim 2, characterized in that, The first part of quantifying the nonlinear distortion correction value includes: The first scaling factor, representing the difference in nonlinear distortion correction values ​​between adjacent quantization levels of the first quantization, is determined as follows: ,in, It is the maximum nonlinear distortion correction value. It is the minimum nonlinear distortion correction value. It is the first plurality of quantization levels of the first quantization; The first quantized value ( ) determined as Where ROUND is the rounding function. It is the nonlinear distortion correction value of the access.

9. The method according to claim 8, characterized in that, The first plurality of quantization levels are either an even number or an odd number of levels.

10. The method according to claim 8, characterized in that, The second part of quantizing the nonlinear distortion correction value includes: The second scaling factor, representing the difference in nonlinear distortion correction values ​​between adjacent quantization levels of the second quantization, is determined as follows: ,in, It is the second or more quantization levels of the second quantization; The nonlinear distortion correction value is determined as follows: ; The second quantization value is determined as , where ROUND is the rounding function.

11. The method according to claim 10, characterized in that, The second plurality of quantization levels is an odd number of levels.

12. The method according to claim 11, characterized in that, The second plurality of quantization levels includes a 0 quantization level, and the remaining levels of the second plurality of quantization levels are symmetrically distributed around the 0 quantization level.

13. The method according to claim 8, characterized in that, The second part of quantizing the nonlinear distortion correction value includes: The second scaling factor, representing the difference in nonlinear distortion correction values ​​between adjacent quantization levels of the second quantization, is determined as follows: ,in, It is the second or more quantization levels of the second quantization; The nonlinear distortion correction value is determined as follows: ; The second quantization value is determined as , where ROUND is the rounding function.

14. The method according to claim 13, characterized in that, The second plurality of quantization levels is an even number of levels.

15. The method according to any one of claims 1 to 3, characterized in that, The quantization step includes three or more quantization steps, wherein the quantization level of each of the three or more quantizations is determined as follows: ,in, It refers to multiple quantization levels of a single quantization. It is the number of quantization levels of the nth quantization in the three or more quantizations.

16. The method according to claim 15, characterized in that, The single quantization and the multiple quantizations can achieve the same precision.

17. A digital signal processor (DSP) for a transmitter, characterized in that, include: The processor is configured as follows: The nonlinear distortion correction value of the symbols in the symbol sequence to be transmitted by the transmitter in the access mode related lookup table PDLUT; The accessed nonlinear distortion correction value is quantized into one or more quantized values ​​according to one or more quantization steps to reduce the bit width of the nonlinear distortion correction value; One or more FIR filters are configured to apply linear correction compensation to the one or more quantized values ​​and the symbol sequence, wherein the one or more quantized correction values ​​having a lower bit width reduce the number of computational steps performed during the linear correction compensation; The adder is configured to combine the linearly compensated quantized values ​​and the linearly compensated symbol sequence into a pre-corrected signal.

18. The DSP according to claim 17, characterized in that, The processor is also configured to: According to the first quantization step, the first part of the nonlinear distortion correction value is quantized into a first quantized value; According to the second quantization step, the second part of the nonlinear distortion correction value is quantized into a second quantized value. The second part of the nonlinear distortion correction value is the difference between the accessed nonlinear distortion correction value and the first quantization value.

19. The DSP according to claim 18, characterized in that, The one or more FIR filters include: A first FIR filter has a first plurality of input levels for receiving the first quantized value; The second FIR filter has a second plurality of input levels for receiving the second quantized value.

20. The DSP according to any one of claims 17 to 19, characterized in that, The adder is any one of the following: half adder, full adder, ripple carry adder, carry-lookahead adder, Brent-Kung adder, Kogge-Stone adder, carry-save adder, carry-select adder, and carry-skip adder.

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