Signal detection circuit and signal detection method

Abstract

The present application provides a signal detection circuit, which includes a signal peak detection circuit, a reference voltage generation circuit and a comparator circuit. The signal peak detection circuit is used for receiving a plurality of differential voltage input signals and generating a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is used for generating a single-ended reference voltage signal. The comparator circuit is used for receiving the single-ended peak signal and the single-ended reference voltage signal and comparing the single-ended peak signal and the single-ended reference voltage signal to generate a signal detection result.

Description

Technical Field

[0001] This invention relates to signal detection, and more particularly to a signal detection circuit with low input parasitic capacitance and a related signal detection method. Background Technology

[0002] In communication system chips, a signal detection circuit is typically coupled alongside the high-speed signal path to determine if a signal from another device has been received, enabling subsequent operations. Therefore, the size of the input parasitic capacitance of the signal detection circuit affects the signal quality of high-speed data transmission. Traditional signal detection circuits employ an architecture related to the input common-mode voltage. Since the optimal common-mode operating voltage of the signal detection circuit's input stage may not be the same as the optimal common-mode operating voltage of the high-speed signal path, traditional signal detection circuits require an additional common-mode voltage rebiasing circuit. This rebiasing circuit uses capacitive coupling and resistive rebiasing to regenerate the common-mode bias. However, implementing capacitive coupling in the layout generates significant ground parasitic capacitance. Furthermore, this common-mode voltage rebiasing circuit occupies a considerable chip area.

[0003] Traditional signal detection circuits use differential comparators to compare the differential input signal with a differential reference voltage signal to determine if a signal from another device has been received. However, the common-mode voltage of all inputs to the differential comparator must be the same. To solve this problem, traditional signal detection circuits additionally require a reference voltage generation circuit that ensures the common-mode voltage of the differential reference voltage signal matches the common-mode voltage of the differential input signal, which also occupies a significant portion of the chip area. Therefore, there is an urgent need for a signal detection circuit with low input parasitic capacitance to simultaneously maintain the quality of high-speed data transmission and reduce chip area. Summary of the Invention

[0004] Therefore, one object of the present invention is to provide a signal detection circuit with low input parasitic capacitance and a related signal detection method to solve the above-mentioned problems.

[0005] An embodiment of the present invention provides a signal detection circuit, which may include a signal peak detection circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detection circuit is used to receive multiple differential voltage input signals and generate a single-ended peak signal based on the multiple differential voltage input signals. The reference voltage generation circuit is used to generate a single-ended reference voltage signal. The comparator circuit is used to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal and the single-ended reference voltage signal to generate a signal detection result.

[0006] Another embodiment of the present invention provides a signal detection method. The signal detection method may include: receiving a plurality of differential voltage input signals; generating a single-ended peak signal based on the plurality of differential voltage input signals; generating a single-ended reference voltage signal; and comparing the single-ended peak signal and the single-ended reference voltage signal to generate a signal detection result.

[0007] One advantage of this invention is that, since the signal detection circuit of this invention uses an architecture independent of the input common-mode voltage, it eliminates the need for an additional common-mode voltage generation circuit, as well as a reference voltage generation circuit that makes the common-mode voltage of the differential reference voltage signal the same as the common-mode voltage of the differential input signal. As a result, the signal detection circuit of this invention can reduce parasitic capacitance near high-speed signals to maintain the signal quality of high-speed data transmission and achieve the advantage of reducing chip area. In addition, the signal detection circuit of this invention adopts a single-ended detection method, which can reduce parasitic capacitance at the input end. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a high-speed data processing architecture according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram of a signal detection circuit according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of a signal peak detection circuit according to an embodiment of the present invention.

[0011] Figure 4 According to an embodiment of the present invention Figure 3 The diagram shows a single-ended peak signal generated by the signal peak detection circuit.

[0012] Figure 5 According to an embodiment of the present invention Figure 2 The diagram shows the relevant signals of the signal detection circuit.

[0013] Figure 6 This is a flowchart illustrating a signal detection method according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures: Detailed Implementation

[0015] Figure 1 This is a schematic diagram of a high-speed data processing architecture 10 according to an embodiment of the present invention. Figure 1As shown, the high-speed data processing architecture 10 may include multiple terminals 100 and 110, a signal detection circuit 120, and a high-speed data processing circuit 130 (e.g., a high-speed data amplifier and a clock data recovery (CDR) circuit). Terminals 100 and 110 may be two terminating resistors, but this invention is not limited thereto. A first terminal of terminal 100 may be coupled to a common-mode voltage VCM, and a second terminal of terminal 100 may be used to receive a differential voltage input signal A_P corresponding to high-speed input data, wherein the common-mode voltage VCM is the optimal common-mode operating voltage of the high-speed data processing circuit 130. A first terminal of terminal 110 may be coupled to the common-mode voltage VCM, and a second terminal of terminal 110 may be used to receive another differential voltage input signal A_N corresponding to high-speed input data. The signal detection circuit 120 may be coupled to the second terminals of terminals 100 and 110, and may be used to receive the differential voltage input signals A_P and A_N, and to determine whether the differential voltage input signals A_P and A_N are noise. The high-speed data processing circuit 130 can be coupled to the second terminal of terminal 100 and the second terminal of terminal 110, and can be used to receive differential voltage input signals A_P and A_N, and process the valid data transmitted through the differential voltage input signals A_P and A_N.

[0016] Figure 2 This is a schematic diagram of a signal detection circuit 20 according to an embodiment of the present invention, wherein... Figure 1 The signal detection circuit 120 shown can be derived from... Figure 2 The signal detection circuit 20 shown is used to implement this. For example... Figure 2As shown, the signal detection circuit 20 may include a signal peak detection circuit 200, a reference voltage generation circuit 210, and a comparator circuit 220. The signal peak detection circuit 200 can be used to receive differential voltage input signals A_P and A_N, and can generate a single-ended peak signal PEAK by sampling and holding the differential voltage input signals A_P and A_N. It should be noted that the signal peak detection circuit 200 is only related to the differential voltage of the input signals (i.e., the differential voltage input signals A_P and A_N), and does not need to use the common-mode voltage of the input signals for subsequent operations. Therefore, the signal peak detection circuit 200 uses an architecture independent of the input common-mode voltage, and the signal detection circuit 20 does not require an additional common-mode voltage generation circuit. In this way, not only can the chip area occupied by the common-mode voltage generation circuit be saved, but the parasitic capacitance generated by the common-mode voltage generation circuit can also be avoided. In addition, in order to reduce the parasitic capacitance at the input end, the signal peak detection circuit 200 uses a single-ended detection method to generate the single-ended peak signal PEAK. In this way, compared with the signal detection circuit with a common-mode voltage related architecture, the signal detection circuit 20 can reduce the parasitic capacitance at the input end by half, thus improving the signal quality of high-speed data transmission.

[0017] The reference voltage generation circuit 210 can be used to generate a single-ended reference voltage REF. Since the signal peak detection circuit 200 uses an architecture independent of the input common-mode voltage, the reference voltage generation circuit 210 only needs to generate the single-ended reference voltage signal REF according to the circuit design requirements, without considering the common-mode voltage between the single-ended reference voltage signal REF and the single-ended peak signal PEAK. The comparator circuit 220 has a positive terminal (+) coupled to the signal peak detection circuit 200 and a negative terminal (-) coupled to the reference voltage generation circuit 210, and can be used to receive the single-ended peak signal PEAK and the single-ended reference voltage signal REF, and compare the single-ended peak signal PEAK and the single-ended reference voltage signal REF to generate a signal detection result COMP, wherein the differential voltage input signals A_P and A_N can be determined as noise based on the signal detection result COMP.

[0018] Figure 3 This is a schematic diagram of a signal peak detection circuit 30 according to an embodiment of the present invention, wherein... Figure 2 The signal peak detection circuit 200 shown can be derived from... Figure 3 The signal peak detection circuit 30 shown is used to implement this. Figure 3As shown, the signal peak detection circuit 30 may include a switching circuit 300, a switching circuit 310, and a capacitor 320, wherein the switching circuit 300 and the switching circuit 310 may be implemented by active elements (e.g., transistors). The switching circuit 300 has a first terminal and a second terminal. The first terminal of the switching circuit 300 can be used to receive a differential voltage input signal A_P, and the switching circuit 300 can determine whether to conduct according to the differential voltage input signal A_N to transmit the differential voltage input signal A_P to the second terminal of the switching circuit 300. The switching circuit 310 has a first terminal and a second terminal. The first terminal of the switching circuit 310 can be used to receive a differential voltage input signal A_N, and the switching circuit 310 can determine whether to conduct according to the differential voltage input signal A_P to transmit the differential voltage input signal A_N to the second terminal of the switching circuit 310. Therefore, the differential voltage input signal A_P received by the switching circuit 300 is also used as a control signal of the switching circuit 310, and the differential voltage input signal A_N received by the switching circuit 310 is also used as a control signal of the switching circuit 300. Capacitor 320 has a first terminal and a second terminal, and can be used to output a single-ended peak signal PEAK. The first terminal of capacitor 320 can be coupled to the second terminal of switching circuit 300 and the second terminal of switching circuit 310, and the second terminal of capacitor 320 can be coupled to a reference voltage (e.g., a ground voltage GND).

[0019] In this embodiment, when the differential voltage input signal A_P is at a high level (marked as "1") and the differential voltage input signal A_N is at a low level (marked as "0"), the switch circuit 300 is turned on and the switch circuit 310 is turned off, and the single-ended peak signal PEAK is the differential voltage input signal A_P at this time. On the other hand, when the differential voltage input signal A_P is at a low level and the differential voltage input signal A_N is at a high level, the switch circuit 300 is turned off and the switch circuit 310 is turned on, and the single-ended peak signal PEAK is the differential voltage input signal A_N at this time. In this way, the signal peak detection circuit 30 can obtain the single-ended peak signal PEAK by sampling and holding the switch circuits 300 and 310.

[0020] Figure 4 According to an embodiment of the present invention Figure 3 The diagram shows a single-ended peak signal PEAK generated by the signal peak detection circuit 30, where the horizontal axis represents time and the vertical axis represents voltage. Figure 4As shown, when the differential voltage input signal A_P is high and the differential voltage input signal A_N is low, the single-ended peak signal PEAK is the differential voltage input signal A_P. On the other hand, when the differential voltage input signal A_P is low and the differential voltage input signal A_N is high, the single-ended peak signal PEAK is the differential voltage input signal A_N. For the sake of simplicity, similar content described in the above embodiments will not be repeated in detail here.

[0021] Figure 5 According to an embodiment of the present invention Figure 2 The diagram shows a related signal of the signal detection circuit 20, where the horizontal axis represents time and the vertical axis represents voltage. Figure 5 In this circuit, the single-ended peak signal PEAK is generated by single-ended detection, and the single-ended reference voltage signal REF can be generated according to circuit design requirements. The differential voltage input signals A_P and A_N can be determined as noise based on the signal detection result COMP generated by the comparator circuit 220. For example, based on the signal detection result COMP indicating that the voltage value of the single-ended peak signal PEAK is less than the voltage value of the single-ended reference voltage signal REF, the differential voltage input signals A_P and A_N will be determined as noise. Conversely, based on the signal detection result COMP indicating that the voltage value of the single-ended peak signal PEAK is not less than the voltage value of the single-ended reference voltage signal REF, the differential voltage input signals A_P and A_N will be determined as valid signals from other devices. For the sake of brevity, similar content described in the above embodiments will not be described in detail again here.

[0022] Figure 6 The flowchart illustrates a signal detection method according to an embodiment of the present invention. If the same result can be obtained, the steps do not necessarily need to be followed exactly. Figure 6 The process shown will be executed sequentially. For example... Figure 6 The signal detection method shown can be implemented by the signal detection circuit 20, wherein the signal peak detection circuit 200 in the signal detection circuit 20 is composed of... Figure 3 The signal peak detection circuit 30 shown is used to achieve this.

[0023] In step S600, the signal peak detection circuit 30 receives the differential voltage input signals A_P and A_N.

[0024] In step S602, the signal peak detection circuit 30 determines whether to turn on a switching circuit (e.g., switching circuit 300) in the signal peak detection circuit 30 according to the differential voltage input signal A_N to transmit the differential voltage input signal A_P to the first end of the capacitor 320 for use as a single-ended peak signal PEAK.

[0025] In step S604, the signal peak detection circuit 30 determines whether to turn on another switching circuit (e.g., switching circuit 310) in the signal peak detection circuit 30 based on the differential voltage input signal A_P to transmit the differential voltage input signal A_N to the first end of the capacitor 320 for use as a single-ended peak signal PEAK.

[0026] In step S606, the reference voltage generation circuit 210 generates a single-ended reference voltage signal REF.

[0027] In step S608, comparator circuit 220 compares single-ended peak signal PEAK and single-ended reference voltage signal REF to generate signal detection result COMP.

[0028] Since those skilled in the art can easily understand the contents of the relevant specifications for signal detection circuit 20 and signal peak detection circuit 30... Figure 6 For the sake of brevity, similar operations shown in this embodiment will not be repeated here.

[0029] In summary, because the signal detection circuit of the present invention uses an architecture independent of the input common-mode voltage, it eliminates the need for both an additional common-mode voltage generation circuit and a reference voltage generation circuit that makes the common-mode voltage of the differential reference voltage signal the same as the common-mode voltage of the differential input signal. This allows the signal detection circuit of the present invention to reduce parasitic capacitance near high-speed signals to maintain signal quality for high-speed data transmission and achieve the advantage of reduced chip area. Furthermore, the signal detection circuit of the present invention employs a single-ended detection method; therefore, compared to signal detection circuits with common-mode voltage-dependent architectures, the signal detection circuit of the present invention can reduce the parasitic capacitance at the input by half.

[0030] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall be protected by the present invention.

Claims

1. A signal detection circuit, comprising: A signal peak detection circuit is used to receive multiple differential voltage input signals and generate a single-ended peak signal based on the multiple differential voltage input signals. A reference voltage generation circuit is used to generate a single-ended reference voltage signal. as well as A comparator circuit is used to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal and the single-ended reference voltage signal to generate a signal detection result. The plurality of differential voltage input signals includes a first differential voltage input signal and a second differential voltage input signal, and the signal peak detection circuit includes: A first switching circuit has a first terminal and a second terminal. The first terminal of the first switching circuit is used to receive the first differential voltage input signal, and the first switching circuit determines whether to conduct according to a first control signal to transmit the first differential voltage input signal to the second terminal of the first switching circuit. A second switching circuit has a first terminal and a second terminal. The first terminal of the second switching circuit is used to receive a second differential voltage input signal, and the second switching circuit determines whether to conduct according to a second control signal to transmit the second differential voltage input signal to the second terminal of the second switching circuit; and A capacitor has a first terminal and a second terminal, and is used to output the single-ended peak signal. The first terminal of the capacitor is coupled to the second terminal of the first switching circuit and the second terminal of the second switching circuit, and the second terminal of the capacitor is coupled to a reference voltage.

2. The signal detection circuit according to claim 1, characterized in that, The first control signal is the second differential voltage input signal, and the second control signal is the first differential voltage input signal.

3. The signal detection circuit according to claim 2, characterized in that, When the first differential voltage input signal is at a first level and the second differential voltage input signal is at a second level lower than the first level, the first switching circuit is turned on and the second switching circuit is turned off, and the single-ended peak signal is the first differential voltage input signal.

4. The signal detection circuit according to claim 2, characterized in that, When the first differential voltage input signal is at a first level and the second differential voltage input signal is at a second level higher than the first level, the first switching circuit is not turned on and the second switching circuit is turned on, and the single-ended peak signal is the second differential voltage input signal.

5. A signal detection method, comprising: Receives multiple differential voltage input signals; A single-ended peak signal is generated based on the plurality of differential voltage input signals; Generate a single-ended reference voltage signal; and A signal detection result is generated by comparing the single-ended peak signal with the single-ended reference voltage signal. in, The plurality of differential voltage input signals includes a first differential voltage input signal and a second differential voltage input signal, and the step of sampling and holding the plurality of differential voltage input signals to generate the single-ended peak signal includes: A first control signal determines whether to activate a first switching circuit to transmit the first differential voltage input signal to a first terminal of a capacitor; and A second control signal is used to determine whether to turn on a second switching circuit to transmit the second differential voltage input signal to the first terminal of the capacitor; The capacitor is used to output the single-ended peak signal, and the second end of the capacitor is coupled to a reference voltage.

6. The signal detection method according to claim 5, characterized in that, The first control signal is the second differential voltage input signal, and the second control signal is the first differential voltage input signal.

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