A programmable logic-based radar operational data acquisition platform

Abstract

The present application relates to a kind of radar operation data acquisition platform based on programmable logic, including the radar operation data acquisition circuit based on programmable logic and selectable signal form, the logical link of instruction issuing and data uploading based on C / S architecture, remote one-key upgrade link based on C / S architecture, radar operation data acquisition circuit is triggered by fault state variation time recording function, collects radar operation information, logical link realizes the issuing of configuration command, data upload command, fault self-checking command and data upload, remote one-key upgrade link will be received through network configuration file, write to the FLASH device of configuration, realize the solidification and download of FPGA logic remote data. Through the automation of radar operation data, the integrity and accuracy of radar operation data collection are realized. By establishing automatic acquisition rule, a set of radar operation data acquisition platform is established, and the characteristic data of equipment operation can be completely collected.

Description

Technical Field

[0001] This invention relates to the field of radar operation data processing, and in particular to a radar operation data acquisition platform based on programmable logic. Background Technology

[0002] As a large and complex electronic product, radar requires the statistical analysis of the operational data it generates during operation. In the past, radar data statistical analysis often involved post-processing data collection followed by entry into a database platform for analysis. However, this sampling method raises questions about data integrity and is detrimental to radar data acquisition and processing. Therefore, a platform capable of achieving complete radar data acquisition is needed. Summary of the Invention

[0003] To address the existing technical problems, this invention provides a radar operation data acquisition platform based on programmable logic.

[0004] The specific content of this invention is as follows: A radar operation data acquisition platform based on programmable logic includes a radar operation data acquisition circuit based on programmable logic and selectable signal forms, a logic link based on C / S architecture for command issuance and data upload, and a remote one-click upgrade link based on C / S architecture. The radar operation data acquisition circuit triggers the recording function at any time the fault state changes to collect radar operation information. The logic link implements the issuance and data upload of configuration commands, data upload commands, and fault self-check commands. The remote one-click upgrade link burns the configuration file received through the network into the configured FLASH device, realizing the solidification and download of FPGA logic remote data.

[0005] Furthermore, the radar operation data acquisition circuit based on programmable logic and selectable signal formats includes:

[0006] Signal format configuration conversion circuit: Distinguishes external fault identification signals, uses configuration logic to convert level-type and heartbeat-type fault signals into pulse-type fault signals, and performs logical combination to form external fault indication signals;

[0007] Radar operation data acquisition trigger circuit: It completes the monitoring and sampling of internal temperature and voltage parameters, compares them with the fault threshold, and generates an internal abnormality trigger signal after three-level filtering; it performs three-level filtering on the external fault indication signal; and it logically ORs the internal and external trigger signals to form the final data acquisition trigger signal.

[0008] Radar operation data acquisition and storage circuit: When the data acquisition trigger signal is detected to have a change in state, the radar operation data is sampled in real time; after being latched, the data can be recorded in a designated storage unit via a storage link. If there is a host computer upload command, the real-time data can be uploaded to the host computer according to the command, or the data in the designated storage unit can be uploaded for conversion, recording and display.

[0009] Radar operation data recording standards: Establish a radar operation data recording format.

[0010] Furthermore, the signal format configuration conversion circuit includes:

[0011] For level-type signals, level sampling is performed; upper and lower limit level values ​​are configured. When the sampled level value exceeds the upper limit, an overvoltage mark pulse is output, and when the sampled level value is lower than the lower limit, an undervoltage mark pulse is output, thus converting it into a pulse-type signal. The accuracy of the configured upper and lower limit level values ​​is no greater than 0.1V.

[0012] For heartbeat-type signals, the longest allowable period value is configured to be no more than 1.2s with an accuracy of 0.1μs. Using a counting device, when no heartbeat is detected within the longest allowable period, a no-heartbeat fault marker pulse is triggered, thereby converting it into a pulse-type signal.

[0013] Furthermore, the radar operation data acquisition trigger circuit includes:

[0014] This circuit latches the radar operation data in real time at the point where the trigger signal is acquired;

[0015] The date and time data are synchronized uniformly after the platform is powered on, and then counted automatically by the acquisition module; the platform can also perform uniform synchronization during operation.

[0016] The acquisition trigger signal simultaneously triggers the recording link, recording the latched radar operation data into the designated storage unit;

[0017] When the host computer issues an upload command, it can upload latched data or the current status in real time according to the command.

[0018] Furthermore, the real-time latched radar operation data includes fault source codes, fault numbers, date data, time data, temperature detection values, and various voltage detection values.

[0019] Furthermore, the radar operation data acquisition and storage circuitry includes:

[0020] The kernel module of the programmable device is used to sample environmental parameters to record radar operation-related data, namely sampling FPGA temperature and various operating voltages, while retaining one internal control parameter monitoring channel, and comparing each parameter with the specified parameter threshold to form the parameter trigger signals for internal environmental abnormal faults. These signals are then filtered in three stages to eliminate the risk of false triggering and form the internal environmental abnormal trigger signal.

[0021] The acquisition circuit also decodes commands sent from the host computer management system and generates a system trigger signal, which is used to trigger the maintenance status.

[0022] After the external trigger signal is filtered in three stages to eliminate the risk of false triggering, it is logically combined with the internal environmental abnormal trigger signal and the system trigger signal to form the data acquisition trigger signal.

[0023] The minimum time interval for three-stage filtering is no greater than 0.1 μs.

[0024] Furthermore, the radar operation data recording specifications include: establishing a working status register, configuring the status register, the time status register, and matching command data formats to complete various functions of the platform.

[0025] Furthermore, the logical link for command issuance and data upload based on the C / S architecture includes: establishing host computer management software to realize graphical interface management; establishing an exchange system and a multi-module ID identification mechanism, which can be independently configured through ID; and using broadcast mode to send data to realize the sending of specific data across all modules.

[0026] Furthermore, the host computer management software includes:

[0027] Real-time online search and location of FPGA boards;

[0028] Online FPGA board detection and identification;

[0029] Board fault information acquisition and statistics: Obtain board buffer fault information, form a local fault information file, and perform graphic and text display, local storage, file conversion and statistical analysis based on the board buffer fault information and the local fault information file;

[0030] Board configuration file upgrade and readback: Read back the FPGA board configuration file and store it; upgrade the configuration file, read the local configuration file, and compare the configuration files;

[0031] The download and basic characteristics display of the FPGA board operation data collection are as follows: FPGA board operating status parameters are collected, the collected operating parameters are logged, and the log records and FPGA board operating status parameters are displayed in text and graphics.

[0032] Furthermore, the remote one-click upgrade link based on the C / S architecture includes: establishing a version update link based on the update bitstream, which facilitates remote one-click upgrades when parameters / thresholds are updated, thereby reducing the configuration work after each power-on.

[0033] The beneficial effects of this invention are: by automating the acquisition of radar operation data, the completeness and accuracy of radar operation data collection are achieved. By establishing automatic acquisition rules, a radar operation data acquisition platform is built, which can comprehensively collect characteristic data during equipment operation. Attached Figure Description

[0034] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.

[0035] Figure 1 A flowchart for establishing a remote data acquisition framework;

[0036] Figure 2 This is a functional block diagram of the host computer management software;

[0037] Figure 3 Block diagram of FPGA logic design for remote data acquisition;

[0038] Figure 4 The main structure of the remote upgrade file;

[0039] Figure 5 This is the interface for acquiring and statistically analyzing radar operation data.

[0040] Figure 6 This is for collecting data on the board's operational status. Detailed Implementation

[0041] Combination Figures 1-6 The present invention provides a radar operation data acquisition platform based on programmable logic. The platform establishes a host computer and a built-in client module that can realize usable data acquisition according to the C / S architecture.

[0042] This built-in module utilizes the radar operation data acquisition circuit to trigger the recording function at specific times based on changes in fault status (fault occurrence, fault clearance, maintenance status change, etc.), collecting radar operation information such as fault information, time information, and environmental information. The timing acquisition circuit can track different signal detection types such as level, pulse, and heartbeat signals, and accumulates time during operation (combining power-on time and platform time) and can sense environmental conditions (temperature, voltage). Once the fault status change recording condition is triggered, this logic can automatically store the radar operation data under the power-on environment, and can realize remote data download as described in the previous section according to the data download command from the host computer.

[0043] The developed host computer management system can issue configuration commands, data upload commands, and other commands to interact with the client, realizing functions such as real-time online FPGA board search and location, online FPGA board detection and identification, board fault information acquisition and statistics, board configuration file upgrade and readback, downloading board operation data, and displaying basic characteristics of operation data. Simultaneously, considering potential future cross-platform requirements for Windows / Linux, the management application is developed using Java. While ensuring data reliability and security, it provides a simple and user-friendly interface. Furthermore, the system can simulate self-testing functions such as simulated state, buffer periodic or event-based faults, including overheating faults, power supply voltage faults, FPGA internal logic faults, and FPGA external input faults, achieving simulated fault self-testing.

[0044] Finally, considering the need for convenient upgrade capabilities to accommodate adjustments to platform parameters or fault criteria, the platform is designed with remote logic upgrade capabilities: configuration files received over the network can be burned into the configured FLASH device, enabling remote data storage and downloading of FPGA logic. This function provides the fundamental capability for downloading acquired data.

[0045] The platform specifically includes the following modules: a radar operation data acquisition circuit based on programmable logic and selectable signal format; a logical link for command issuance and data upload based on a C / S architecture; and a remote one-click upgrade link based on a C / S architecture.

[0046] The radar operation data acquisition circuit, based on programmable logic and with selectable signal formats, includes:

[0047] Signal format configuration conversion circuit: Distinguishes external fault identification signals, uses configuration logic to convert level-type and heartbeat-type fault signals into pulse-type fault signals, and performs logical combination to form external fault indication signals;

[0048] Radar operation data acquisition trigger circuit: It completes the monitoring and sampling of internal temperature and voltage parameters, compares them with the fault threshold, and forms an internal abnormality trigger signal after three-level filtering; it performs three-level filtering on the external fault indication signal; and it logically ORs the internal and external trigger signals to form the final data acquisition trigger signal.

[0049] Radar operation data acquisition and storage circuit: When a change in the state of the data acquisition trigger signal is detected, the radar operation data is sampled in real time; after being latched, this data is recorded in a designated storage unit via a storage link. If there is a host computer upload command, real-time data can be uploaded to the host computer according to the command, or data in the designated storage unit can be uploaded for conversion, recording, and display.

[0050] Radar operation data recording standards: Establish a radar operation data recording format.

[0051] Signal format conversion circuit, including:

[0052] For level-type signals, level sampling is performed; upper and lower limit level values ​​are configured. When the sampled level value exceeds the upper limit, an overvoltage warning pulse is output; when the sampled level value is below the lower limit, an undervoltage warning pulse is output, thus converting it into a pulse-type signal. The accuracy of the configured upper and lower limit level values ​​is no greater than 0.1V.

[0053] For heartbeat-type signals, a maximum allowable period value is configured, typically no greater than 1.2s, with an accuracy of 0.1μs. Using a counting device, if no heartbeat is detected within the maximum allowable period, a no-heartbeat fault marker pulse is triggered, thus converting it into a pulse-type signal.

[0054] The radar operation data acquisition electrical trigger circuit includes:

[0055] This circuit latches radar operation data in real time at the trigger signal acquisition point, including fault source code, fault number, date data, time data, temperature detection value, and various voltage detection values.

[0056] The date and time data are synchronized uniformly after the platform is powered on, and then counted automatically by the acquisition module; the platform can also perform uniform synchronization during operation.

[0057] The acquisition trigger signal simultaneously triggers the recording link, recording the latched radar operation data into the designated storage unit;

[0058] When the host computer issues an upload command, it can upload latched data or the current status in real time according to the command.

[0059] Radar operation data acquisition and storage circuitry, including:

[0060] The kernel module of the programmable device is used to sample environmental parameters to record radar operation-related data. Specifically, it samples FPGA temperature and various operating voltages, while simultaneously retaining one channel of internal control parameter monitoring. Each parameter is compared with specified threshold values ​​to generate trigger signals for internal environmental anomalies. These signals undergo three levels of filtering to eliminate the risk of false triggers and establish the final internal environmental anomaly trigger signal.

[0061] The acquisition circuit also decodes commands sent from the host computer management system and generates a system trigger signal, which is generally used for maintenance status triggering.

[0062] External trigger signals are also filtered in three stages to eliminate the risk of false triggering, and then logically combined with internal environmental abnormal trigger signals and system trigger signals to form data acquisition trigger signals.

[0063] The minimum time interval for the three-stage filtering is no greater than 0.1 μs.

[0064] Radar operation data recording specifications include:

[0065] Establish working status registers, configure status registers, time status registers, and matching command data formats to complete various functions of the platform;

[0066] The logical link for command issuance and data upload based on a C / S architecture includes:

[0067] Establish host computer management software to achieve graphical interface management;

[0068] Establish an exchange system and a multi-module ID identification mechanism, which can be configured independently via ID;

[0069] Data can be distributed via broadcast to enable the distribution of specific data across all modules.

[0070] This includes establishing host computer management software to achieve graphical interface management. Figure 2 Specifically, it includes:

[0071] Real-time online search and location of FPGA boards;

[0072] Online FPGA board detection and identification;

[0073] Board fault information acquisition and statistics: Obtain board buffer fault information, form a local fault information file, and perform graphic and text display, local storage, file conversion and statistical analysis based on the board buffer fault information and the local fault information file;

[0074] Board configuration file upgrade and readback: Read back the FPGA board configuration file and store it; upgrade the configuration file, read the local configuration file, and compare the configuration files;

[0075] The download and basic characteristics display of the FPGA board operation data collection are as follows: FPGA board operating status parameters are collected, the collected operating parameters are logged, and the log records and FPGA board operating status parameters are displayed in text and graphics.

[0076] The remote one-click upgrade link based on C / S architecture includes:

[0077] Establish a version update link based on the update bitstream to facilitate remote one-click upgrades when parameters / thresholds are updated, thereby reducing configuration work after each power-on.

[0078] The following is a specific example of data collection using the data collection platform of this application.

[0079] According to C / S architecture (see) Figure 1 Establish a host computer and a client-side built-in module that can acquire radar operation data.

[0080] The client's built-in module utilizes the Xilinx 7 series FPGA's built-in analog-to-digital converter (XADC) to establish environmental condition monitoring. The XADC integrates two ADC modules with a maximum sampling rate of 1MHz and a voltage of 1Vpp, capable of acquiring analog signals from external inputs or internal circuitry of the FPGA and converting them into digital signals. The XADC incorporates temperature and power sensors, allowing for the measurement of internal FPGA temperature and the voltages of the VCCINT, VCCBRAM, and VCCAUX power supplies without requiring any external input signals. By configuring the upper and lower limits of these monitored values, the detection and output of internal environmental fault conditions can be achieved.

[0081] Simultaneously, FPGA external interface logic is designed to convert level-type and heartbeat-type signals into pulse-type signals. Level-type signals include temperature signals, power supply voltage signals, and reference or feedback levels. After sampling, the level values ​​of these signals can be monitored. When the level value exceeds the limit (above the upper limit or below the lower limit), a fault pulse is output, thus converting it into a pulse-type signal. Heartbeat-type signals, such as clock signals, periodic interrupts, and timing signals, indicate a system-wide fault if they stop. By designing a counting circuit with a reset function and a counting over-limit comparison circuit, heartbeat signal monitoring is achieved. When the heartbeat signal stops at a specified time, a fault pulse is output, thus converting it into a pulse-type signal.

[0082] Pulse-type signals generally refer to fault indication signals where a low level indicates normal operation and a high level indicates a fault. To avoid false triggering during detection and improve system robustness, this design performs three-stage filtering on all fault signals converted into pulse-type signals. After filtering, all fault signals, environmental anomaly signals, and maintenance status trigger signals sent by the system are logically ORed to generate data recording pulses, recording the currently latched fault, environmental, and status data into a designated data area.

[0083] The design can support up to 8 external input sources and 6 internal environment sources.

[0084] The FPGA board can be simulated via network connection by starting up through host computer software. After receiving instructions from the host computer, the FPGA board simulates various hardware, software, and external fault modes for self-testing, while simultaneously monitoring faults and caching fault information. Upon receiving instructions from the host computer, it supports real-time status uploads or uploading of fault information from the cache. Each client machine generates its own ID based on the slot it is inserted into, enabling point-to-point communication with the server.

[0085] Due to platform upgrade requirements, this design incorporates a one-click upgrade function. The implementation principle utilizes the configuration solution technology provided by Xilinx FPGAs. We add a small amount of extra logic to the FPGA and program the configuration file received via the network into the configured FLASH device, fulfilling the requirement for remote data acquisition and solidification of FPGA logic. The FPGA requiring upgrade must implement a network interface, and all FPGA configuration files are stored uniformly on the host computer. To ensure programming security, a dual-insurance strategy is adopted: two programming configuration file areas are set in the FLASH. One area stores the basic configuration file, the gold bitstream, which is written at the factory and implements basic functions. The configuration file to be upgraded, the update bitstream, is located in the other area. Normally, each FPGA startup defaults to writing to and reading the update bitstream area, and subsequent updates involve rewriting the update bitstream. However, if the update bitstream is damaged or incomplete, and the FPGA fails to boot from the update bitstream, it will read the gold bitstream, allowing the FPGA to restore its factory configuration. Converting this function into a reprogramming function creates a relatively safe upgrade programming method.

[0086] Establish a remote data exchange interface with the host computer and system services: This project implements the remote data acquisition function using an Ethernet interface, but other systems can also achieve this through other networks or buses. Considering the lightweight design and the fact that current mainstream devices such as A7, K7, and V7 all have soft or hard cores for the network MAC layer, only a network PHY device and a network transformer need to be added externally to the FPGA. The FPGA and the network PHY device are connected via...

[0087] The MII_RMII_GMII_RGMII interface can easily implement 100 Mbps or 1 Gbps network interfaces to meet the needs of interface with the host computer.

[0088] Establishing a configuration device interface: When designing an FPGA board that requires remote data embedding and acquisition, the FPGA configuration method should typically be SPI or BPI. Considering upgrade security requirements, the configuration device needs to hold two configuration files. Therefore, when selecting a configuration device, a FLASH device with a capacity at least twice that of the FPGA configuration file should be chosen. For example, if the upgraded FPGA is an XC7K160T, the configuration manual indicates a configuration file size of 53Mbit. Therefore, at least 64Mb of FLASH is generally needed to store this configuration file. If used as a storage chip for remote data embedding and acquisition, 128Mb is required. Because the pins of FLASH devices with different capacities are designed for compatibility, the circuitry between the FPGA and the configuration device does not need to be modified to achieve remote data embedding and radar operation data acquisition and recording functions.

[0089] The FPGA's internal logic utilizes a MicroBlaze processor connected to the MAC layer. MicroBlaze handles network protocols, and each FPGA chip is configured with an IP address according to a pre-defined protocol, facilitating the reception of bitstream data files from the host computer. After receiving the network data, the MicroBlaze processor configures the FLASH programming logic and writes it into the FPGA's configuration device FLASH, thus completing the radar operation data acquisition and program embedding process. See the internal design block diagram below. Figure 3 .

[0090] To store the basic configuration file (gold bitstream) and the update bitstream file transmitted over the network in the configuration FLASH, based on the bitstream structure and the configuration process after FPGA power-on, we split the update bitstream into two parts. The synchronization word and the starting address are stored before the gold bitstream, and the rest are stored after the gold bitstream. A CRC checksum is also added to the end of the update bitstream. The main structure diagram of the remote upgrade file is shown below. Figure 4 .

[0091] The established host computer functional block diagram is shown below. Figure 2 .

[0092] The system consists of modules for communication, FPGA board monitoring and identification, fault information acquisition and statistics, configuration file upgrade and readback, and FPGA board working status indicator acquisition.

[0093] The "communication module" enables real-time online FPGA board searching; through the agreed application layer protocol, it enables the host computer software to issue commands such as writing configuration files, reading back configuration files or fault information, and collecting working status of the FPGA verification system, thereby realizing data transmission between the host computer software and the FPGA verification system.

[0094] The online "FPGA board detection and identification" function searches for online boards in real time, obtaining information such as board type, IP / MAC address, etc., and recording search logs. Using the board's MAC address or IP address as an ID, for new boards with no historical records, a folder named after the board ID is created, containing three subfolders: working status log, configuration file, and fault information. For boards with historical records, the relevant board information is loaded and displayed in a file tree format.

[0095] The board's "Fault Information Acquisition and Statistics" function sends commands to acquire radar operation data (or existing fault information files). It displays fault data in list and graph formats, categorized by fault type, fault duration, fault start time, fault end time, system temperature, and operating voltage. It calculates and displays six key performance indicators (MTTR, MTTF, MTBF, etc.) and performs correlation analysis and display of operating status parameters with different types of faults. Based on the start timestamp, it stores or updates fault information in .dat format files and provides an Excel file conversion function for fault information files. (See [link to relevant documentation]). Figure 5 .

[0096] "Board configuration file upgrade and readback" includes functions such as opening configuration files, remote upgrade, remote readback, local storage, and file comparison.

[0097] "Board Operating Status Acquisition" can independently collect board operating environment data in real time, record it in log form, and display it in real time as a graph. It supports reviewing log files and displaying graphs, such as... Figure 6 As shown.

[0098] This software adopts a client / server (C / S) architecture. It also considers the potential future cross-platform requirements of Windows / Linux, and the possibility of switching to a browser / server (B / S) architecture to support multiple concurrent services. The management application is developed using Java, providing a simple and user-friendly interface while ensuring data reliability and security, and creating conditions for future cross-platform system applications and B / S architecture porting.

[0099] In addition, the system design incorporates a fault simulation environment, which can simulate the following faults:

[0100] Over-temperature fault;

[0101] Overvoltage fault;

[0102] FPGA input fault;

[0103] Internal logic failure;

[0104] The software interface commands and data between the host computer and the client include command data in Tables 1 to 4, as well as interface data tables such as configuration registers, uploaded data formats, and fault maintenance status.

[0105] Table 1: Interface Commands

[0106]

[0107] Table 2: Operating Status Register

[0108]

[0109] Table 3: Register Configuration (Output Data)

[0110]

[0111]

[0112] Table 3: ID

[0113]

[0114] Table 4: Version Upgrade (Output Data)

[0115]

[0116] This invention establishes a radar operation data acquisition platform based on programmable logic. While achieving automated acquisition of radar operation data, it also leverages the advantages of programmable logic to enable remote upgrades. This ensures the completeness and accuracy of the acquired operation data, bringing benefits to the analysis of operation data from ultra-large digital systems like radar.

[0117] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A radar operation data acquisition platform based on programmable logic, characterized in that: It includes a radar operation data acquisition circuit based on programmable logic and selectable signal forms, a logic link based on C / S architecture for command issuance and data upload, and a remote one-click upgrade link based on C / S architecture. The radar operation data acquisition circuit triggers the recording function at any time the fault state changes to collect radar operation information. The logic link realizes the issuance and data upload of configuration commands, data upload commands, and fault self-test commands. The remote one-click upgrade link will burn the configuration file received through the network into the configured FLASH device to realize the remote solidification and download of FPGA logic data. Radar operation data acquisition circuits based on programmable logic and selectable signal formats include: Signal format configuration conversion circuit: Distinguishes external fault identification signals, uses configuration logic to convert level-type and heartbeat-type fault signals into pulse-type fault signals, and performs logical combination to form external fault indication signals; Radar operation data acquisition trigger circuit: It completes the monitoring and sampling of internal temperature and voltage parameters, compares them with the fault threshold, and generates an internal abnormality trigger signal after three-level filtering; it performs three-level filtering on the external fault indication signal; and it logically ORs the internal and external trigger signals to form the final data acquisition trigger signal. Radar operation data acquisition and storage circuit: When the data acquisition trigger signal is detected to have a change in state, the radar operation data is sampled in real time; after being latched, the data can be recorded in a designated storage unit via a storage link. If there is a host computer upload command, the real-time data can be uploaded to the host computer according to the command, or the data in the designated storage unit can be uploaded for conversion, recording and display. Radar operation data recording standards: Establish radar operation data recording format; The signal format configuration conversion circuit includes: For level-type signals, level sampling is performed; upper and lower limit level values ​​are configured. When the sampled level value exceeds the upper limit, an overvoltage mark pulse is output, and when the sampled level value is lower than the lower limit, an undervoltage mark pulse is output, thus converting it into a pulse-type signal. The accuracy of the configured upper and lower limit level values ​​is no greater than 0.1V. For heartbeat-type signals, the longest allowable period value is configured to be no more than 1.2s with an accuracy of 0.1μs. Using a counting device, when no heartbeat is detected within the longest allowable period, a no-heartbeat fault marker pulse is triggered, thereby converting it into a pulse-type signal. The radar operation data acquisition and storage circuit includes: The kernel module of the programmable device is used to sample environmental parameters to record radar operation-related data, namely sampling FPGA temperature and various operating voltages, while retaining one internal control parameter monitoring channel, and comparing each parameter with the specified parameter threshold to form the parameter trigger signals for internal environmental abnormal faults. These signals are then filtered in three stages to eliminate the risk of false triggering and form the internal environmental abnormal trigger signal. The acquisition circuit also decodes commands sent from the host computer management system and generates a system trigger signal, which is used to trigger the maintenance status. After performing three-stage filtering on the external trigger signal to eliminate the risk of false triggering, it is logically combined with the internal environment abnormal trigger signal and the system trigger signal to form the data acquisition trigger signal. The minimum time interval for three-stage filtering is no greater than 0.1 μs.

2. The radar operation data acquisition platform based on programmable logic according to claim 1, characterized in that: The radar operation data acquisition trigger circuit includes: This circuit latches the radar operation data in real time at the point where the trigger signal is acquired; The date and time data are synchronized uniformly after the platform is powered on, and then counted automatically by the acquisition module; the platform can also perform uniform synchronization during operation. The acquisition trigger signal simultaneously triggers the recording link, recording the latched radar operation data into the designated storage unit; When the host computer issues an upload command, it can upload latched data or the current status in real time according to the command.

3. The radar operation data acquisition platform based on programmable logic according to claim 2, characterized in that: The real-time latched radar operation data includes fault source code, fault number, date data, time data, temperature detection value, and voltage detection value.

4. The radar operation data acquisition platform based on programmable logic according to claim 1, characterized in that: The radar operation data recording specifications include: establishing a working status register, configuring the status register, the time status register, and the matching command data format to complete the various functions of the platform.

5. The radar operation data acquisition platform based on programmable logic according to claim 1, characterized in that: The logical link for command issuance and data upload based on the C / S architecture includes: establishing host computer management software to realize graphical interface management; establishing an exchange system and a multi-module ID identification mechanism, which can be independently configured through ID; and using broadcast mode to send data to realize the sending of specific data across all modules.

6. The radar operation data acquisition platform based on programmable logic according to claim 5, characterized in that: The host computer management software includes: Real-time online search and location of FPGA boards; Online FPGA board detection and identification; Board fault information acquisition and statistics: Obtain board buffer fault information, form a local fault information file, and perform graphic and text display, local storage, file conversion and statistical analysis based on the board buffer fault information and the local fault information file; Board configuration file upgrade and readback: Read back the FPGA board configuration file and store it; upgrade the configuration file, read the local configuration file, and compare the configuration files; The download and basic characteristics display of the FPGA board operation data collection are as follows: FPGA board operating status parameters are collected, the collected operating parameters are logged, and the log records and FPGA board operating status parameters are displayed in text and graphics.

7. The radar operation data acquisition platform based on programmable logic according to claim 1, characterized in that: The remote one-click upgrade link based on the C / S architecture includes: establishing a version update link based on the update bitstream, which facilitates remote one-click upgrades when parameters / thresholds are updated, thereby reducing the configuration work after each power-on.

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