Processing systems, related integrated circuits, devices, and methods

Abstract

Processing systems, related integrated circuits, devices and methods are disclosed. A slave responds to a master read request by providing second data bits and ECC bits. First data bits are generated by selecting between the second data bits and third data bits generated by error correction on the second data bits. The third data bits are generated with a one clock cycle delay relative to the second data bits. If the address of the read request is stored to memory, a control signal is set indicating that the first data bits are invalid, and this drives the selection of the third data bits (the first data bits are now valid in the next clock cycle). If an error signal is asserted when the address is not stored to memory, action is taken to store the address to memory and another control signal is set to indicate that the read request should be repeated.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Italian patent application No. 102022000004046, filed on March 3, 2022, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] Embodiments of this disclosure relate to error correction within processing systems such as microcontrollers. Background Technology

[0004] Figure 1 An electronic system, such as the electronic system of a vehicle, is shown, including multiple processing systems (PS) 10, such as embedded systems or integrated circuits, such as field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or microcontrollers (e.g., dedicated to the automotive market).

[0005] For example, in Figure 1 The diagram illustrates three processing systems 101, 102, and 103 connected via a suitable communication system 20. For example, the communication system may include a vehicle control bus, such as a Controller Area Network (CAN) bus, and possibly a multimedia bus, such as a Media-Oriented System Transport (MOST) bus, connected to the vehicle control bus via a gateway. Processing systems 10 may be located, for example, in different locations within the vehicle, and may include, for example, an engine control unit, a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system. Therefore, one or more processing systems 10 may also implement real-time control and adjustment functions. These processing systems are generally identified as electronic control units.

[0006] Figure 2 A block diagram of an exemplary digital processing system 10 is shown, such as a microcontroller, which can be used as... Figure 1 Any processing system 10.

[0007] In the considered example, the processing system 10 includes a microprocessor (MP) 102, typically a central processing unit (CPU) programmed via software instructions. Typically, the software executed by the microprocessor 102 is stored in non-volatile program memory (Mem) 104, such as flash memory or EEPROM. Therefore, memory 104 is configured to store the firmware of the processing unit 102, which includes software instructions to be executed by the microprocessor 102. Typically, non-volatile memory 104 can also be used to store other data, such as configuration data or calibration data.

[0008] The microprocessor 102 also typically has an associated volatile memory (Vmem) 104b, such as random access memory (RAM). For example, memory 104b can be used to store temporary data.

[0009] like Figure 2 As shown, communication with the memories 104 and / or 104b is typically performed via one or more memory controllers (MCs) 100. The memory controllers 100 may be integrated into the microprocessor 102 or connected to the microprocessor 102 via a communication channel (e.g., the system bus of the processing system 10). Similarly, the memories 104 and / or 104b may be integrated with the microprocessor 102 in a single integrated circuit, or the memories 104 and / or 104b may be in the form of separate integrated circuits and connected to the microprocessor 102, for example, via traces on a printed circuit board.

[0010] In the example under consideration, microprocessor 102 may have one or more associated (hardware) resources / peripherals 106 selected from the following group:

[0011] - For example, one or more communication interfaces IF used for exchanging data via communication system 20, such as Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface Bus (SPI), Internal Integrated Circuit (I) 2 C) Controller Area Network (CAN) bus, and / or Ethernet interface, and / or debug interface; and / or

[0012] - One or more analog-to-digital converters (AD) and / or digital-to-analog converters (DA); and / or

[0013] - One or more dedicated digital components (DCs), such as hardware timers and / or counters, or cryptographic coprocessors; and / or

[0014] - One or more analog components AC, such as comparators, sensors, such as temperature sensors, etc.; and / or

[0015] - One or more mixed signal component MSCs, such as PWM (Pulse Width Modulation) drivers.

[0016] Typically, the dedicated digital component DC may also correspond to an FPGA integrated in the processing system 10. For example, in this case, the memory 104 may also include program data for such an FPGA.

[0017] Therefore, the digital processing system 10 can support different functions. For example, the behavior of the microprocessor 102 is determined by firmware stored in the memory 104, such as software instructions executed by the microprocessor 102 of the microcontroller 10. Thus, by installing different firmware, the same hardware (microcontroller) can be used for different applications.

[0018] In this regard, future generations of this processing system 10, such as microcontrollers suitable for use in automotive applications, are expected to exhibit increased complexity, primarily due to the increased number of requested functions (new protocols, new features, etc.) and stricter constraints on execution conditions (e.g., lower power consumption, increased computing power and speed, etc.).

[0019] For example, more sophisticated multi-core processing systems have recently been proposed. For instance, such multi-core processing systems can be used to execute (in parallel)... Figure 1 The shown are several processing systems 10, such as several ECUs of a vehicle.

[0020] Figure 3 An example of a multi-core processing system 10 is shown. Specifically, in the considered example, the processing system 10 includes a plurality of n processing cores (PCs) 1021, ..., 102 connected to a (on-chip) communication system 114. n For example, in the context of a real-time control system, processing cores 1021, ..., 102... n It can be ARM -R52 core. Typically, the communication system 114 may include one or more bus systems, such as those based on the Advanced Scalable Interface (AXI) bus architecture and / or Network on Chip (NoC).

[0021] For example, as illustrated in the example of processing core 1021, each processing core 102 may include a microprocessor (m) 1020 and a communication interface (i) 1022, which is configured to manage communication between the microprocessor 1020 and the communication system 114. Typically, interface 1022 is a master interface, configured to forward a given (read or write) request from the microprocessor 1020 to the communication system 114 and to forward an optional response from the communication system 114 to the microprocessor 1020. However, communication interface 1022 may also include slave interfaces. For example, in this way, a first microprocessor 1020 may send a request to a second microprocessor 1020 (via the communication interface 1022 of the first microprocessor, the communication system 114, and the communication interface 1022 of the second microprocessor).

[0022] Typically, each processing core has 1021, ..., 102 kilometres. n It may also include additional local resources, such as one or more local memories 1026, which are typically identified as tightly coupled memory (TCM).

[0023] As mentioned earlier, cores 1021, ..., 102 are typically processed. nIt is arranged to exchange data with non-volatile memory 104 and / or volatile memory 104b. In the multi-core processing system 10, these memories are typically system memories, i.e., for processing cores 1021, ..., 102 n Shared. As mentioned earlier, however, each processing core 1021, ..., 102 n It may include one or more additional local memories 1026.

[0024] For example, such as Figure 3 As shown, the processing system 10 may include one or more memory controllers 100 configured to connect at least one non-volatile memory 104 and at least one volatile memory 104b to the communication system 114. As previously described, one or more of the memories 104 and / or 104b may be integrated into an integrated circuit of the processing system 10 or externally connected to an integrated circuit.

[0025] As previously described, the processing system 10 may include one or more resources 106, such as one or more communication interfaces or coprocessors (e.g., cryptographic coprocessors). Resources 106 are typically connected to the communication system 114 via a corresponding communication interface (i) 1062. Generally, the communication interface 1062 includes at least a slave interface. For example, in this way, the processing core 102 can send a request to the resource 106, and the resource returns the given data. Typically, one or more of the communication interfaces 1062 may also include a corresponding master interface. For example, such a master interface may be useful where a resource must initiate communication to exchange data with another circuit (e.g., resource 106 or processing core 102) connected to the communication system 114 via (read and / or write) requests. For example, for this purpose, the communication system 114 may actually include an Advanced Microcontroller Bus Architecture (AMBA) High Performance Bus (AHB) and an Advanced Peripheral Bus (APB) for connecting the resource / peripheral device 106 to the AMBA AHB bus.

[0026] Typically, such a processing system 10 also includes one or more direct memory access (DMA) controllers 110. For example, as Figure 3 As shown, the DMA controller 110 can be used to exchange data directly with memory (e.g., memory 104b) based on requests received from resource 106. For example, in this way, the communication interface IF can directly read data from memory 104b (via the DMA controller 110) and send that data without having to exchange further data with processing unit 102. Typically, the DMA controller 110 can communicate with one or more memories via communication system 114 or via one or more dedicated communication channels.

[0027] Typically, this processing circuitry also includes one or more circuits configured to verify error correction codes (ECC).

[0028] For example, Figure 4 and Figure 5 A general processing system 10 is shown, comprising a master device 40 and a slave device 42, wherein the master device 40 and the slave device 42 use a conventional ECC protection scheme.

[0029] Specifically, in Figure 4 In this process, the master circuit 40 sends data DATA to the slave device 42. Specifically, the slave device 42 receives the data bits DATA and additional error correction code bits ECC generated by the error correction code generation circuit (ECCG) 44, which is configured to generate ECC bits based on the data bits DATA.

[0030] For example, in various embodiments, the master device 40 may be a processing core 102, particularly a microprocessor 1020 or a DMA controller 110. Conversely, the slave device 42 may be a memory, such as non-volatile memory 104 or volatile memory, such as RAM memory 104b or TCM 1026. For example, error correction code generation circuitry 44 may be integrated into the memory controller of memory 42. For a general description of these circuits and the corresponding processing system 10, refer to... Figures 1 to 3 As previously described. For example, microprocessor 1020 or DMA controller 110 (master device 40) may send a write request including data DATA to memory controller 100 via communication system 114, and / or send a write request including data DATA to memory controller of TCM 1026 via a dedicated communication system within processing core 102. The memory controller may then calculate bit ECC via corresponding error correction code generation circuit 44 and write the data bits DATA and bit ECC to memory, for example, to the memory address included in the write request.

[0031] On the contrary, Figure 5 In this circuit, the master circuit 40 receives given data DATA from the slave device 42. Specifically, the slave device 42 provides data bits DATA and additional error correction code bits ECC.

[0032] For example, for this purpose, the microprocessor 1020 or DMA controller 110 (master device 40) may send a read request to the memory controller 100 via communication system 114, and / or send a read request to the memory controller of TCM 1026 via a dedicated communication system within processing core 102. The memory controller may then read the data bits DATA and ECC bits from memory (e.g., from the memory address included in the read request) and send the data bits DATA to the microprocessor 1020 or DMA controller 110.

[0033] However, as Figure 5 As shown, in this configuration, the error detection circuit (ED) 46 is configured to verify the DATA and ECC bits and may generate one or more error signals ERR. For example, one or more error signals ERR may be provided to the main circuit 40 and / or the fault collection and error management circuit (ERR) 120.

[0034] For example, error detection circuit 46 can be integrated into memory controller 100. Specifically, in the case of a simple error detection circuit 46, this circuit only verifies the correctness of bits DATA and ECC. However, error detection circuit 46 can also provide information about the location of errors, so error correction circuitry can use this information to correct errors in data bits DATA. Typically, error correction circuitry can be integrated with error detection circuitry in error detection and correction circuitry 46, or error correction circuitry can be a separate circuit. Thus, circuitry 46 can indeed provide corrected data bits DATA to master device 40.

[0035] Furthermore, this ECC scheme can also be used for communication exchanged via communication system 114. For example, a bus master such as interface 1022 can add an ECC bit to a request sent via communication system 1144. Therefore, a receiver slave circuit such as from interface 1062 can verify the ECC bit to detect errors in the sent request. Typically, such an ECC bit can be verified for each of the address, data, and control information in the request, or a combination of these, by appropriate error detection circuitry.

[0036] Typically, the number K of ECC bits depends on the number N of DATA bits and the ECC scheme, for example, how many bits can be corrected. Therefore, depending on the complexity of the implemented error correction code (ECC), circuit 46 can detect up to a given number of flipped bits and ultimately correct them. For example, in the field of microcontrollers for the automotive market, the ECC schemes employed are typically capable of detecting up to two error bits and correcting one error bit using so-called single error correction (SEC) double error detection (DED) codes. For a general description of error detection and optional correction codes, refer to the corresponding Wikipedia page "Error detection and correction," e.g., the version dated May 6, 2021, the contents of which are incorporated herein by reference. Application Note XAPP383 "Single Error Correction and Double Error Detection (SECDED) with CoolRunner-II" TMA possible implementation of the SECDED code is described in "CPLDs", v1.1, August 1, 2003 (incorporated herein by reference). Another possible error detection and correction circuit using the SECDED code is disclosed in U.S. Patent No. 8,381,083 B2 (incorporated herein by reference). That document also discloses that the bit ECC can be calculated for other data, such as data DATA and the corresponding address.

[0037] in this regard, Figure 6 An embodiment of an error detection circuit 46 suitable for use in the SECDED scheme is shown, for example, as used in an ARM Cortex R52 microcontroller.

[0038] Specifically, in the considered embodiment, the error detection circuit 46 includes a checksum calculation circuit 460 configured to: receive data bits DATA and ECC bits; calculate the ECC bits of the received data bits DATA; and compare the calculated ECC bits with the received ECC bits.

[0039] In the case of error-correcting codes, the result of this comparison is called the syndrome SYN, which indicates the location of the incorrect bit in the event of a single bit error. Therefore, the syndrome SYN corresponds to a bit sequence with K bits. Specifically, an error is detected when the syndrome SYN differs from a bit sequence of K bits set to zero, i.e., differs from the value 0. For example, this is in... Figure 6 The diagram schematically illustrates that a logic gate 464, such as a logic OR gate, is used to generate an error signal ERR1 based on the check SYN, that is, the error signal ERR1 is asserted when at least one of the bits of the check SYN is asserted.

[0040] Typically, the specific implementation of the error detection circuit 46 can depend on the ECC scheme used. For example, in the case of SEC codes, the checksum calculation circuit 460 may often fail to detect double-bit errors. In fact, the error signal ERR1 will be asserted for both single-bit and double-bit errors. Therefore, in various embodiments, the error correction code verification circuit 46 may also include a circuit (SBE) 462 configured specifically to detect single-bit errors. For example, in the simplest case, the single-bit error detection circuit 462 may verify even or odd parity, thereby generating a signal SB indicating that a single-bit error has occurred. For example, in this case, the bit ECC may include one or more dedicated parity bits, which may not be provided to the checksum calculation circuit 460.

[0041] In this situation, the single-bit error detection circuit 462 may not be able to distinguish between correct data and double-bit errors. Therefore, by combining the error signal ERR1 (indicating a single-bit error or a double-bit error) and the signal SB (indicating a single-bit error), a signal ERR2 indicating a double-bit error can be generated via combinational logic circuitry, for example, by asserting the error signal ERR2 when the error signal ERR1 is asserted and the signal SB is deasserted. For example, in the considered embodiment, the combinational logic circuitry includes an inverter 468 and a logic AND gate 470.

[0042] Therefore, error detection circuit 46 can be configured to use checksum SYN and bit SB to generate a single bit error signature SIG with N+K bits. For example, in the considered embodiment, this operation is implemented in single bit error detection circuit 462. Specifically, in the case of a single bit error, i.e., when signal SB is asserted, circuits 46 / 462 are configured to assert the bit of signal SIG corresponding to the position indicated by checksum SYN, while the other bits of signal SIG are deasserted.

[0043] Since circuit 462 does not directly provide signal SB, the corresponding signal SB can be generated by logical combination of the bits of signal SIG, for example by logic OR gate 466, because at most one bit of signal SIG should be asserted.

[0044] Typically, other ECC schemes can also be used to generate the bit-flipped signature SIG, which can also indicate, for example, that more than one bit should be flipped in the case of a double error correction code. Similarly, in this case, error signals ERR1 and ERR2 can typically indicate that an error has occurred (error signal ERR1), and optionally indicate whether the error is correctable (error signal ERR2).

[0045] In fact, what these solutions have in common is that the error detection circuit 46 is configured to compare the checksum SYN with a plurality of reference checksums, each of which corresponds to a given bit-flipped signature SIG. Therefore, when the checksum SYN corresponds to a reference checksum, the error detection circuit 46 can assert individual bits of the erroneous signature SIG. For example, in the case of a SECDED code, the error detection circuit would use N+K reference checksums, each corresponding to a specific single-bit error. For example, the verification of the reference signature and the setting of the signature SIG (and the error signal) can be implemented via combinational logic circuitry. In this respect, by using a suitable SECDED ECC code, each reference checksum associated with a single-bit error can also have a unique pattern compared to a double-bit-flipped error.

[0046] Therefore, the error detection circuit 46 is typically configured as follows:

[0047] - No error signal is issued when all bits of the check SYN are deasserted (e.g., by deasserting error signals ERR1 and ERR2);

[0048] - When the checksum SYN corresponds to one of the reference checksums (e.g., a single bit error) (e.g., via the assertion error signal ERR1 and the deassertion error signal ERR2), a correctable error signal is emitted, and the individual bits of the bit-flipped signature SIG are also asserted; and

[0049] - When at least one bit of the check SYN is asserted and the check SYN does not correspond to any reference check, an uncorrectable error is indicated by a signal (e.g., by asserting error signals ERR1 and ERR2).

[0050] Therefore, in various embodiments, signals ERR1, ERR2, and SIG can be provided to error correction circuitry, for example, implemented in a memory controller. Thus, the error correction circuitry can:

[0051] - In the absence of an error signal (e.g., signal ERR1 is deasserted and signal ERR2 is deasserted), the raw data DATA is provided to the requesting master device, for example, by sending data DATA to communication system 114;

[0052] - In the case of a correctable bit error (e.g., signal ERR1 is asserted while signal ERR2 is deasserted), toggle the logic level of the corresponding bit, especially in the case of the data bit DATA, as indicated by the signature SIG, and provide the corrected data DATA to the requesting master device 40; and

[0053] In the event of an uncorrectable bit error (e.g., signal ERR1 is asserted and signal ERR2 is asserted), an error signal is sent to the requesting master device and / or the fault collection and error management circuitry 120.

[0054] Therefore, the error detection and correction circuitry can be complex combinational logic circuitry that introduces additional propagation delays to verify the DATA and ECC bits. Those skilled in the art will understand that these delays in the path between the master circuitry 40 and the slave circuitry 42 limit the clock frequency in the processing system 10, for example, limiting the clock frequency of the processing core 102 in the case of TCM 1026, or limiting the clock frequency of at least the communication system 114 in the case of communication with the memory controller 100.

[0055] In this regard, two common solutions can be used to increase the clock frequency of the processing system 10:

[0056] - Use faster circuitry, such as faster memory; and / or

[0057] - A pipelined architecture is used, in which memory read access is performed in the first clock cycle and ECC verification is performed in the second (waiting) state.

[0058] However, the first solution typically means a larger area and higher power consumption, while the second solution results in lower overall system performance, especially in the case of the TCM memory 1026, which is required to provide read / correct data DATA within one clock cycle. Summary of the Invention

[0059] In view of the above, various embodiments of this disclosure provide solutions for improving the performance of processing systems including one or more ECC error detection and correction circuits.

[0060] One or more embodiments relate to processing systems. Embodiments also relate to related integrated circuits, devices, and methods.

[0061] As previously described, various embodiments of this disclosure relate to, for example, processing systems integrated into integrated circuits. Such processing systems include master circuitry, slave circuitry, and error detection and correction circuitry. For example, the master circuitry may be a microprocessor, and the slave circuitry may be tightly coupled memory. For example, the microprocessor may be an ARM-based microprocessor, such as an ARM Cortex-M7 processor.

[0062] In various embodiments, the main circuit is configured to generate a read request including an address, wherein the main circuit is configured to signal the read request by asserting a first control signal (e.g., a request signal). The main circuit is also configured to receive N (first) data bits, a second control signal, and a third control signal. Specifically, the main circuit is configured to determine the logic level of the second control signal, such as a wait signal, wherein a corresponding first logic level indicates that the N (first) data bits contain valid data, and a corresponding second logic level indicates that the N (first) data bits do not contain valid data. Furthermore, the main circuit is configured to determine the logic level of a third control signal, such as a RETRY signal, wherein a corresponding first logic level indicates that the read request should be repeated, and a corresponding second logic level indicates that the read request should not be repeated. Therefore, in response to determining that the second control signal has a corresponding first logic level, the main circuit reads N (first) data bits, and in response to determining that the third control signal has a corresponding first logic level, the main circuit repeats the read request.

[0063] In various embodiments, the slave circuitry is configured to receive a read request and, in response to determining that a first control signal is asserted, provide N (second) data bits and K ECC bits associated with an address included in the read request. Typically, the address associated with the read request may correspond to the address contained in the read request, or the processing system may include an address decoder configured to determine the address associated with the read request by mapping the address contained in the read request.

[0064] In various embodiments, the error detection and correction circuitry is configured to receive a read request from the master circuitry, and N (second) data bits and K ECC bits from the slave circuitry. Furthermore, the error detection and correction circuitry is configured to provide the master circuitry with N (first) data bits, a second control signal, and a third control signal. Specifically, in various embodiments, the error detection and correction circuitry includes a multiplexer configured to provide the master circuitry with N (first) data bits by selecting N (second) data bits received from the slave circuitry when a selection signal has a corresponding first logic level, and by selecting N additional (third / corrected) data bits generated by the error detection and correction circuitry when a selection signal has a corresponding second logic level. Specifically, in various embodiments, the error detection and correction circuitry is configured to generate additional N (third / corrected) data bits by processing the N (second) data bits and K ECC bits received from the slave circuitry to determine whether the N (second) data bits do not contain errors or contain one or more correctable bit errors. In response to determining that the N (second) data bits received from the slave circuit include one or more correctable bit errors, the error detection and correction circuit asserts an error signal and generates a bit-flip signature having bits asserted at the locations of the one or more correctable bit errors. In this case, the error detection and correction circuit can generate an additional N (third / correction) data bits by flipping the bits of the N (second) data bits received from the slave circuit at the locations where the bits of the bit-flip signature are asserted.

[0065] Specifically, in various embodiments, the error detection and correction circuitry includes a pipelined architecture whereby N additional (third / corrected) data bits are generated with a one-clock-cycle delay relative to the corresponding N (second) data bits provided by the slave circuitry. For example, the pipelined architecture of the error detection and correction circuitry can be implemented by a register configured to store the N (second) data bits and K ECC bits provided by the slave circuitry, or by a register configured to store an error signal and a bit-flipping signature.

[0066] As will be described in more detail below, in various embodiments, the error detection and correction circuitry includes a memory and control circuitry including a first sub-circuit and a second sub-circuit. The first sub-circuit is configured to monitor a first control signal to detect a read request. In response to detecting a read request, the first sub-circuit determines the address associated with the read request and verifies whether the address associated with the read request has been stored in the memory.

[0067] In response to determining that the address associated with the read request is not stored in memory, the first sub-circuit sets the logic level of the select signal to a corresponding first logic level, thereby enabling the multiplexer to provide N (second) data bits received from the slave circuit. Furthermore, the first sub-circuit sets the logic level of the second control signal to a corresponding first logic level indicating that the N (first) data bits provided to the master circuit contain valid data.

[0068] Conversely, in response to determining that the address associated with the read request is stored in memory, the first sub-circuit sets the logic level of the second control signal to the corresponding second logic level within one clock cycle, indicating that the N first data bits do not contain valid data. Furthermore, the first sub-circuit sets the logic level of the select signal to the corresponding second logic level, thereby providing the multiplexer with an additional N (third / correction) data bits to the main circuit. However, in this case, the first sub-circuit only sets the logic level of the second control signal to the corresponding first logic level indicating that the N (first) data bits contain valid data within the next clock cycle, thereby the main circuit only samples the N (first) data bits containing valid data within the next clock cycle.

[0069] Conversely, the second sub-circuit manages the storage of addresses into memory. Specifically, in various embodiments, the second sub-circuit is configured to monitor error signals. In response to determining that an error signal has been asserted, the second sub-circuit verifies whether the address associated with the read request has been stored in memory.

[0070] Specifically, in response to determining that the address associated with the read request is not stored in memory, the second sub-circuit stores the address associated with the read request in memory. Furthermore, the second sub-circuit sets the logic level of a third control signal to a corresponding first logic level, which indicates that the read request should be repeated. For example, the memory may have a given number of memory slots. In this case, the second sub-circuit may manage the memory as a ring memory and store the address associated with the read request in the next memory slot of the ring memory. Optionally, the second sub-circuit may associate corresponding further data with each uniform address stored in a given memory slot, specifying the number of occurrences and / or the last access time.

[0071] Conversely, in response to determining that the address associated with the read request has been stored in memory, the second sub-circuit sets the logic level of the third control signal to the corresponding second logic level, indicating that the read request should not be repeated.

[0072] In various embodiments, the error detection and correction circuitry can also be configured to process N (second) data bits and K ECC bits received from the slave circuitry to determine whether the N second data bits include an uncorrectable bit error, and in response to determining that the N second data bits include an uncorrectable bit error, assert another error signal. In this case, in response to determining that another error signal is asserted, the second sub-circuit can also set the logic level of the third control signal to a corresponding first logic level indicating that a read request should be repeated.

[0073] Therefore, in various embodiments, when the processing system generates a first read request, including a given address and containing erroneous data, via the master circuit, the slave circuit provides N (second) data bits and K error ECC bits associated with the given address within a first clock cycle. Furthermore, the first sub-circuit determines that the address associated with the first read request is not stored in memory, sets the logic level of the select signal to a corresponding first logic level, thereby enabling the multiplexer to provide the N (second) data bits received from the slave circuit and set the logic level of the second control signal to a corresponding first logic level, indicating that the N (first) data bits provided to the master circuit contain valid data.

[0074] However, in the subsequent second clock cycle, the second sub-circuit then determines that an error signal has been asserted and that the address associated with the read request has not been stored in memory, and accordingly stores the address associated with the read request in memory, and sets the logic level of the third control signal to the corresponding first logic level indicating that the read request should be repeated.

[0075] Therefore, in response to the third control signal being set to the corresponding first logic level, the processing system generates a second read request via the main circuit, including a given address. This causes the slave circuit to provide N (second) data bits and K error ECC bits associated with the given address in the third clock cycle. Furthermore, the first sub-circuit determines that the address associated with the second read request is stored in memory and sets the logic level of the second control signal to the corresponding second logic level indicating that the N first data bits do not contain valid data. Therefore, in the subsequent fourth clock cycle, the first sub-circuit sets the logic level of the select signal to the corresponding second logic level, thereby the multiplexer provides N further (third / corrected) data bits and sets the logic level of the second control signal to the corresponding first logic level, indicating that the N first data bits contain valid data. Attached Figure Description

[0076] Embodiments of this disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting example, in which:

[0077] Figure 1 An example of an electronic system including multiple processing systems is shown;

[0078] Figure 2 and Figure 3 An example of a processing system is shown;

[0079] Figure 4 An example of a processing system configured to generate ECC bits based on data bits is shown;

[0080] Figure 5 An example of a processing system configured to use ECC bits to detect and optionally correct errors in data bits is shown;

[0081] Figure 6 It shows that it is suitable for use in Figure 5 An example of an error detection circuit used in a processing system;

[0082] Figure 7 A first example of an error detection and correction circuit is shown;

[0083] Figure 8 A second example of an error detection and correction circuit is shown;

[0084] Figure 9 An embodiment of an error detection and correction circuit according to the present disclosure is shown;

[0085] Figure 10 It shows Figure 9 The operation of the first sub-circuit of the error detection and correction circuit; and

[0086] Figure 11 It shows Figure 9 The operation of the second sub-circuit of the error detection and correction circuit. Detailed Implementation

[0087] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. The embodiments may be implemented without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring various aspects of the embodiments.

[0088] In this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the appearance of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0089] The headings provided herein are for convenience only and do not define the scope or meaning of the embodiments.

[0090] In the following Figures 7 to 11 In the middle, it has been referenced Figures 1 to 6 The parts, elements or components described are indicated by the same reference numerals previously used in the figure; in order not to burden this detailed description, the description of such previously described elements will not be repeated below.

[0091] As previously described, various embodiments of this disclosure relate to solutions for improving the performance of a processing system 10a, including ECC error detection and correction circuitry.

[0092] Figure 7 An example of a processing system 10a including an error detection circuit (ED) 46 and an error correction circuit 48 is shown.

[0093] Typically, in this case, the master circuit 40 receives the given data DATA from the slave device 42. Specifically, the slave device 42 provides the data bits DATA and additional error correction code bits ECC.

[0094] For example, the main circuit 40, such as microprocessor 1020 or DMA controller 110, can be configured to send a read request including address ADR. Figure 7 As illustrated, in order to generate a read request, the master device 40 may also generate one or more control signals CTRL. For example, the control signal CTRL may indicate to execute the request, for example, by using a request signal, and optionally, for example, by using a read / write signal to execute a read or write request.

[0095] For example, the slave device 42 may be: internal circuitry of the processing core 102 of the microprocessor 1020 connected to the processing core 102 via a dedicated communication system (e.g., TCM 1026) of the processing core 102; or circuitry connected to the communication system 114, such as memory controller 100 or resource / peripheral device 106.

[0096] Therefore, in various embodiments, read requests can be sent, for example, to the memory controller 100 via the communication system 114, and / or to the TCM 1026 via a dedicated communication system within the processing core 102.

[0097] Therefore, the slave device 42 associated with address ADR receives a read request, obtains the corresponding data DATA associated with address ADR, and provides the data DATA to the master circuit 40. For example, in the case of memory (e.g., 104, 104b, and / or 1026), the memory can return the data stored in the memory location associated with address ADR. As previously described, the slave device 42 provides not only the data bits DATA but also additional ECC bits. For example, as described above, in the case of memory, the ECC bits can be stored together with the corresponding data bits DATA.

[0098] Specifically, in the considered embodiment, the processing system 10a further includes an error detection circuit 46 configured to verify the DATA and ECC bits. Specifically, for this purpose, the error detection circuit 46 is configured to: receive the DATA and ECC bits from the slave circuit 42; calculate the ECC bit of the received DATA; and generate a checksum SYN by comparing the calculated ECC bit with the received ECC bit.

[0099] Furthermore, the error detection circuit 46 is configured to generate one or more error signals ERR, wherein the error detection circuit 46 is configured to: not issue an error signal via one or more error signals ERR when all bits of the check SYN are deasserted; issue a correctable error signal via one or more error signals ERR when the check SYN corresponds to one of a plurality of (e.g., a single bit error) reference check SYN; and optionally, issue an uncorrectable error signal via one or more error signals ERR when at least one bit of the check SYN is asserted and the check SYN does not correspond to any reference check SYN.

[0100] In the considered embodiment, error detection circuit 46 also generates a bit-flipped signature SIG. Therefore, in the case of a correctable error, error detection circuit 46 can assert the individual bits of the bit-flipped signature SIG associated with the detected reference checksum. Thus, for a general description of circuits 40, 42, and 46, refer to... Figures 1 to 6 The previous description.

[0101] In the considered embodiment, one or more error signals ERR and signature SIG are provided to error correction circuit 48. Specifically, error correction circuit 48 is configured to generate correction data CDATA when one or more error signals ERR emit a correctable error signal. For example, for this purpose, error correction circuit 48 can determine the bits of the asserted signature SIG and generate signal CDATA by inverting the corresponding bits of data signal DATA. Thus, error correction circuit 48 can be implemented, for example, by N logic XOR gates, where each XOR gate receives the corresponding bits of signal DATA and signature SIG at its input and provides the corresponding bits of signal CDATA at its output.

[0102] Therefore, as schematically shown via a multiplexer 50 that can also be implemented directly within the error correction circuit 48, the error correction and detection circuits 46 / 48 can provide a signal RDATA to the main circuit 40, which corresponds to: the original data DATA provided by the slave circuit 42 when one or more error signals ERR do not issue an error signal; or the corrected data CDATA generated by the error correction circuit 48 when one or more error signals ERR indicate a correctable error.

[0103] In various embodiments, one or more of the error signals ERR may also be provided to the main circuit 40. Specifically, in various embodiments, the main circuit 40 is configured to receive a RETRY signal indicating whether a read request has failed; that is, the error detection circuit 46 is configured to assert the RETRY signal when it detects an uncorrectable error, such as a double-bit error in the SECDED scheme. Therefore, in various embodiments, the main circuit 40 may be configured to repeat the read request when the RETRY signal is asserted, for example, when the error detection circuit 46 detects an uncorrectable error.

[0104] Therefore, as described above, the error detection and correction circuits 46 / 48 can be implemented by one or more combinational logic circuits. However, such combinational logic circuits introduce an additional maximum propagation delay in the path between circuit 42 and main circuit 40, which limits the maximum clock frequency that main circuit 40 can use to sample the data signal RDATA.

[0105] Figure 8 A modified example is shown, which uses a pipelined architecture to separate data read operations from ECC verification operations.

[0106] Specifically, in the considered embodiment, the processing system 10a includes a register (Reg) 52 configured to store bits DATA and ECC provided by the slave circuit 42 in response to a clock signal CLK, such as the clock signal of the master circuit 40.

[0107] Therefore, the error detection circuit 46 can operate on the data bits stored in the register 52, and similarly, the main circuit 40 can receive the stored data DATA (hereinafter referred to as data DATA') provided by the register 52 or the correction data CDATA provided by the error correction circuit via the signal RDATA.

[0108] Therefore, in the considered embodiment, the main circuit 40 is configured to receive data RDATA after two clock cycles (or even more clock cycles, if additional clock cycles are needed to send signals DATA and ECC from slave circuit 42 to register 52 and / or signal RDATA from error detection and correction circuit 46 / 48 to main circuit 40).

[0109] For example, to manage data transmission, the main circuit 40 can generate a read request, for example, via a request signal REQ, and the control circuit (Cont) 54 associated with the error detection and correction circuits 46 / 48 can generate a control signal indicating when the data signal RDATA is valid. Typically, the control signal can be: a wait signal WAIT, which asserts to indicate that the signal DATA' does not contain valid data for the current clock cycle; or an acknowledgment signal ACK, which asserts to indicate that the signal DATA' does indeed contain valid data for the current clock cycle.

[0110] Therefore, in this embodiment, the main circuit 40 is configured to read the signal DATA' in response to a clock signal, such as the clock signal CLK, based on the signals WAIT and / or ACK. For example, the main circuit 40 may store bits of the signal DATA' into an internal register.

[0111] Therefore, while this solution reduces propagation delay, it requires additional clock cycles until the main circuit 40 can read the data DATA'.

[0112] Figure 9 An embodiment of a processing system 10a according to the present disclosure is shown, wherein the processing system 10a again includes a main circuit 40 and a slave circuit 42.

[0113] Specifically, in the considered embodiments, the main circuit 40 is again configured to generate a read request including address ADR, wherein the read request is signaled via one or more control signals (e.g., the previously mentioned request signal REQ). Furthermore, the main circuit 40 is configured to receive a data signal RDATA. To properly manage the read request, the main circuit 40 is again configured to receive a control signal indicating whether the data signal RDATA contains valid data, such as the previously mentioned wait signal WAIT (and / or acknowledge signal ACK). That is, the main circuit 40 is configured to read the data signal RDATA in response to a clock signal and in response to determining that the control signal WAIT indicates that the data signal RDATA contains valid data. Furthermore, in the considered embodiments, the main circuit 40 is configured to receive a control signal indicating whether the read request should be repeated, such as the previously mentioned retry signal RETRY. For example, in various embodiments, the main circuit 40 is a microprocessor 1020. For example, the aforementioned control signals are typically used by an ARM-based microprocessor 1020 to interface with the TCM memory 1026. For example, reference may be made to the "TCM interface protocol" of current ARM Cortex processors, such as the ARM Cortex-M7 processor described in the "ARM Cortex-M7 Processor Technical Reference Manual", such as revision r1p2, which is incorporated herein by reference for this purpose.

[0114] Conversely, in the considered embodiments, the slave circuit 42 is configured to receive the address signal ADR and determine the individual data bits DATA and the individual ECC bits associated with the data bits DATA. For example, in various embodiments, the slave circuit 42 is a volatile memory, such as RAM, such as the RAM of the TCM memory 1026 that implements the processing core 102.

[0115] Usually, although Figure 9 Although not shown, communication between the main circuit 40 and the slave circuit 42 can be exchanged via any suitable communication system, such as communication system 114 and / or a dedicated communication system within the processing core 102.

[0116] In this regard, such as Figure 9 As illustrated, the address range of the master circuit 40 can indeed be mapped to the address range of the slave circuit 42 via the address decoder (Dec) 58, such as the physical memory address range of the memory. In this case, the address decoder 58 can be configured to receive read requests, specifically the address signal ADR and control signals indicating the request, such as the signal REQ, and can: generate a mapped / converted address ADR'; and assert control signals, such as the chip select signal CS, indicating that the address ADR provided by the master circuit 40 is managed by the slave circuit 42.

[0117] Therefore, in this configuration, the slave circuit 42 is configured to provide the bits DATA and ECC associated with the address ADR' in response to the assertion of the determination signal CS. Typically, the address decoder 58 can be implemented in the corresponding communication system and / or in the master circuit 40 and / or in the slave circuit 42. For example, in the case of the TCM memory 1026, the microprocessor 1020 may have already provided the physical address ADR of the TCM memory 42, and the request signal REQ may directly correspond to the chip select signal CS. Typically, the address mapping operation is entirely optional, and the address decoder 58 can also be configured—similar to a slave communication interface—to assert the control signal CS once it is determined that a given address ADR is associated with the slave circuit 42.

[0118] In the considered embodiment, the processing system 10a further includes an error detection and correction circuit 500. In this regard, the error detection and correction circuit 500 may be configured with: the main circuit 40, i.e., the error correction detection and correction circuit 500 is configured to verify the data once the bits DATA and ECC have been sent, for example, in the case of generating bit ECC to protect the bits DATA during data transmission operations; or from circuit 42, i.e., the error correction detection and correction circuit 500 is configured to verify the data before RDATA is sent to the main circuit 40, for example, in the case of a memory with ECC protection.

[0119] Specifically, in the considered embodiment, the error detection and correction circuit 500 is configured to receive data bits DATA and ECC bits, and to generate correction data CDATA by processing the bits DATA and ECC according to a given ECC scheme. Furthermore, the error detection and correction circuit 500 is configured to generate at least one error signal ERR indicating whether the data bits DATA contain an error. For example, as described above, the error detection and correction circuit 500 may include an error detection circuit 46 and an error correction circuit 48 for this purpose.

[0120] Furthermore, in the considered embodiment, the error detection and correction circuit 500 has a pipelined architecture, meaning that the error detection and correction circuit 500 includes at least one register 52. For example, in the considered embodiment, register 52 is configured to receive bits DATA and ECC from slave circuit 42 and provide the stored data to error detection circuit 46. However, instead of storing bits DATA and ECC, register 52 can also be used to store other signals used for error detection and correction functions, such as the checksum SYN or bit-flip signature SIG. In fact, in various embodiments, and as will be described in more detail below, it is sufficient that the content of the correction data signal CDATA is valid one clock cycle after the individual bits provided by slave circuit 42 via signals DATA and ECC.

[0121] In the considered embodiment, the signal DATA provided by the slave circuit 42 and the corrected data signal CDATA are (preferably directly) provided to the multiplexer 50, that is, the multiplexer 50 is configured to generate the signal RDATA of the master circuit 40 by selecting the signal DATA provided by the slave circuit when the selection signal SEL has a first value and selecting the signal CDATA provided by the error correction circuit 48 when the selection signal SEL has a second value.

[0122] Therefore, with Figure 7 and Figure 8 Compared to the embodiment shown, for a given data signal DATA provided by circuit 42, signal CDATA will contain valid data exactly after another clock cycle.

[0123] In the considered embodiment, the error detection and correction circuit 500 therefore also includes a control circuit 54 configured to receive read requests from the main circuit 40, specifically address ADR (or mapped address ADR') and control signals indicating the read request, such as a request signal REQ or a chip select signal CS, as well as one or more error signals ERR from the error detection circuit 46. Furthermore, the control circuit 54 is configured to generate a wait signal WAIT (or similarly an acknowledgment signal ACK) and a retry signal RETRY for the main circuit 40, and a select circuit SEL for the multiplexer 50, based on these signals.

[0124] Specifically, in the considered embodiment, control circuitry 54 should be configured to assert the wait signal WAIT (or similarly cancel the assertion (de-assertion) ACK) when one or more error signals ERR indicate an error in the DATA bit and / or ECC bit, particularly in the case of a correctable error, because in this case, main circuitry 40 should read data CDATA; however, data CDATA is only valid in the next clock cycle. However, in the considered embodiment, due to the pipelined architecture, one or more error signals ERR may also be asserted only after one clock cycle with respect to the data signal DATA. Therefore, error signals ERR cannot be used to directly generate the wait signal WAIT.

[0125] Therefore, in order to properly manage the generation of the wait signal WAIT (or acknowledgment signal ACK), in various embodiments, the control circuit 54 is configured to track the address ADR (or similar ADR') where the error detection and correction circuit 500 has previously detected an ECC error. For example, the address with the error can be stored in memory 56, preferably implemented using registers. For example, memory 56 may include a given number of slots, such as 2, 4, 8, or 16 slots, such as slots S1, S2, etc.

[0126] Figure 10 An embodiment of the operation of the first sub-circuit of the control circuit 54 is shown, which may be implemented, for example, via a finite state machine, i.e. via sequential logic circuitry.

[0127] Specifically, after the initial step 1100, which begins, for example, when processing system 10a is turned on, control circuitry 54 waits for a read request in step 1102. For example, control circuitry 54 may be configured in step 1102 to verify whether the assertion request signal REQ or the chip select signal CS is valid for the current clock cycle. If control circuitry 54 determines that no read request has been received (verifying the output "N" of step 1102), control circuitry can therefore return to step 1102.

[0128] Conversely, if the control circuit 54 determines that a read request has been received (verifying the output "Y" of step 1102), the control circuit 54 proceeds to step 1104, where the control circuit 54 obtains the address ADR (or ADR') of the read request and determines whether the obtained address should be stored in memory 56.

[0129] Then, in step 1106, the control circuit 54 verifies whether the obtained address has been stored in the memory 56. Specifically, if the obtained address has not been stored in the memory 56 (the output of verification step 1106 is "N"), the control circuit 54 proceeds to step 1108, where the control circuit 54 cancels the assertion wait signal WAIT (or assertion acknowledgment signal ACK) and sets the selection signal SEL to select the signal DATA provided by the slave circuit 40.

[0130] Conversely, with the obtained address stored in memory 56 (verifying the output "Y" of step 1106), control circuit 54 proceeds to step 1110, where control circuit 54 asserts the wait signal WAIT (or deasserts the acknowledgment signal ACK). Next, control circuit 54 proceeds to step 1112, where control circuit 54 cancels the assertion on the wait signal WAIT (or the acknowledgment signal ACK) in the next clock cycle, thereby signaling to master circuit 40 that it should only acquire data RDATA in the next cycle, which should correspond to the corrected data CDATA. Therefore, at least in step 1112, control circuit 54 sets the selection signal SEL to select the signal CDATA provided by error correction circuit 48. Typically, the value of the selection signal SEL in step 1110 is irrelevant, as master circuit 40 should not read signal RDATA in step 1110.

[0131] Therefore, at the end of steps 1108 and 1112, the control circuit 54 can return to step 1102 to process the next read request.

[0132] Therefore, in the considered embodiment, by directly providing data DATA to the main circuit, a read request for an address ADR (or ADR') that typically does not contain errors can be processed within one clock cycle. Conversely, a read request for an address ADR (or ADR') that typically contains errors is processed within two clock cycles by providing data CDATA to the main circuit. Typically, even if data CDATA refers to corrected data, in practice, this data can also correspond to the original data DATA if the error detection circuit 46 does not detect errors in bits DATA and ECC, i.e., if the bit flip signature SIG sets all bits to "0".

[0133] However, Figure 10 The operation shown does not handle the function of adding a new address to memory 56 in the event of an error.

[0134] in this regard, Figure 11 An embodiment of the operation of the second sub-circuit of the control circuit 54 is shown, which enables parallel processing of the control circuit 54. Typically, based on the architecture of the first sub-circuit, the second sub-circuit can be implemented by sequential logic circuits or simply combinational logic circuits.

[0135] Specifically, after the initial step 1100, which begins, for example, when the processing system 10a is turned on, the control circuit 54 waits in step 1202 for the error detection circuit 46 to issue an error signal, such as whether the error signal ERR is asserted. If the control circuit 54 determines that no error signal has been issued (verifying the output "N" in step 1202), the control circuit can therefore return to step 1202.

[0136] Conversely, if control circuit 54 determines that an error signal has been issued (verifying the output "Y" of step 1202), control circuit 54 proceeds to step 1204. Specifically, in step 1204, control circuit 54 determines whether the address ADR (or ADR') associated with the request that generated the error has been stored in memory 56.

[0137] In this regard, in the event of an error, the error signal ERR will only be asserted in the second clock cycle. However, if the control circuit 54 determines that the address ADR (or ADR') has not been stored in memory 54, the request can be processed in a single clock cycle. Therefore, in order to correctly use the address ADR (or ADR') associated with the request that has generated an error to be stored in memory 56, the control circuit 54 can be configured to temporarily store the address of each read request, for example, in Figure 10 Step 1104. Therefore, the control circuit 54 can use the temporarily stored address in step 1204.

[0138] Furthermore, in step 1204, the control circuit manages the storage of address ADR (or ADR') into memory 56. Typically, when memory 56 is empty, the control circuit 54 can add an address to memory 56, for example, by storing address ADR (or ADR') into the first slot S1.

[0139] However, for further errors, the control circuit 54 can use different strategies.

[0140] For example, in the simplest case, the control circuit 54 can be configured to use the memory as a ring memory, where—even if the memory also includes the same address—the control circuit 54 simply adds the address to the next memory slot of the memory, where the control circuit covers the oldest memory slot.

[0141] Conversely, in other embodiments, the control circuit 54 is configured to add addresses that have not yet been stored in the memory 56. Preferably, in this case, the control circuit 54 may also associate additional data with each address stored in the memory slot, such as the number of errors occurring at the corresponding address and / or data identifying the timestamp of the last error at the corresponding address. Thus, in this case, the aforementioned additional data can be used by the control circuit 54 to determine, for example, whether to clear a given memory slot when the memory 54 is full and / or periodically.

[0142] Typically, in various embodiments, a given address can also be removed from memory 56 if the error detection circuit 46 does not issue an error signal during a subsequent read request.

[0143] Next, the control circuit 54 proceeds to verification step 1206. Specifically, if the control circuit 54 determines that the address ADR (or ADR') associated with the request that generated the error has been stored in memory 56 (the output "Y" of verification step 1210), the control circuit 54 has already... Figure 10 Steps 1104 and 1106 determine that two clock cycles are needed to provide the correction data.

[0144] Therefore, in this situation, control circuit 54 can return to the step of waiting for further errors. Specifically, as schematically shown by step 1212, in this situation, control circuit 54 can cancel the assertion of the retry signal RETRY in order to signal to main circuit 40 that main circuit 40 should not repeat the request.

[0145] However, in various embodiments, the error detection and correction circuit 500 may support ECC codes that allow correction of a given number of flip bits and only detect a higher number of flip bits, such as SECDED. In this case, the control circuit 54 may proceed to optional step 1210, where the control circuit 54 verifies the error signal ERR to determine whether the error is correctable or uncorrectable. Specifically, if the control circuit determines a correctable error (verification step 1210 output "SBE"), such as a single-bit error, the control circuit 54 may return to step 1202 via step 1212. Conversely, if the control circuit determines an uncorrectable error (verification step 1210 output "DBE"), such as a double-bit error, the data CDATA provided by the error correction circuit 48 does not contain corrected data. Therefore, in this case, the control circuit 54 may assert the retry signal RETRY in step 1208 to signal the master circuit 40 that the read request should be repeated, and the control circuit 54 may then return to step 1202.

[0146] Conversely, if control circuit 54 determines that the address ADR (or ADR') associated with the request that generated the error is not stored in memory 56 (verifying the output "N" of step 1210), control circuit 54 can also proceed to step 1208. In fact, in this case, control circuit 54... Figure 10 Steps 1104 and 1106 determine that only one clock cycle is needed to provide the data DATA, even though the data CDATA must actually be used after two clock cycles. Therefore, in the same case, control circuit 54 can assert the retry signal RETRY in step 1208 to signal the main circuit 40 that the request should be repeated. In fact, when the request is repeated, the corresponding address will be stored in memory 54, and control circuit 54 will indicate that processing the data through error detection and correction circuit 500 requires two clock cycles.

[0147] Therefore, the aforementioned solution allows access to slave device 42 in a single clock cycle, and in the case of an error associated with a specific address, read requests for those addresses are executed in two clock cycles, so that error correction circuit 48 can generate correction data CDATA, which can then be read by master circuit 40.

[0148] The claims are an integral part of the technical teachings disclosed herein.

[0149] Of course, without prejudice to the principles of the invention, the details of the structure and embodiments may vary considerably from what is described and shown herein purely by way of example, without departing from the scope of the invention as defined by the appended claims.

Claims

1. A processing system, comprising: A main circuit is configured to generate a read request including an address, wherein the main circuit signals the read request by asserting a first control signal, wherein the main circuit is further configured to receive N first data bits, a second control signal, and a third control signal, and wherein the main circuit operates as follows: The logic level of the second control signal is determined, the second control signal having a first logic level indicating that the N first data bits contain valid data and a second logic level indicating that the N first data bits do not contain valid data; The logic level of the third control signal is determined, the third control signal having a first logic level indicating that the read request should be repeated and a second logic level indicating that the read request should not be repeated; In response to determining that the second control signal has the first logic level, the N first data bits are read; as well as In response to determining that the third control signal has the first logic level, the read request is repeated; The circuit is configured to receive the read request and, in response to an assertion of the first control signal, provide N second data bits and K error correction code bits associated with the address included in the read request; as well as An error detection and correction circuit is configured to receive the read request, the N second data bits, and the K ECC bits, and to provide the N first data bits, the second control signal, and the third control signal. The error detection and correction circuit includes a multiplexer configured to provide the N first data bits by selecting the N second data bits when the selection signal has a first logic level, and to provide the N third data bits when the selection signal has a second logic level. The error detection and correction circuit is configured to generate the N third data bits by: The N second data bits and the K ECC bits are processed to determine whether the N second data bits do not contain errors or contain one or more correctable bit errors; In response to determining that the N second data bits include one or more correctable bit errors, an error signal is asserted and a bit-flip signature is generated having bits asserted at the location of the one or more correctable bit errors; as well as The N third data bits are generated by inverting the bits of the N second data bits at the positions where the bit of the bit-flipped signature is asserted. The error detection and correction circuitry includes a pipelined architecture such that the N third data bits are generated with a one-clock-cycle delay relative to the corresponding N second data bits provided by the slave circuitry; and The error detection and correction circuit includes a memory and a control circuit, wherein the control circuit includes a first sub-circuit and a second sub-circuit; The first sub-circuit is configured as follows: Monitor the first control signal to detect a read request; In response to detecting the read request, the address associated with the read request is determined, and it is verified whether the address associated with the read request is stored in the memory; In response to determining that the address associated with the read request is not stored in the memory: a) Set the selection signal to the first logic level to control the multiplexer to provide the N second data bits; as well as b) Set the second control signal to the first logic level to indicate that the N first data bits contain valid data; In response to determining that the address associated with the read request is stored in the memory: a) Set the second control signal to the second logic level during the first clock cycle to indicate that the N first data bits do not contain valid data; b) Set the selection signal to the second logic level to control the multiplexer to provide the N third data bits, and c) Set the second control signal to the first logic level during a second clock cycle following the first clock cycle to indicate that the N first data bits contain valid data; The second sub-circuit is configured as follows: Monitor the error signal; In response to determining that the error signal has been asserted, verify whether the address associated with the read request is stored in the memory; In response to determining that the address associated with the read request is not stored in the memory: a) Store the address associated with the read request in the memory; as well as b) Set the third control signal to the first logic level to indicate that the read request should be repeated; as well as In response to determining that the address associated with the read request is stored in the memory: a) Set the third control signal to the second logic level to indicate that the read request should not be repeated.

2. The processing system according to claim 1: The error detection and correction circuitry is configured to process the N second data bits and the K ECC bits to determine whether the N second data bits include an uncorrectable bit error, and in response to determining that the N second data bits include the uncorrectable bit error, assert another error signal; and The second sub-circuit is configured as follows: Monitor the other error signal; and In response to determining that the other error signal has been asserted, the third control signal is set to the first logic level to indicate that the read request should be repeated.

3. The processing system of claim 1, wherein the memory has a given number of memory slots, and wherein the second sub-circuit is configured to: In response to determining that the address associated with the read request is stored in the memory, the memory is managed as a ring memory, and the address associated with the read request is stored in the next memory slot of the ring memory.

4. The processing system of claim 1, wherein the memory has a given number of memory slots, and wherein the second sub-circuit is configured to: In response to determining that the address associated with the read request is stored in the memory, the memory is managed as a ring memory, and corresponding further data is associated with each single address stored in a given memory slot, the further data specifying one or more of the occurrence count and last access time.

5. The processing system of claim 1, wherein the address associated with the read request corresponds to the address included in the read request.

6. The processing system of claim 1, wherein the processing system includes an address decoder configured to determine the address associated with the read request by mapping an address included in the read request.

7. The processing system of claim 1, wherein the main circuit is a microprocessor and the slave circuit is a tightly coupled memory (TCM).

8. The processing system according to claim 7, wherein the microprocessor is an ARM-based microprocessor.

9. The processing system of claim 1, wherein the pipelined architecture of the error detection and correction circuit is implemented via a register configured to store the N second data bits and the K ECC bits.

10. The processing system of claim 1, wherein the pipelined architecture of the error detection and correction circuit is implemented via a register configured to store the error signal and the bit-flip signature.

11. The processing system of claim 1, wherein the N third data bits are generated with a delay of one clock cycle relative to the corresponding N second data bits provided by the slave circuit.

12. An integrated circuit comprising the processing system according to claim 1.

13. An apparatus comprising a plurality of processing systems, wherein at least one of the plurality of processing systems comprises the processing system of claim 1, and wherein the processing systems of the plurality of processing systems are connected via a communication system.

14. The device according to claim 13, wherein the device is a vehicle.

15. A memory read control method, comprising: A first read request, including a given address, is generated via the main circuit. In the first clock cycle: The slave circuit provides N second data bits and K error ECC bits associated with the given address; as well as If the first sub-circuit determines that the given address associated with the first read request is not stored in memory, it sets the logic level of the selection signal to the first logic level to control the multiplexer to provide N second data bits to the main circuit, and sets the logic level of the second control signal to the first logic level to indicate that the N first data bits contain valid data. In the second clock cycle: The second sub-circuit determines that the error signal is asserted and that the given address associated with the read request is not stored in the memory. Then, the given address associated with the read request is stored in the memory, and the logic level of the third control signal is set to the first logic level to indicate that the read request should be repeated. In response to the third control signal being set to the first logic level, a second read request including the given address is generated via the main circuit. In the third clock cycle: The slave circuit provides the N second data bits and the K error ECC bits associated with the given address; as well as The first sub-circuit determines that a given address associated with the second read request is stored in the memory, and sets the logic level of the second control signal to the second logic level to indicate that the N first data bits do not contain valid data; In the fourth clock cycle: The first sub-circuit sets the logic level of the selection signal to the second logic level to control the multiplexer to provide the N third data bits, and sets the logic level of the second control signal to the first logic level to indicate that the N first data bits contain valid data.

16. A processing system, comprising: The main circuit is configured to generate read requests, including addresses. The circuit is configured to receive the read request and respond to the read request by providing N first data bits and K error correction code bits; The register is configured to store the N first data bits and the K error correction code bits in response to a clock signal; An error detection circuit is configured to receive the N first data bits and the K error correction code bits output from the register, and process the N first data bits and the K error correction code bits to assert an error signal when a correctable bit error exists in the N first data bits, and generate a bit flip signature signal that identifies the position of the correctable bit error. An error correction circuit is configured to receive the N first data bits, the error signal, and the bit-flip signature signal. When the error signal is asserted, the bit-flip signature signal is applied to the N first data bits to generate N second data bits. When the error signal indicates that a correctable bit error exists, a control signal with a first logic state is generated. When the error signal indicates that no bit error exists, a control signal with a second logic state is generated. as well as A multiplexer circuit having: a first input configured to receive the N first data bits output from the register; And a second input, configured to receive the N second data bits output from the error correction circuit; Furthermore, the multiplexer circuit has a selection input configured to receive a control signal for controlling the selection between the N first data bits and the N second data bits, so as to output as N third data bits to be transmitted to the main circuit.

17. The processing system according to claim 16, further comprising: Memory; as well as Control circuit, wherein the control circuit is configured to: Determine whether the address is stored in the memory; as well as When the address is not stored in the memory: The control signal is set so that the multiplexer circuit selects the N first data bits output from the register as the N third data bits for transmission to the main circuit. as well as The main circuit is signaled to notify that the N first data bits output from the register contain valid data.

18. The processing system of claim 17, further comprising, when the address is stored in the memory, the control circuit operates to: During one cycle of the clock signal, a signal is sent to the main circuit to notify that the N first data bits output from the register do not contain valid data; The control signal is set so that the multiplexer circuit selects the N second data bits output from the error correction circuit as the N third data bits for transmission to the main circuit. as well as Then, in the next cycle of the clock signal, a signal is sent to the main circuit to notify that the N first data bits output from the register contain valid data.

19. The processing system according to claim 16, further comprising: Memory; as well as Control circuit, wherein the control circuit is configured to: Determine whether the address is stored in the memory; as well as When the address is stored in the memory: During one cycle of the clock signal, a signal is sent to the main circuit to notify that the N first data bits output from the register do not contain valid data; The control signal is set so that the multiplexer circuit selects the N second data bits output from the error correction circuit as the N third data bits for transmission to the main circuit. as well as Then, in the next cycle of the clock signal, a signal is sent to the main circuit to notify that the N first data bits output from the register contain valid data.

20. The processing system according to claim 16, further comprising: Memory; as well as Control circuit, wherein the control circuit is configured to: In response to the assertion of the error signal, determine whether the address is stored in the memory; as well as When the address is not stored in the memory: Store the address in the memory; as well as The main circuit is signaled to repeat the read request.

21. The processing system of claim 20, further comprising, when the address is stored in the memory, signaling to the main circuit not to repeat the read request.

22. The processing system of claim 16, wherein the error detection circuit is further configured to process the N first data bits and the K error correction code bits to assert another error signal when an uncorrectable bit error exists in the N first data bits, and further comprises being configured to: In response to the assertion of the other error signal, a signal is sent to the main circuit to repeat the read request.

23. The processing system of claim 16, further comprising an address decoder configured to determine the address associated with the read request by mapping an address included in the read request.

24. The processing system of claim 16, wherein the master circuit is a microprocessor and the slave circuit is a tightly coupled memory (TCM).

25. The processing system of claim 24, wherein the microprocessor is an ARM-based microprocessor.

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