Internal mapping address resource management method and system, terminal and storage medium

Abstract

The application relates to the technical field of servers, and specifically provides an internal mapping address resource management method and system, a terminal and a storage medium, which comprise the following steps: acquiring the space range of the PCI internal mapping address of a server; collecting the allocated internal mapping address, calculating the allocated space of the internal mapping address; taking the difference value between the space range and the allocated space as a space margin, monitoring the space margin based on a warning threshold; confirming that the space margin reaches the warning threshold, moving a new PCIE device into a waiting queue, and sequentially allocating internal mapping addresses to PCIE devices with demand spaces within the space margin range. The application monitors the internal mapping address space of the server, discovers the insufficient address space margin in time, can controllably allocate internal mapping addresses to part of the devices when the space margin is insufficient, and avoids the situation that the internal mapping address error affects the server performance.

Description

Technical Field

[0001] This invention belongs to the field of server technology, specifically relating to an internal mapping address resource management method, system, terminal, and storage medium. Background Technology

[0002] As AI technology matures, its role in data processing, imaging, artificial intelligence, and other fields is becoming increasingly important. This leads to a corresponding increase in the performance and quantity requirements of basic components, especially the increased proportion of high-performance components such as PCI and PCIE.

[0003] When a PCIe device is connected to the server, the server needs to allocate an internal mapped address (MMIO) to it. This internal mapped address requires configuration space, but the server's address space is limited. When a large number of PCIe devices are connected, the internal mapped address space may become insufficient, leading to failure in allocating internal mapped addresses to the PCIe devices. Furthermore, if a large number of PCIe devices connect simultaneously, and the required address space exceeds the address space provided by the server, errors may occur when the server allocates internal mapped addresses, thus affecting the server's communication quality. Summary of the Invention

[0004] To address the problem that insufficient internal mapping address space in existing technologies leads to invalid allocated internal mapping addresses, thereby affecting server communication quality, this invention provides an internal mapping address resource management method, system, terminal, and storage medium to solve the aforementioned technical problems.

[0005] In a first aspect, the present invention provides an internal mapped address resource management method, comprising:

[0006] Obtain the spatial range of the server's internal PCI mapping addresses;

[0007] Collect the allocated internal mapping addresses and calculate the allocated space for the internal mapping addresses;

[0008] The difference between the spatial range and the allocated space is used as the spatial margin, and the spatial margin is monitored based on the early warning threshold.

[0009] Once the available space has been confirmed to reach the warning threshold, the new PCIe device is moved into the waiting queue, and internal mapping addresses are allocated sequentially to PCIe devices whose space requirements are within the available space range.

[0010] In one optional implementation, the allocated internal mapping addresses are collected, and the allocated space of the internal mapping addresses is calculated, including:

[0011] Configure the server to trigger the operation of obtaining the internal mapping address when a new PCIe device is added;

[0012] Confirm that a new PCIe device has been added to the server, and export the address range of the allocated internally mapped addresses from the address management item of the basic input / output system;

[0013] Extract the previous and next values ​​of the address region, and convert the difference between the previous and next values ​​into a decimal address space;

[0014] The allocated internal mapping address space is accumulated to obtain the allocated space.

[0015] In an optional implementation, the address space of the allocated internal mapped addresses is accumulated to obtain the allocated space, including:

[0016] Based on the spatial partitioning rules, the internal mapped addresses are divided into Class I addresses and Class II addresses;

[0017] The address space of the first type of address is accumulated to obtain the first occupied space;

[0018] The address space of the second type of address is accumulated to obtain the second occupied space.

[0019] In an optional implementation, the method further includes, before calculating the allocated space for the internal mapped address:

[0020] Obtain the PCIe device mount information of the server using query tools;

[0021] Determine if the allocated internal mapping address matches the PCIe device mount information:

[0022] If so, the required space is calculated based on the PCIe device mounting information, and it is verified whether the required space is within the specified space range;

[0023] If not, output the difference information.

[0024] In an optional implementation, calculating the required space based on the PCIe device mounting information and verifying whether the required space is within the specified range includes:

[0025] Extract the internal mapping address type of the PCIe device from the PCIe device mount information, and classify the internal mapping address into Class I address and Class II address based on the type.

[0026] The configuration space capacity of the first type of address is accumulated to obtain the first required space;

[0027] The configuration space capacity of the second type of address is accumulated to obtain the second required space;

[0028] Determine whether both the first and second demand spaces are within the corresponding space range:

[0029] If so, then it is determined that the current internal mapping address resources are sufficient;

[0030] If not, a message indicating insufficient internal mapping address resources will be generated.

[0031] In one optional implementation, after confirming that the available space has reached the warning threshold, the newly connected PCIe device is moved into the waiting queue, and internal mapped addresses are allocated sequentially to PCIe devices whose space requirements are within the available space range, including...

[0032] If the remaining space is confirmed to be no higher than the warning threshold, disable the BIOS's internal mapping address direct allocation function, and restore the BIOS's internal mapping address direct allocation function when the remaining space is higher than the warning threshold.

[0033] Establish a waiting queue and move information about newly connected PCIe devices into the waiting queue in order of their connection time;

[0034] PCIe device information is extracted sequentially from the waiting queue, and the configuration space is parsed from the PCIe device information as the demand space.

[0035] Determine whether the required space is lower than the available space:

[0036] If so, the BIOS is authorized to allocate an internal mapping address to the corresponding PCIe device based on the PCIe device information;

[0037] If not, retrieve the information of the next PCIe device in the waiting queue.

[0038] In an optional implementation, when allocating internal mapped addresses to a PCIe device, the method further includes:

[0039] Multiple granularities are pre-defined and sorted in ascending order;

[0040] The BIOS controls the granularity to be set sequentially to the internal mapped address space capacity of the target PCIe device;

[0041] When the system stops reporting a PCIe error, the BIOS controls the BIOS to terminate the refresh of the internal mapped address space capacity of the target PCIe device and fixes the current space value to the optimal space value of the target PCIe device.

[0042] In a second aspect, the present invention provides an internal mapping address resource management system, comprising:

[0043] The standard acquisition module is used to obtain the spatial range of the server's internal PCI mapping address.

[0044] The data acquisition module is used to collect the allocated internal mapping addresses and calculate the allocated space of the internal mapping addresses;

[0045] The margin monitoring module is used to take the difference between the spatial range and the allocated space as the spatial margin, and monitor the spatial margin based on the early warning threshold.

[0046] The address allocation module is used to confirm that the space margin has reached the warning threshold, move the new PCIe device into the waiting queue, and allocate internal mapping addresses to PCIe devices whose space requirements are within the space margin range in turn.

[0047] In one optional implementation, the data acquisition module includes:

[0048] The condition setting unit is used to set the presence of a newly added PCIe device on the server as an event that triggers the operation of obtaining the internal mapping address;

[0049] A new identification unit is added to confirm the presence of a new PCIe device on the server and to export the address range of the allocated internally mapped addresses from the address management items of the basic input / output system.

[0050] A spatial calculation unit is used to extract the previous and next values ​​of the address region and convert the difference between the previous and next values ​​into a decimal address space.

[0051] The space accumulation unit is used to accumulate the address space of the allocated internal mapped addresses to obtain the allocated space.

[0052] In an optional implementation, the spatial accumulation unit includes:

[0053] The address classification subunit is used to divide the internal mapped addresses into Class I addresses and Class II addresses based on spatial partitioning rules.

[0054] The first accumulation subunit is used to accumulate the address space of the first type of address to obtain the first occupied space;

[0055] The second accumulation subunit is used to accumulate the address space of the second type of address to obtain the second occupied space.

[0056] In one optional implementation, the system includes:

[0057] The mount module is used to obtain PCIe device mount information of the server through query tools;

[0058] The information matching module is used to determine whether the allocated internal mapping address matches the PCIe device mount information.

[0059] The space verification module is used to calculate the required space based on the PCIE device mounting information if the allocated internal mapping address matches the PCIE device mounting information, and to verify whether the required space is within the space range.

[0060] The difference output module is used to output difference information if the allocated internal mapping address does not match the PCIe device mount information.

[0061] In an optional implementation, the space verification module includes:

[0062] The type extraction unit is used to extract the internal mapping address type of the PCIe device from the PCIe device mounting information, and divide the internal mapping address into a first type address and a second type address based on the type.

[0063] The first calculation unit is used to accumulate the configuration space capacity of the first type of address to obtain the first required space;

[0064] The second calculation unit is used to accumulate the configuration space capacity of the second type of address to obtain the second required space;

[0065] The capacity determination unit is used to determine whether both the first demand space and the second demand space are within the corresponding space range;

[0066] The first determination unit is used to determine that the current internal mapping address resources are sufficient if both the first demand space and the second demand space are within the corresponding space range.

[0067] The second determination unit is used to generate a prompt message indicating insufficient internal mapping address resources if the first or second demand space is not within the corresponding space range.

[0068] In one optional implementation, the margin monitoring module includes:

[0069] The function management unit is used to confirm that the space margin is not higher than the warning threshold, disable the BIOS's internal mapping address direct allocation function, and restore the BIOS's internal mapping address direct allocation function when the space margin is higher than the warning threshold.

[0070] The queue building unit is used to build a waiting queue and move information of newly connected PCIe devices into the waiting queue according to their access time.

[0071] The configuration parsing unit is used to extract PCIe device information sequentially from the waiting queue, and parse the configuration space from the PCIe device information as the demand space;

[0072] A margin judgment unit is used to determine whether the required space is lower than the space margin.

[0073] A matching allocation unit is used to authorize the BIOS to allocate an internal mapping address to the corresponding PCIe device based on the PCIe device information if the required space is lower than the space margin.

[0074] The target switching unit is used to extract the information of the next PCIe device in the waiting queue if the required space is not less than the space margin.

[0075] In an optional implementation, the system further includes:

[0076] The capacity setting module is used to pre-set multiple granularities and sort the multiple granularities in ascending order;

[0077] The granularity verification module is used to control the BIOS to sequentially set the granularity to the space capacity of the internal mapped address of the target PCIe device;

[0078] The optimal fixation module is used to control the BIOS to terminate the refresh of the internal mapped address space capacity of the target PCIe device when the system stops reporting a PCIe error, and fix the current space value to the optimal space value of the target PCIe device.

[0079] Thirdly, a terminal is provided, including:

[0080] Processor, memory, among which,

[0081] This memory is used to store computer programs.

[0082] The processor is used to retrieve and run the computer program from memory, causing the terminal to perform the terminal method described above.

[0083] Fourthly, a computer storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the methods described in the above aspects.

[0084] The beneficial effects of the present invention are that the internal mapping address resource management method, system, terminal and storage medium provided by the present invention can monitor the internal mapping address space of the server, detect the insufficient address space in a timely manner, and controllably allocate internal mapping addresses to some devices when the space is insufficient, so as to avoid the situation where internal mapping address errors affect the server performance.

[0085] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects. Attached Figure Description

[0086] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0087] Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention.

[0088] Figure 2 This is another illustrative flowchart of a method according to an embodiment of the present invention.

[0089] Figure 3 This is a schematic block diagram of a system according to an embodiment of the present invention.

[0090] Figure 4 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present invention. Detailed Implementation

[0091] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0093] The key terms used in this invention will be explained below.

[0094] PCI is a local bus designed to connect various external devices. Its design goals are high speed, higher bandwidth, and lower power consumption (allowing for the connection of more peripherals). It is typically not CPU-bound and can be used as a general-purpose peripheral connected to CPUs across different architectures. However, the root bridge is unique, with each chip manufacturer developing its own bridge chips to implement the PCI protocol. PCI uses a parallel bus; at lower frequencies, parallel buses offer higher bandwidth than serial buses. However, at higher frequencies, parallel buses are more susceptible to external interference. Later, PCIe gradually replaced the parallel bus with a high-speed serial bus.

[0095] PCI provides several methods: configuration space and MMIO / IO ports. All PCI devices must provide a standard configuration space to provide device information and control interfaces. PCI devices have their own unique identifier address, but this is not hard-coded into the device; instead, it is assigned based on the PCI slot location. The address consists of three parts: Bus, Device, and Function (BDF). Bus: PCI bus number, occupying 8 bits, so the PCI / PCIe bus supports a maximum of 256 subbuses. Device: The PCI device ID on the bus, occupying 5 bits, so each subbus supports a maximum of 32 devices. Sometimes also called a slot, representing the location of the PCI slot. Function: The PCI device's function ID. A PCI physical device can implement multiple functions, and these functions are logically independent. This occupies 3 bits, so each physical device supports a maximum of 8 functions. The traditional PCI bus supports a maximum of 256 buses. To overcome this limitation, the PCI domain was added; the traditional PCI uses the default domain 0.

[0096] The PCI specification stipulates that software needs to initialize and configure devices through a configuration space. The PCI configuration space is 256 bytes, while the PCIe device configuration space is 4KB, with the first 256 bytes being PCI-compatible. The expansion of the configuration space is mainly due to the increasing complexity of devices, requiring more space for various capabilities. The total number of configuration spaces that PCI / PCIe can accommodate is the same: 2^16. Accessing the configuration space via MMIO requires reserving some address space for PCI / PCIe configuration space, so 32MB of address space needs to be reserved: 16MB for type 0 and 16MB for type 1, while 256MB of address space needs to be reserved for PCIe. PCI devices specify little-endian data access, so if the CPU uses big-endian, endianness conversion is required when accessing multiple bytes. There are two ways to access PCI: through I / O ports or via MMIO. The PCI bus was first used on x86, so it is full of x86 influences. x86 has an ioport space, so it is specified to use ioport to access it. However, other architectures do not have an ioport design, so other architectures access the configuration space through MMIO when using PCI.

[0097] BIOS is an abbreviation for "Basic Input Output System." On IBM PC-compatible systems, it's an industry-standard firmware interface. It's a set of programs embedded in a ROM chip on the computer's motherboard. It stores the computer's most important basic input / output programs, power-on self-test (POST) programs, and system boot programs. It can read and write specific system settings from the CMOS. Its main function is to provide the lowest-level, most direct hardware settings and control for the computer. In addition, the BIOS provides some system parameters to the operating system. Changes to system hardware are hidden by the BIOS; programs use BIOS functions rather than directly controlling the hardware. Modern operating systems often bypass the abstraction layer provided by the BIOS and directly control hardware components.

[0098] The CPU (Central Processing Unit) is the core of a computer system for computation and control, and is the final execution module for information processing and program execution.

[0099] BAR: Base Address register, is responsible for mapping the internal address space of a PCI device. The PCI configuration space is just a standard header, but it does not participate in actual operations. PCI devices have many register interfaces. PCI allows you to show the size of the address space you need through the BAR, and you can directly access it after configuring and mapping the address space.

[0100] The internal mapping address resource management method provided in this embodiment of the invention is executed by a computer device, and correspondingly, the internal mapping address resource management system runs in the computer device.

[0101] Figure 1 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Wherein, Figure 1 The executing entity can be an internal mapping address resource management system. Depending on different needs, the order of the steps in this flowchart can be changed, and some can be omitted.

[0102] like Figure 1 As shown, the method includes:

[0103] Step 110: Obtain the spatial range of the server's internal PCI mapping address;

[0104] Step 120: Collect the allocated internal mapping addresses and calculate the allocated space of the internal mapping addresses;

[0105] Step 130: The difference between the spatial range and the allocated space is taken as the spatial margin, and the spatial margin is monitored based on the early warning threshold;

[0106] Step 140: Confirm that the space margin has reached the warning threshold, move the new PCIe device into the waiting queue, and allocate internal mapping addresses to PCIe devices that require space within the space margin range in sequence.

[0107] To facilitate understanding of the present invention, the following description further illustrates the internal mapping address resource management method provided by the present invention, based on the principle of the method and the process of managing internal mapping address resources in the embodiments.

[0108] For details, please refer to Figure 2 The internal mapping address resource management method includes:

[0109] S1. Obtain the space range of the server's internal PCI mapping address.

[0110] Obtain the target server's model number, and based on the model number, determine its address space, for example: the BAR address space address range, defined by the Intel architecture.

[0111] BAR address availability range: 10h-24h

[0112] The BAR address is divided into two parts: MMI0l BAR address: <4GB; Mmioh BAR address: 32GB-32TB.

[0113] S2. Collect the allocated internal mapping addresses and calculate the allocated space of the internal mapping addresses.

[0114] Set the presence of a new PCIe device on the server as the event that triggers the acquisition of internal mapping addresses; confirm the presence of a new PCIe device on the server, and export the address range of the allocated internal mapping addresses from the address management item of the basic input / output system; extract the previous and next values ​​of the address range, and convert the difference between the previous and next values ​​into a decimal address space; accumulate the address space of the allocated internal mapping addresses to obtain the allocated space.

[0115] When accumulating the address space of the allocated internal mapping addresses, it is necessary to distinguish the internal mapping addresses. The specific methods include: dividing the internal mapping addresses into a first type of address and a second type of address based on the space partitioning rules; accumulating the address space of the first type of address to obtain the first occupied space; and accumulating the address space of the second type of address to obtain the second occupied space.

[0116] For example, the allocated address range for Mmiol under BUS 0x00-0xff is 0xA0000000-0xD2FFFFFF.

[0117] Calculation: Previous value - Next value + 1: 0xD2FFFFFF - 0xA0000000 + 1, converted to decimal: 816MB;

[0118] The allocated address range of Mmiol under BUS 0x00-0xff is 0x0000143FFFFFFFFF-0x0000100000000000. Calculate: 0x0000143FFFFFFFFF-0x0000100000000000+1, which is approximately 4T in decimal.

[0119] Furthermore, in one embodiment of the present invention, after capturing the allocated internal mapping address, the currently allocated address can be verified. The specific verification method includes: obtaining the PCIE device mounting information of the server through a query tool; determining whether the allocated internal mapping address matches the PCIE device mounting information; if so, calculating the required space based on the PCIE device mounting information and verifying whether the required space is within the space range; if not, outputting the difference information.

[0120] When matching allocated internal mapped addresses with PCIe devices, the matching is performed from two perspectives: first, the quantity is matched, and then the device name is matched. If the quantity does not match, a difference message is output directly; if the quantity matches, then the device name is matched.

[0121] Furthermore, after the above comparison, the current PCIe device's required space is estimated and evaluated. Specific methods include: extracting the internal mapping address type of the PCIe device from its mounting information; classifying the internal mapping address into a first-class address and a second-class address based on the type; summing the configuration space capacity of the first-class address to obtain the first required space; summing the configuration space capacity of the second-class address to obtain the second required space; determining whether both the first and second required spaces are within their respective space ranges: if so, the current internal mapping address resources are sufficient; if not, generating a message indicating insufficient internal mapping address resources. For example, confirming that the number of mounted PCI / PIC-E components matches the corresponding number under CPU resource Allocation; component lookup method: using `lspci –vvv|grep –I'Memory at'`. The BAR size corresponding to 32-bit is statistically accumulated; the total size should not exceed 4GB, belonging to the Mmiol region; the BAR size corresponding to 64-bit is statistically accumulated; the addressing range is between 32GB and 32TB, belonging to the MmioH region.

[0122] S3. The difference between the spatial range and the allocated space is taken as the spatial margin, and the spatial margin is monitored based on the early warning threshold.

[0123] In step S2, after each calculation of the allocated space, the remaining space is calculated based on the latest allocated space. Simultaneously, it is determined whether the latest remaining space is not higher than a pre-set warning threshold. If it is not higher than the warning threshold, it indicates that the remaining space is too low, and a warning message is generated. For example, if the BAR address is insufficient, a PCIe error message will appear in the OS.

[0124] S4. Confirm that the space margin has reached the warning threshold, move the new PCIe device into the waiting queue, and allocate internal mapping addresses to PCIe devices that require space within the space margin range in sequence.

[0125] If the available space is confirmed to be no higher than the warning threshold, disable the BIOS's direct allocation function for internal mapped addresses, and restore the BIOS's direct allocation function for internal mapped addresses when the available space is higher than the warning threshold; construct a waiting queue and move newly connected PCIe device information into the waiting queue in order of access time; extract PCIe device information sequentially from the waiting queue, and parse the configuration space from the PCIe device information as the required space; determine whether the required space is lower than the available space: if yes, authorize the BIOS to allocate internal mapped addresses to the corresponding PCIe device based on the PCIe device information; if no, extract the next PCIe device information from the waiting queue.

[0126] Specifically, if there is sufficient space and no warning is triggered, the BIOS will normally allocate internal mapped addresses to PCIe devices. If there is insufficient space, the allocation process of internal mapped addresses needs to be controlled. The specific control method is to allocate them one by one to avoid address space congestion.

[0127] In addition, when allocating internal mapped addresses, the granularity of the internal mapped addresses of PCIe devices can be verified. The specific verification process includes: pre-setting multiple granularities and sorting them in ascending order; controlling the BIOS to sequentially set the granularity to the space capacity of the internal mapped address of the target PCIe device; controlling the BIOS to terminate the refresh of the space capacity of the internal mapped address of the target PCIe device when the system stops reporting a PCIe error, and fixing the current space value as the optimal space value of the target PCIe device.

[0128] For example, MmioH granularities range from 1G, 4G, 16G, 64G, 256G, to 1024G. In the BIOS, 1G is initially selected as the internal mapped address space for the target PCIe device. If a PCIe error message appears in the OS, the space value is set to 4G. If a PCIe error message still appears in the OS, the space value is set to 16G. If no PCIe error message appears in the OS at this point, it means the optimal space value for the target PCIe is 16G. No further changes are made to the space value of the target PCIe device.

[0129] In some embodiments, the internal mapped address resource management system 300 may include multiple functional modules composed of computer program segments. The computer programs of each program segment in the internal mapped address resource management system 300 may be stored in the memory of a computer device and executed by at least one processor to perform (see details). Figure 1 (Description) Functionality of internal mapped address resource management.

[0130] In this embodiment, the internal mapping address resource management system 300 can be divided into multiple functional modules according to its functions, such as... Figure 3 As shown. The functional modules may include: a standard acquisition module 310, a data acquisition module 320, a margin monitoring module 330, and an address allocation module 340. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, and are stored in memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0131] The standard acquisition module 310 is used to acquire the spatial range of the server's internal PCI mapping address;

[0132] The data acquisition module 320 is used to acquire the allocated internal mapping addresses and calculate the allocated space of the internal mapping addresses;

[0133] The margin monitoring module 330 is used to take the difference between the spatial range and the allocated space as the space margin, and monitor the space margin based on the early warning threshold.

[0134] Address allocation module 340 is used to confirm that the space margin has reached the warning threshold, move the new PCIe device into the waiting queue, and allocate internal mapping addresses to PCIe devices with required space within the space margin range in sequence.

[0135] Optionally, as an embodiment of the present invention, the data acquisition module includes:

[0136] The condition setting unit is used to set the presence of a newly added PCIe device on the server as an event that triggers the operation of obtaining the internal mapping address;

[0137] A new identification unit is added to confirm the presence of a new PCIe device on the server and to export the address range of the allocated internally mapped addresses from the address management items of the basic input / output system.

[0138] A spatial calculation unit is used to extract the previous and next values ​​of the address region and convert the difference between the previous and next values ​​into a decimal address space.

[0139] The space accumulation unit is used to accumulate the address space of the allocated internal mapped addresses to obtain the allocated space.

[0140] Optionally, as an embodiment of the present invention, the spatial accumulation unit includes:

[0141] The address classification subunit is used to divide the internal mapped addresses into Class I addresses and Class II addresses based on spatial partitioning rules.

[0142] The first accumulation subunit is used to accumulate the address space of the first type of address to obtain the first occupied space;

[0143] The second accumulation subunit is used to accumulate the address space of the second type of address to obtain the second occupied space.

[0144] Optionally, as an embodiment of the present invention, the system includes:

[0145] The mount module is used to obtain PCIe device mount information of the server through query tools;

[0146] The information matching module is used to determine whether the allocated internal mapping address matches the PCIe device mount information.

[0147] The space verification module is used to calculate the required space based on the PCIE device mounting information if the allocated internal mapping address matches the PCIE device mounting information, and to verify whether the required space is within the space range.

[0148] The difference output module is used to output difference information if the allocated internal mapping address does not match the PCIe device mount information.

[0149] Optionally, as an embodiment of the present invention, the spatial verification module includes:

[0150] The type extraction unit is used to extract the internal mapping address type of the PCIe device from the PCIe device mounting information, and divide the internal mapping address into a first type address and a second type address based on the type.

[0151] The first calculation unit is used to accumulate the configuration space capacity of the first type of address to obtain the first required space;

[0152] The second calculation unit is used to accumulate the configuration space capacity of the second type of address to obtain the second required space;

[0153] The capacity determination unit is used to determine whether both the first demand space and the second demand space are within the corresponding space range;

[0154] The first determination unit is used to determine that the current internal mapping address resources are sufficient if both the first demand space and the second demand space are within the corresponding space range.

[0155] The second determination unit is used to generate a prompt message indicating insufficient internal mapping address resources if the first or second demand space is not within the corresponding space range.

[0156] Optionally, as an embodiment of the present invention, the margin monitoring module includes:

[0157] The function management unit is used to confirm that the space margin is not higher than the warning threshold, disable the BIOS's internal mapping address direct allocation function, and restore the BIOS's internal mapping address direct allocation function when the space margin is higher than the warning threshold.

[0158] The queue building unit is used to build a waiting queue and move information of newly connected PCIe devices into the waiting queue according to their access time.

[0159] The configuration parsing unit is used to extract PCIe device information sequentially from the waiting queue, and parse the configuration space from the PCIe device information as the demand space;

[0160] A margin judgment unit is used to determine whether the required space is lower than the space margin.

[0161] A matching allocation unit is used to authorize the BIOS to allocate an internal mapping address to the corresponding PCIe device based on the PCIe device information if the required space is lower than the space margin.

[0162] The target switching unit is used to extract the information of the next PCIe device in the waiting queue if the required space is not less than the space margin.

[0163] Optionally, as an embodiment of the present invention, the system further includes:

[0164] The capacity setting module is used to pre-set multiple granularities and sort the multiple granularities in ascending order;

[0165] The granularity verification module is used to control the BIOS to sequentially set the granularity to the space capacity of the internal mapped address of the target PCIe device;

[0166] The optimal fixation module is used to control the BIOS to terminate the refresh of the internal mapped address space capacity of the target PCIe device when the system stops reporting a PCIe error, and fix the current space value to the optimal space value of the target PCIe device.

[0167] Figure 4 This is a schematic diagram of the structure of a terminal 400 provided in an embodiment of the present invention. The terminal 400 can be used to execute the internal mapping address resource management method provided in the embodiment of the present invention.

[0168] The terminal 400 may include a processor 410, a memory 420, and a communication module 430. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figure does not constitute a limitation of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0169] The memory 420 can be used to store the execution instructions of the processor 410. The memory 420 can be implemented by any type of volatile or non-volatile memory terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 420 are executed by the processor 410, the terminal 400 is able to perform some or all of the steps in the above method embodiments.

[0170] The processor 410 serves as the control center of the storage terminal, connecting various parts of the electronic terminal via various interfaces and lines. It executes software programs and / or modules stored in the memory 420, and calls data stored in the memory to perform various functions of the electronic terminal and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 410 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0171] The communication module 430 is used to establish a communication channel, enabling the storage terminal to communicate with other terminals. It receives user data sent by other terminals or sends user data to other terminals.

[0172] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0173] Therefore, by monitoring the internal mapping address space of the server, the present invention can promptly detect insufficient address space and controllably allocate internal mapping addresses to some devices when the address space is insufficient, thereby avoiding the situation where internal mapping address errors affect server performance. The technical effects achieved by this embodiment can be found in the description above, and will not be repeated here.

[0174] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. It includes several instructions to cause a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0175] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0176] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0177] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0178] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0179] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A method for managing internal mapped address resources, characterized in that, include: Obtain the spatial range of the server's internal PCI mapping addresses; Collect the allocated internal mapping addresses and calculate the allocated space for the internal mapping addresses; The difference between the spatial range and the allocated space is used as the spatial margin, and the spatial margin is monitored based on the early warning threshold. Once the available space has been confirmed to reach the warning threshold, the newly connected PCIe devices are moved into the waiting queue, and internal mapping addresses are allocated sequentially to PCIe devices that require space within the available space. Once the available space has been confirmed to reach the warning threshold, newly connected PCIe devices are moved into the waiting queue. Internal mapped addresses are then allocated sequentially to PCIe devices within the available space range that require space, including… If the remaining space is confirmed to be no higher than the warning threshold, disable the BIOS's internal mapping address direct allocation function, and restore the BIOS's internal mapping address direct allocation function when the remaining space is higher than the warning threshold. Establish a waiting queue and move information about newly connected PCIe devices into the waiting queue in order of their connection time; PCIe device information is extracted sequentially from the waiting queue, and the configuration space is parsed from the PCIe device information as the demand space. Determine whether the required space is lower than the available space: If so, the BIOS is authorized to allocate an internal mapping address to the corresponding PCIe device based on the PCIe device information; If not, retrieve the information of the next PCIe device in the waiting queue.

2. The method according to claim 1, characterized in that, Collect the allocated internal mapping addresses, calculate the allocated space of the internal mapping addresses, including: Configure the server to trigger an event that retrieves the internal mapped address when a new PCIe device is connected. Confirm that a new PCIe device has been connected to the server, and export the address range of the allocated internal mapped addresses from the address management item of the basic input / output system; Extract the previous and next values ​​of the address region, and convert the difference between the previous and next values ​​into a decimal address space; The allocated internal mapping address space is accumulated to obtain the allocated space.

3. The method according to claim 2, characterized in that, The allocated internal mapped address space is accumulated to obtain the allocated space, including: Based on the spatial partitioning rules, the internal mapped addresses are divided into Class I addresses and Class II addresses; The address space of the first type of address is accumulated to obtain the first occupied space; The address space of the second type of address is accumulated to obtain the second occupied space.

4. The method according to claim 1, characterized in that, Before calculating the allocated space for the internal mapped address, the method further includes: Obtain the PCIe device mount information of the server using query tools; Determine if the allocated internal mapping address matches the PCIe device mount information: If so, the required space is calculated based on the PCIe device mounting information, and it is verified whether the required space is within the specified space range; If not, output the difference information.

5. The method according to claim 4, characterized in that, Calculating the required space based on the PCIe device mount information, and verifying whether the required space is within the specified range, includes: Extract the internal mapping address type of the PCIe device from the PCIe device mount information, and classify the internal mapping address into Class I address and Class II address based on the type. The configuration space capacity of the first type of address is accumulated to obtain the first required space; The configuration space capacity of the second type of address is accumulated to obtain the second required space; Determine whether both the first and second demand spaces are within the corresponding space range: If so, then it is determined that the current internal mapping address resources are sufficient; If not, a message indicating insufficient internal mapping address resources will be generated.

6. The method according to claim 1, characterized in that, When allocating internal mapped addresses to a PCIe device, the method further includes: Multiple granularities are pre-defined and sorted in ascending order; The BIOS controls the granularity of the settings to sequentially configure the internal mapped address space capacity of the PCIe devices. The BIOS controls the system to stop refreshing the internal mapped address space capacity of the PCIe device when the system stops reporting a PCIe error, and to fix the current space value as the optimal space value of the PCIe device.

7. An internal mapping address resource management system, used to implement the method as described in any one of claims 1-6, characterized in that, include: The standard acquisition module is used to obtain the spatial range of the server's internal PCI mapping address. The data acquisition module is used to collect the allocated internal mapping addresses and calculate the allocated space of the internal mapping addresses; The margin monitoring module is used to take the difference between the spatial range and the allocated space as the spatial margin, and monitor the spatial margin based on the early warning threshold. The address allocation module is used to confirm that the space margin has reached the warning threshold, move the new PCIe device into the waiting queue, and allocate internal mapping addresses to PCIe devices whose space requirements are within the space margin range in turn.

8. A terminal, characterized in that, include: Memory, used to store internal mapped address resource management programs; A processor, configured to implement the steps of the internal mapped address resource management method as described in any one of claims 1-6 when executing the internal mapped address resource management program.

9. A computer-readable storage medium storing a computer program, characterized in that, The readable storage medium stores an internal mapped address resource management program, which, when executed by a processor, implements the steps of the internal mapped address resource management method as described in any one of claims 1-6.

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