SONOS EEPROM VPOS PUMP Output Voltage Generation Circuit and Control Method

Abstract

The application discloses a SONOS EEPROM VPOS PUMP output voltage generation circuit and a control method. The circuit comprises a charge pump module, wherein the charge pump module comprises a plurality of charge pump circuits, and the plurality of charge pump circuits are connected through a plurality of switches. The plurality of switches can be selectively opened and closed through an external control signal, so that the connection state between the plurality of cascaded charge pump circuits is changed, the parallel connection and the series connection between the charge pump circuits in the module are switched, the circuit can meet the output requirement of different states of high voltage output and strong driving capability, and better support for a plurality of working modes of a memory is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and manufacturing, and in particular to a SONOS EEPROM VPOS PUMP output voltage generation circuit and control method. Background Technology

[0002] In storage devices, reading, writing, and erasing memory cells all involve different operating voltages, especially the erase operation, where the programming voltage is often higher than the voltage provided by the power supply. A pump circuit, also known as a switched-capacitor voltage converter, is a DC-DC converter that uses "flying" or "pumping" capacitors (not inductors or transformers) to store energy. It generates high voltage through the accumulation of charge by the capacitor, causing current to flow from a low potential to a high potential. Simply put, it charges the capacitor, removes it from the charging circuit to isolate the charged charge, and then connects it to another circuit to transfer the isolated charge. In FLASH devices, its function is to use the "pumping capacitor" to boost the power supply voltage to the required erase / write voltage. FLASH products require a charge pump charging circuit to provide the power for erasing and writing. The PUMP circuit in a FLASH device uses multiple capacitors to achieve the voltage boost.

[0003] The equivalent circuit structure of the SONOS memory cell is as follows: Figure 1 As shown, it includes a storage transistor (SONOS) and a selection transistor (FNPASS). Erasing and writing require high-voltage pumps. High level VPOS = 7V; Low level VNEG = -4V; During read operation, the word line WL = VDD. As VDD decreases, using VDD voltage for WL becomes less suitable, as it will severely suppress the current of the SONOS memory transistor.

[0004] In the P cell margin mode of the VTP test, in this test mode, such as Figure 2 As shown, an external voltage is pumped from the TP PAD to VTP, at which point the VTP voltage is 0 < VTP < 2V. The VTP voltage is then transmitted to the Gate terminal (WLS) of the SONOS transistor in the left memory cell via the NCH5 transistor. To ensure sufficient transmission of the external voltage to the WLS terminal, the gate voltage VDD_MARG of the NCH5 transistor must be ≥ VTP + Vthn. This voltage needs to be generated by the PUMP.

[0005] Therefore, a voltage higher than VDD is required. A voltage VPOS_R is generated using PUMP and supplied to the word line WL. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a SONOS EEPROM VPOS PUMP output voltage generation circuit and control method that can output a higher operating voltage.

[0007] To solve the above problems, the present invention provides a SONOS EEPROM VPOS PUMP output voltage generation circuit and control method, comprising: A charge pump module includes at least four charge pump circuits, and at least three switches are connected between the multiple charge pumps. The multiple switches can be selectively turned on and off by external control signals to change the connection state between the multiple cascaded charge pump circuits, thereby enabling the switching between parallel and series connection of the charge pump circuits within the module. The charge pump module includes an input terminal IN and a first output terminal, namely the VPOS node; A first resistor, a second resistor, and a third resistor are connected in series. The series connection point of the first and second resistors is called the first node, and the series connection point of the second and third resistors is called the second node VP2. The other end of the first resistor is grounded. A first NMOS transistor and a first PMOS transistor are connected in parallel between the first output terminal and the first terminal of the third resistor; the gate and drain of the first NMOS transistor are shorted and connected to the source of the first PMOS transistor and the first output terminal; the source of the first NMOS transistor, the drain of the first PMOS transistor, and the first terminal of the third resistor are connected to form a third node VP1; the gate of the first PMOS transistor is connected to the first control signal RDEN. The second NMOS transistor and the second PMOS transistor are connected, with the source of the second PMOS transistor connected to the first output terminal, the gate of the second PMOS transistor connected to the second control signal TM_VTP_B, and the drain of the second PMOS transistor being the second output terminal. The drain and source of the third PMOS transistor are connected across the two ends of the third resistor, that is, between the second node and the third node. The gate of the third PMOS transistor is connected to the third control signal RDEN_B. The third control signal RDEN_B and the first control signal RDEN are opposite signals to each other. The gate and drain of the second NMOS transistor are shorted and connected to the first output terminal, and the source of the second NMOS transistor is the third output terminal.

[0008] Furthermore, in the charge pump module, when the multiple switches connect the multiple charge pump circuits in series, the charge pump module can cascade the multiple charge pump circuits step by step internally, and can output a higher voltage; when the multiple switches connect the multiple charge pump circuits in parallel, the charge pump module can output a larger current and has a stronger driving capability.

[0009] Furthermore, the connection node between the first resistor and the second resistor is also connected to the comparator of the charge pump module for comparison with the reference voltage VREF.

[0010] The control method for the SONOS EEPROM VPOS PUMP output voltage generation circuit described in this invention includes a high-voltage erase / write voltage, a read voltage, and a test mode voltage. The high-voltage erase / write voltage is controlled by an external control signal to open or close multiple switches, cascading multiple charge pump circuits inside the charge pump module to achieve the highest output voltage of the charge pump module. At this time, the first control signal RDEN is low, making the first PMOS transistor in the conducting state, and the third control signal RDEN_B is high, making the third PMOS transistor in the off state. The voltage at the first output terminal is determined by the resistance values ​​of the first resistor, the second resistor, and the third resistor. The read voltage is used to perform a read operation on the memory cell. At this time, multiple switches are turned on and off by external control signals to form a parallel structure of multiple charge pump circuits inside the charge pump module, including a series-parallel connection. The charge pump module in this state has a stronger driving capability. The voltage at the first output terminal is determined by the resistance values ​​of the first resistor and the second resistor, as well as the first NMOS transistor. In test mode, while maintaining the read voltage, the second control signal is set to a low level to turn on the second PMOS transistor. At this time, the voltage at the second output terminal is equal to the voltage at the first output terminal, controlling the VTP voltage in the memory cell to the gate of the memory transistor.

[0011] The second NMOS transistor is a diode, which can achieve a threshold voltage drop across the voltage at the first output terminal and provide the word line to the storage unit when reading data.

[0012] By adjusting the source voltage of the first NMOS transistor, the drain voltage of the first NMOS transistor, i.e., the VPOS voltage, is made to be higher than the source voltage by a threshold voltage. In test mode, this VPOS voltage can be used to control the voltage transmission of the selection transistor.

[0013] The SONOS EEPROM VPOS PUMP output voltage generation circuit and control method described in this invention add multiple switches and control modules to the charge pump circuit to change the connection state of multiple charge pump circuits, switch between different states of high voltage output and strong driving capability, meet different output needs, and achieve better support for multiple working modes of the memory. Attached Figure Description

[0014] Figure 1 It is the equivalent circuit diagram of a memory storage cell.

[0015] Figure 2 This is a connection status diagram of the memory storage unit under test mode.

[0016] Figure 3 This is a schematic diagram of the connection inside the charge pump module according to an embodiment of the present invention.

[0017] Figure 4 This is the charge pump module output voltage feedback control circuit in the test mode of this invention.

[0018] Figure 5 This is a schematic diagram of the output voltage generation circuit of the SONOS EEPROM VPOS PUMP of the present invention. Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0021] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0022] The circuit described in this invention, such as Figure 5 As shown, it includes a charge pump module, a high-voltage erase / write circuit, and a charge pump module output voltage feedback control circuit in test mode.

[0023] The charge pump module comprises at least four charge pump circuits (STAGE1-4), as shown in the figure. At least three switches (S1-S3) connect the multiple charge pumps. These switches can be selectively opened and closed via external control signals to change the connection state between the cascaded charge pump circuits. When the switches connect the multiple charge pump circuits in series, the charge pump module internally cascades the circuits, resulting in a higher output voltage (i.e., a high-voltage erase / write voltage). When the switches connect the multiple charge pump circuits in parallel, the charge pump module outputs a larger current, providing stronger driving capability.

[0024] The charge pump module includes an input terminal IN and a first output terminal, which is the node voltage VPOS.

[0025] The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series to form a series connection. The node where the first resistor R1 and the second resistor R2 are connected in series is the first node DIV; the node where the second resistor R2 and the third resistor R3 are connected in series is the second node VP2. The other end of the first resistor R1 is grounded. The connection node between the first resistor and the second resistor is also connected to the comparator of the charge pump module for comparison with the reference voltage VREF.

[0026] A first NMOS transistor N1 and a first PMOS transistor P1 are connected in parallel between the first output terminal and the first terminal of the third resistor R3. The gate and drain of the first NMOS transistor are shorted and connected to the source of the first PMOS transistor and the first output terminal. The source of the first NMOS transistor, the drain of the first PMOS transistor, and the first terminal of the third resistor R3 are connected to form a third node VP1. The gate of the first PMOS transistor is connected to the first control signal RDEN, which is a read enable signal.

[0027] The second NMOS transistor N2 and the second PMOS transistor P2 are connected. The source of the second PMOS transistor P2 is connected to the first output terminal. The gate of the second PMOS transistor is connected to the second control signal TM_VTP_B. The drain of the second PMOS transistor is the second output terminal VDD_MARG.

[0028] The drain and source of the third PMOS transistor are connected across the two ends of the third resistor R3, that is, between the second node VP2 and the third node VP1. The gate of the third PMOS transistor is connected to the third control signal RDEN_B. This signal is the inverse of the first control signal RDEN; that is, when RDEN is low, RDEN_B is high, and when RDEN is high, RDEN_B is low.

[0029] The first node is also connected to the comparator of the charge pump module for comparison with the reference voltage VREF.

[0030] The gate and drain of the second NMOS transistor are shorted and connected to the first output terminal, and the source of the second NMOS transistor is the third output terminal VPOS_R.

[0031] When the above circuit is working: The high-voltage erase / write voltage is controlled by an external control signal to open or close multiple switches, cascading multiple charge pump circuits inside the charge pump module to achieve the highest output voltage of the charge pump module. At this time, the first control signal is low, making the first PMOS transistor in the on state and the third PMOS transistor in the off state. The voltage at the first output terminal is determined by the resistance values ​​of the first resistor R1, the second resistor R2 and the third resistor R3.

[0032] During READ, the read voltage is used to perform a read operation on the memory cell. At this time, multiple switches are turned on and off by external control signals, forming a parallel structure of multiple charge pump circuits inside the charge pump module, including a series-to-parallel configuration. In this state, the charge pump module has a stronger driving capability. The voltage at the first output terminal is determined by the resistance values ​​of the first and second resistors, as well as the first NMOS transistor N1.

[0033] In test mode, while maintaining the read voltage, the second control signal is set to a low level to turn on the second PMOS transistor. At this time, the voltage at the second output terminal is equal to the voltage at the first output terminal, controlling the VTP voltage in the memory cell to the gate of the memory transistor.

[0034] During high-voltage erasing and writing, the VPOS voltage is 6-7V; during reading, the WL voltage is 2-3V, and the PUMP output voltage is low, but requires greater drive capability. Therefore, the SW control module, such as... Figure 3 As shown, the connection mode of the charge pump circuit is adjusted, and its operating state is as follows: In high-voltage erase / write mode: switches S1 and S3 are open, and S2 is closed. At this time, the four pump stages are connected in series, that is, the charge pump circuit STAGE1 to STAGE4 are cascaded in four stages to gradually increase the voltage, which can achieve a higher output voltage VPOS and realize high-voltage erase / write.

[0035] Read mode: S1 and S3 are closed, S2 is open, and the charge pump circuits STAGE1 to STAGE4 are connected in series and then in parallel, which has a stronger current capability and improves the VPOS drive capability.

[0036] During margin testing, the VPOS PUMP requires both a WL voltage of approximately 2V and a higher voltage to control the transmission of the externally supplied VTP voltage (within 2V) to WLS. Adjusting the VPOS voltage feedback control circuit, such as... Figure 4 As shown.

[0037] Figure 4 In read mode, the circuit shown uses a diode-connected NCH5 transistor to change VPOS from the original DIV*(R1+R2) / R1 to DIV*(R1+R2) / R1 +Vth (multiple Vth values ​​can also be added).

[0038] Adjust the voltage at control point VP1 to approximately 2V, the voltage required for WL, where VPOS = 2V + Vth. When measuring the VTP margin, the VPOS value can be used to control the voltage transmission of the byte select transistor.

[0039] The voltage VPOS_R required for WL can be obtained by reducing VPOS by one Vth through the NCH5 diode, which is connected in a diode configuration, to around 2V.

[0040] refer to Figure 5 During high-voltage erasure and writing, S1 and S3 are open, and S2 is closed. The charge pump module is connected in series internally, providing the highest voltage output capability. When RDEN=0, transistor P1 is on; when RDEN_B=1, transistor P3 is off. At this time, the VPOS voltage is determined by the values ​​of resistors R1, R2, and R3. VPOS=DIV*(R1+R2+R3) / R1, where DIV≈VREF.

[0041] In normal Read mode, S1 and S3 are closed, and S2 is open. The charge pump internally operates by first connecting in series and then in parallel, resulting in stronger driving capability. At this time, the read enable signal RDEN=1, transistor P1 is off, RDEN_B=0, and transistor P3 is on. The VPOS voltage is determined by resistors R1 and R2 and transistor N1, VPOS=DIV*(R1+R2) / R1+Vgsn1. VPOS_R=VPOS-Vgsn2, where Vgsn1≈Vgsn2, therefore VPOS_R≈DIV*(R1+R2) / R1, close to the potential at the third node VP1. It can be seen that the VPOS voltage is high during erase / write operations and low during read operations.

[0042] When measuring VTP margin read, the second control signal TM_VTP_B is 0. In addition to the settings required for normal read mode, P2 transistor must be turned on, and VDD_MARG must be equal to the VPOS potential to control the VTP voltage transmitted to the gate of the SONOS cell.

[0043] The SONOS EEPROM VPOS PUMP output voltage generation circuit and control method described in this invention add multiple switches and control modules to the charge pump circuit, enabling changes in the connection state of multiple charge pump circuits. This allows switching between different states—high voltage output and strong drive capability—to meet various output needs and provides better support for multiple operating modes of the memory. In read data mode, the word line WL voltage is obtained by reducing the VPOS voltage by one Vth using a diode-connected MOSFET, which is simple and effective.

[0044] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A SONOS EEPROM VPOS PUMP output voltage generation circuit, characterized in that: Include: A charge pump module includes at least four charge pump circuits, and at least three switches are connected between the charge pump circuits. The switches can be selectively opened and closed by external control signals to change the connection state between the cascaded charge pump circuits, thereby enabling the switching between parallel and series connections of the charge pump circuits within the module. The charge pump module includes an input terminal and a first output terminal; A first resistor, a second resistor, and a third resistor are connected in series. The series connection point of the first and second resistors is the first node, and the series connection point of the second and third resistors is the second node. The other end of the first resistor is grounded. A first NMOS transistor and a first PMOS transistor are connected in parallel between the first output terminal and the first terminal of the third resistor; the gate and drain of the first NMOS transistor are shorted and connected to the source of the first PMOS transistor and the first output terminal; the source of the first NMOS transistor, the drain of the first PMOS transistor, and the first terminal of the third resistor are connected to form a third node; the gate of the first PMOS transistor is connected to the first control signal RDEN. The second NMOS transistor and the second PMOS transistor are connected, with the source of the second PMOS transistor connected to the first output terminal, the gate of the second PMOS transistor connected to the second control signal TM_VTP_B, and the drain of the second PMOS transistor being the second output terminal. The drain and source of the third PMOS transistor are connected across the two ends of the third resistor, that is, between the second node and the third node. The gate of the third PMOS transistor is connected to the third control signal RDEN_B. The third control signal RDEN_B and the first control signal RDEN are opposite signals to each other. The gate and drain of the second NMOS transistor are shorted and connected to the first output terminal, and the source of the second NMOS transistor is the third output terminal.

2. The SONOS EEPROM VPOS PUMP output voltage generation circuit as described in claim 1, characterized in that: In the charge pump module, when the multiple switches connect the multiple charge pump circuits in series, the charge pump module can cascade the multiple charge pump circuits step by step internally, and can output a higher voltage; when the multiple switches connect the multiple charge pump circuits in parallel, the charge pump module can output a larger current and has a stronger driving capability.

3. The SONOS EEPROM VPOS PUMP output voltage generation circuit as described in claim 1, characterized in that: The connection node between the first resistor and the second resistor is also connected to the comparator of the charge pump module for comparison with the reference voltage VREF.

4. The control method for the SONOS EEPROM VPOS PUMP output voltage generation circuit as described in claim 1, characterized in that: The output voltages include high-voltage erase / write voltage, read voltage, and test mode voltage; The high-voltage erase / write voltage is controlled by an external control signal to open or close multiple switches, cascading multiple charge pump circuits inside the charge pump module to achieve the highest output voltage of the charge pump module. At this time, the first control signal is low, making the first PMOS transistor in the conducting state, and the third control signal RDEN_B is high, making the third PMOS transistor in the off state. The voltage at the first output terminal is determined by the resistance values ​​of the first resistor, the second resistor, and the third resistor. The read voltage is used to perform a read operation on the memory cell. At this time, multiple switches are turned on and off by external control signals to form a parallel structure of multiple charge pump circuits inside the charge pump module, including a series-to-parallel configuration. The output voltage of the charge pump module in this state is lower than the output voltage during erase and write operations, but it has a stronger driving capability. The voltage at the first output terminal is determined by the resistance values ​​of the first resistor and the second resistor, as well as the first NMOS transistor. In test mode, while maintaining the read voltage, the second control signal is set to a low level to turn on the second PMOS transistor. At this time, the voltage at the second output terminal is equal to the voltage at the first output terminal, controlling the VTP voltage in the memory cell to the gate of the memory transistor.

5. The control method for the SONOS EEPROM VPOS PUMP output voltage generation circuit as described in claim 4, characterized in that: The second NMOS transistor is a diode, which can achieve a threshold voltage drop across the voltage at the first output terminal and provide the word line to the storage unit when reading data.

6. The control method for the SONOS EEPROM VPOS PUMP output voltage generation circuit as described in claim 5, characterized in that: By adjusting the source voltage of the first NMOS transistor, the drain voltage of the first NMOS transistor, i.e., the VPOS voltage, is made to be higher than the source voltage by a threshold voltage. In test mode, this VPOS voltage can be used to control the voltage transmission of the selection transistor.

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