Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of good control. A semiconductor storage device of one embodiment includes a memory string, a sense amplifier connected to the memory string, a first latch circuit, a second latch circuit, a third latch circuit, and a fourth latch circuit, a first wiring connected to the sense amplifier, the first latch circuit, and the second latch circuit, a second wiring connected to the third latch circuit, a third wiring connected to the fourth latch circuit, a first switching transistor that electrically connects the first wiring and the third wiring, a second switching transistor that electrically connects the first wiring and the second wiring, and a third switching transistor that electrically connects the second wiring and the third wiring.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-026486 (filed on February 24, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known to have a memory cell array and multiple sense amplifier units. The memory cell array has multiple memory cells and multiple bit lines connected to the multiple memory cells. The multiple sense amplifier units are respectively connected to the multiple bit lines. Summary of the Invention

[0005] This embodiment provides a semiconductor memory device that can be well controlled.

[0006] One embodiment of a semiconductor memory device includes: a memory string; a bit line connected to the memory string; a sense amplifier connected to the bit line; a first latch circuit, a second latch circuit, a third latch circuit, and a fourth latch circuit electrically connected to the sense amplifier; a first wiring connected to the sense amplifier, the first latch circuit, and the second latch circuit; a second wiring connected to the third latch circuit; a third wiring connected to the fourth latch circuit; a first switching transistor electrically disconnectably connecting the first wiring and the third wiring; a second switching transistor electrically disconnectably connecting the first wiring and the second wiring; and a third switching transistor electrically disconnectably connecting the second wiring and the third wiring. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the storage system 10 according to the first embodiment.

[0008] Figure 2 This is a schematic block diagram showing the structure of a memory die (MD).

[0009] Figure 3 This is a schematic circuit diagram showing the configuration of a memory cell array (MCA).

[0010] Figure 4 This is a schematic block diagram showing the configuration of the sense amplifier module (SAM).

[0011] Figure 5 This is a schematic circuit diagram showing the configuration of the sense amplifier unit SAU.

[0012] Figure 6This is a schematic three-dimensional diagram showing the structure of a memory die (MD).

[0013] Figure 7 It is shown Figure 6 A schematic enlarged diagram consisting of a portion of it.

[0014] Figure 8 (a) and (b) are schematic diagrams used to illustrate the data recorded in the storage unit MC.

[0015] Figure 9 It is a schematic cross-sectional diagram used to illustrate the reading action.

[0016] Figure 10 This is a schematic diagram used to illustrate hard bit reading and soft bit reading.

[0017] Figure 11 This is a diagram showing the timing of the operation of the Sensing Amplifier Module (SAM).

[0018] Figure 12 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0019] Figure 13 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0020] Figure 14 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0021] Figure 15 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0022] Figure 16 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0023] Figure 17 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0024] Figure 18 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0025] Figure 19 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0026] Figure 20 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0027] Figure 21 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0028] Figure 22 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0029] Figure 23 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0030] Figure 24 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0031] Figure 25 This is a diagram showing the timing of the operation of the sensing amplifier module SAM involved in the comparative example.

[0032] Figure 26 This is a block diagram used to illustrate the data exchange between multiple latch circuits involved in the comparative example.

[0033] Figure 27 This is a schematic block diagram illustrating a portion of the semiconductor memory device according to the second embodiment.

[0034] Figure 28 This is a schematic block diagram illustrating a portion of the semiconductor memory device according to the third embodiment.

[0035] Figure 29 This is a schematic block diagram illustrating a portion of the semiconductor memory device according to the fourth embodiment. Detailed Implementation

[0036] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention.

[0037] Additionally, in this specification, the term "semiconductor memory device" sometimes means a memory die, and sometimes it means a storage system that includes a controller die, such as a memory chip, memory card, or SSD. Furthermore, it sometimes also means a device that includes a host, such as a smartphone, tablet, or personal computer.

[0038] Furthermore, in this specification, when referring to the first component and the second component as "electrically connected," it can mean that the first component and the second component are directly connected, or that the first component is connected to the second component via wiring, a semiconductor component, or a transistor. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0039] Additionally, in this specification, when it is mentioned that the first component is "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the first component is disposed on the current path of the second and third components.

[0040] Furthermore, in this specification, when referring to a circuit or the like that makes two wires "conduct", it sometimes means, for example, that the circuit or the like contains a transistor or the like that is disposed in the current path between the two wires, and that the transistor or the like is in a conducting state.

[0041] [First Implementation Method]

[0042] [Storage System 10]

[0043] Figure 1 This is a schematic block diagram showing the configuration of the storage system 10 according to the first embodiment.

[0044] The storage system 10 performs user data reading, writing, and erasing based on signals sent from the host 20. That is, it executes read, write, and erase operations. The storage system 10 is, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The storage system 10 includes multiple memory dies (MDs) for storing user data, and a controller die (CD) connected to the multiple memory dies (MDs) and the host 20. The controller die (CD) includes, for example, a processor, RAM, ROM, ECC circuitry, etc., and performs processing such as logical address to physical address conversion, bit error detection / correction, and wear leveling.

[0045] Figure 2 This is a schematic block diagram illustrating the configuration of the memory die MD according to the first embodiment. Figures 3-5 This is a schematic circuit diagram showing a portion of the memory die MD.

[0046] like Figure 2 As shown, the memory die MD has a memory cell array MCA for storing data and peripheral circuitry PC connected to the memory cell array MCA.

[0047] [Memory Cell Array MCA]

[0048] A storage cell array (MCA) has multiple storage blocks (MB). For example... Figure 3 As shown, each of these multiple memory blocks MB has multiple string units SU. Each of these multiple string units SU has multiple memory strings MS. One end of each of these multiple memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other end of each of these multiple memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0049] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0050] The memory cell MC involved in this embodiment is a field-effect transistor (memory transistor) comprising a semiconductor layer that functions as a channel region, a gate insulating film containing a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. In addition, word lines WL are connected to the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all memory strings MS in one memory block MB.

[0051] A selection transistor (STD, STS) is a field-effect transistor that includes a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. Selection gate lines (SGD, SGS) are connected to the gate electrode of the selection transistor (STD, STS). The drain-side selection gate line SGD is provided corresponding to a string cell SU and is commonly connected to all memory strings MS in one string cell SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block MB.

[0052] [Peripheral Circuit PC]

[0053] like Figure 2 As shown, the peripheral circuit PC includes a line decoder RD, a sense amplifier module SAM, a buffer memory CM, a voltage generation circuit VG, and a sequencer SQC. Additionally, the peripheral circuit PC includes an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuit PC includes input / output control circuitry (I / O), logic circuitry CTR, and an output buffer OB.

[0054] The row decoder RD, for example, includes a decoding circuit and a switching circuit. The decoding circuit decodes the row address RA held in the address register ADR. The switching circuit, based on the output signal of the decoding circuit, connects the word line WL corresponding to the row address RA and the select gate lines (SGD, SGS) to the corresponding voltage supply lines.

[0055] like Figure 4As shown, the sense amplifier module SAM has multiple sense amplifier units SAU corresponding to multiple bit lines BL. Each sense amplifier unit SAU includes: a sense amplifier SA connected to the bit line BL; a wiring LBUS1 connected to the sense amplifier SA; latch circuits SDL, BDL, CDL, and TDL connected to the wiring LBUS1; and a pre-charging charging transistor 55 connected to the wiring LBUS1. Figure 5 ), and switching transistors DSW1 and DSW2 connected to wiring LBUS1. Additionally, each of the multiple sense amplifier units SAU includes: wiring LBUS2 connected to the switching transistor DSW2, latch circuit ADL connected to wiring LBUS2, and a pre-charging charging transistor 56 connected to wiring LBUS2. Figure 5 The switching transistor DSW3 is connected to the wiring LBUS2. Additionally, a charging transistor 60 for pre-charging is connected to the wiring DBUS.

[0056] Wiring LBUS1 and wiring DBUS are electrically disconnected via switching transistor DSW1. That is, when switching transistor DSW1 is in the on state, wiring LBUS1 and wiring DBUS are electrically connected, and when switching transistor DSW1 is in the off state, wiring LBUS1 and wiring DBUS are electrically disconnected.

[0057] Wiring LBUS1 and wiring LBUS2 are electrically disconnected via switching transistor DSW2. That is, when switching transistor DSW2 is in the on state, wiring LBUS1 and wiring LBUS2 are electrically connected, and when switching transistor DSW2 is in the off state, wiring LBUS1 and wiring LBUS2 are electrically disconnected.

[0058] Wiring LBUS2 and wiring DBUS are electrically disconnected via switching transistor DSW3. That is, when switching transistor DSW3 is in the on state, wiring LBUS2 and wiring DBUS are electrically connected, and when switching transistor DSW3 is in the off state, wiring LBUS2 and wiring DBUS are electrically disconnected.

[0059] like Figure 5 As shown, the sense amplifier SA includes a sense transistor 31, which discharges the charge on the wiring LBUS1 according to the current flowing through the bit line BL. The source electrode of the sense transistor 31 is connected to the ground voltage supply terminal. The drain electrode is connected to the wiring LBUS1 via a switching transistor 32. The gate electrode is connected to the bit line BL via the sense node SEN, the discharge transistor 33, the node COM, the clamping transistor 34, and the withstand voltage transistor 35. The sense node SEN is connected to the supply voltage V via the charging transistor 36 and the charging transistor 37. DDThe voltage supply line is connected and via capacitor 38 is connected to the internal control signal CLK. Node COM is connected to the supply voltage V via charging transistors 39 and 37. DD The voltage supply line is connected and connected to the supply voltage V via the discharge transistor 40. SRC The voltage supply line is connected.

[0060] Sensing transistor 31, switching transistor 32, discharging transistor 33, clamping transistor 34, charging transistor 36, charging transistor 39, and discharging transistor 40 are, for example, enhancement-mode NMOS transistors. Voltage-degrading transistor 35 is, for example, a depletion-mode NMOS transistor. Charging transistor 36 is, for example, a PMOS transistor.

[0061] The gate electrode of switching transistor 32 is connected to sequencer SQC via signal line STB. The gate electrode of discharge transistor 33 is connected to sequencer SQC via signal line XXL. The gate electrode of clamping transistor 34 is connected to sequencer SQC via signal line BLC. The gate electrode of withstand transistor 35 is connected to sequencer SQC via signal line BLS. The gate electrode of charging transistor 36 is connected to sequencer SQC via signal line HLL. The gate electrode of charging transistor 37 is connected to node INV of latch circuit SDL. The gate electrode of charging transistor 39 is connected to sequencer SQC via signal line BLX. The gate electrode of discharge transistor 40 is connected to node INV of latch circuit SDL.

[0062] The latch circuit SDL includes: nodes LAT and INV; inverters 41 and 42 connected in parallel with these nodes LAT and INV; a switching transistor 43 connected to node LAT and wiring LBUS1; and a switching transistor 44 connected to node INV and wiring LBUS1. Switching transistors 43 and 44 are, for example, NMOS transistors. The gate electrode of switching transistor 43 is connected to the sequencer SQC via signal line STI. The gate electrode of switching transistor 44 is connected to the sequencer SQC via signal line STL.

[0063] The latch circuits ADL, BDL, CDL, and TDL have almost the same structure as the latch circuit SDL. However, although the node LAT or node INV of the latch circuit SDL is connected to the sense amplifier SA, the configurations of the latch circuits ADL, BDL, CDL, and TDL corresponding to the node LAT or node INV are not connected to the sense amplifier SA.

[0064] The switching transistor DSW1 is, for example, an enhancement-mode NMOS transistor. The switching transistor DSW1 is connected between wiring LBUS1 and wiring DBUS. The gate electrode of the switching transistor DSW1 is connected to the sequencer SQC via signal line DBS1.

[0065] Switching transistors DSW2 and DSW3 are, for example, enhancement-mode NMOS transistors. Switching transistor DSW2 is connected between wiring LBUS1 and wiring LBUS2. Switching transistor DSW3 is connected between wiring LBUS2 and wiring DBUS. The gate electrodes of switching transistors DSW2 and DSW3 are connected to the sequencer SQC via signal lines DBS2 and DBS3, respectively.

[0066] like Figure 4 As illustrated, the aforementioned signal lines STB, XXL, BLC, BLS, HLL, and BLX are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. Additionally, the voltage V supplied is... DD and voltage V SRC The voltage supply lines are commonly connected between all the sense amplifier units (SAUs) contained in the sense amplifier module (SAM).

[0067] Furthermore, the signal lines STI and STL of the latch circuit SDL are commonly connected among all the sense amplifier units SAU contained in the sense amplifier module SAM. Similarly, the signal lines ATI, ATL, BTI, BTL, CTI, CTL, TTI, and TTL in the latch circuits ADL, BDL, CDL, and TDL, respectively, corresponding to the signal lines STI and STL, are commonly connected among all the sense amplifier units SAU contained in the sense amplifier module SAM.

[0068] Furthermore, multiple signal lines DBS1 and DBS3 are provided for each of the various sense amplifier units (SAUs) included in the sense amplifier module SAM, and each is independently connected to each sense amplifier unit (SAU). Additionally, signal line DBS2 is connected in a common manner to all sense amplifier units (SAUs) included in the sense amplifier module SAM.

[0069] Buffer memory CM ( Figure 2 XDL ( ) has multiple latching circuits Figure 5 The latch circuit XDL and the bidirectional bus YIO ( Figure 2 as well as Figure 5 The latch circuit XDL temporarily holds write data sent from the input / output control circuit I / O via the bidirectional bus YIO. Additionally, the latch circuit XDL temporarily holds read data sent from the latch circuit CDL or latch circuit ADL via wiring LBUS1, DBUS or wiring LBUS2, DBUS.

[0070] Voltage generation circuit VG ( Figure 2For example, it includes a boost circuit such as a charge pump circuit connected to a power supply terminal and a ground terminal, a buck circuit such as a regulator, and multiple voltage supply lines (not shown). Furthermore, the aforementioned boost circuit and buck circuit are respectively connected to the power supply voltage supply terminal V. CC V SS Connection. The voltage generation circuit VG supplies the power supply voltage to terminal V according to the internal control signal from the sequencer SQC. CC -V SS The voltage is boosted or bucked between the bits to generate multiple operating voltages supplied to the bit line BL, source line SL, word line WL, and select gate line (SGD, SGS) during read, write, and erase operations of the memory cell array MCA, and output simultaneously from multiple voltage supply lines.

[0071] The sequencer SQC sequentially decodes the command data CMD held in the command register CMR and outputs internal control signals to the line decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. Additionally, the sequencer SQC appropriately outputs status data indicating its own status to the status register STR. For example, during a write or erase operation, it outputs information indicating whether the write or erase operation has completed normally. Furthermore, the sequencer SQC outputs a ready / busy signal RB to the output buffer OB. The ready / busy signal RB informs the controller die CD whether it is in a ready state (able to accept commands from the controller die CD) or a busy state (not accepting commands).

[0072] The input / output control circuit (I / O) includes data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS and / DQS, multiple input circuits, multiple output circuits, shift registers, and buffer circuits.

[0073] Data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the buffer memory CM, address register ADR, or command register CMR based on internal control signals from the logic circuit CTR. Additionally, data input via data signal input / output terminals DQ0 to DQ7 is input to the buffer circuit from the buffer memory CM or status register STR based on internal control signals from the logic circuit CTR.

[0074] Multiple input circuits include, for example, a comparator connected to one of the data signal input / output terminals DQ0 to DQ7 or both the trigger signal input / output terminals DQS and / DQS. Multiple output circuits include, for example, an OCD (Off-Chip Driver) circuit connected to one of the data signal input / output terminals DQ0 to DQ7 or both the trigger signal input / output terminals DQS and / DQS.

[0075] The logic circuit CTR receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, / RE, and RE, and correspondingly outputs internal control signals to the input / output control circuit (I / O). The output buffer OB outputs the ready / busy signal RB from the sequencer SQC to the controller die CD via the external output terminal RBn. Furthermore, the "H" state of the external output terminal RBn indicates the ready state, and the "L" state indicates the busy state.

[0076] Next, refer to Figure 6 as well as Figure 7 Hereinafter, an example of the configuration of the semiconductor memory device involved in this embodiment will be described. Figure 6 This is a schematic perspective view of the semiconductor memory device involved in this embodiment. Figure 7 It is shown Figure 6 A schematic enlarged view comprising a portion of it. Additionally, Figure 6 as well as Figure 7 The diagram shows an illustrative configuration; the actual configuration can be modified as appropriate. Furthermore, in Figure 6 as well as Figure 7 In the text, a portion of the composition is omitted.

[0077] like Figure 6 As shown, the memory die MD includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR and set in transistor layer L TR The upper storage cell array layer L MCA .

[0078] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing P-type impurities. An N-type well containing N-type impurities such as phosphorus (P) is provided on a portion of the surface of the semiconductor substrate 100. Additionally, a P-type well containing P-type impurities such as boron (B) is provided on a portion of the surface of the N-type well. Furthermore, an insulating region 100I is provided on a portion of the surface of the semiconductor substrate 100.

[0079] In transistor layer L TR In the semiconductor substrate 100, multiple transistors Tr are disposed to form the peripheral circuit PC. The source region, drain region, and channel region of transistor Tr are disposed on the surface of semiconductor substrate 100. The gate electrode gc of transistor Tr is disposed on transistor layer L. TR In the middle, contacts CS are disposed on the source region, drain region, and gate electrode gc of these multiple transistors Tr. These multiple contacts CS are connected via transistor layer L. TR The wiring D0, D1, D2 and other transistors Tr, memory cell array layer L MCA The components and connections in the text.

[0080] Storage cell array layer L MCA It has multiple memory blocks BLK arranged alternately in the Y direction and multiple inter-block structures ST. The memory block BLK has multiple conductive layers 110 and multiple insulating layers 101 arranged alternately in the Z direction, multiple semiconductor pillars 120 extending in the Z direction, and multiple gate insulating films 130 respectively disposed between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0081] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction, and multiple layers are arranged along the Z direction. The conductive layer 110 may, for example, contain a stacked film of titanium nitride (TiN) and tungsten (W), or it may contain polycrystalline silicon containing impurities such as phosphorus or boron.

[0082] Among the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side selected gate line (SGS). Figure 3 The gate electrodes of the multiple source-side selection transistors (STS) connected thereto also function as the word lines (WL). Additionally, multiple conductive layers 110 located above them serve as the gate electrodes of the multiple source-side selection transistors (STS). Figure 3 ) and multiple storage units MC connected to it. Figure 3 The gate electrode of the transistor functions as a drain-side selected gate line (SGD) and a plurality of drain-side selected transistors (STDs) connected thereto. Additionally, one or more conductive layers 110 located above it serve as drain-side selected gate lines (SGD) and connected to them as multiple drain-side selected transistors (STDs). Figure 3 The gate electrode plays a role.

[0083] A conductive layer 112 is disposed below the conductive layer 110. The conductive layer 112 includes a semiconductor layer 113 connected to the lower end of the semiconductor pillar 120, and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may, for example, contain a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 110.

[0084] Conductive layer 112 serves as the source line SL ( Figure 3 ) plays a role. Source lines (SLs) are used, for example, in memory cell arrays (MCAs). Figure 3 All storage blocks (BLK) contained in the ) are configured in a common manner.

[0085] Multiple semiconductor pillars 120 are arranged in the X and Y directions. The semiconductor pillars 120 are, for example, undoped polycrystalline silicon (Si) or other semiconductor films. The semiconductor pillars 120 have a generally cylindrical shape, with an insulating film 125, such as silicon oxide, disposed in the central portion. Furthermore, the outer peripheral surfaces of the semiconductor pillars 120 are surrounded by conductive layers 110. The lower end of the semiconductor pillar 120 is connected to the semiconductor layer 113 of the aforementioned conductive layer 112. The upper end of the semiconductor pillar 120 is connected to the bit line BL via an impurity region 121 containing N-type impurities such as phosphorus (P) and contacts Ch and Cb. The semiconductor pillars 120 each serve as a memory string MS ( Figure 3 The multiple memory cells MC contained in the transistor, as well as the channel regions of the selection transistors STD and STS, play a role.

[0086] For example, such as Figure 7 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0087] In addition, Figure 7 The example shown is a gate insulating film 130 having a charge storage film 132 such as silicon nitride, but the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0088] Inter-block ST construction, for example, Figure 6 As shown, it extends in the X and Z directions. The inter-block structure ST may also include, for example, an insulating layer such as silicon oxide (SiO2). In addition, the inter-block structure ST may also include, for example, a conductive layer extending in the X and Z directions and connected to the conductive layer 112, and an insulating layer such as silicon oxide (SiO2) disposed on both sides of the conductive layer in the Y direction.

[0089] [Threshold voltage of memory cell MC]

[0090] Next, refer to Figure 8 The threshold voltage of the memory cell MC is explained. Figure 8 (a) is a schematic histogram illustrating the threshold voltage of the memory cell MC. The horizontal axis shows the voltage of the word line WL, and the vertical axis shows the number of memory cells MC. Figure 8 (b) is an example of the threshold voltage of the storage cell MC and the data recorded in the storage cell MC.

[0091] As described above, the memory cell array MCA has multiple memory cells (MCs). When a write operation is performed on these multiple memory cells (MCs), the threshold voltage of these memory cells (MCs) is controlled to various states. Figure 8 (a) shows the distribution of threshold voltages for memory cells MC controlled in eight states. For example, the threshold voltage of a memory cell MC controlled in state A is higher than that of a memory cell MC controlled in state A. Figure 8 The reading voltage V of (a) CGAR Larger than the reading voltage V CGBR Small. Furthermore, the threshold voltage of all memory cell MCs is less than... Figure 8 (a) Reading the on-state voltage V READ .

[0092] In this embodiment, by adjusting the storage unit MC to 8 states, 3 bits of data are recorded in each storage unit MC.

[0093] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erase state). The memory cell MC corresponding to the Er state is, for example, assigned the data "111".

[0094] Furthermore, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er mentioned above. For example, the memory cell MC corresponding to state A is assigned the data "110".

[0095] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A above. The memory cell MC corresponding to state B is, for example, assigned the data "100".

[0096] Similarly, in the diagram, states C through G correspond to threshold voltages that are higher than those corresponding to states B through F. The memory cells MC corresponding to these distributions are, for example, assigned the data “000”, “010”, “011”, “001”, and “101”.

[0097] In addition, Figure 8 In the configuration illustrated in (b), the data of the lower-order bits can be read via two read voltages V. CGAR V CGER To determine this, the data of the median bit can be obtained through three read voltages V. CGBR V CGDR V CGFR To determine this, the high-order bits of data can be read through two voltage V. CGCR V CGGR This is used to make a judgment. Sometimes such data allocation is called 2-3-2 code.

[0098] In addition, the number of bits of data recorded in the storage unit MC, the number of states, and the data allocation for each state can be changed appropriately.

[0099] [Reading action]

[0100] Next, the read operation of the semiconductor memory device according to this embodiment will be described.

[0101] Figure 9 This is a schematic cross-sectional diagram used to illustrate the read operation. Furthermore, the following description illustrates examples of each memory cell (MC) storing multiple bits of data and using various read voltages during the read operation.

[0102] Additionally, in the following explanation, the word line WL that will sometimes become the object of the action is referred to as the selection word line WL. S The word lines WL other than these are called non-selective word lines WL. U Additionally, in the following explanation, the selection word line WL is described as being related to the multiple memory units MC contained in the string unit SU that becomes the action object. S An example of a connected storage unit (hereinafter sometimes referred to as a "selection storage unit MC") performing a read operation. Additionally, in the following description, a configuration containing multiple such selection storage units MCs is sometimes referred to as a selection page PG.

[0103] In the read operation, for example, supplying voltage V to the bit line BL. DD For example, to make Figure 5 The latching circuit SDL latches "H", setting the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". This supplies voltage V to bit line BL and sensing node SEN. DD Additionally, a voltage V is supplied to the source line SL. SRC Voltage V SRC It can be greater than the ground voltage V SS It can also be related to the ground voltage V SS Equal. Voltage V DD Greater than voltage V SRC .

[0104] Additionally, during the read operation, a voltage V is supplied to the gate line SGD on the drain side. SG Voltage V SG Greater than voltage V DD Additionally, voltage V SG With voltage V DD The voltage difference between them is greater than the threshold voltage at which the drain-side select transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD, transferring voltage V. DD .

[0105] Additionally, during the read operation, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG Greater than voltage V SRC Additionally, voltage V SG With voltage V SRC The voltage difference between them is greater than the threshold voltage at which the source-side select transistors STS and STSb function as NMOS transistors. Therefore, an electron channel is formed in the channel region of the source-side select transistors STS and STSb, transferring voltage V. SRC .

[0106] Additionally, during the read operation, the non-select word line WL is... U Supply reads the on-state voltage V READ Read the on-state voltage V READ Greater than voltage V DD V SRC Additionally, regardless of the data recorded in the storage cell MC, the read conduction voltage V is... READ With voltage V DD V SRC The voltage difference between them is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transferring a voltage V to the selected memory cell MC. DD V SRC .

[0107] Additionally, during the read operation, select the word line WL. S Supply reading voltage V CGR Read voltage V CGR Less than the read conduction voltage V READ Read voltage V CGR It is a reference Figure 8 Explanation of the reading voltage V CGAR ~V CGGR One of them. Read the voltage V. CGR With voltage V SRC The voltage difference between the two is greater than the threshold voltage of the storage cell MC that records a portion of the data. Therefore, the storage cell MC that records a portion of the data becomes conductive. Consequently, current flows through the bit line BL connected to this storage cell MC. On the other hand, the read voltage V... CGR With voltage V SRC The voltage difference between the two is less than the threshold voltage of the memory cell MC that records a portion of the data. Therefore, the memory cell MC that records a portion of the data is in the off state. Consequently, current does not flow through the bit line BL connected to such a memory cell MC.

[0108] Additionally, during the reading operation, the sensing amplifier SA ( Figure 5 The system detects whether current flows through the bit line BL, thereby detecting the on / off state of the memory cell MC. This action will be referred to as a "sensing action." In a sensing action, for example, when current flows through the bit line BL... Figure 3 Supply voltage V DD In this state, the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, H, H, H, L, L". This causes the sensing amplifier SA ( Figure 5 The sensing node SEN of the sensor is turned on and the bit line BL is turned on. Additionally, after a certain period, the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, L". This activates the sensing amplifier SA ( Figure 5 The sensing node SEN of the sensing transistor 31 is electrically disconnected from the bit line BL. After the sensing action is performed, the sensing transistor 31 and the wiring LBUS1 ( Figure 5 When the circuit is turned on, the charge on wiring LBUS1 is either discharged or maintained. Additionally, a latch circuit within the sense amplifier unit SAU is connected to wiring LBUS1, latching the data on wiring LBUS1 through this latch circuit.

[0109] Furthermore, during the read operation, AND, OR, and other operations are performed on the data indicating the state of the aforementioned storage unit MC as needed, thereby calculating the data recorded in the storage unit MC. Additionally, this data is transmitted via wiring LBUS1 ( Figure 5 Switching transistors DSW1, or switching transistors DSW2, DSW3 and wiring LBUS2, and wiring DBUS are transmitted to the buffer memory CM. Figure 2 The latch circuit XDL () within Figure 5 ).

[0110] [Cache read]

[0111] The semiconductor memory device described in this embodiment is configured to perform cache reads in addition to normal read operations. Cache reads are performed essentially the same as normal read operations. However, as will be explained later... Figure 11 During a normal read operation, the external output terminal RBn is in the "L" state. On the other hand, during a cache read operation, the external output terminal RBn is generally in the "H" state.

[0112] Hard bit read and soft bit read

[0113] Figure 10This is a diagram used to illustrate hard bit reading and soft bit reading. (See reference...) Figure 8 As explained, during the read operation, by sending a selection word line WL... S Supply reading voltage V CGR (Read voltage V) CGAR ~V CGGR (One of them), to detect the on / off state of the memory cell MC. Read voltage V CGR It is set as the boundary for the distribution of the threshold voltage of the memory cell MC.

[0114] However, sometimes the threshold voltage distribution of a memory cell (MC) is not accurately distributed. For example... Figure 10 As shown, sometimes the actual threshold voltage distribution ( Figure 10 The distribution shown by the dashed line will be relative to the distribution of the ideal threshold voltage. Figure 10 The distribution shown by the solid line deviates from the specified voltage value. Furthermore, sometimes the actual threshold voltage distribution is wider than the ideal threshold voltage distribution, causing the actual threshold voltage distribution to overlap with adjacent threshold voltage distributions. In this case, it is possible that data different from the written data will be read in some memory cells (MC).

[0115] Here, during the read operation, both hard bit reads and soft bit reads are performed to improve error correction accuracy. Sometimes, the data read in hard bit reads is called "read data HB". "Read data HB" refers to data such as the applied voltage level of word line WL obtained at a standard level. Sometimes, the data read in soft bit reads is called "read data SB". "Read data SB" refers to data obtained, for example, by changing the applied voltage level of word line WL, used for accuracy verification during read operations.

[0116] In hard-bit reading, a read voltage set at the boundary of the threshold voltage distribution is used to perform the reading operation, and it is determined whether the threshold voltage of the memory cell MC is higher than the read voltage. That is, hard-bit reading is the same as normal reading.

[0117] In soft bit reading, the reading operation is performed under different conditions than in hard bit reading. The controller on the CD uses the read data from both hard bit and soft bit reading to extract potentially erroneous bits and perform error correction.

[0118] In this embodiment, during hard bit reading, the select word line WL is... S Apply a certain reading voltage ( Figure 10 The notation is "V" HB The voltage of the selected word line WL is measured and a sensing action is performed for a specified time. Additionally, during soft bit reading, the selected word line WL is... SApply the same read voltage ("V") as in the case of hard bit read. HB "), performing sensing actions at different times. More specifically, in soft bit reads, the hard bit read performed just before the soft bit read is applied to the select word line WL. S Reading voltage ("V") HB "), and at the same time change the time of the sensing action (sensing time).

[0119] By extending the sensing time, the signal from the sensing node SEN during the sensing action ( Figure 5 The discharge amount will increase, making it easy to determine that the memory cell MC is turned on. Equivalently, this is equivalent to increasing the discharge applied to the select word line WL. S The voltage on the sensor. Additionally, by shortening the sensing time, the voltage from the sensing node SEN ( Figure 5 The discharge amount will decrease, so it is easy to determine that the memory cell MC is cut off. Equivalently, this is equivalent to reducing the amount of discharge applied to the select word line WL. S The voltage applied to the select word line WL. That is, by adjusting the sensing action, it is possible to obtain the voltage applied to the select word line WL. S The effect of a false change in the read voltage.

[0120] That is, the soft-bit reading of the implementation method yields the same result as the case where the reading operation is performed with a spuriously different reading voltage instead of directly changing the reading voltage of the hard-bit reading. Specifically, by shortening the sensing time of the sensing amplifier SA, a reading voltage lower than the standard reading voltage is obtained ( Figure 10 The notation is "V" SB- The same result was obtained when the reading operation was performed at a voltage higher than the standard voltage. Furthermore, by extending the sensing time of the sensing amplifier SA, a reading voltage (higher than the standard voltage) was obtained. Figure 10 The notation is "V" SB+ The same result is obtained when reading the voltage.

[0121] Additionally, in soft bit reading, the select word line WL can also be selected. S A different read voltage is applied than that used for hard-bit reads. In this case, the sensing time for hard-bit reads and soft-bit reads can also be the same. Furthermore, the read voltage and sensing time can also be different for both hard-bit and soft-bit reads.

[0122] [Sensor Amplifier Module (SAM) Operation]

[0123] Next, refer to Figures 11-24 The operation of the Sensing Amplifier Module (SAM) will be explained.

[0124] Figure 11This is a diagram showing the timing of the operation of the Sensing Amplifier Module (SAM). Figures 12-24 It is a schematic block diagram used to illustrate data exchange between multiple latching circuits.

[0125] Furthermore, in the reading operation involved in this embodiment, such as Figure 11 As shown, corresponding to each state of the memory cell MC, the execution of hard bit reads ( Figure 10 voltage V HB ) and the soft bit read on the positive side ( Figure 10 voltage V SB+ The two sensing actions correspond to this. Additionally, as shown in the reference... Figure 4 and Figure 5 As explained, a sensing amplifier SA is connected to wiring LBUS1, but... Figures 12-24 The sensing amplifier SA is omitted. Furthermore, in the following description, it is explained according to... Figure 8 Example of 2-3-2 code allocation data in (b).

[0126] Furthermore, in the following explanation, sometimes a 2-digit hexadecimal number is used to represent the 8-bit data input to the 8 data signal input / output terminals DQ0 to DQ7. For example, when "0,0,0,0,0,0,0,0,0" is input to the 8 data signal input / output terminals DQ0 to DQ7, this data is sometimes represented as data 00h, etc. Similarly, when "1,1,1,1,1,1,1,1,1" is input, this data is sometimes represented as data FFh, etc.

[0127] When a read operation begins, the controller CD outputs a set of commands instructing the read operation (hereinafter sometimes referred to as read commands for the read operation) to the memory MD via data signal input / output terminals DQ0-DQ7. For example... Figure 11 As shown, the read command used for the read action includes data 00h, ADD, and 30h.

[0128] Data 00h is the command data CMD input to the Command Register (CMR). This data 00h is input at the start of the read operation. Data ADD is the data input to the Address Register (ADR). This data ADD contains the column address CA and the row address RA. Data ADD can, for example, contain 8 bits of data for 5 to 6 cycles. Data 30h is the command data CMD input to the Command Register (CMR). This data 30h indicates that the input of the command set used for the read operation has ended.

[0129] The sequencer SQC changes the external output terminal RBn from the "H" state to the "L" state based on the read command input for the read operation. Simultaneously, access to the memory die MD is disabled. Furthermore, a read operation is performed on the memory die MD.

[0130] Figure 11 The "True busy" status indicates that access to the sense amplifier module (SAM) is disabled, or that a write, read, or erase operation is being performed on the memory cell array (MCA). When a read operation begins in the sense amplifier module (SAM), "True busy" changes from "H" to "L". Figure 11 The “tR” in the text means the period during which the read operation is performed.

[0131] like Figure 11 As shown, during the read operation, the sequencer SQC directs the select word line WL. S Supply reads the on-state voltage V READ .

[0132] Additionally, the sequencer SQC directs the select word line WL S Supply reading voltage V CGER Therefore, with Figure 8 In (a), the memory cells MC corresponding to states Er to D become on, and the memory cells MC corresponding to states E to G become off. Additionally, the sequencer SQC charges the bit line BL. Furthermore, the sequencer SQC controls the charging transistor 55 for pre-charging. Figure 5 The circuit LBUS1 is charged. At this time, the switching transistors DSW1, DSW2, and DSW3 are all in the off state.

[0133] In addition, the sequencer SQC performs sensing actions corresponding to hard bit readings. Figure 11 The “sense ER(HB)” in the text. Here, as mentioned above, the read voltage V of the hard bit read. CGER ( Figure 10 voltage V HB The reading voltage V of the normal reading operation CGER ( Figure 8 The same. Therefore, in the sensing action corresponding to hard bit reading, the select word line WL is... S Supply reading voltage V CGER And the sensing time is set to the same as the reading voltage V during a normal reading operation. CGER And the same magnitude as the sensing time. By performing the sensing action corresponding to the hard bit read, the sensing amplifier SA obtains the same value as the read voltage V. CGER The corresponding read data (read data HB(ER)).

[0134] Figure 12 Shown in Figure 11 The flow of data HB(ER) read at time t1. For example... Figure 12As shown, the read data HB(ER) obtained through sensing action is transmitted to the latch circuit CDL via wiring LBUS1. The latch circuit CDL holds the read data HB(ER).

[0135] In addition, the sequencer SQC performs sensing actions corresponding to the soft bit reading. Figure 11 The "sense ER(SB+)" in the text refers to the false or direct application of the read voltage V to the hard bit read. CGER ( Figure 10 voltage V HB Different voltages. Figure 11 In the example, select word line WL S Supply voltage V HB This makes the read time for soft-bit reads longer than that for hard-bit reads. Therefore, it is possible to extend the read time of the sensing node SEN ( Figure 5 The discharge time of ) is substantially the same as that of the select word line WL. S Supply voltage V SB+ The same effect is achieved in the case of [the situation]. By performing the sensing action corresponding to the soft bit readout, the sensing amplifier SA obtains the reading voltage V. CGER The corresponding read data (read data SB(ER)).

[0136] Figure 13 Shown in Figure 11 The flow of data SB(ER) read at time t2. For example... Figure 13 As shown, the read data SB(ER) obtained through sensing action is transmitted to the latch circuit BDL via wiring LBUS1. The latch circuit BDL holds the read data SB(ER).

[0137] Next, the sequencer SQC directs the select word line WL. S Supply reading voltage V CGAR Therefore, with Figure 8 In (a), the memory cell MC corresponding to the Er state becomes the on state, and the memory cell MC corresponding to the A state to the G state becomes the off state.

[0138] In addition, the sequencer SQC performs sensing actions corresponding to hard bit readings. Figure 11 The "sense AR(HB)" in the text. Therefore, the sense amplifier SA obtains the reading voltage V. CGAR The corresponding read data (read data HB(AR)).

[0139] Figure 14 Shown in Figure 11 The flow of data HB(AR) read under timer t3. For example... Figure 14As shown, the read data HB(AR) obtained through sensing is transmitted via wiring LBUS1. At this time, the read data HB(ER) is held in the latch circuit CDL. The sensing amplifier SA performs a prescribed logical operation on the read data HB(ER) and the read data HB(AR). The latch circuit CDL holds the result of this logical operation, HB(ER / AR). The result of this logical operation, HB(ER / AR), is the read data HB[LP] of the low-order bit (low-order page).

[0140] In addition, the sequencer SQC performs sensing actions corresponding to the soft bit reading. Figure 11 The "sense AR(SB+)" in the text. Therefore, the sense amplifier SA obtains the reading voltage V. CGAR The corresponding read data (read data SB(AR)).

[0141] Figure 15 Shown in Figure 11 The flow of data SB(AR) read under timer t4. For example... Figure 15 As shown, the read data SB(AR) acquired through sensing is transmitted via wiring LBUS1. At this time, the latch circuit BDL holds the read data SB(ER). The sensing amplifier SA performs a prescribed logic operation on the read data SB(ER) and the read data SB(AR). The latch circuit BDL holds the result of this logic operation, SB(ER / AR). The result of this logic operation, SB(ER / AR), is the read data SB[LP] of the low-order bit (low-order page).

[0142] Sequencer SQC directs select word line WL S Supply reads the on-state voltage V READ .

[0143] Figure 16 Shown in Figure 11 The flow of read data HB[LP] at time t5. Before time t5, the sequencer SQC controls the charging transistor 60 for pre-charging. Figure 5 This charges the wiring DBUS. Additionally, the sequencer SQC controls switching transistor DSW1 to the ON state and switching transistors DSW2 and DSW3 to the OFF state. For example... Figure 16 As shown, the read data HB[LP] is transmitted from the latch circuit CDL to the latch circuit XDL via wiring LBUS1 and DBUS. The latch circuit XDL holds the read data HB[LP].

[0144] Figure 17 Shown in Figure 11The flow of read data SB[LP] at time t6. Before time t6, the sequencer SQC controls the charging transistor 56 for pre-charging. Figure 5 The circuit LBUS2 is charged. Additionally, the sequencer SQC controls switching transistor DSW1 to the off state, switching transistor DSW2 to the on state, and DSW3 to the off state. For example... Figure 17 As shown, the read data SB[LP] is transmitted from latch circuit BDL to latch circuit ADL via wiring LBUS1 and LBUS2. Latch circuit XDL holds the read data HB[LP].

[0145] In addition, Figure 11 In the example shown, at time t3, the read data HB[LP] is held in latch circuit CDL; at time t4, the read data SB[LP] is held in latch circuit BDL; and then, at time t5, the read data HB[LP] held in latch circuit CDL is transferred to latch circuit XDL. However, it is also possible to transfer the read data HB[LP] held in latch circuit CDL to latch circuit XDL before the read data SB[LP] is held in latch circuit BDL at time t4.

[0146] Then, the sequencer SQC directs the select word line WL. S Supply ground voltage V SS .

[0147] Next, the memory die MD controls the external output terminal RBn from the "L" state (busy state) to the "H" state (ready state).

[0148] exist Figure 11 In the example, after the external output terminal RBn changes from the "L" state to the "H" state, the controller die CD outputs a set of commands (hereinafter sometimes referred to as cache read commands) instructing the memory die MD to read the cache via data signal input / output terminals DQ0~DQ7. Figure 11 As shown, the read commands used for cache reading include data 00h, ADD, and 31h.

[0149] Data 00h and data ADD are the same as the data 00h and data ADD of the read command. Data 31h is the command data CMD input to the command register CMR. This data 31h indicates that the input of the command set used for buffered read has ended.

[0150] The sequencer SQC, based on the input of the command set for cache reads, controls the external output terminal RBn from the "H" state to the "L" state. This disables access to the memory die MD. Meanwhile, a cache read is performed on the memory die MD. At this time, Figure 11 The "True busy" status also changed from "H" to "L".

[0151] Here, in a normal read operation, upon receiving the command set instructing the normal read operation, after the external output terminal RBn changes from the "H" state to the "L" state, the read data held in the latch circuits BDL and CDL within the sensing amplifier SA is transferred to the latch circuits ADL and XDL, at which point the external output terminal RBn is controlled from the "L" state to the "H" state. That is, in a normal read operation, the state of the external output terminal RBn is... Figure 11 This aligns with the "True busy" state. On the other hand, during buffer reads, upon receiving the command set instructing a buffer read, after the external output terminal RBn changes from the "H" state to the "L" state, before the read data held in the latch circuits BDL and CDL within the sense amplifier SA is transmitted to the latch circuits ADL and XDL, the external output terminal RBn is controlled from the "L" state to the "H" state. That is, during buffer reads, the state of the external output terminal RBn is consistent with... Figure 11 The "True busy" state is inconsistent. More specifically, during a cache read, after the memory die MD receives a set of commands instructing a cache read, the external output terminal RBn temporarily changes from the "H" state to the "L" state and immediately returns to the "H" state. Further, as the next action, receiving a set of commands instructing a cache read, if cache read actions are consecutive, the next cache read action begins after the previous cache read action is completed. In this case, after receiving the second set of commands instructing a cache read, the external output terminal RBn changes from the "H" state to the "L" state and returns to the "H" state after the second cache read action begins.

[0152] exist Figure 11 In the example, after the external output terminal RBn changes in the order of "H", "L", and "H" to indicate that the memory die MD has received a set of commands instructing a cache read, the controller die CD outputs a set of commands instructing data output (hereinafter sometimes referred to as data output commands) to the memory die MD via data signal input / output terminals DQ0 to DQ7. Figure 11 As shown, the data output command includes data 05h, ADD, and E0h.

[0153] Data 05h is the command data CMD input to the command register CMR. This data 05h is input at the start of data output. Data ADD is the same data as the data ADD for the read command. Data E0h is the command data CMD input to the command register CMR. This data E0h indicates that the input of the data output command has ended.

[0154] Figure 18 Shown in Figure 11 The flow of data read under timer t7. For example... Figure 18 As shown, the sequencer SQC controls all switching transistors DSW1, DSW2, and DSW3 to the off state. Figure 11 In the example, when a data output command is input, data transfer between latch circuits within the sense amplifier SA does not occur. However, data transfer between latch circuits within the sense amplifier SA can also occur in parallel with the input of the data output command.

[0155] Figure 19 Shown in Figure 11 The flow of data HB[LP] read under timer t8. For example... Figure 19 As shown, the sequencer SQC outputs the read data HB[LP] held in the latch circuit XDL to the controller die CD via the bidirectional bus YIO, input / output control circuit I / O, and data signal input / output terminals DQ0 to DQ7, based on the input of the data output command.

[0156] like Figure 11 As shown, in parallel with the output of the read data HB[LP] held in the latch circuit XDL to the controller die CD, during the read operation, the sequencer SQC sends data to the select word line WL. S Supply reads the on-state voltage V READ .

[0157] Sequencer SQC directs select word line WL S Supply reading voltage V CGFR Therefore, with Figure 8 In (a), the memory cells MC corresponding to Er state to E state become on, and the memory cells MC corresponding to F state to G state become off. Additionally, the sequencer SQC charges the bit line BL. Furthermore, the sequencer SQC controls the charging transistor 55 for pre-charging. Figure 5 The circuit LBUS1 is charged. At this time, the switching transistors DSW1, DSW2, and DSW3 are all in the off state.

[0158] In addition, the sequencer SQC performs sensing actions corresponding to hard bit readings. Figure 11(The "sense FR(HB)" in the text). Therefore, the sense amplifier SA obtains the reading voltage V. CGFR The corresponding read data (read data HB(FR)).

[0159] Figure 20 Shown in Figure 11 The flow of data HB(FR) read under timer t9. For example... Figure 20 As shown, the read data HB(FR) obtained through sensing action is transmitted to the latch circuit CDL via wiring LBUS1. The latch circuit CDL holds the read data HB(FR).

[0160] In addition, the sequencer SQC performs sensing actions corresponding to the soft bit reading. Figure 11 (as shown in "sense FR(SB+)"). Therefore, the sense amplifier SA obtains the reading voltage V. CGFR The corresponding read data (read data SB(FR)).

[0161] Figure 21 Shown in Figure 11 The flow of read data SB(FR) under timer t10. For example... Figure 21 As shown, the read data SB(FR) acquired through sensing action is transmitted to the latch circuit BDL via wiring LBUS1. The latch circuit BDL holds the read data SB(FR).

[0162] Next, the sequencer SQC directs the select word line WL. S Supply reading voltage V CGDR Therefore, with Figure 8 In (a), the memory cell MC corresponding to the Er state to the C state becomes the on state, and the memory cell MC corresponding to the D state to the G state becomes the off state.

[0163] exist Figure 11 In the example, when data output ends, the controller die CD outputs a command (hereinafter sometimes referred to as a transfer command) to the memory die MD via data signal input / output terminals DQ0~DQ7, instructing the transfer of data to be read. Figure 11 As shown, the transmission command is the command for data XXh.

[0164] Furthermore, the 8 bits constituting the data XXh can be either "0" or "1". Also, in the 8 bits constituting the data XXh, the data from the 1st to the 4th bit can be the same as or different from the data from the 5th to the 8th bit.

[0165] Figure 22 Shown in Figure 11 The flow of data SB[LP] read under timer t11. For example... Figure 22 As shown, the sequencer SQC, based on the input transmission command, controls switching transistors DSW1 and DSW2 to the off state and switching transistor DSW3 to the on state. Additionally, the sequencer SQC controls the external output terminal RBn from the "H" state to the "L" state. Furthermore, the sequencer SQC transmits the read data SB[LP] held in the latch circuit ADL to the latch circuit XDL via wiring LBUS2 and DBUS. The latch circuit XDL holds the read data SB[LP].

[0166] In parallel with the transfer of read data SB[LP] from latch circuit ADL to latch circuit XDL, in Figure 11 At time t11, the sequencer SQC performs the sensing action corresponding to the hard bit reading. Figure 11 The "sense DR(HB)" in the text. Therefore, the sense amplifier SA obtains the read voltage V. CGDR The corresponding read data (read data HB(DR)).

[0167] In this embodiment, wiring LBUS1 and wiring LBUS2 are electrically connected or disconnected depending on the on or off state of switching transistor DSW2. Similarly, wiring LBUS2 and wiring DBUS are electrically connected or disconnected depending on the on or off state of switching transistor DSW3. Furthermore, wiring LBUS2 is connected to latch circuit ADL. Therefore, even during the execution of sensing operations corresponding to hard-bit or soft-bit reading, and the transmission of read data to latch circuits CDL and BDL, the sense amplifier module SAM can simultaneously execute the transmission of read data previously stored in latch circuit ADL to latch circuit XDL.

[0168] Figure 23 Shown in Figure 11 The flow of read data HB(DR) under timing t12. When the transfer of read data SB[LP] from latch circuit ADL to latch circuit XDL ends, the sequencer SQC controls all switching transistors DSW1, DSW2, and DSW3 to the off state. When the transfer of read data SB[LP] from latch circuit ADL to latch circuit XDL ends, the memory die MD controls the external output terminal from the "L" state to the "H" state.

[0169] like Figure 23As shown, the read data HB(DR) acquired through sensing is transmitted via wiring LBUS1. At this time, the latch circuit CDL holds the read data HB(FR). The sensing amplifier SA performs a prescribed logic operation on the read data HB(FR) and the read data HB(DR). The latch circuit CDL holds the result of this logic operation, HB(FR / DR).

[0170] In addition, the sequencer SQC performs sensing actions corresponding to the soft bit reading. Figure 11 (as shown in "sense DR(SB+)"). Therefore, the sense amplifier SA obtains the read voltage V. CGDR The corresponding read data (read data SB(DR)).

[0171] Figure 24 Shown in Figure 11 The flow of data SB(DR) and SB[LP] read under timed t13 and t14. For example... Figure 24 As shown, at time t13, the read data SB(DR) acquired through the sensing action is transmitted to wiring LBUS1. At this time, the latch circuit BDL holds the read data SB(FR). The sensing amplifier SA performs a prescribed logic operation on the read data SB(FR) and the read data SB(DR). The latch circuit BDL holds the result of this logic operation, SB(FR / DR).

[0172] exist Figure 11 In the example, after the transfer operation is completed, the controller die CD outputs a data output command to the memory die MD via the data signal input / output terminals DQ0 to DQ7.

[0173] like Figure 24 As shown, at time t14, the sequencer SQC outputs the read data SB[LP] held in the latch circuit XDL to the controller die CD according to the input of the data output command via the bidirectional bus YIO, the input / output control circuit I / O, and the data signal input / output terminals DQ0 to DQ7.

[0174] The controller die CD performs bit error detection / correction on the data output from the memory die MD, and then transmits it to the host 20. Figure 1 ).

[0175] Next, the sequencer SQC directs the select word line WL. S Supply reading voltage V CGBR In addition, the sequencer SQC performs sensing actions corresponding to the hard bit reading. Figure 11The "sense BR(HB)" in the diagram. At time t15, the read data HB(BR) acquired through the sensing action is transmitted to wiring LBUS1. At this time, the latch circuit CDL holds the read data HB(FR / DR). The sense amplifier SA performs a prescribed logic operation on the read data HB(FR / DR) and the read data HB(BR). The latch circuit CDL holds the result of this logic operation, HB(FR / DR / BR). The result of this logic operation, HB(FR / DR / BR), is the read data HB[MP] of the middle bit (middle page).

[0176] In addition, the sequencer SQC performs sensing actions corresponding to the soft bit reading. Figure 11 The "sense BR(SB+)" in the code. At time t16, the read data SB(BR) acquired by the sensing action is transmitted to wiring LBUS1. At this time, the latch circuit BDL holds the read data SB(FR / DR). The sense amplifier SA performs a prescribed logic operation on the read data SB(FR / DR) and the read data SB(BR). The latch circuit BDL holds the result of this logic operation, SB(FR / DR / BR). The result of this logic operation, SB(FR / DR / BR), is the read data SB[MP] of the middle bit (middle page).

[0177] Then, the read data HB[MP] is transmitted to the latch circuit XDL via wiring LBUS1 and DBUS. The read data HB[MP] held in the latch circuit XDL is output via the bidirectional bus YIO according to the input of the data output command. Additionally, the read data SB[MP] is transmitted to the latch circuit ADL via wiring LBUS1 and LBUS2, and then to the latch circuit XDL via wiring LBUS2 and DBUS. The read data SB[MP] held in the latch circuit XDL is output via the bidirectional bus YIO according to the input of the data output command.

[0178] In addition, although Figures 11-24 The example illustrates the reading of low-order and middle-order bits, but the reading of high-order bits can also be performed. The reading of high-order bits is essentially the same as the reading of low-order and middle-order bits. However, in the reading of high-order bits, firstly, the select word line WL is... S Supply reading voltage V CGGR The system performs sensing actions corresponding to hard bit and soft bit reads. Then, it transmits the read data obtained through the sensing actions. Next, it sends the data to the select word line WL. S Supply reading voltage V CGCRThe system performs sensing actions corresponding to hard bit reading and soft bit reading. Then, it transmits the read data obtained through the sensing actions.

[0179] [Comparative Example]

[0180] Next, refer to Figure 25 as well as Figure 26 The operation of the SAM (Sensing Amplifier Module) involved in the comparative example will be explained.

[0181] Figure 25 This is a diagram showing the timing of the operation of the sensing amplifier module SAM involved in the comparative example. Figure 26 This is a block diagram illustrating the data exchange between multiple latch circuits involved in the comparative example. Figure 25 and Figure 26 In the middle, to and Figures 11-24 The same components are assigned the same symbols, and their descriptions are omitted.

[0182] like Figure 26 As shown, in the sense amplifier module of the comparative example, all latch circuits SDL, ADL, BDL, CDL, and TDL are connected to wiring LBUS1. Furthermore, in the sense amplifier module of the comparative example, wiring LBUS2 and switching transistors DSW2 and DSW3 are not provided. Therefore, the data held in the latch circuits SDL, ADL, BDL, CDL, and TDL is transmitted to the latch circuit XDL via only one path, including wiring LBUS1 and wiring DBUS.

[0183] [Sensor Amplifier Module (SAM) Operation]

[0184] exist Figure 25 In the example, when the data output ends, the controller die CD sends a command to the memory die MD via the data signal input / output terminals DQ0 to DQ7.

[0185] At time t21, the sequencer SQC controls the switching transistor DSW1 to the on state according to the input transmission command. Additionally, the sequencer SQC controls the external output terminal RBn from the "H" state to the "L" state. Furthermore, the sequencer SQC interrupts the read operation of the sense amplifier module SAM. And, the sequencer SQC transmits the read data SB[LP] held in the latch circuit ADL to the latch circuit XDL via wiring LBUS1 and DBUS. The latch circuit XDL holds the read data SB[LP].

[0186] In the sense amplifier module SAM involved in the comparative example, the read data obtained through the sensing operation is transmitted to the latch circuit (e.g., latch circuit CDL or BDL) via wiring LBUS1. Additionally, the read data SB[LP] held in the latch circuit ADL is transmitted to the latch circuit XDL via wiring LBUS1 and DBUS. Thus, the transmission of read data from the sense amplifier SA to the latch circuit, and the transmission of read data SB[LP] from the latch circuit ADL to the latch circuit XDL, both use wiring LBUS1, making it impossible to perform these operations (processing) simultaneously. Therefore, when the sequencer SQC receives a transmission command, it must interrupt the read operation before the transmission of read data SB[LP] from the latch circuit ADL to the latch circuit XDL is completed (during the period t21 to t22). Alternatively, when the sequencer SQC receives a transmission command, it must wait for the transmission of read data SB[LP] from the latch circuit ADL to the latch circuit XDL before the read operation is completed.

[0187] In this case, the reading operation will be slower. Alternatively, the controller's bare CD will receive the read data SB[LP] more slowly via the latch circuit XDL, the bidirectional bus YIO, the input / output control circuit I / O, and the data signal input / output terminals DQ0 to DQ7.

[0188] [Effects of the First Embodiment]

[0189] In the sense amplifier module SAM according to the first embodiment, even during the execution of a read operation, the read data SB[LP] can be immediately transferred from the latch circuit ADL to the latch circuit XDL based on the input of a transfer command. That is, the read operation, such as the sensing operation of the sense amplifier, and the transfer operation of the read data SB[LP] from the latch circuit ADL to the latch circuit XDL can be executed in parallel. Therefore, the memory die MD can provide the read data HB[LP] and SB[LP] to the controller die CD relatively quickly without interrupting the read operation in the sense amplifier module SAM. As a result, the host 20 (i.e., the user) can obtain the read data relatively quickly.

[0190] Furthermore, the sense amplifier module SAM according to the first embodiment is implemented by adding two switching transistors DSW2 and DSW3 instead of adding a latch circuit. Therefore, in the sense amplifier module SAM, the impact of adding components on the component area is suppressed.

[0191] [Second Implementation]

[0192] Figure 27 This is a schematic block diagram illustrating a portion of the semiconductor memory device according to the second embodiment. Figure 27The configuration of the plurality of latching circuits included in the sense amplifier unit SAU of the semiconductor memory device according to the second embodiment is shown. Additionally, in Figure 27 In the middle, to and Figures 11-24 The same components are assigned the same symbols, and their descriptions are omitted.

[0193] The semiconductor memory device according to the second embodiment is configured in essentially the same way as the semiconductor memory device according to the first embodiment. However, as shown in reference... Figure 5 As explained, in the sense amplifier unit SAU according to the first embodiment, only one latch circuit ADL is connected to the wiring LBUS2. On the other hand, in the sense amplifier unit SAU according to the second embodiment, two latch circuits ADL1 and ADL2 are connected to the wiring LBUS2.

[0194] In this configuration, the sensing amplifier SA can perform three sensing operations: hard bit read, positive-side soft bit read, and negative-side soft bit read. The read data HB obtained through the sensing operation corresponding to the hard bit read can also be held in the latch circuit CDL. The read data SB+ obtained through the sensing operation corresponding to the positive-side soft bit read can also be held in the latch circuit BDL. The read data SB obtained through the sensing operation corresponding to the negative-side soft bit read can also be held, for example, in the latch circuit SDL or the latch circuit TDL.

[0195] Furthermore, the read data HB held in latch circuit CDL can also be transmitted to latch circuit XDL via wiring DBUS. The read data SB+ held in latch circuit BDL can also be transmitted to latch circuit ADL1 via wiring LBUS1 and LBUS2. The read data SB- held in latch circuit SDL or latch circuit TDL can also be transmitted to latch circuit ADL2 via wiring LBUS1 and LBUS2. Alternatively, after the read data HB held in latch circuit XDL is output to the controller die CD, the read data SB+ held in latch circuit ADL1 can be transmitted to latch circuit XDL via wiring LBUS2 and DBUS. Additionally, the read data SB- held in latch circuit ADL2 can also be transmitted to latch circuit XDL via wiring LBUS2 and DBUS. Latch circuit XDL can also hold the result of a logical operation (e.g., XNOR) between the read data SB+ and read data SB- transmitted from latch circuit ADL1. Then, the data held in latch circuit XDL is output to the controller die CD.

[0196] Based on this configuration, the memory die MD can output data including both positive and negative information as read data SB while suppressing the amount of data.

[0197] [Third Implementation Method]

[0198] Figure 28 This is a schematic block diagram illustrating a portion of the semiconductor memory device according to the third embodiment. Figure 28 The diagram illustrates the configuration of multiple latching circuits included in the sense amplifier unit (SAU) of the semiconductor memory device according to the third embodiment. Additionally, in Figure 28 In the middle, to and Figures 11-24 The same components are assigned the same symbols, and their descriptions are omitted.

[0199] The semiconductor memory device according to the third embodiment is basically constructed in the same way as the semiconductor memory device according to the first embodiment. However, in the sense amplifier module SAM according to the third embodiment, a switching transistor DSW4 and a wiring LBUS3 are disposed between the switching transistor DSW3 and the wiring DBUS. A latch circuit DDL and a pre-charging charging transistor 57 are connected to the wiring DBUS. The switching transistor DSW4 is connected to the wiring DBUS.

[0200] In this configuration, similar to the second embodiment, the sensing amplifier SA can perform three sensing operations: hard bit read, positive soft bit read, and negative soft bit read. Alternatively, for example, the latch circuit ADL can hold the positive read data SB+, and the latch circuit DDL can hold the negative read data SB-. In this case, the sequencer SQC can transmit the positive read data SB+ and the negative read data SB- to the latch circuit XDL respectively, and output them to the controller die CD respectively.

[0201] [Fourth Implementation Method]

[0202] Figure 29 This is a schematic block diagram showing a portion of the structure of a semiconductor memory device. Figure 27 This is a schematic block diagram illustrating the configuration of the sense amplifier module SAM of the semiconductor memory device according to the fourth embodiment, which is included in the sense amplifier unit SAU of the semiconductor memory device according to the second embodiment. Furthermore, in Figure 29 In the middle, to and Figures 11-24 The same components are assigned the same symbols, and their descriptions are omitted.

[0203] The semiconductor memory device according to the fourth embodiment is configured in essentially the same way as the semiconductor memory device according to the first embodiment. However, the sense amplifier module SAM according to the fourth embodiment has a different configuration than the sense amplifier module SAM according to the fourth embodiment.

[0204] like Figure 29 As shown, the sensing amplifier module SAM according to the fourth embodiment has multiple sensing amplifier units SAU1 to SAUn corresponding to multiple bit lines BL. The multiple sensing amplifier units SAU1 to SAUn are respectively associated with reference to... Figure 5 The described sensing amplifier unit SAU has the same configuration.

[0205] In the illustrated example, the wiring LBUS2 of the k-th (k is an integer between 1 and n-1) sense amplifier unit SAUk among the multiple sense amplifier units SAU1 to SAUun, and the wiring LBUS2 of the (k+1)-th sense amplifier unit SAUk+1 are electrically connected via wiring LBUS4 and switching transistor DSW5(k). Additionally, a compression circuit 200 is connected to the wiring LBUS2 of the sense amplifier unit SAU1.

[0206] Alternatively, the compression circuit 200 can be connected to the wiring LBUS2 of a sense amplifier unit other than the sense amplifier unit SAU1. Additionally, the compression circuit 200 can be connected to the wiring LBUS4. Furthermore, the compression circuit 200 can be located either inside or outside the sense amplifier module SAM.

[0207] In the configuration described above, the read data SB held in the latch circuit ADL of each sense amplifier unit SAU1 to SAU1 is transferred to the compression circuit 200 before being transferred to the latch circuit XDL. For example, when the read data SB held in the latch circuit ADL of sense amplifier unit SAU2 is transferred to the compression circuit 200, the switching transistor DSW5(1) is controlled to be in the on state. In addition, when the read data SB held in the latch circuit ADL of sense amplifier unit SAU3 is transferred to the compression circuit 200, the switching transistors DSW5(1) and DSW5(2) are controlled to be in the on state.

[0208] For example, suppose there are 16 sense amplifier units SAU1 to SAU16 connected by wiring LBUS4 (n = 16). In this case, the read data SB is transmitted from each sense amplifier unit SAU1 to SAU16 to the compression circuit 200 and becomes 16-bit data. The compression circuit 200 compresses the 16-bit data into, for example, 4-bit data.

[0209] For example, each sense amplifier unit SAU1 to SAU16 transmits read data HB and read data SB to compression circuit 200. Compression circuit 200 includes, for example, an XOR circuit and a counter. Compression circuit 200 compares, for example, the 16-bit read data HB with the 16-bit read data SB. If the k-th bit of read data SB matches the k-th bit of read data HB, the counter value is incremented; otherwise, the counter value is output. Thus, compression circuit 200 can identify which bit in the 16-bit read data SB differs from the read data HB.

[0210] The compression circuit 200 can also transmit compressed data to the latch circuit XDL. Furthermore, the number of sense amplifier units SAU1 to SAUn connected via wiring LBUS4 is not limited to 16 (n=16), but can also be 64 (n=64), 128 (n=128), 256 (n=256), etc. In this case, the compression circuit 200 performs data compression operations in units of 64 bits, 128 bits, and 256 bits.

[0211] With this configuration, the amount of data read from the latch circuit XDL (SB) can be suppressed.

[0212] [Other Implementation Methods]

[0213] The semiconductor memory device according to the embodiments has been described above. However, the above description is merely illustrative, and the above configuration, method, etc., can be appropriately adjusted.

[0214] For example, the semiconductor memory device according to the first embodiment can also perform three sensing operations corresponding to hard bit reads, positive-side soft bit reads, and negative-side soft bit reads. In this case, the latch circuit BDL holds the result of a logical operation (e.g., XNOR) between the sensing result of the sensing operation corresponding to the positive-side soft bit read (read data SB+) and the sensing result of the sensing operation corresponding to the negative-side soft bit read (read data SB-). Then, the data held in the latch circuit BDL is transferred to the latch circuit XDL.

[0215] Furthermore, in the above description, examples of reading operations corresponding to hard bit reading and soft bit reading were shown as the reading operations involved in the first to fourth embodiments. However, such operating methods are merely illustrative, and specific operating methods and utilization methods can be appropriately adjusted. For example, the storage system 10 sometimes has a function of sequential reading, which reads data from the low-order page, the middle-order page, and the high-order page simultaneously. In sequential reading, in the case of TLC (Triple Level Cell), data is output when the amounts of the low-order page, the middle-order page, and the high-order page are all available.

[0216] For example, in the sense amplifier module SAM according to the third embodiment, when sequential reading is applied, the latch circuit CDL may hold the data of the low-order page, the latch circuit ADL may hold the data of the middle-order page, and the latch circuit DDL may hold the data of the high-order page. Furthermore, the data held in the latch circuits CDL, ADL, and DDL may be sequentially transferred to the latch circuit XDL.

[0217] Furthermore, although the sense amplifier module SAM described in the first to fourth embodiments is based on a read operation, it is not limited to this configuration and can also be applied to write operations, verification operations, etc. For example, sometimes a fast pass-through write operation is performed where multiple verification voltages are set for a threshold level and the programming voltage is changed. In this case, a latch circuit (ADL, etc.) connected to the wiring LBUS1 by an electrically disconnectable wiring (LBUS2, etc.) can be used to perform data transmission between the latch circuit (ADL, etc.) and the latch circuit XDL in parallel with the verification operation.

[0218] Furthermore, the storage system 10 described in the first to fourth embodiments is configured using a TLC storage cell MC, but it may also be configured using an SLC (Single Level Cell), MLC (Multi Level Cell), QLC (Quad Level Cell), or PLC (Penta Level Cell).

[0219] [other]

[0220] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to that of the invention as described in the claims.

[0221] [Symbol Explanation]

[0222] BL: Bit line, SA: Sensing amplifier, SAU: Sensing amplifier unit, SAM: Sensing amplifier module, ADL, ADL1: Latch circuit (third latch circuit), ADL2: Latch circuit (fifth latch circuit), BDL: Latch circuit (second latch circuit), CDL: Latch circuit (first latch circuit), DDL: Latch circuit (sixth latch circuit), XDL: Latch circuit (fourth latch circuit), LBUS1: Wiring (first wiring), LBUS2: Wiring (second wiring), LBUS3: Wiring (fourth wiring), LBUS4: Wiring, DBUS: Wiring (third wiring), DSW1: Switching transistor (first switching transistor), DSW2: Switching transistor (second switching transistor), DSW3: Switching transistor (third switching transistor), DSW4: Switching transistor (fourth switching transistor), SQC: Sequencer (control circuit), 55, 56, 57, 60: Charging transistor, 200: Compression circuit.

Claims

1. A semiconductor memory device comprising: Storage string; Bit lines connected to the memory string; A plurality of sensing amplifier units corresponding to the plurality of bit lines, each of the plurality of sensing amplifier units comprising: The sensing amplifier connected to the bit line; A first latch circuit, a second latch circuit, and a third latch circuit are electrically connected to the sensing amplifier; A first wiring connection to the sensing amplifier, the first latch circuit, and the second latch circuit; The second wiring connected to the third latch circuit; First switching transistor; A second switching transistor that electrically disconnects the first wiring from the second wiring; as well as Third switching transistor; A buffer memory equipped with a fourth latch circuit; as well as The third wiring connected to the fourth latch circuit, in, The first switching transistor electrically disconnects the first wiring from the third wiring. The third switching transistor electrically disconnects the second wiring from the third wiring. During the first timing of the read operation, the first latch circuit holds the first data according to the output of the sensing amplifier. At a second timing point, later than the first timing point, the second latch circuit holds the second data based on the output of the sensing amplifier. At a third timing point, later than the second timing point, the first data is transmitted from the first latch circuit to the fourth latch circuit via the first wiring and the third wiring. At a fourth timing point, later than the third timing point, the second data is transmitted from the second latch circuit to the third latch circuit via the first wiring and the second wiring. At a fifth timing later than the fourth timing, the second data is transmitted from the third latch circuit to the fourth latch circuit via the second wiring and the third wiring.

2. The semiconductor memory device according to claim 1, wherein, Based on the input of the transmission command, the second data is transmitted from the third latch circuit to the fourth latch circuit.

3. The semiconductor memory device according to claim 1, wherein, It has a first charging transistor, a second charging transistor, and a third charging transistor for pre-charging, which are respectively connected to the first wiring, the second wiring, and the third wiring.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein, It has a fifth latch circuit connected to the second wiring.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein, have: A sixth latch circuit electrically connected to the sensing amplifier; The fourth wiring connected to the sixth latch circuit; and The fourth switching transistor is electrically disconnected from the third wiring. The third switching transistor electrically disconnects the second wiring from the fourth wiring.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein, It includes a compression circuit connected to the second wiring and configured to compress data held in the third latch circuit.

7. The semiconductor memory device according to claim 6, wherein, The compression circuit is connected to a plurality of the second wirings corresponding to the plurality of the plurality of the sensing amplifiers.

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