Memory device and operating method thereof
By synchronously applying different gradually decreasing signal line reference voltages to the select line and serial select line at the end of a read or write verification operation in a three-dimensional memory device, the problem of hot electronic mode interference is solved, and the operational stability and performance of the memory device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MACRONIX INTERNATIONAL CO LTD
- Filing Date
- 2022-03-10
- Publication Date
- 2026-08-04
AI Technical Summary
In three-dimensional memory devices, there is no electrical contact between the channel and the P-well, causing the channel voltage to drop to a negative voltage during programming or reading operations, which triggers hot-electron mode interference and affects the operation and performance of the memory device.
At the end of the read or write verification operation, multiple different gradually decreasing signal line reference voltages are simultaneously applied to the ground select line, string select line, redundant ground select line, and redundant string select line. Different voltage values are set according to the location differences of these signal lines to avoid hot electronic mode interference.
It effectively reduces the voltage difference between word lines, mitigates hot electronic mode interference, protects select lines and serial select lines from additional interference, and improves the operational stability and performance of memory devices.
Smart Images
Figure CN116705118B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory device and a method of operating the same. Background Technology
[0002] In a two-dimensional memory device, there is an electrical contact between the channel and the P-well. Therefore, when a negative word line voltage is applied while the P-well remains at 0V, the channel voltage will not drop to a negative voltage. This is because the P-well can continuously provide holes to maintain the channel voltage.
[0003] However, in 3D memory devices, there is no electrical contact between the channel and the P-well. Therefore, during programming or reading operations, as the word line voltage decreases, causing the channel to float (without a conductive path to the source and bit line), the channel voltage may capacitively couple and drop to a negative voltage. This will result in a large electric field between the programming word line and the adjacent word line (in the erase state), leading to hot-electron mode interference.
[0004] For example, word lines WL1 and WL(N-1) (where N is a positive integer and N>2) are programmed to a high threshold state, while the remaining word lines are in an erase state. As the voltage of the high threshold word lines WL1 and WL(N-1) decreases, word lines WL2 to WL(N-2) located between WL1 and WL(N-1) will become floating. Furthermore, a large electric field appears between word lines WL0 and WL1, and between word lines WLN and WL(N-1). Therefore, word lines WL0 and WLN will be subject to hot-electron mode disturbance. As the number of read cycles increases, the threshold voltage of the word lines affected by hot-electron mode disturbance will become increasingly higher, which is detrimental to the operation and performance of the memory device.
[0005] Therefore, avoiding hot electron mode interference within three-dimensional memory devices is one of the directions of our efforts. Summary of the Invention
[0006] According to an embodiment of the present invention, an operation method for a memory device is proposed. The memory device includes a plurality of ground select lines, a plurality of string select lines, a plurality of redundant ground select lines, and a plurality of redundant string select lines. The operation method for the memory device includes: at the end of a read operation or a write verification operation, during a word line voltage drop phase, simultaneously applying a plurality of different gradually decreasing signal line reference voltages to the ground select lines and the string select lines, wherein the values of the different gradually decreasing signal line reference voltages are related to the positions of the plurality of signal lines of the ground select lines and the string select lines.
[0007] According to another embodiment of the present invention, a memory device is provided, comprising: a plurality of memory cells; a plurality of ground select lines; a plurality of redundant ground select lines; a plurality of bit lines; a plurality of string select lines; a plurality of redundant string select lines; a plurality of word lines coupled to the memory cells, the memory cells being further coupled to the bit lines; and a plurality of switches coupled to the ground select lines, the redundant ground select lines, the bit lines, the string select lines, and the redundant string select lines; wherein, at the end of a read operation or a write verification operation, during a word line voltage drop phase, a plurality of different gradually decreasing signal line reference voltages are synchronously applied to the ground select lines and the string select lines, wherein the values of the different gradually decreasing signal line reference voltages are relative to the positions of the plurality of signal lines of the ground select lines and the string select lines.
[0008] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0009] Figure 1 This diagram shows an equivalent circuit diagram of a memory device according to an embodiment of the present invention.
[0010] Figure 2 A waveform diagram of a memory device according to an embodiment of the present invention is shown.
[0011] Figure 3 A waveform diagram of a memory device according to another embodiment of the present invention is shown.
[0012] Figure 4 This diagram shows the channel voltage waveform of an embodiment of the present invention compared to that of conventional technology.
[0013] Figure 5 A flowchart illustrating a method for operating a memory device according to yet another embodiment of the present invention is shown.
[0014] Explanation of reference numerals in the attached figures
[0015] 100: Memory device; B0~BQ: Memory block
[0016] CSL: Common Source Line
[0017] WL0~WLN: Word lines; BL0~BLP: Bit lines
[0018] SW: Switch
[0019] SSL0~SSL2: Serial select lines
[0020] SSLD0~SSLD2: Redundant String Select Lines
[0021] GSL0~GSL2: Grounding selection line
[0022] GSLD0~GSLD3: Redundant grounding selection lines
[0023] SS: Memory String
[0024] MC: Memory Unit
[0025] P1~P4: Stages
[0026] T1: Timing
[0027] L41, L42: Curve graphs
[0028] 510: Steps Detailed Implementation
[0029] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0030] Figure 1 This diagram shows an equivalent circuit diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 is, for example, but not limited to, a three-dimensional (3D) memory device. Figure 1 As shown, the memory device 100 includes multiple memory blocks B0 to BQ (Q is a positive integer), a common source line CSL, multiple word lines WL0 to WLN (N is a positive integer), multiple bit lines BL0 to BLP (P is a positive integer), multiple string select lines (SSL), multiple dummy string select lines, multiple ground select lines (GSL), and multiple redundant ground select lines. Figure 1 Although the diagram shows 3 string select lines SSL0 to SSL2, 3 redundant string select lines SSLD0 to SSLD2, 3 ground select lines GSL0 to GSL2, and 4 redundant ground select lines GSLD0 to GSLD3, the present invention is not limited thereto. These string select lines, these redundant string select lines, these ground select lines, and these redundant ground select lines may have other numbers, which are also within the spirit of the present invention.
[0031] Taking memory device 100 as an example, the order from bottom to top is as follows: ground select lines GSL0~GSL2, redundant ground select lines GSLD0~GSLD3, word lines WL0~WLN, redundant string select lines SSLD0~SSLD2, and string select lines SSL0~SSL2. That is, ground select line GSL0 is located at the bottom, and string select line SSL2 is located at the top. Alternatively, in one embodiment of the present invention, "outer side" is defined as being farther away from these word lines, while "inner side" is defined as being closer to these word lines. For example, ground select line GSL0 and string select line SSL2 can be regarded as the outermost signal lines because ground select line GSL0 and string select line SSL2 are farthest from these word lines WL0~WLN; and redundant ground select line GSLD3 and redundant string select line SSLD0 can be regarded as the innermost signal lines because redundant ground select line GSLD3 and redundant string select line SSLD0 are closest to these word lines WL0~WLN.
[0032] Each of these memory blocks B0 to BQ includes multiple switches SW and multiple memory strings SS. Each memory string SS includes multiple memory cells MC. These memory cells MC are located at the intersections of these word lines WL0 to WLN and these bit lines BL0 to BLP. Within the same memory block, these memory cells MC coupled to the same bit line form a memory string SS.
[0033] These switches SW are located at the intersections of the string select lines SSL0-SSL2 with the bit lines BL0-BLP, or at the intersections of the redundant string select lines SSLD0-SSLD2 with the bit lines BL0-BLP, or at the intersections of the ground select lines GSL0-GSL2 with the bit lines BL0-BLP, or at the intersections of the redundant ground select lines GSLD0-GSLD3 with the bit lines BL0-BLP. When a relevant memory string SS is selected, the relevant switch SW will be turned on.
[0034] The current flowing through the multiple cells of these memory strings SS will flow through the common source line CSL to the relevant back-end circuitry for related operations.
[0035] Figure 2 A waveform diagram of a memory device according to an embodiment of the present invention is shown. Figure 2 The invention is illustrated using a read operation as an example, but it should be understood that the invention is not limited thereto. Other embodiments of the invention can also be applied to write verify operations, which include program verify operations and erase verify operations.
[0036] like Figure 2As shown, before the read operation begins, the voltage across the selected word line SWL, multiple unselected word lines UWL, the redundant string select lines SSLD0 to SSLD2, the redundant ground select lines GSLD0 to GSLD3, the string select lines SSL0 to SSL2, the ground select lines GSL0 to GSL2, the bit lines BL0 to BLP, and the common source line CSL is a first reference voltage, for example, but not limited to, 0V. The selected word line SWL is one of these word lines WL0 to WLN, while the unselected word line UWL represents the remaining unselected word lines.
[0037] The read operation consists of four stages, P1 to P4, which will be explained below.
[0038] During the first phase P1, the selected word line SWL remains at the first reference voltage; the unselected word line UWL rises from the first reference voltage to the second reference voltage Vpass (e.g., but not limited to, 8V to 9V); the redundant ground select lines GSLD0 to GSLD3 and the redundant string select lines SSLD0 to SSLD2 rise from the first reference voltage to the second reference voltage Vpass; the ground select lines GSL0 to GSL2 and the string select lines SSL0 to SSL2 rise from the first reference voltage to the second reference voltage Vpass; the bit lines BL0 to BLP rise from the first reference voltage to the third reference voltage VBL (e.g., but not limited to, 1.3V); and the common source line CSL rises from the first reference voltage to the fourth reference voltage VCSL (e.g., but not limited to, 0.6V).
[0039] During the second phase P2, the selected word line SWL rises from the first reference voltage to the fifth reference voltage Vread1 (e.g., but not limited to, 2V), and from the fifth reference voltage Vread1 to the sixth reference voltage Vread2 (e.g., but not limited to, 6V); the unselected word line UWL remains at the second reference voltage Vpass; the redundant ground select lines GSLD0~GSLD3 and the redundant string select lines SSLD0~SSLD2 remain at the second reference voltage Vpass; the ground select lines GSL0~GSL2 and the string select lines SSL0~SSL2 remain at the second reference voltage Vpass; the bit lines BL0~BLP remain at the third reference voltage VBL; and the common source line CSL remains at the fourth reference voltage VCSL.
[0040] Within the third stage P3, the selected word line SWL is maintained at the sixth reference voltage Vread2; the unselected word line UWL is maintained at the second reference voltage Vpass; the redundant ground select lines GSLD0~GSLD3 and the redundant string select lines SSLD0~SSLD2 are maintained at the second reference voltage Vpass; the ground select lines GSL0~GSL2 and the string select lines SSL0~SSL2 are maintained at the second reference voltage Vpass; the bit lines BL0~BLP are maintained at the third reference voltage VBL; and the common source line CSL is maintained at the fourth reference voltage VCSL.
[0041] In the fourth stage P4, the selected word line SWL drops from the sixth reference voltage Vread2 to the first reference voltage; the unselected word line UWL drops from the second reference voltage Vpass to the first reference voltage; the redundant ground select lines GSLD0 to GSLD3 and the redundant string select lines SSLD0 to SSLD2 drop from the second reference voltage Vpass to the first reference voltage; the ground select line GSL0 and the string select line SSL2 drop from the second reference voltage Vpass to the seventh reference voltage (e.g., but not limited to 0V); the ground select line GSL1 and the string select line SSL1 drop from the second reference voltage Vpass to the eighth reference voltage (e.g., but not limited to -1V); the ground select line GSL2 and the string select line SSL0 drop from the second reference voltage Vpass to the ninth reference voltage (e.g., but not limited to -2V); the bit lines BL0 to BLP drop from the third reference voltage VBL to the first reference voltage; and the common source line CSL drops from the fourth reference voltage VCSL to the first reference voltage.
[0042] like Figure 2 As shown, during the fourth stage P4 (i.e., during the word line voltage drop stage), a gradually decreasing reference voltage is applied to these ground select lines (GSL0~GSL2) and these string select lines (SSL0~SSL2) to avoid thermionic mode interference of conventional technology, the reason for which will be explained below.
[0043] After the four phases P1 to P4 of the read operation are completed, at timing T1, the selected word line SWL is maintained at the first reference voltage; the unselected word line UWL is maintained at the first reference voltage; the redundant ground select lines GSLD0 to GSLD3 and the redundant string select lines SSLD0 to SSLD2 are maintained at the first reference voltage; the ground select line GSL0 and the string select line SSL2 are maintained at the seventh reference voltage; the ground select line GSL1 and the string select line SSL1 are maintained at the eighth reference voltage; the ground select line GSL2 and the string select line SSL0 are maintained at the ninth reference voltage; the bit lines BL0 to BLP are maintained at the first reference voltage; and the common source line CSL is maintained at the first reference voltage.
[0044] At Figure 2 In this invention, the voltage difference between the seventh, eighth, and ninth reference voltages is 1V, but it should be understood that the invention is not limited to this. In other embodiments of the invention, the voltage difference between the seventh, eighth, and ninth reference voltages may be other values, which are also within the spirit and scope of the invention.
[0045] At Figure 2 Although the voltage waveforms applied to the ground select lines GSL0-GSL2 and the series select lines SSL0-SSL2 are shown as linearly decreasing waveforms, it should be understood that the present invention is not limited thereto. In other embodiments of the present invention, the voltage waveforms applied to the ground select lines GSL0-GSL2 and the series select lines SSL0-SSL2 may be other decreasing waveforms, which are also within the spirit and scope of the present invention.
[0046] Depend on Figure 2 As can be seen, in one embodiment of the present invention, at the end of a read operation or a write verification operation, during the word line voltage drop phase, multiple different gradually decreasing signal line reference voltages (i.e., the seventh reference voltage to the ninth and thirteenth reference voltages) are simultaneously applied to multiple ground select lines and multiple string select lines, wherein the values of these different gradually decreasing signal line reference voltages are related to the multiple signal line positions of these ground select lines and these string select lines.
[0047] Depend on Figure 2 It is understood that, in one embodiment of the present invention, a first signal line reference voltage applied to an outer ground selection line (such as GSL0) and an outer string selection line (such as SSL2) of these ground selection lines and these string selection lines is higher than a second signal line reference voltage applied to an inner ground selection line (such as GSL1) and an inner string selection line (such as SSL1) of these ground selection lines and these string selection lines.
[0048] Figure 3 A waveform diagram of a memory device according to another embodiment of the present invention is shown. Figure 3 The invention is illustrated using a read operation as an example, but it should be understood that the invention is not limited thereto. Other embodiments of the invention can also be applied to write verification.
[0049] Figure 3 The waveform is in principle similar to Figure 2 The differences between the two will be explained below.
[0050] Within stage P4, the selected word line SWL drops from the sixth reference voltage Vread2 to the first reference voltage; the unselected word line UWL drops from the second reference voltage Vpass to the first reference voltage; the redundant ground select line GSLD0 and the redundant string select line SSLD2 drop from the second reference voltage Vpass to the tenth reference voltage (e.g., but not limited to -3V); the redundant ground select line GSLD1 and the redundant string select line SSLD1 drop from the second reference voltage Vpass to the eleventh reference voltage (e.g., but not limited to -4V); the redundant ground select line GSLD2 and the redundant string select line SSLD0 drop from the second reference voltage Vpass to the twelfth reference voltage (e.g., but not limited to -4V). Limited to -5V); the redundant ground select line GSLD3 drops from the second reference voltage Vpass to the thirteenth reference voltage (e.g., but not limited to -6V); the ground select line GSL0 and the series select line SSL2 drop from the second reference voltage Vpass to the seventh reference voltage; the ground select line GSL1 and the series select line SSL1 drop from the second reference voltage Vpass to the eighth reference voltage; the ground select line GSL2 and the series select line SSL0 drop from the second reference voltage Vpass to the ninth reference voltage; these bit lines BL0 to BLP drop from the third reference voltage VBL to the first reference voltage; and the common source line CSL drops from the fourth reference voltage VCSL to the first reference voltage.
[0051] like Figure 3 As shown, during the fourth stage P4 (i.e., during the word line voltage drop stage), a gradually decreasing reference voltage is applied to these ground select lines (GSL0~GSL2), these string select lines (SSL0~SSL2), these redundant ground select lines GSLD0~GSLD3, and these redundant string select lines SSLD0~SSLD2, thereby avoiding thermionic mode interference of conventional technology, the reason for which will be explained below.
[0052] After the four phases P1 to P4 of the read operation are completed, at timing T1, the selected word line SWL is maintained at the first reference voltage; the unselected word line UWL is maintained at the first reference voltage; the redundant ground select line GSLD0 and the redundant string select line SSLD2 are maintained at the tenth reference voltage; the redundant ground select line GSLD1 and the redundant string select line SSLD1 are maintained at the eleventh reference voltage; the redundant ground select line GSLD2 and the redundant string select line SSLD0 are maintained at the twelfth reference voltage; the redundant ground select line GSLD3 is maintained at the thirteenth reference voltage; the ground select line GSL0 and the string select line SSL2 are maintained at the seventh reference voltage; the ground select line GSL1 and the string select line SSL1 are maintained at the eighth reference voltage; the ground select line GSL2 and the string select line SSL0 are maintained at the ninth reference voltage; these bit lines BL0 to BLP are maintained at the first reference voltage; and the common source line CSL is maintained at the first reference voltage.
[0053] At Figure 3 In this invention, although the voltage difference between the tenth, eleventh, twelfth, and thirteenth reference voltages is 1V, it should be understood that the invention is not limited thereto. In other embodiments of the invention, the voltage difference between the tenth, eleventh, twelfth, and thirteenth reference voltages may be other values, which are also within the spirit and scope of the invention.
[0054] At Figure 3 Although the voltage waveforms applied to these redundant ground select lines GSLD0-GSLD3 and these redundant string select lines SSLD0-SSLD2 are shown as linearly decreasing waveforms, it should be understood that the present invention is not limited thereto. In other embodiments of the present invention, the voltage waveforms applied to these redundant ground select lines GSLD0-GSLD3 and these redundant string select lines SSLD0-SSLD2 may be other decreasing waveforms, which are also within the spirit and scope of the present invention.
[0055] Depend on Figure 3 It is understood that, in one embodiment of the present invention, at the end of the read operation or the write verification operation, during the word line voltage drop phase (such as the fourth phase P4), multiple different gradually decreasing redundant signal line reference voltages (i.e., the tenth reference voltage to the thirteenth reference voltage) are simultaneously applied to multiple redundant ground select lines and multiple redundant string select lines, wherein the values of these different gradually decreasing redundant signal line reference voltages are related to the positions of multiple redundant signal lines of these redundant ground select lines and these redundant string select lines.
[0056] Depend on Figure 3As can be seen, in one embodiment of the present invention, a first redundant signal line reference voltage applied to an outer redundant ground selection line (such as GSLD0) and an outer redundant string selection line (such as SSLD2) of these redundant ground selection lines and these redundant string selection lines is higher than a second redundant signal line reference voltage applied to a redundant inner ground selection line (such as GSLD1) and a redundant inner string selection line (such as SSLD1) of these redundant ground selection lines and these redundant string selection lines.
[0057] Figure 4 This diagram shows the channel voltage waveform of an embodiment of the present invention compared to that of conventional technology. Figure 4 The horizontal axis represents the position of the signal line. The leftmost position represents the bottom ground select line GSL0, and the rightmost position represents the top serial select line SSL2. Figure 4 The vertical axis represents the channel voltage. Curve L41 represents, in one embodiment of the invention, at the end of the operation (e.g., Figure 2 or Figure 3 At timing T1, the channel voltage measured at each signal line position; curve L42 represents, in conventional technology, at the end of operation (such as... Figure 2 or Figure 3 The channel voltage measured at each signal line position during timing T1. Figure 4 In this context, it is assumed that word lines WL1 and WL(N-1) are in the programming state, while the remaining word lines WL0, WL2 to WL(N-2) and WLN are in the erasure state.
[0058] Comparing curves L41 and L42, it can be seen that in one embodiment of the present invention, by applying a gradually decreasing reference voltage to these ground select lines, these string select lines, and / or these redundant ground select lines and these redundant string select lines, the voltage difference between word lines WL1 and WL0, and also the voltage between word lines WL(N-1) and WLN, can be reduced. Therefore, the hot-electron mode interference at word lines WL0 and WLN can be mitigated, thereby avoiding negative impacts on the operation and performance of the memory device.
[0059] Furthermore, by applying a gradually decreasing reference voltage to these ground select lines, these string select lines, and / or these redundant ground select lines and these redundant string select lines, embodiments of the present invention can protect these ground select lines, these string select lines, and / or these redundant ground select lines and these redundant string select lines from additional interference.
[0060] Figure 5 A flowchart illustrating a method for operating a memory device according to yet another embodiment of the present invention is shown. Figure 5As shown, the memory device operation method includes: at the end of a read operation or a write verification operation, during a word line voltage drop phase, simultaneously applying a plurality of different gradually decreasing signal line reference voltages to the ground select lines and the string select lines, wherein the values of the different gradually decreasing signal line reference voltages are relative to a plurality of signal line positions (510) of the ground select lines and the string select lines.
[0061] In one embodiment of the present invention, at the end of a read operation or a write verification operation, during the word line voltage drop phase (such as phase 4 P4), the outermost ground selection line (i.e., Figure 1 The ground selection line GSL0 in the middle and the outermost series selection line (i.e., Figure 1 The innermost series select line (SSL2) drops to the first reference voltage (e.g., 0V), while the innermost ground select line (i.e., ...) drops to the first reference voltage. Figure 1 The ground selection lines GSL1 to GSL2 in the middle and the innermost series selection lines (i.e., Figure 1 The series selection lines SSL0 to SSL1 in the circuit gradually decrease to a negative voltage, which can avoid interference from the hot electron mode.
[0062] Furthermore, in one embodiment of the present invention, at the end of a read operation or a write verification operation, during the word line voltage drop phase (such as phase 4 P4), the outermost ground selection line (i.e., Figure 1 The ground selection line GSL0 in the middle and the outermost series selection line (i.e., Figure 1 The innermost series select line (SSL2) drops to the first reference voltage (e.g., 0V), while the innermost ground select line (i.e., ...) drops to the first reference voltage. Figure 1 The ground selection lines GSL1 to GSL2 in the middle and the innermost series selection lines (i.e., Figure 1 The series select lines SSL0 to SSL1 in the middle drop synchronously to gradually negative voltage, and the innermost redundant ground select line (i.e., Figure 1 The redundant ground selection lines GSLD0 to GSLD3 in the middle and the redundant series selection lines further inside (i.e. Figure 1 The redundant string selection lines (SSLD0~SSLD2) in the middle gradually decrease to a more negative voltage, which can avoid hot electron mode interference.
[0063] An embodiment of the present invention can be applied to three-dimensional memory devices that are subject to hot electron mode interference, such as, but not limited to, floating gate three-dimensional memory devices, silicon nitride charge trapping three-dimensional memory devices, and gate-all-around vertical channel three-dimensional memory devices.
[0064] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.
Claims
1. A method of operating a memory device comprising a plurality of ground select lines, a plurality of string select lines, a plurality of redundant ground select lines, and a plurality of redundant string select lines, the method comprising: The operation method of the memory device includes: At the end of a read operation or a write verification operation, during the word line voltage drop phase, multiple different gradually decreasing signal line reference voltages are simultaneously applied to these ground select lines and these string select lines, wherein the values of these different gradually decreasing signal line reference voltages are related to the multiple signal line positions of these ground select lines and these string select lines.
2. The operating method of a memory device according to claim 1, wherein, Also includes: At the end of the read operation or the write verification operation, during the word line voltage drop phase, multiple different gradually decreasing redundant signal line reference voltages are synchronously applied to these redundant ground select lines and these redundant string select lines, wherein the values of these different gradually decreasing redundant signal line reference voltages are related to the multiple redundant signal line positions of these redundant ground select lines and these redundant string select lines. 3.The operating method of a memory device according to claim 1, wherein, A first signal line reference voltage applied to an outer ground select line and an outer string select line of these ground select lines and these string select lines is higher than a second signal line reference voltage applied to an inner ground select line and an inner string select line of these ground select lines and these string select lines. 4.The operating method of a memory device according to claim 2, wherein, A first redundant signal line reference voltage applied to an outer redundant ground selection line and an outer redundant string selection line of these redundant ground selection lines and these redundant string selection lines is higher than a second redundant signal line reference voltage applied to an inner redundant ground selection line and an inner redundant string selection line of these redundant ground selection lines and these redundant string selection lines.
5. The method of operating the memory device according to claim 2, characterized in that, These different gradually decreasing signal line reference voltages decrease linearly; These different redundant signal line reference voltages gradually decrease linearly; These voltage differences between the reference voltages of the gradually decreasing signal lines are the same; and... These differences gradually decrease until the multiple voltage differences between the reference voltages of the redundant signal lines become the same.
6. A memory device, comprising: include: Multiple memory units; Multiple grounding selection lines; Multiple redundant grounding selection lines; Multiple bit lines; Multiple string selection lines; Multiple redundant string selection lines; Multiple word lines are coupled to these memory cells, which in turn are coupled to these bit lines; as well as Multiple switches are coupled to these ground select lines, these redundant ground select lines, these bit lines, these string select lines and these redundant string select lines; in, At the end of a read operation or a write verification operation, during the word line voltage drop phase, multiple different gradually decreasing signal line reference voltages are simultaneously applied to these ground select lines and these string select lines, wherein the values of these different gradually decreasing signal line reference voltages are related to the multiple signal line positions of these ground select lines and these string select lines.
7. The memory device of claim 6, wherein, At the end of the read operation or the write verification operation, during the word line voltage drop phase, multiple different gradually decreasing redundant signal line reference voltages are synchronously applied to these redundant ground select lines and these redundant string select lines, wherein the values of these different gradually decreasing redundant signal line reference voltages are related to the multiple redundant signal line positions of these redundant ground select lines and these redundant string select lines.
8. The memory device of claim 6, wherein, A first signal line reference voltage applied to an outer ground select line and an outer string select line of these ground select lines and these string select lines is higher than a second signal line reference voltage applied to an inner ground select line and an inner string select line of these ground select lines and these string select lines.
9. The memory device of claim 7, wherein, A first redundant signal line reference voltage applied to an outer redundant ground selection line and an outer redundant string selection line of these redundant ground selection lines and these redundant string selection lines is higher than a second redundant signal line reference voltage applied to an inner redundant ground selection line and an inner redundant string selection line of these redundant ground selection lines and these redundant string selection lines.
10. The memory device according to claim 7, characterized in that, These different gradually decreasing signal line reference voltages decrease linearly; These different redundant signal line reference voltages gradually decrease linearly; These voltage differences between the reference voltages of the gradually decreasing signal lines are the same; and... These differences gradually decrease until the multiple voltage differences between the reference voltages of the redundant signal lines become the same.