Data correction circuit and data transmission circuit

Abstract

The present disclosure provides a data correction circuit and a data transmission circuit, the data correction circuit comprising: a decoding module, an input end of which is connected to a data bus, configured to receive first data and a check code of the first data, and output a correction code of the first data based on the check code; and a correction latching module, a first input end of which is connected to the data bus, a second input end of which is connected to an output end of the decoding module, configured to latch the first data corresponding to the correction code, and generate and output second data according to the correction code and the corresponding first data. The embodiment of the present disclosure can realize the checking and correction of the alternately transmitted odd data and even data through one data correction circuit.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and more specifically, to a data error correction circuit and a data transmission circuit capable of efficient data processing. Background Technology

[0002] Error Correcting Code (ECC) is a technique that enables data error checking and correction. By using an ECC checksum transmitted along with the target data, it verifies the target data and can correct data transmission errors as small as one bit. ECC circuits are widely used in circuits such as memory that require accurate data transmission.

[0003] In memory, transmitted data is typically divided into odd and even data, which are transmitted alternately. Odd data is sampled using an odd clock and transmitted through odd data signal lines; even data is sampled using an even clock and transmitted through even data signal lines. The odd and even data signal lines are arranged in parallel, and the alternating transmission of odd and even data avoids crosstalk between signal lines, thus improving data transmission reliability.

[0004] In some embodiments, when data error correction circuits are required to verify and correct the data to be transmitted, the processing time of these circuits is relatively long, making it impossible to complete the verification or correction of even data before the arrival of odd data, or vice versa. Therefore, data error correction circuits need to be set on both the odd and even data signal lines. However, because the data error correction circuits occupy a large area in the layout, the overall area occupied by the data transmission circuits in the layout is also large.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a data error correction circuit and a data transmission circuit that at least partially overcome the problem that a data error correction circuit cannot handle alternating transmission of odd and even data due to limitations and defects in related technologies.

[0007] According to a first aspect of this disclosure, a data error correction circuit is provided, comprising: a decoding module, with its input end connected to a data bus, for receiving first data and a check code of the first data, and outputting an error correction code of the first data based on the check code; and an error correction latching module, with its first input end connected to the data bus and its second input end connected to the output end of the decoding module, for latching the first data corresponding to the error correction code, and generating and outputting second data based on the error correction code and the corresponding first data.

[0008] In an exemplary embodiment of this disclosure, the error correction latch module includes: a first latch unit, with its input end connected to the data bus, for latching the first data; an error correction unit, connected to the output end of the first latch unit and the output end of the decoding module, for correcting the corresponding first data according to the error correction code and outputting the corrected second data; and a second latch unit, with its input end connected to the output end of the error correction unit, for latching and outputting the second data.

[0009] In one exemplary embodiment of this disclosure, the first data includes M bits of data, and the first latch unit includes N L-bit latches, where N*L=M and N≥1.

[0010] In an exemplary embodiment of this disclosure, N=1, L=M, the first latch unit is a serial output, the decoding module is a serial output, the error correction unit includes an error corrector, the input terminal of the error corrector is connected to the output terminal of the first latch unit, the enable terminal of the error correction unit is connected to the output terminal of the decoding module, and the output timing of the error correction code is the same as the data output timing of the first latch unit.

[0011] In an exemplary embodiment of this disclosure, the first latch unit is a parallel output, including M output terminals; the decoding module is a parallel output, including M output terminals; the error correction unit includes M error correctors; the enable terminal of each error corrector is connected to one output terminal of the decoding module; and the input terminal of each error correction unit is connected to one output terminal of the first latch unit.

[0012] In an exemplary embodiment of this disclosure, the second latch unit includes an M-bit shift register, and the second latch unit is a serial input.

[0013] In an exemplary embodiment of this disclosure, the second latch unit includes S K-bit shift registers, S*K = M, and the second latch unit is a parallel input, S ≥ 1.

[0014] In an exemplary embodiment of this disclosure, the first latch unit is connected to the first control unit, and the second latch unit is connected to the second control unit. The first control unit is used to control the first latch unit to start latching at a time point n+mt, where n is a relative delay time, the starting point of the relative delay time is the time it takes for the first data to be transmitted to the decoding module, m is a natural number, t is the transmission interval of the first data, and n is greater than 0 and less than t. The second control unit is used to control the second latch unit to start latching between n+mt and n+(m+1)t.

[0015] In an exemplary embodiment of this disclosure, the error corrector includes an inverter and a transmission tube connected in parallel. The input terminals of the inverter and the transmission tube are connected as the input terminals of the error corrector, and the output terminals of the inverter and the transmission tube are connected as the output terminals of the error corrector. The enable terminals of the inverter and the transmission tube are both connected to the output terminals of the decoding module.

[0016] In one exemplary embodiment of this disclosure, the first latch unit is a serial input or a parallel input.

[0017] In one exemplary embodiment of this disclosure, the second latch unit is a serial output or a parallel output.

[0018] In one exemplary embodiment of this disclosure, the input terminal of the second control unit is connected to the output terminal of the first control unit.

[0019] According to a second aspect of this disclosure, a data transmission circuit is provided, comprising: an odd data signal line for transmitting odd data; an even data signal line for transmitting even data, wherein the even data and the odd data are transmitted alternately at intervals, and a first time interval exists between the arrival time of the even data and the arrival time of the odd data; and a data error correction circuit as described in any of the preceding claims, wherein an input terminal is connected to the odd data signal line and the even data signal line, and an output terminal is connected to an output bus, the output bus being electrically connected to a storage block; wherein the data error correction circuit is used to correct errors in the odd data or the even data when the odd data or the even data is written to the storage block.

[0020] In an exemplary embodiment of this disclosure, the data error correction circuit includes a decoding module and an error correction latch module. The odd data or the even data enters the decoding module at a first time point, and the error correction latch module outputs the corrected data at a second time point. The interval between the first time point and the second time point is greater than the first time interval.

[0021] According to a third aspect of this disclosure, a data transmission circuit is provided, comprising: a first data signal line for transmitting odd data and even data, wherein the even data and the odd data are transmitted alternately at intervals, and the arrival time of the even data and the arrival time of the odd data have a first time interval; a data error correction circuit as described in any of the preceding claims, wherein an input terminal is connected to the odd data signal line and the even data signal line, and an output terminal is connected to an output bus, wherein the output bus is electrically connected to a storage block; wherein the data error correction circuit is used to correct the odd data or the even data when the odd data or the even data is written to the storage block.

[0022] This embodiment of the disclosure divides the data error correction circuit into two parts: a decoding module and an error correction latch module. The data verification and error correction process is divided into decoding and error correction. The decoding module can decode the current data before the next data arrives, and the processing flow is handed over to the error correction latch module just before the next data arrives. This avoids interruption of the current data processing flow or loss of the next data due to its arrival. Therefore, this embodiment of the disclosure can achieve sequential processing of alternating odd and even data using a single data error correction circuit. In the design of the data transmission circuit, this saves one data error correction circuit, reduces the layout area occupied by the data transmission circuit, and lowers the overall power consumption of the data transmission circuit.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1A This is a schematic diagram showing the connection relationship of data error correction circuits in related technologies;

[0026] Figure 1B yes Figure 1A The data processing timing diagram of the data error correction circuit shown is shown below;

[0027] Figure 2 This is a schematic diagram of the data error correction circuit in an exemplary embodiment of this disclosure;

[0028] Figure 3 This is a block diagram of an error correction latch module in one embodiment of this disclosure;

[0029] Figure 4 This is a circuit diagram of an error correction latch module in one embodiment of this disclosure;

[0030] Figure 5 This is a circuit diagram of an error correction latch module in another embodiment of this disclosure;

[0031] Figure 6 This is a timing diagram of data latching in one embodiment of this disclosure;

[0032] Figure 7 This is a schematic diagram of a first control unit and a second control unit in one embodiment of this disclosure;

[0033] Figure 8 This is a schematic diagram of a data transmission circuit in one embodiment of the present disclosure;

[0034] Figure 9 This is a schematic diagram of a data transmission circuit in another embodiment of this disclosure. Detailed Implementation

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0036] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0037] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0038] Figure 1A This is a schematic diagram showing the connection relationship of data error correction circuits in related technologies; Figure 1B yes Figure 1AThe data processing timing diagram of the data error correction circuit is shown.

[0039] refer to Figure 1A In related technologies, the odd data signal line transmits odd data EvenData<127:0> and the ECC checksum EvenParity<8:0> of the odd data. Error correction is performed by the odd data error correction unit 11 set on the odd data signal line, and the error-corrected data EvenDataWr<127:0> is output. The even data signal line transmits even data OddData<127:0> and the ECC checksum OddParity<8:0> of the even data. Error correction is performed by the even data error correction unit 12 set on the even data signal line, and the error-corrected data OddDataWr<127:0> is output. This is due to timing (see...). Figure 1B In this process, both odd data EvenData<127:0> and even data OddData<127:0> have a transmission period of T, and they are transmitted alternately with a transmission interval of T / 2. The error correction processing time of either the odd data error correction unit 11 or the even data error correction unit 12 is Tecc, where Tecc > T / 2. This means that one error correction unit cannot handle the alternating arrival of odd and even data within T / 2 time, necessitating the use of two error correction units to process the odd and even data separately.

[0040] Figure 2 This is a schematic diagram of the data error correction circuit in an exemplary embodiment of this disclosure.

[0041] refer to Figure 2 The data error correction circuit 200 may include:

[0042] The decoding module 21 has its input end connected to the data bus. It is used to receive the first data and the check code of the first data, and output the error correction code of the first data based on the check code.

[0043] The error correction latch module 22 has a first input terminal connected to the data bus and a second input terminal connected to the output terminal of the decoding module 21. It is used to latch the first data corresponding to the error correction code and generate and output the second data according to the error correction code and the corresponding first data.

[0044] In one embodiment of this disclosure, the first data is, for example, 128 bits, represented as Data<127:0>. Correspondingly, the checksum of the first data can be an ECC checksum. When the first data is 128 bits, the ECC checksum of the first data can be represented as Parity<8:0>, where each bit of the ECC checksum is either the XOR result of different rows of the first data (i.e., the row checksum) or the XOR result of different columns of the first data (i.e., the column checksum). The decoding module 21 generates corresponding row checksums and column checksums for the first data according to the ECC checksum logic, compares the generated row checksums and column checksums with the row checksums and column checksums recorded in the ECC checksum, and determines the data bit of the first data that is abnormal based on the position of the checksum where the comparison result is inconsistent, and then outputs the error correction code of the first data.

[0045] In this embodiment of the disclosure, when the first data is 128 bits, the error correction code of the first data is 128 bits, and each bit in the error correction code indicates whether the corresponding bit in the first data is incorrect. For example, if bit 6 of the first data is incorrect, bit 6 in the error correction code is 1; if bit 0 of the first data is correct, bit 0 in the error correction code is 0. In this case, if the verification result of the first data matches the ECC checksum, the error correction code of the first data is all 0s; if the verification result of the first data does not match the ECC checksum, the corresponding bit in the error correction code of the first data is set to 1. The error correction code is represented by different values ​​depending on the location of the error. In other embodiments of this disclosure, the error correction code can also be set to use 1 to indicate that the corresponding bit in the first data is correct and 0 to indicate that the corresponding bit in the first data is incorrect. This disclosure does not impose any special restrictions on this.

[0046] The error correction latch module 22 is used to latch the first data and correct errors in the first data according to the error correction code of the first data. It should be noted that the first data is sent cyclically within the transmission cycle corresponding to the first data. Therefore, when the first data enters the decoding module 21 and is verified and calculated by the decoding module 21, the error correction latch module 22 can delay latching the first data and continue to correct the currently processed data. It is only necessary to ensure that the error correction latch module 22 can latch the first data of a certain transmission within the transmission cycle of the first data.

[0047] Based on the above, by separating the error correction code generation step (verification step) and the error correction step in data error correction, when the error correction latch module 22 performs error correction processing on the preceding data (either odd or even data), the decoding module 21 can simultaneously perform verification and decoding on the subsequent data (the other of odd or even data). In this way, when the subsequent data arrives, the error correction latch module 22 can continue to perform error correction processing on the preceding data, while the decoding module 21 can process the subsequent data in a timely manner, avoiding the loss of subsequent data or interruption of the processing of the current data (the preceding data) due to the long overall time for verification and error correction of the preceding data.

[0048] Figure 3 This is a block diagram of an error correction latch module in one embodiment of this disclosure.

[0049] refer to Figure 3 In one embodiment, the error correction latch module 22 may include:

[0050] The first latch unit 221 has its input terminal connected to the data bus and is used to latch the first data;

[0051] The error correction unit 222 is connected to the output of the first latch unit 221 and the output of the decoding module 21. It is used to correct the corresponding first data according to the error correction code and output the corrected second data.

[0052] The second latch unit 223 has its input terminal connected to the output terminal of the error correction unit 222, and is used to latch and output the second data.

[0053] In one embodiment, the first data includes M bits of data, and the first latch unit 221 includes N L-bit latches, where N*L = M, and N ≥ 1. Here, M is the number of bits; in the 128-bit first data, M = 128.

[0054] The first latch unit 221 can be implemented by one or more latches or shift registers.

[0055] Figure 4 This is a circuit diagram of an error correction latch module in one embodiment of this disclosure.

[0056] refer to Figure 4 In one embodiment, N=1, L=M, and the first latch unit 221 is implemented through an M-bit shift register. For example, when the first data is 128 bits, M=128, and the first latch unit 221 is a 128-bit shift register. In this case, the first latch unit 221 is a serial input.

[0057] When the first latch unit 221 is a serial output, it has one output terminal. The data input port of the error correction unit 222 is one input terminal. The error correction unit 222 is a serial input, and the decoding module 21 is a serial output. The error correction unit 222 is implemented through an error corrector 2221. The input terminal of the error corrector 2221 is connected to the output terminal of the first latch unit 221, and the enable terminal of the error correction unit 222 is connected to the output terminal of the decoding module 21. The time point of each bit of the error correction code Correct<127:0> output matches the time point of each bit of the data DataPre<127:0> output by the first latch unit 221. It should be noted that a set of error correction codes Correct<127:0> can be repeatedly transmitted multiple times within the transmission period t (equal in length to the transmission period t of the first data). The time point of the data DataPre<127:0> output by the first latch unit 221 only needs to match the transmission time point of a certain set of error correction codes of its corresponding first data.

[0058] exist Figure 4 In the illustrated embodiment, the error corrector 2221 includes an inverter INV and a transmission tube SR connected in parallel. The input terminals of the inverter INV and the transmission tube SR are connected as the input terminals of the error corrector 2221, and the output terminals of the inverter INV and the transmission tube SR are connected as the output terminals of the error corrector 2221. The enable terminals of the inverter INV and the transmission tube SR are both connected to the output terminals of the decoding module 21.

[0059] Each bit of the output DataPre<127:0> from the first latch unit 221 corresponds to the corresponding bit of the error correction code Correct<127:0>. If the x-th bit of the error correction code Correct<127:0> is 0, the inverter INV is turned off, the transmission transistor SR is turned on, and the x-th bit of the output data DataPost<127:0> from the error corrector 2221 is equal to the x-th bit of DataPre<127:0>, with no error correction performed. If the y-th bit of the error correction code Correct<127:0> is 0, the inverter INV is turned on, the transmission transistor SR is turned off, and the y-th bit of the output data DataPost<127:0> from the error corrector 2221 is equal to the inverted data of the y-th bit of DataPre<127:0>, thus achieving bitwise error correction of DataPre<127:0>, i.e., the first data Data<127:0>. Here, x and y are both natural numbers. The above data bit length is only an example; in actual applications, the data bit length is set according to processing requirements.

[0060] Therefore, when the error correction unit 222 is implemented through an error corrector 2221 and has one output, the second latch unit 223 includes an M-bit shift register and is a serial input. The second latch unit 223 can be either a serial output or a parallel output, depending on the requirements of the external circuit.

[0061] In one embodiment, the first latch unit 221 is connected to the first control unit 224, and the second latch unit 223 is connected to the second control unit 225. The first control unit 224 outputs a first control signal to control the latching of the first latch unit 221; the second control unit 225 outputs a second control signal to control the latching of the second latch unit 223.

[0062] Figure 5 This is a circuit diagram of an error correction latch module in another embodiment of this disclosure.

[0063] refer to Figure 5 In another embodiment, the first latch unit 221 can be a parallel output, including M output terminals. Correspondingly, the decoding module 21 is a parallel output, including M output terminals. The error correction unit 222 includes M error correctors 2221. The enable terminal of each error corrector 2221 is connected to one output terminal of the decoding module 21, and the input terminal of each error corrector 2221 is connected to one output terminal of the first latch unit 221. Further, the second latch unit 223 is a parallel input, having M input terminals. The second latch unit 223 can be implemented using S K-bit shift registers, where S*K = M, S ≥ 1. The error corrector 2221 is, for example, a... Figure 4 As shown in the figure.

[0064] Meanwhile, the first latch unit 221 can be either a serial input or a parallel input. The second latch unit 2231 can be either a serial output or a parallel output.

[0065] and Figure 4 The embodiments shown are the same. The first latching unit 221 is controlled by the first control signal output by the first control unit 224 to start latching, and the second latching unit 223 is controlled by the second control signal output by the second control unit 225 to start latching.

[0066] Figure 6 This is a timing diagram of data latching in one embodiment of this disclosure.

[0067] refer to Figure 6 In one embodiment, the first data Data<127:0> is alternately transmitted odd or even data, with a transmission interval of t between odd and even data. Within this transmission interval t, the first data Data<127:0> is transmitted. It can be understood that the transmission interval t equals... Figure 1BThe transmission period T of the odd or even data shown is half of the transmission period.

[0068] The first control unit 224 controls the first latching unit 221 to latch the first data starting at a first time point T1, where T1 = n + mt, n is the relative delay time, the starting point of the relative delay time is the time point T0 when the first data is transmitted to the decoding module 21, 0 < n < t, and m is a natural number. The second control unit 225 controls the second latching unit 223 to start latching at a certain time point between the first time point T1 and the next first time point T1', where the next first time point T1' is T1' = n + (m + 1)t. Figure 6 In the illustrated embodiment, m = 1.

[0069] The second latch unit 223 receives and outputs the error-corrected second data, DataWr<127:0>, starting from the second time point T2. The time between the first data, Data<127:0>, entering the decoding module 21 at time point T0 and the second data, DataWr<127:0>, being output at the second time point T2 is the error correction and verification duration Tecc for the first data. Tecc is greater than the transmission period t of the first data. (Reference) Figure 6 In the process, before the second time point T2, the first data 61 arrives at the decoding module 21. After time t, i.e., the third time point T3, the next first data 62 enters the decoding module 21. The decoding module 21 begins to calculate the next first data 62. However, at this time (at the third time point T3), the first latch unit 221 still latches the first data 61 (outputting DataPre<127:0>) until time t has elapsed and the next third time point T3' is reached, at which point the first latch unit 221 latches the next first data 62. When the error correction unit 222 and the second latch unit 223 are serial input and output, more data processing time is required. Therefore, controlling the time for the first latch unit 221 to latch the first data 61 to t allows the error correction unit 222 more data processing time while ensuring that the next first data 62 can be processed.

[0070] It should be noted that the time when the decoding module 21 outputs the error correction code should be after the first time point T1 and before the third time point T3 after the first data transmission is completed (the time between T0 and T3 is t). That is, the maximum time for the decoding module 21 to perform verification and decoding is no greater than t, so as to ensure that each first data can be verified and decoded.

[0071] In one embodiment, the first control signal can be used to align the first time point T1 at which the first latch unit 221 begins latching the first data with the first bit of the first data. When the first latch unit 221 is a serial output, the timing of the output data DataPre<127:0> by the first latch unit 221 can be controlled to be the same as the timing of the output error correction code (the time point at which each bit is output) by the decoding module 21. Simultaneously, the second control signal can be used to control the second time point T2 at which the second latch unit 223 begins latching after the decoding module 21 outputs the error correction code. In extreme cases, the second time point T2 can be controlled to be equal to the time when the error correction unit 222 begins outputting data DataPost<127:0>. When the second latch unit 223 is a serial output, it is also necessary to control the start latching time point of the second latch unit 223 to have a delay compared to the time point when the decoding module 21 begins outputting the error correction code, because there is a certain delay between the time the error correction unit 222 receives the error correction code and the time it outputs a certain bit in DataPost<127:0>.

[0072] Figure 7 This is a schematic diagram of a first control unit and a second control unit in one embodiment of this disclosure.

[0073] refer to Figure 7In one embodiment, the input terminal of the second control unit 225 can be connected to the output terminal of the first control unit 224. The input terminal of the first control unit 225 is used to receive a latch signal Catch. The first control unit 224 is used to generate a first control signal based on the latch signal Catch. The second control unit 225 is used to generate a second control signal based on the first control signal. The first control signal is used to control the first latch unit 221 to start latching, and the second control signal is used to control the second latch unit 223 to start latching. Under the excitation of the first control signal and the second control signal, the first latch unit 221 starts latching at a first time point T1, and the second latch unit 223 starts latching between the first time point T1 and the next first time point T1'. Specifically, the first control unit 224 and the second control unit 225 are used to delay the input signal to obtain the corresponding output signal. By adjusting the delay of the first control unit 224 and the second control unit 225, the data output timing of the first latch unit 221 (the time point at which each bit is output) can be controlled to be the same as the timing of the error correction code output by the decoding module 21 (the time point at which each bit is output), and the latch timing of the second latch unit 223 can be controlled to be the same as the timing of the data DataPost<127:0> output by the error correction unit 222. That is, when the control signal Catch and the first data are input simultaneously, the delay time of the first control unit 224 can be equal to the decoding time of the decoding module 21, and the delay time of the second control unit 225 can be equal to the processing time of the error correction unit 222, that is, the time difference between the data input and data output of the error correction unit 222.

[0074] The data error correction circuit provided in this embodiment divides the entire ECC operation with a computation time of Tecc into smaller time intervals and performs verification and error correction on data with a transmission interval of t (t < Tecc). Thus, a single data error correction circuit can be used to verify and correct alternating odd and even data, reducing the number of data error correction circuits required in the data transmission circuit.

[0075] Figure 8 This is a schematic diagram of a data transmission circuit in one embodiment of the present disclosure.

[0076] refer to Figure 8 In one embodiment, the data transmission circuit 800 may include:

[0077] Odd data signal line 81 is used to transmit odd data;

[0078] Even data signal line 82 is used to transmit even data. Even data and odd data are transmitted alternately at intervals. There is a first time interval between the arrival time of even data and the arrival time of odd data.

[0079] As described in the above embodiment, the data error correction circuit 83 has an input terminal connected to the odd data signal line and the even data signal line, an output terminal connected to the output bus 84, and the output bus electrically connected to the storage block 85.

[0080] The data error correction circuit 83 is used to correct odd or even data when it is written to the storage block 85.

[0081] In one embodiment, the data error correction circuit 83 includes a decoding module 831 and an error correction latch module 832. Odd or even data enters the decoding module 831 at a first time point, and the error correction latch module 832 outputs the corrected data at a second time point. The interval between the first time point and the second time point is greater than the first time interval.

[0082] Figure 9 This is a schematic diagram of a data transmission circuit in another embodiment of this disclosure.

[0083] refer to Figure 9 In another embodiment, the data transmission circuit 900 may include:

[0084] The first data signal line 91 is used to transmit odd data and even data. Even data and odd data are transmitted alternately at intervals. There is a first time interval between the arrival time of even data and the arrival time of odd data.

[0085] As described in the above embodiment, the data error correction circuit 92 has an input terminal connected to the first data signal line 91, an output terminal connected to the output bus 93, and the output bus 93 electrically connected to the storage block 94.

[0086] The data error correction circuit 92 is used to correct odd or even data when it is written to the storage block 94.

[0087] The data error correction circuit 92 includes a decoding module 921 and an error correction latch module 922. Odd or even data enters the decoding module 921 at a first time point, and the error correction latch module 922 outputs the corrected data at a second time point. The interval between the first time point and the second time point is greater than the first time interval.

[0088] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0089] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A data error correction circuit, characterized in that, include: Decoding module and error correction latch module; The decoding module, with its input end connected to the data bus, is used to receive first data and the verification code of the first data during the process of the error correction latching module latching and correcting prior data, and to output the error correction code of the first data based on the verification code. The error correction latch module has a first input terminal connected to the data bus and a second input terminal connected to the output terminal of the decoding module. It is used to latch the first data corresponding to the error correction code during the process of the decoding module verifying subsequent data, and generate and output the second data according to the error correction code and the corresponding first data.

2. The data error correction circuit as described in claim 1, characterized in that, The error correction latch module includes: The first latch unit has its input terminal connected to the data bus and is used to latch the first data; An error correction unit, connected to the output of the first latch unit and the output of the decoding module, is used to correct the corresponding first data according to the error correction code and output the corrected second data. The second latch unit has its input connected to the output of the error correction unit and is used to latch and output the second data.

3. The data error correction circuit as described in claim 2, characterized in that, The first data includes M bits of data, and the first latch unit includes N L-bit latches, where N L=M, N≥1.

4. The data error correction circuit as described in claim 3, characterized in that, N=1, L=M, the first latch unit is a serial output, the decoding module is a serial output, the error correction unit includes an error corrector, the input of the error corrector is connected to the output of the first latch unit, the enable of the error correction unit is connected to the output of the decoding module, and the output timing of the error correction code is the same as the data output timing of the first latch unit.

5. The data error correction circuit as described in claim 3, characterized in that, The first latch unit is a parallel output, including M output terminals. The decoding module is a parallel output, including M output terminals. The error correction unit includes M error correctors. The enable terminal of each error corrector is connected to one output terminal of the decoding module. The input terminal of each error correction unit is connected to one output terminal of the first latch unit.

6. The data error correction circuit as described in claim 4, characterized in that, The second latch unit includes an M-bit shift register and is a serial input.

7. The data error correction circuit as described in claim 5, characterized in that, The second latch unit includes S K-bit shift registers, S K=M, the second latch unit is a parallel input, and S≥1.

8. The data error correction circuit as described in any one of claims 2 to 7, characterized in that, The first latch unit is connected to the first control unit, and the second latch unit is connected to the second control unit. The first control unit is used to control the first latch unit to start latching at a time point n+mt, where n is the relative delay time, the starting point of the relative delay time is the time it takes for the first data to be transmitted to the decoding module, m is a natural number, t is the transmission interval of the first data, and n is greater than 0 and less than t. The second control unit is used to control the second latch unit to start latching between n+mt and n+(m+1)t.

9. The data error correction circuit as described in claim 4 or 5, characterized in that, The error corrector includes an inverter and a transmission tube connected in parallel. The input terminals of the inverter and the transmission tube are connected as the input terminals of the error corrector, and the output terminals of the inverter and the transmission tube are connected as the output terminals of the error corrector. The enable terminals of the inverter and the transmission tube are both connected to the output terminals of the decoding module.

10. The data error correction circuit as described in claim 2, characterized in that, The first latch unit is a serial input or a parallel input.

11. The data error correction circuit as described in claim 2 or 10, characterized in that, The second latch unit is either a serial output or a parallel output.

12. The data error correction circuit as described in claim 8, characterized in that, The input terminal of the second control unit is connected to the output terminal of the first control unit.

13. A data transmission circuit, characterized in that, include: Odd data signal line, used to transmit odd data; An even data signal line is used to transmit even data, wherein even data and odd data are transmitted alternately at intervals, and there is a first time interval between the arrival time of even data and the arrival time of odd data. The data error correction circuit as described in any one of claims 1 to 12 has an input terminal connected to the odd data signal line and the even data signal line, and an output terminal connected to an output bus, wherein the output bus is electrically connected to a storage block. The data error correction circuit is used to correct the odd data or the even data when the odd data or the even data is written to the storage block.

14. The data transmission circuit as described in claim 13, characterized in that, The data error correction circuit includes a decoding module and an error correction latch module. The odd data or the even data enters the decoding module at a first time point, and the error correction latch module outputs the corrected data at a second time point. The interval between the first time point and the second time point is greater than the first time interval.

15. A data transmission circuit, characterized in that, include: A first data signal line is used to transmit odd data and even data, wherein the even data and the odd data are transmitted alternately at intervals, and there is a first time interval between the arrival time of the even data and the arrival time of the odd data. The data error correction circuit as described in any one of claims 1 to 12 has an input terminal connected to the odd data signal line and the even data signal line, and an output terminal connected to an output bus, wherein the output bus is electrically connected to a storage block. The data error correction circuit is used to correct the odd data or the even data when the odd data or the even data is written to the storage block.

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