Test method, device, electronic equipment, storage medium and computer program

Abstract

Embodiments of the present application provide a test method, device, electronic equipment, storage medium and computer program, the method comprising: writing a first value to all second bits in a redundancy array; repairing corresponding first bits in a main array through the second bits of the redundancy array by using a target mapping relationship to be verified, the mapping relationship comprising a repair relationship between the addresses of the second bits and the addresses of the corresponding first bits; writing a second value to all first bits in the main array, the first value being different from the second value; determining whether the values in the second bits are the first value, if not, taking the second bits as actual repair bits, and recording the addresses of the actual repair bits; and determining whether the target mapping relationship is correct according to the preset mapping relationship and the addresses of the actual repair bits. Embodiments of the present application can effectively verify the target mapping relationship through the repair of the main array and the simple read-write process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a testing method, apparatus, electronic device, storage medium, and computer program. Background Technology

[0002] DRAM (dynamic random access memory) is a common type of memory. DRAM consists of a main array and a redundant array. The main array is used to store data, and the redundant array is used to repair the main array.

[0003] The main array consists of several rows and columns of bits, with each bit storing one bit of data. During DRAM use, some bits in the main array may fail. Failed bits can no longer store data and are called fail bits (FB). To repair fail bits in the main array, a mapping relationship (fuse mapping) needs to be generated based on the fail bits and preset repair rules. This mapping relationship describes the correspondence between fail bits and redundant bits in the redundant array used to repair them. Therefore, according to this mapping relationship, data that would have been stored in the fail bits can be moved to the corresponding redundant bits. It can be seen that the accuracy of this mapping relationship determines the success of the main array repair.

[0004] However, no effective scheme for verifying this mapping relationship is provided in the existing technology. Summary of the Invention

[0005] This application provides a testing method, apparatus, electronic device, storage medium, and computer program to provide an effective solution for verifying the mapping relationship.

[0006] On one hand, embodiments of this application provide a testing method applied to a target circuit comprising a main array and a redundant array, wherein the main array includes one or more first bits, and the redundant array includes one or more second bits; the method includes:

[0007] Write the first value to all the second bits in the redundant array;

[0008] The target mapping relationship to be verified is used to repair the corresponding first bit in the main array through the second bit of the redundant array. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit.

[0009] Write a second value to all first bits in the main array, where the first value is different from the second value.

[0010] Determine whether the value in the second bit is the first value. If not, use the second bit as the actual repair bit and record the address of the actual repair bit.

[0011] The correctness of the target mapping relationship is determined based on the preset mapping relationship and the address of the actual repair bit.

[0012] Optionally, determining whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repaired bit includes:

[0013] Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship;

[0014] If the address of the actual repair bit is inconsistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be incorrect.

[0015] Optionally, determining whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repaired bit includes:

[0016] Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship;

[0017] If the address of the actual repair bit is consistent with the address of the corresponding preset second bit, then the target mapping relationship is determined to be correct.

[0018] Optionally, after determining that the target mapping relationship is incorrect, the method further includes:

[0019] Output a prompt message, which includes the address of the actual repair bit, to indicate that the actual repair bit is in an incorrect correspondence in the target mapping relationship.

[0020] Optionally, the prompt message may also include the address of the preset second bit, to prompt that the address of the actual repair bit in the target mapping relationship be modified to the address of the preset second bit.

[0021] Optionally, before writing the second value to all first bits in the main array, the method further includes:

[0022] Disable write and / or read permissions for the redundant array.

[0023] Optionally, the method further includes:

[0024] The circuit that has not been repaired is selected from multiple circuits as the target circuit.

[0025] Optionally, before writing the first value to all the second bits in the redundant array, the method further includes:

[0026] Enable the test mode for the redundant array, which is used to write to and / or read from the redundant array.

[0027] Optionally, determining whether the value in the second bit is the first value, and if not, using the second bit as the actual repair bit, includes:

[0028] The access interface of the test mode is invoked to read the first value from each second bit of the redundant array and obtain the reading result;

[0029] The second bit in the read result indicating a read failure is taken as the actual repair bit.

[0030] Optionally, the target circuit is a dynamic random access memory (DRAM) circuit.

[0031] Optionally, the first value and the second value are two different values ​​of binary bits.

[0032] On the other hand, embodiments of this application provide a testing apparatus applied to a target circuit comprising a main array and a redundant array, wherein the main array includes one or more first bits, and the redundant array includes one or more second bits; the apparatus includes:

[0033] The first writing module is used to write a first value to all the second bits in the redundant array;

[0034] A mapping relationship establishment module is used to repair the corresponding first bit in the main array through the second bit of the redundant array using the target mapping relationship to be verified. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit.

[0035] The second writing module is used to write a second value to all the first bits in the main array, wherein the first value is different from the second value.

[0036] The actual repair bit recording module is used to determine whether the value in the second bit is the first value. If not, the second bit is used as the actual repair bit, and the address of the actual repair bit is recorded.

[0037] The testing module is used to determine whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repair bit.

[0038] Optionally, the above testing module is also used for:

[0039] Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship;

[0040] If the address of the actual repair bit is inconsistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be incorrect.

[0041] Optionally, the above testing module is also used for:

[0042] Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship;

[0043] If the address of the actual repair bit is consistent with the address of the corresponding preset second bit, then the target mapping relationship is determined to be correct.

[0044] Optionally, the device further includes:

[0045] The prompting module is used to output prompting information after the target mapping relationship is determined to be incorrect. The prompting information includes the address of the actual repair bit, so as to indicate that the actual repair bit is in an incorrect correspondence in the target mapping relationship.

[0046] Optionally, the prompt message may also include the address of the preset second bit, to prompt that the address of the actual repair bit in the target mapping relationship be modified to the address of the preset second bit.

[0047] Optionally, the above-mentioned device further includes:

[0048] The redundant array shutdown module is used to disable the write and / or read permissions of the redundant array before writing the second value to all first bits in the main array.

[0049] Optionally, the device further includes:

[0050] The target circuit selection module is used to select an unrepaired circuit from a plurality of circuits as the target circuit.

[0051] Optionally, the above-mentioned device further includes:

[0052] The test module is enabled to activate the test mode of the redundant array before writing the first value to all the second bits in the redundant array. The test mode is used to write to and / or read from the redundant array.

[0053] Optionally, the actual repair bit recording module is further used for:

[0054] The access interface of the test mode is invoked to read the first value from each second bit of the redundant array and obtain the reading result;

[0055] The second bit in the read result indicating a read failure is taken as the actual repair bit.

[0056] Optionally, the target circuit is a dynamic random access memory (DRAM) circuit.

[0057] Optionally, the first value and the second value are two different values ​​of binary bits.

[0058] The testing method, apparatus, electronic device, storage medium, and computer program provided in this application can write a first value to all second bits in a redundant array; use the target mapping relationship to be verified to repair the corresponding first bit in the main array through the second bits of the redundant array, the mapping relationship including the repair relationship between the address of the second bit and the address of the corresponding first bit; write a second value to all first bits in the main array, the first value being different from the second value; determine whether the value in the second bit is the first value; if not, use the second bit as the actual repair bit and record the address of the actual repair bit; determine whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repair bit. This application embodiment can effectively verify the target mapping relationship through the repair of the main array and a simple read / write process. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those of this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0060] Figure 1 This is a schematic diagram of the structure of the main array and redundant array provided in the embodiments of this application;

[0061] Figure 2 This is a flowchart of the steps of a testing method provided in an embodiment of this application;

[0062] Figure 3 This is a schematic diagram of the result after writing the first value into the second bit, as provided in an embodiment of this application;

[0063] Figure 4 This is a schematic diagram of the result after writing a second value into the first bit, as provided in an embodiment of this application;

[0064] Figure 5 This application provides an embodiment of the method from which to obtain the data. Figure 4 The diagram shows the reading results after reading the first value in the redundant array.

[0065] Figure 6 This is a schematic diagram of the structure of a testing device provided in an embodiment of this application.

[0066] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the embodiments of this application in any way, but rather to illustrate the concepts of the embodiments of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0067] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0068] As described in the background section, repairing the main array in a memory requires a mapping relationship to describe the correspondence between a failed bit and a redundant bit in the redundant array used to repair the failed bit. However, the prior art does not provide an effective scheme for verifying the above mapping relationship.

[0069] To address the aforementioned technical problems, this application provides a testing method to verify the mapping relationship. In this application, to distinguish between the mapping relationship to be verified and the correct mapping relationship, the mapping relationship to be verified can be referred to as the target mapping relationship, and the correct mapping relationship can be referred to as the preset mapping relationship.

[0070] The embodiments of this application can be applied to target circuits that include a main array and a redundant array. The main array includes one or more first bits, and the redundant array includes one or more second bits. Here, the first and second bits are only used to distinguish the bits of the main array and the bits of the redundant array, and do not represent the numbering order.

[0071] The target circuit can be any unrepaired circuit; that is, the target circuit is one where the repair relationship between the main array and the redundant array has not been established. The value written to the memory is written to the first bit of the main array, not the second bit of the redundant array. This ensures that when verifying the correctness of the target mapping relationship through the target circuit, the repair relationship between the first bit of the main array and the second bit of the redundant array is established only through this target mapping relationship, thus guaranteeing the accuracy of the verification.

[0072] Optionally, the target circuit is a dynamic random access memory (DRAM) circuit.

[0073] The primary array typically includes M1 rows and N1 columns of first bits, each storing a one-bit value. Similarly, the redundant array typically includes M2 rows and N2 columns of second bits, each storing a one-bit value. The redundant array has fewer second bits (M2*N2) than the primary array has fewer first bits (M1*N1). It's understandable that a larger number of second bits in the redundant array allows for the repair of more first bits. This means that even when there are many faulty bits in the primary array's first bits, more faulty bits can be repaired, reducing the number of unrepairable faulty bits. Conversely, a smaller number of second bits in the redundant array allows for smaller memory sizes and ensures the repair of faulty bits even when there are fewer faulty bits in the primary array's first bits.

[0074] Figure 1 This is a schematic diagram of the main array and redundant array provided in the embodiments of this application. Referring to Figure 1, the main array MX1 includes an 8-row, 10-column first element B1, and the redundant array MX2 includes an 8-row, 8-column second element B2. The first element in the m-th row and n-th column of the main array can be denoted as B1(m, n), and the second element in the m-th row and n-th column of the redundant array can be denoted as B2(m, n).

[0075] The embodiments of this application can be implemented according to the target mapping relationship as described above. Figure 1 The redundant array shown repairs the main array, and the target mapping relationship used in the above repair process is verified by reading and writing the redundant array and the main array.

[0076] The process of verifying the target mapping relationship is explained in detail below. Figure 2 This is a flowchart illustrating the steps of a testing method provided in an embodiment of this application. Please refer to... Figure 2 The above methods include:

[0077] S101: Write the first value to all second bits in the redundant array.

[0078] The first value can be any binary value. Since each second bit in the redundant array is used to store a one-bit value, the first value can be any binary bit value, such as 0 or 1. Figure 3 This is a schematic diagram provided in an embodiment of this application after writing the first value into the second bit. Figure 3 The first value shown is 0. From Figure 3As can be seen, the 8x8 redundant array includes 64 second bits, each of which is written with the first value 0. Of course, if the first value is 1, Figure 3 All 64 second bits in the redundant array were written with 1.

[0079] In this embodiment, to accurately verify the target mapping relationship, it is sufficient to ensure that the same first value is written to all second bits, without concern for the specific value of the first value. In this embodiment, both the first and second bits are physical devices for storing data, also referred to as storage elements. The first and second bits are only used to distinguish whether a bit is in the main array or the redundant array, and do not represent its number.

[0080] It should be noted that S101 can be executed not only before S102, but also after S102, but S101 must be executed before S103. The embodiments of this application do not limit the order of execution.

[0081] When executing S101, it can be performed in test mode. This distinguishes test mode from normal read / write mode, ensuring the independence between read / write in test mode and read / write in normal mode, and avoiding mutual interference that could lead to lower test accuracy and / or read / write errors.

[0082] S102: The target mapping relationship to be verified is used to repair the corresponding first bit in the main array through the second bit of the redundant array. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit.

[0083] In this configuration, the address of a bit is used to uniquely represent a single bit. Different first bits in the main array have different addresses, and different second bits in the redundant array have different addresses. The address of the first bit in the main array is not the same as the address of any second bit in the redundant array. This ensures that when writing a value to a bit, the target bit can be accurately written according to the address, thus guaranteeing the accuracy of the written value and, consequently, the accuracy of the verification of the target mapping relationship in this embodiment.

[0084] Understandably, before the main array is repaired, no repair relationship is established between the first bit of the main array and the second bit of the redundant array. At this point, the value to be written to memory is written to the first bit. For example, ... Figure 1 As shown, no repair relationship is established between B1 in MX1 and B2 in MX2. Therefore, the value to be written to memory is written to the first cell B1 of the main array. Of course, the address of the first cell to be written needs to be specified.

[0085] The process of repairing the main array can be understood as establishing a repair relationship between the first and second bits based on the target mapping relationship. For example, if the target mapping relationship indicates that the second bit of the fourth column in MX2 repairs the first bit of the third column in MX1, then a repair relationship can be established according to this mapping relationship, such as... Figure 3 The repair relationship MP1 is shown. If B1(m, n) represents the first element in the m-th row and n-th column of the primary array, and B2(m, n) represents the second element in the m-th row and n-th column of the redundant array, then... Figure 3 The repair relationship in the code is actually used to instruct the following repairs to be performed: repair the first bit B1 (1,3) in the main array using the second bit B2 (1,3) in the redundant array; repair the first bit B1 (2,3) in the main array using the second bit B2 (2,3) in the redundant array; repair the first bit B1 (3,3) in the main array using the second bit B2 (3,3) in the redundant array; repair the first bit B1 (4,3) in the main array using the second bit B2 (4,3) in the redundant array; repair the first bit B1 (5,3) in the main array using the second bit B2 (5,3) in the redundant array; repair the first bit B1 (6,3) in the main array using the second bit B2 (6,3) in the redundant array; repair the first bit B1 (7,3) in the main array using the second bit B2 (7,3) in the redundant array; and repair the first bit B1 (8,3) in the main array using the second bit B2 (8,3) in the redundant array.

[0086] After establishing the repair relationship MP1, if a value needs to be written to the first element of the third column of MX1, that value is actually written to the second element of the fourth column of MX2, not to the first element of the third column of MX1. For example, as... Figure 3 As shown, the value that needs to be written into B1(1,3) is actually written into B2(1,3).

[0087] Of course, if a value needs to be written to the first element of columns one through two, or columns four through ten, then it can actually be written to the first element of those columns. For example, ... Figure 3 As shown, if a value needs to be written into B1(2,1), since no repair relationship has been established for B1(2,1), the value is actually written into B1(2,1).

[0088] S103: Write the second value to all first bits in the main array. The first value is different from the second value.

[0089] In this embodiment of the application, in order to accurately verify the target mapping relationship, it is only necessary to ensure that the first value written to the second bit is different from the second value written to the first bit, and the specific values ​​of the first and second values ​​are not important.

[0090] The second value is a different binary representation than the first value; that is, the first and second values ​​are two different values ​​for the binary bits. Specifically, when the first value is 0, the second value is 1, and when the first value is 1, the second value is 0.

[0091] Figure 4 This is a schematic diagram illustrating the result after writing a second value into the first bit, as provided in an embodiment of this application. Figure 4 The second value in the table is 1. (Refer to...) Figure 4 As shown, due to the influence of MP1, the second value 1 in the first bit of the third column of MX1, which was to be written to, is actually written to the second bit of the fourth column of MX2. Meanwhile, the second value 1 is written into the first bit of the remaining bits where the repair relationship with the second bit has not been established.

[0092] Optionally, before writing the second value to all first bits of the primary array, write and / or read permissions for the redundant array can be disabled. This prevents the first bit of the redundant array from being written with other values ​​by other write instructions while the second value is being written to it. In other words, it ensures that the second value is written to the redundant array only through the repair relationship between the first bit of the primary array and the second bit of the redundant array. During this process, the change in the value of the second bit of the redundant array is caused by this repair relationship, thus ensuring that subsequent verification verifies the changes introduced by this repair relationship. This avoids interference from external factors and guarantees the accuracy of the verification of the target mapping relationship.

[0093] It should be noted that S103 must be executed after S102, meaning the second value can only be written to the main array after the main array has been repaired (post-fuse). This ensures that the process of writing the second value to the main array, due to the aforementioned... Figure 4 The second value of the first bit originally written to the main array is actually written to the second bit of the redundant array due to the influence of the repair relationship. Therefore, the actual repair bit can be determined based on the value in the redundant array, and then the correctness of the target mapping relationship can be determined based on the actual repair bit.

[0094] S104: Determine whether the value in the second bit is the first value. If not, use the second bit as the actual repair bit and record the address of the actual repair bit.

[0095] Specifically, after S103, the redundancy matrix can be read first to obtain the value of each second bit in the redundancy matrix, and then it can be determined whether the value of each second bit is the first value. If the value in a second bit is not the first value, then the second bit can be identified as the actual repair bit, that is, the second bit actually used when repairing the first bit of the main array using the target mapping relationship. Of course, if the value in this second bit is the first value, then it can be determined that this second bit is an unrepaired bit, that is, the first bit was not repaired using this second bit.

[0096] It should be noted that, assuming the target mapping is correct, the unrepaired bits here only include the second bit that does not require repair of the first bit. However, if the target mapping is incorrect, the unrepaired bits here may also include the expected bit that requires repair of the first bit.

[0097] For example, such as Figure 4 As shown, the value read from the second bit of the fourth column of the redundancy matrix is ​​not the first value 0, so the second bit of the fourth column is taken as the actual repair bit. Since the values ​​in the second bits outside the fourth column of the redundancy matrix are the first value 0, these second bits outside the fourth column are determined as unrepaired bits. If the target mapping relationship is incorrect, these unrepaired bits include not only the second bits of columns 1 to 3 and columns 6 to 8 that do not require repair of the first bit, but also the expected bit for repairing the first bit of column 3: the second bit of column 5.

[0098] Optionally, the above process can be performed in test mode, and the interface of test mode can be called. Specifically, first, the access interface of test mode is called to read the first value from each second bit of the redundant array, and the reading result is obtained, where the reading result can be either successful or unsuccessful. Then, the second bit with the reading result of unsuccessful is used as the actual repair bit.

[0099] The aforementioned access interface is provided by the test mode. When calling this interface, the target value to be read can be provided, which is the first value. Therefore, if the access interface reads the first value from the second bit, the output result will be "read successfully." If the access interface does not read the first value from the second bit, meaning the second value was read, the output result will be "read failed."

[0100] Reference Figure 4As shown, the data read by the access interface from the second bit of the fourth column of the redundant array is not the first value 0, thus the read result output for the second bit of the fourth column is read failure. The data read by the access interface from the second bit outside the fourth column of the redundant array is the first value 0, thus the read result output for the second bit outside the fourth column is read success. Figure 4 The read results of the redundant array shown can be Figure 5 As shown, from Figure 5 It can be seen that the reading results of the second bit of the fourth column of the redundant array are all failures (F), while the reading results of the second bit outside the fourth column are all successes (S).

[0101] The embodiments of this application can obtain the actual repair bits through existing access interfaces, which can reduce the amount of development work and improve development efficiency.

[0102] S105: Determine whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repair bit.

[0103] The preset mapping is the correct mapping, while the target mapping is the mapping to be verified, which is the mapping we actually use. The target mapping is correct when it matches the preset mapping. It is incorrect when the target mapping differs from the preset mapping.

[0104] In practical applications, designers can determine a repair scheme based on the failed bits and repair rules, and design a preset mapping relationship based on the repair scheme, in order to repair the failed bits of the main array through the preset mapping relationship.

[0105] However, due to various reasons, such as errors in the program's configuration files or the designed mapping relationships, the repair fails. In other words, the target mapping relationship used for repair is not the default mapping relationship we expect, resulting in a repair result that is not what we anticipated.

[0106] Specifically, the process of determining whether the target mapping relationship is correct may include the following steps:

[0107] First, based on the address of the first bit repaired by the actual repair bit, the address of the corresponding preset second bit is found in the preset mapping relationship. Since the preset mapping relationship is correct, the preset second bit is the expected bit of the first bit repaired by the actual repair bit. For example, the preset mapping relationship indicates that the first bit of the third column of the main array is repaired through the second bit of the fifth column of the redundant array, but the target mapping relationship indicates that the first bit of the third column of the main array is repaired through the second bit of the fourth column. In this case, the actual repair bit determined by S104 is the second bit of the fourth column of the redundant array. Therefore, based on the target mapping relationship, it can be determined that the first bit repaired by the actual repair bit is the first bit of the third column of the main array. Furthermore, based on the preset mapping relationship, it can be determined that the preset second bit corresponding to the first bit of the third column of the main array is the second bit of the seventh column of the redundant array.

[0108] Then, it is determined whether the address of the actual repair bit is consistent with the address of the preset second bit. If the address of the actual repair bit is inconsistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be incorrect; if the address of the actual repair bit is consistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be correct.

[0109] The embodiments of this application can determine whether the target mapping relationship is correct based on the preset mapping relationship, which helps to ensure the accuracy of the test.

[0110] Optionally, after determining that the target mapping relationship is incorrect, a prompt message can be output. This prompt message may include the address of the actual repair bit mentioned above, to indicate that the correspondence of the actual repair bit in the target mapping relationship is incorrect. This embodiment of the application can use this prompt message to indicate which correspondence is incorrect, avoiding the need for developers to locate the erroneous correspondence, reducing the workload of developers, saving the time required for developers to find the erroneous correspondence, and improving the efficiency of developers in correcting the target mapping relationship.

[0111] Of course, the above prompts may also include the address of the preset second bit, so as to prompt that the address of the actual repair bit in the target mapping relationship be modified to the address of the preset second bit.

[0112] The embodiments of this application can further assist developers in correcting erroneous target mapping relationships through the above-mentioned prompt information, thereby further improving the efficiency of developers in correcting target mapping relationships.

[0113] Optionally, the target circuit used in the embodiments of this application may be a circuit that has not been repaired. In order to determine the target circuit, before performing S101, multiple circuits may be read and written separately through functional test items to obtain the test results of each circuit. The test results may include at least one of the following: whether the main array of the circuit has been repaired.

[0114] The multiple circuits can be any type of circuit. When performing read / write tests on multiple circuits, a first value can be written to the redundant array first, and then a second value can be written to the circuit, which is to say, a second value is written to the main array. Finally, the value is read from the redundant array of the circuit. If the second value exists in the redundant array, it can be determined that the main array of the circuit has been repaired. If the second value does not exist in the redundant array, it can be determined that the main array of the circuit has not been repaired.

[0115] In addition, the test results of the above read / write tests may also include whether the read / write functions are normal. Whether the read / write functions are normal here includes whether the main array's read / write functions are normal and whether the redundant array's read / write functions are normal. When both the main array and the redundant array's read / write functions are normal, it indicates that the circuit's read / write functions are normal. When the main array and / or the redundant array's read / write functions are abnormal, it indicates that the circuit's read / write functions are abnormal.

[0116] Based on the above test results, this embodiment of the application can select a circuit that has not been repaired and has normal read / write functions from multiple circuits as the target circuit. In this way, on the one hand, it can be ensured that the repair of the main array of the target circuit is performed through the target mapping relationship to be verified, thereby improving the accuracy of the verification of the target mapping relationship. On the other hand, it can also ensure the smooth execution of S101, S103, and S104, thereby ensuring the smooth verification of the target mapping relationship.

[0117] Optionally, the testing method provided in this application embodiment can be performed in a test mode. That is, before writing the first value to all second bits in the redundant array, a test mode for the redundant array is activated. This test mode is used to write to and / or read from the redundant array. Therefore, steps S101 to S104 are all performed under this test mode. In other words, the first value is written to all second bits in the redundant array through the test mode, and the second value is written to all first bits in the main array through the test mode.

[0118] The embodiments of this application can implement the above tests using a test model to avoid affecting the normal use of the target circuit.

[0119] In summary, the testing method provided in this application embodiment can verify the target mapping relationship through only repair and simple read / write processes, and the verification method has low complexity.

[0120] Corresponding to the above method embodiments, Figure 6 This is a schematic diagram of a testing device provided in an embodiment of this application. Please refer to... Figure 6 The aforementioned testing device 200 includes: a first writing module 201, a mapping relationship establishment module 202, a second writing module 203, an actual repair bit recording module 204, and a testing module 205.

[0121] The first writing module 201 is used to write a first value to all the second bits in the redundant array.

[0122] The mapping relationship establishment module 202 is used to repair the corresponding first bit in the main array through the second bit of the redundant array using the target mapping relationship to be verified. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit.

[0123] The second writing module 203 is used to write a second value to all the first bits in the main array, wherein the first value is different from the second value.

[0124] The actual repair bit recording module 204 is used to determine whether the value in the second bit is the first value. If not, the second bit is used as the actual repair bit, and the address of the actual repair bit is recorded.

[0125] The test module 205 is used to determine whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repair bit.

[0126] Optionally, the above-mentioned test module 205 is also used for:

[0127] Based on the address of the first bit repaired by the actual repaired bit, the address of the corresponding preset second bit is found in the preset mapping relationship.

[0128] If the address of the actual repair bit is inconsistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be incorrect.

[0129] Optionally, the above-mentioned test module 205 is also used for:

[0130] Based on the address of the first bit repaired by the actual repaired bit, the address of the corresponding preset second bit is found in the preset mapping relationship.

[0131] If the address of the actual repair bit is consistent with the address of the corresponding preset second bit, then the target mapping relationship is determined to be correct.

[0132] Optionally, the device further includes:

[0133] The prompting module is used to output prompting information after the target mapping relationship is determined to be incorrect. The prompting information includes the address of the actual repair bit, so as to indicate that the actual repair bit is in an incorrect correspondence in the target mapping relationship.

[0134] Optionally, the prompt message may also include the address of the preset second bit, to prompt that the address of the actual repair bit in the target mapping relationship be modified to the address of the preset second bit.

[0135] Optionally, the above-mentioned device further includes:

[0136] The redundant array shutdown module is used to disable the write and / or read permissions of the redundant array before writing the second value to all first bits in the main array.

[0137] Optionally, the device further includes:

[0138] The target circuit selection module is used to select an unrepaired circuit from a plurality of circuits as the target circuit.

[0139] Optionally, the above-mentioned device further includes:

[0140] The test module is enabled to activate the test mode of the redundant array before writing the first value to all the second bits in the redundant array. The test mode is used to write to and / or read from the redundant array.

[0141] Optionally, the actual repair bit recording module 204 is further configured to:

[0142] The access interface of the test mode is invoked to read the first value from each second bit of the redundant array, and the reading result is obtained.

[0143] The second bit in the read result indicating a read failure is taken as the actual repair bit.

[0144] Optionally, the target circuit is a dynamic random access memory (DRAM) circuit.

[0145] Optionally, the first value and the second value are two different values ​​of binary bits.

[0146] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0147] This application also provides an electronic device, which includes at least one processor and a memory.

[0148] The memory stores computer-executed instructions.

[0149] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described above.

[0150] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause a computing device to implement the method described above.

[0151] This application also provides a computer program for implementing the method described above.

[0152] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0153] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0154] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A test method applied to a target circuit comprising a main array and a redundant array, wherein the main array includes one or more first bits, and the redundant array includes one or more second bits; characterized in that, The method includes: Write the first value to all the second bits in the redundant array; The target mapping relationship to be verified is used to repair the corresponding first bit in the main array through the second bit of the redundant array. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit. The repair of the corresponding first bit in the main array refers to the process of establishing the repair relationship between the first bit and the second bit according to the target mapping relationship. Write a second value to all first bits in the main array, where the first value is different from the second value. Determine whether the value in the second bit is the first value. If not, use the second bit as the actual repair bit and record the address of the actual repair bit. The correctness of the target mapping relationship is determined based on the preset mapping relationship and the address of the actual repair bit. The method further includes: The circuit that has not been repaired is selected from multiple circuits as the target circuit.

2. The method according to claim 1, characterized in that, The step of determining whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repaired bits includes: Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship; If the address of the actual repair bit is inconsistent with the address of the corresponding preset second bit, the target mapping relationship is determined to be incorrect.

3. The method according to claim 1, characterized in that, The step of determining whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repaired bits includes: Based on the address of the first bit repaired by the actual repaired bit, find the address of the corresponding preset second bit in the preset mapping relationship; If the address of the actual repair bit is consistent with the address of the corresponding preset second bit, then the target mapping relationship is determined to be correct.

4. The method according to claim 2, characterized in that, After determining that the target mapping relationship is incorrect, the method further includes: Output a prompt message, which includes the address of the actual repair bit, to indicate that the actual repair bit is in an incorrect correspondence in the target mapping relationship.

5. The method according to claim 4, characterized in that, The prompt message also includes the address of the preset second bit, to prompt that the address of the actual repair bit in the target mapping relationship be modified to the address of the preset second bit.

6. The method according to any one of claims 1 to 5, characterized in that, Before writing the second value to all the first bits in the main array, the process also includes: Disable write and / or read permissions for the redundant array.

7. The method according to any one of claims 1 to 5, characterized in that, Before writing the first value to all the second bits in the redundant array, the method further includes: Enable the test mode for the redundant array, which is used to write to and / or read from the redundant array.

8. The method according to claim 7, characterized in that, The step of determining whether the value in the second bit is the first value, and if not, using the second bit as the actual repair bit, includes: The access interface of the test mode is invoked to read the first value from each second bit of the redundant array and obtain the reading result; The second bit in the read result indicating a read failure is taken as the actual repair bit.

9. The method according to any one of claims 1 to 5, characterized in that, The target circuit is a dynamic random access memory circuit.

10. The method according to any one of claims 1 to 5, characterized in that, The first value and the second value are two different values ​​of binary bits.

11. A testing apparatus applied to a target circuit comprising a main array and a redundant array, the main array comprising one or more first bits, and the redundant array comprising one or more second bits; characterized in that, The device includes: The first writing module is used to write a first value to all the second bits in the redundant array; The mapping relationship establishment module is used to repair the corresponding first bit in the main array through the second bit of the redundant array using the target mapping relationship to be verified. The mapping relationship includes the repair relationship between the address of the second bit and the address of the corresponding first bit. The repair of the corresponding first bit in the main array refers to the process of establishing the repair relationship between the first bit and the second bit according to the target mapping relationship. The second writing module is used to write a second value to all the first bits in the main array, wherein the first value is different from the second value. The actual repair bit recording module is used to determine whether the value in the second bit is the first value. If not, the second bit is used as the actual repair bit, and the address of the actual repair bit is recorded. The testing module is used to determine whether the target mapping relationship is correct based on the preset mapping relationship and the address of the actual repair bit; The target circuit selection module is used to select an unrepaired circuit from a plurality of circuits as the target circuit.

12. An electronic device, characterized in that, The electronic device includes: at least one processor and a memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, cause a computing device to implement the method as described in any one of claims 1 to 10.

14. A computer program, characterized in that, The computer program is used to implement the method as described in any one of claims 1 to 10.

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