Memory devices and their operation methods

Abstract

This disclosure provides a memory device and a method of operating the same, the method comprising: selecting a target block; reading the target block column by column; transmitting the read data to an error correction circuit; and checking and correcting the read data to generate corrected data.

Description

Technical Field

[0001] This disclosure relates to a storage block, a memory device, and a method of operating the same. Background Technology

[0002] In-memory search (IMS) technology is widely used in fields such as artificial intelligence, big data, and IP search. However, data stored in memory may contain errors for various reasons. When stored data contains errors, the reliability of search results is affected. Therefore, to ensure the reliability of search results, it is necessary to address the problem of errors in the data stored in the in-memory search array. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device including multiple memory blocks, multiple drive circuits, an error correction circuit, and a control circuit. Each memory block includes multiple memory cells. The drive circuits are coupled to these memory blocks. The error correction circuits are coupled to the memory blocks. The control circuit is coupled to the drive circuits and the error correction circuits for selecting one of the memory blocks as a target block and performing an error correction operation on the target block. The memory cells of the target block have multiple rows and multiple columns. These rows include at least one data row and at least one check row. The data stored in the memory cells of the data rows is user data. The data stored in the memory cells of the check rows is a check code. The check code stored in the memory cells of each column is generated based on the user data stored in the memory cells of the same column. The error correction operation includes reading the memory cells of the target block column by column and transmitting the data stored in the memory cells of the target block to the error correction circuit. The error correction circuit checks whether there are any error bits in the user data stored in each column of storage cells based on the check codes stored in each column of storage cells, and corrects them to generate corrected data corresponding to the data stored in each column of storage cells.

[0004] Another embodiment of this disclosure provides a method for operating a memory device, comprising: selecting one of a plurality of memory blocks as a target block to perform an error correction operation, the target block comprising a plurality of memory cells having multiple rows and multiple columns, the rows comprising at least one data row and at least one check row, the memory cells of the data rows storing user data, the memory cells of the check rows storing check codes, and the check codes stored in the memory cells of each column being generated based on the user data stored in the memory cells of the same column; reading the memory cells of the columns of the target block column by column; transmitting the data stored in the memory cells of the columns of the target block to an error correction circuit; and the error correction circuit checking whether there are error bits in the user data stored in the memory cells of each column based on the check codes stored in the memory cells of each column and correcting them to generate corrected data corresponding to the data stored in the memory cells of each column.

[0005] Another embodiment of this disclosure provides a storage block including multiple storage cells. These storage cells have multiple rows and multiple columns. The storage cells in the columns are coupled to a first driving circuit via multiple first signal lines. The storage cells in the rows are coupled to a second driving circuit via multiple second signal lines and to a sensing circuit via multiple third signal lines. The storage cells are also coupled to an error correction circuit. The rows include at least one data row and at least one check row. The data stored in the storage cells of the data rows is user data. The data stored in the storage cells of the check rows is a check code. The check code stored in the storage cells of each column is generated based on the user data stored in the storage cells of the same column. Attached Figure Description

[0006] Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure;

[0007] Figure 2 This is a schematic diagram of a storage block according to an embodiment of the present disclosure;

[0008] Figure 3 This is a flowchart of an operation method of a memory device according to an embodiment of the present disclosure;

[0009] Figure 4 This is a diagram illustrating the data set stored in a storage block.

[0010] Figures 5A-5D A diagram illustrating the process of reading data from storage blocks line by line for inspection and correction;

[0011] Figure 6 A diagram illustrating how to program the corrected data set, after inspection and correction, into another storage block;

[0012] Figure 7This is a schematic diagram of the operation of an error correction circuit according to an embodiment of the present disclosure;

[0013] Figure 8 The present disclosure describes the operation flow of a memory device according to an embodiment of the present disclosure.

[0014] Explanation of reference numerals in the attached figures

[0015] 10: Memory devices

[0016] 102: First driving circuit

[0017] 104: Second drive circuit

[0018] 106: Sensing Circuit

[0019] 108-1~108-3: Storage Blocks

[0020] 110: Error correction circuit

[0021] 112: Control Circuit

[0022] SL1~SLm: First signal lines

[0023] BL1~BLn: Second signal lines

[0024] ML1~MLn: Third signal lines

[0025] U1-1~Um-n: Storage unit

[0026] S301~S307, S801~S807: Steps

[0027] 400, 500, 620: Data sets

[0028] 700: Column data read

[0029] 710: Logic

[0030] 720: Correction Data

[0031] 730~760: Inspection Unit

[0032] 770: Computing Unit Detailed Implementation

[0033] Please refer to Figure 1 , Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure. The memory device 10 includes a first driving circuit 102, a second driving circuit 104, a sensing circuit 106, a plurality of memory blocks 108-1 to 108-2, an error correction circuit 110, and a control circuit 112. It should be noted that... Figure 1The arrangement of storage blocks 108-1 to 108-3 and the positions of each circuit block are configured for the purpose of clearly indicating the connection relationship, and are not intended to limit this disclosure, and may differ from the actual configuration. In addition, this disclosure does not limit the number of storage blocks.

[0034] Each storage block 108-1 to 108-3 is coupled to a first driving circuit 102 via multiple first signal lines, to a second driving circuit 104 via multiple second signal lines, and to a sensing circuit 106 via multiple third signal lines. In one embodiment, the first signal lines are word lines or search lines, the second signal lines are bit lines, and the third signal lines are match lines. The first driving circuit 102 can be a word line driving circuit, and the second driving circuit 104 can be a bit line driving circuit.

[0035] Please refer to Figure 2 This is a schematic diagram of a memory block according to an embodiment of the present disclosure. Since memory blocks 108-1 to 108-3 have similar structures, Figure 2 Only storage block 108-1 is shown. Storage block 108-1 may include multiple storage cells U1-1 to Um-n. Storage cells U1-1 to Um-n may be resistive storage elements, ferroelectric transistors, and floating-gate transistors, etc. These storage cells U1-1 to Um-n form an in-memory search array (IMS array). Storage cells U1-1 to Um-n are configured with m columns and n rows, where m and n are positive integers. The i-th column storage cell is coupled to the first driving circuit 102 through the first signal line SL1, where i = 1, 2, ..., m. The j-th row storage cell is coupled to the second driving circuit 104 through the second signal line BLj and to the sensing circuit 106 through the third signal line MLj, where j = 1, 2, ..., n.

[0036] The memory cells U1-1 to Um-n can be programmed into one of two different states. Taking the floating gate transistor as an example, the state is determined by the threshold voltage. The two different states are high threshold voltage and low threshold voltage. The low threshold voltage can represent one of 0 and 1, and the high threshold voltage can represent the other of 0 and 1.

[0037] In one embodiment, a storage unit is configured as a storage cell. Depending on the state of the storage unit, a storage cell can store data representing 0 or 1. This architecture is called content-addressable memory (CAM).

[0038] In another embodiment, two storage units are configured into one storage cell. For example, storage units U1-1 and U2-1 may be configured as one storage cell, storage units U1-2 and U2-2 may be configured as another storage cell, and so on. Based on the state combination of the two storage units, a storage cell can store data representing 0, 1, or any (don't care) value. This architecture is called ternary content addressable memory (TCAM).

[0039] It should be noted that in some embodiments, taking a TCAM that stores feature values ​​of multiple images as an example, the data stored in a storage cell may represent a single bit of the feature value of an image, while the data stored in a single storage unit has no specific meaning. However, the correctness of the data is unrelated to the specific meaning it represents. As long as the data stored in each storage unit is correct, the data stored in the storage cell composed of storage units will also be correct. In other words, if the data stored in each column of storage units is correct, the data stored in each row of storage units will also be correct. Therefore, the data described below refers to the data stored in storage units.

[0040] Error correction circuit 110 is coupled to storage blocks 108-1 to 108-3. Details about error correction circuit 110 will be described below.

[0041] The control circuit 112 is coupled to the first drive circuit 102, the second drive circuit 104, the sensing circuit 106, and the error correction circuit 110. The control circuit 112 is used to control the operation of the first drive circuit 102, the second drive circuit 104, the sensing circuit 106, and the error correction circuit 110 through signals.

[0042] The memory device 10 can perform operations including basic CAM and TCAM operations such as programming, reading, erasing, and searching. Programming and erasing operations are implemented by the control circuit 112 controlling the first drive circuit 102 and the second drive circuit 104 to apply appropriate bias voltages to the first signal lines SL1-SLm and the second signal lines BL1-BLn, respectively. Reading and searching operations are implemented by the control circuit 112 controlling the first drive circuit 102 and the second drive circuit 104 to apply appropriate bias voltages to the first signal lines SL1-SLm and the second signal lines BL1-BLn, respectively, and controlling the sensing circuit 106 to detect the current flowing out of the third signal lines ML1-MLn. In the searching operation, the bias voltage applied by the first drive circuit 102 to the first signal lines SL1-SLm represents the data to be searched, and the sensing circuit 106 determines whether any row of memory cells stores data that matches the data to be searched based on the magnitude of the detected current flowing out of the third signal lines ML11-MLn. It is important to note that the specific implementation methods of programming, reading, erasing, and searching operations will vary depending on the type of memory device 10 (e.g., NOR type, NAND type), the type of memory cell (e.g., resistive storage element, ferroelectric transistor, floating gate transistor), and other factors. It is also important to note that while some memory blocks are undergoing searching operations, other memory blocks may be in an idle state or undergoing operations other than searching. An idle state refers to a memory block not undergoing programming, reading, erasing, searching, or error correction operations as described below.

[0043] The memory device 10 can further perform error correction operations.

[0044] Please refer to Figure 3 , Figure 3 A flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure is provided. This process is used to perform error checking and correction on data stored in a memory block.

[0045] In step S301, the control circuit 112 determines a target block from storage blocks 108-1 to 108-3. The control circuit 112 can select an idle block from storage blocks 108-1 to 108-3 as the target block. For example, assuming storage block 108-2 is performing a search operation, and storage blocks 108-1 and 108-3 are not performing any operations, the control circuit 112 can select storage block 108-1 as the target block. In one embodiment, the data set stored in storage block 108-1 is as follows... Figure 4 As shown.

[0046] Please refer to Figure 4 , Figure 4This is a schematic diagram of a data set stored in a storage block according to an embodiment of the present disclosure. Data set 400 is stored in storage cells of storage block 108-1. For example, the four columns of data counting from top to bottom are stored in four columns of storage cells in storage block 108-1 corresponding to the first signal lines SL1 to SL4, and the eleven rows of data counting from left to right are stored in eleven rows of storage cells in storage block 108-1 corresponding to the second signal lines BL1 to BL11. For example, the data 0011 in the first row from left to right is stored in storage cells U1-1 to U4-1 corresponding to the first signal line BL1, where storage cell U1-1 stores 0, storage cell U2-1 stores 0, storage cell U3-1 stores 1, and storage cell U4-1 stores 1. For ease of explanation, "storage cell corresponding to a specific signal line" will be described as "storage cell of a specific signal line". For example, storage units U1-1 to U1-n corresponding to the first signal line SL1 will be described as storage units U1-1 to U1-n on the first signal line SL1; storage units U1-1 to Um-1 corresponding to the second signal line BL1 (or the third signal line ML1) will be described as storage units U1-1 to U1-n on the second signal line BL1 (or the third signal line ML1). In this embodiment, at least one row of storage units in storage block 108-1 is configured as a data row, and at least one row of storage units is configured as a check row. The data stored in the data row is user data, and the data stored in the check row is a check code. User data may include, for example, image feature values ​​and IP addresses. In dataset 400, counting from left to right, the first row contains user data 0011, the second row contains user data 1110, the third row contains user data 1111, the fourth row contains check code 1101, the fifth row contains user data 1001, the sixth row contains user data 0010, the seventh row contains user data 0110, the eighth row contains check code 0010, the ninth row contains user data 0101, the tenth row contains check code 1100, and the eleventh row contains check code 1001. The bits of the check code are represented by dots. That is, in storage block 108-1, the storage units on the first signal lines BL1-BL3, BL5-BL7, and BL9 are data rows, storing user data, while the storage units on the first signal lines BL4, BL8, BL10, and BL11 are check rows, storing check codes. The check code contained in each column of data is generated based on the user data in the same column. For example, in the first row of data counting from the top, the fourth, eighth, tenth, and eleventh bits are check codes. These check codes are generated based on the user data in the first, second, third, fifth, sixth, seventh, and ninth bits of the same first row.The algorithm used to generate the check code can be any well-known and applicable algorithm, such as Reed-Solomon code, parity check code, check sum, or cyclic redundancy code.

[0047] In step S303, the control circuit 112 determines whether error checking and correction should be triggered. If not, the process ends; if yes, S303 is executed. The control circuit 112 can determine whether to trigger error checking and correction for the target block based on parameters such as the number of reads, the number of searches, and the duration of the data (time elapsed since the previous programming). For example, when the number of reads, the number of searches, or the duration of the data exceeds the corresponding threshold, the control circuit 112 determines that error checking and correction for the target block should be triggered.

[0048] In step S304, the control circuit 112 commands the first drive circuit 102 and the second drive circuit 104 to apply a read bias voltage to the target block (storage block 108-1) to read the data stored in the storage cells of each column in the target block column by column, and transmit the data stored in the storage cells of each column to the error correction circuit 110.

[0049] In step S305, the error correction circuit 110 determines whether there are any error bits in the data read from the storage cells of each column. If yes, proceed to step S306; otherwise, end the process.

[0050] In step S306, the error correction circuit 110 determines whether the error bit can be corrected. If yes, proceed to step S307; otherwise, end the process. Every error correction code has a correction rate. When the number of error bits exceeds the upper limit of the number of error bits that the error correction code can correct, it cannot be corrected even if the existence of error bits is known.

[0051] In S307, the error correction circuit 110 corrects the error bits in the data read from the storage cells of each column and generates (outputs) corrected data.

[0052] Please refer to Figures 5A-5D , Figures 5A-5D This is a schematic diagram illustrating the process of reading data from the target block column by column and sending it to the error correction circuit for inspection and correction. Figures 5A-5D The displayed data set 500 is because... Figure 4 The displayed data set 400 is formed due to an error bit. In this embodiment, the data stored in storage unit U2-3 is incorrect, that is, data bit 502 in data set 500 is actually an error bit. This bit is 1 in data set 400, but 0 (error) in data set 500.

[0053] exist Figure 5A In the first driving circuit 102, a read voltage Vread is applied to the first signal line SL1, and a pass voltage Vpass is applied to the other first signal lines SL2 to SLm to read the data 510, i.e., 01111000011, stored in the memory cells U1-1 to U1-11 on the first signal line SL1. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 530 indicating that 01111000011 has no error bits.

[0054] exist Figure 5B In the first driving circuit, a read voltage Vread is applied to the first signal line SL2, and a pass voltage Vpass is applied to other first signal lines SL1, SL3 to SLm to read the data 540, i.e., 01010010110, stored in the memory cells U2-1 to U2-11 on the first signal line SL2. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 finds that the third bit from the left in 01010010110 is an error bit. Then, the error correction circuit 106 corrects the error bit from 0 to 1 and outputs the corrected data 550, i.e., 01110010110.

[0055] exist Figure 5C In the first driving circuit, a read voltage Vread is applied to the first signal line SL3, and a pass voltage Vpass is applied to other first signal lines SL1-SL2 and SL4-SLm to read the data 560, i.e., 11100111000, stored in the memory cells U3-1 to U3-11 on the first signal line SL3. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 570 that 11100111000 has no error bits.

[0056] exist Figure 5D In the first driving circuit, a read voltage Vread is applied to the first signal line SL4, and a pass voltage Vpass is applied to other first signal lines SL1-SL3 and SL5-SLm to read the data 580, i.e., 10111000101, stored in the memory cells U4-1 to U4-11 on the first signal line SL4. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 590 that 10111000101 has no error bits.

[0057] In one embodiment, after obtaining a check result indicating no error bits, the error correction circuit 110 can output a signal representing "no error" to the control circuit 112. Upon receiving the "no error" signal, the control circuit will not modify the data stored in the memory cells of the column in memory block 108-1 where no error bits have appeared. For example, in Figures 5A-5D In this example, the control unit 1112 does not modify the data stored in the memory cells on the first signal lines SL1, SL3-SL4. On the other hand, the error correction circuit 110 can output corrective data corresponding to the data stored in the memory cell of the column where the error was detected to the control circuit 112. The control circuit 112 can then program the memory cell of the first signal line where the error occurred based on the corrective data, thereby changing the erroneous data to correct data. Figures 5A-5D For example, in Figure 5B After the operation is executed, the error correction circuit 110 outputs the correction data 550, i.e., 01110010110, to the control circuit 112. The control circuit 112 commands the first drive circuit 102 and the second drive circuit 104 to apply programming bias voltages to the first signal lines SL1 to SLm and the second signal lines BL1 to BLn respectively, so as to program the memory cells U2-1 to U2-n, thereby changing the data stored in the memory cell U2-3 from 0 to 1.

[0058] In another embodiment, after obtaining a check result showing no error bits, the error correction circuit 110 can output the data that has been checked and found to be error-free as corrected data (the same as the read data). For example, in Figure 5A , 5C In the 5D example, after checking the read data 510, 560, and 580 and finding no errors, the error correction circuit 110 outputs the error-free data as corrected data 530, 570, and 590 (identical to the read data 510, 560, and 580). The control circuit 112 can receive the corrected data output by the error correction circuit 110 (including corrected data 530, 570, and 590 for data without detected errors, and corrected data 550 obtained after correction), and command the first drive circuit 102 and the second drive circuit 104 to apply a programming bias to another memory block to program these corrected data into another memory block. For example, since memory block 10-2 is performing a search operation and memory block 108-1 is performing an error correction operation, the control circuit 112 can program the corrected data obtained from the error correction operation in memory block 108-1 into memory block 108-3. Figure 6As shown, the data set 500 originally stored in storage block 108-1, after being checked and corrected by the error correction circuit 110, becomes a data set 620 consisting of corrected data corresponding to each column of data in data set 500. Data set 620 is then programmed into storage block 108-3. In this way, the data set originally stored in storage block 108-1 is considered to have been "moved" to storage block 108-3. That is, data set 620 stored in storage block 108-3 is considered the correct version of data set 500, and storage block 108-3 is used to replace storage block 108-1 for search operations.

[0059] Please refer to Figure 7 , Figure 7 This is a schematic diagram illustrating error correction according to an embodiment of the present disclosure. Data 700 is... Figure 5B The data read from the storage cell on the first signal line SL2, where bit b9 is an error bit. Logic 710 is an arithmetic block equivalent to an error correction circuit. Bits b1, b3, b5, b7, b9, and b11 are retrieved and sent to the checking unit 730 for even parity check, i.e., calculating whether the number of these bits that are 1 is even (if yes, the check result is 1; if no, the check result is 0), resulting in C1 = 1. Bits b2, b3, b6, b7, b10, and b11 are retrieved and sent to the checking unit 740 for even parity check, resulting in C2 = 0. Bits b4, b5, b6, and b7 are retrieved and sent to the checking unit 750 for even parity check, resulting in C3 = 0. Bits b8, b9, b10, and b11 are retrieved and sent to the checking unit 760 for even parity check, resulting in C4 = 1. Next, the outputs of the checking units 730-760 are sent to the calculation unit 770 to calculate N = 8*C4 + 4*C3 + 2*C2 + C1. If N is 0, it means there is no error; if N is not 0, it means the Nth bit from the least significant bit is an error bit. In this embodiment, the least significant bit is bit b1, and N is 9, which means the ninth bit b9 from bit b1 is an error bit. Therefore, the calculation unit 770 can change the ninth bit from 0 to 1 according to the result N of the calculation to obtain the corrected data 720 and output it.

[0060] Please refer to Figure 8 , Figure 8 The present disclosure describes the operation flow of a memory device according to an embodiment of the present disclosure.

[0061] In step S801, an error correction check (ECC check) is performed, checking column by column until the entire range has been checked. Here, the entire range refers to the storage units within a storage block that contain stored data. That is, storage units without stored data do not need to undergo error correction checks. For example, with… Figures 5A-5DFor example, storage block 108-1 actually has m columns of storage cells, but when performing error correction checks, only the four columns of storage cells containing stored data can be read, namely the storage cells on the first signal lines SL1 to SL4.

[0062] In step S802, it is determined whether an error bit has been detected. If yes, proceed to step S803; otherwise, proceed to step S806. Referring to the preceding text, step S802 can be executed by the error correction circuit 110.

[0063] In step S803, the memory cell corresponding to the first signal line containing the error bit detected in the error correction check is programmed to correct the data in the memory cell storing the error bit. The control circuit 112 can determine which memory cell of the first signal line to program based on the check result of the error correction circuit 110. This method is suitable for memory types that allow individual programming and erasing operations on single word lines.

[0064] In step S804, it is determined whether the memory cell storing the error bit can be reprogrammed. If yes, proceed to step S805; otherwise, proceed to step S805. The control circuit 112 can verify, after programming the memory cell corresponding to the first signal line containing the error bit detected in the error correction check according to the output of the error correction circuit 110, whether the data in the programmed memory cell is the same as the corrected data (correct data) to be programmed. The reason why the error bit stored in the memory cell cannot be changed by reprogramming may be that the memory cell is damaged.

[0065] In step S805, another row of storage cells (i.e., storage cells on another bit line / matching line) is used to store the correct version of the data. The reason why the erroneous bits stored in a storage cell cannot be corrected by reprogramming may be that the storage cell is damaged. Therefore, the control circuit 112 can select another bit line / matching line's storage cell to store the correct version of the user data corresponding to the unreprogrammable storage cell (i.e., the user data with the erroneous bits corrected). Figure 2 and Figure 5B For example, if storage cell U2-3 cannot be reprogrammed to store the correct data, control circuit 112 can program the correct version of the user data (i.e., 1111, not 1011) stored in storage cells U1-3 to U4-3 on the second signal line BL3 to storage cells U1-12 to U4-12 on the second signal line BL12.

[0066] In step S806, a search request is applied.

[0067] In step S807, it is determined whether the error correction check has been triggered. If yes, proceed to step S801; otherwise, proceed to step S806.

[0068] The process in this embodiment can be executed individually for each memory block in the memory device.

[0069] During a search operation, the check rows used to store check codes may not be searched, or the search results may not be output. In one embodiment, the control circuit 112 may command the second drive circuit not to apply a search bias to the second signal line corresponding to the check row when performing a search operation on the memory block. In another embodiment, the control circuit 112 may command the sensing circuit not to detect the current flowing from the third signal line corresponding to the check row when performing a search operation on the memory block. A specific implementation example is disabling a current sensing unit (e.g., a sensing amplifier) ​​in a sensing circuit used to detect the third signal line corresponding to the check row.

[0070] In one embodiment, the position and number of check rows are fixed. In another embodiment, the position and number of check rows are variable, for example, they can be dynamically configured by control circuitry 112.

[0071] On the other hand, this disclosure can be combined with an error correction mechanism for the input during the search to achieve better search result reliability. For example, an error correction circuit for the input data (the data to be searched) during the search can be configured in the first driving circuit to ensure that the search voltage applied to the storage block by the first driving circuit corresponds to the actual data to be searched.

[0072] This disclosure allows for error correction operations on storage blocks not used in search operations, thereby increasing the accuracy of the data sets stored in those blocks. This enables search operations to target the correct data sets, thus improving the reliability of search results.

[0073] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A memory device, comprising: Multiple storage blocks, each of which includes multiple storage units; Multiple drive circuits are coupled to these memory blocks; An error correction circuit is coupled to these memory blocks; as well as A control circuit, coupled to the drive circuits and the error correction circuit, is used to select one of the storage blocks as a target block and perform an error correction operation on the target block. The storage units of the target block have multiple rows and multiple columns. The rows include at least one data row and at least one check row. The data stored in the storage units of the at least one data row is user data, and the data stored in the storage units of the at least one check row is check code. The at least one check code stored in the storage units of each column is generated based on the user data stored in the storage units of the same column. The error correction operation includes reading the storage units of the columns of the target block column by column, transmitting the data stored in the storage units of the columns of the target block to the error correction circuit, and the error correction circuit checking whether there are error bits in the user data stored in the storage units of each column according to the at least one check code stored in the storage units of each column and correcting them to generate corrected data corresponding to the data stored in the storage units of each column. These driving circuits include a bit line driving circuit that, when performing a search operation on the target block, does not apply a search bias to at least one bit line corresponding to the at least one check row; or, when performing a search operation on the target block, the sensing circuit does not detect the current flowing out of at least one matching line corresponding to the at least one check row.

2. The memory device of claim 1, wherein the correction data of the data stored in these memory cells corresponding to each column of the target block is programmed into another memory block in these memory blocks.

3. The memory device of claim 1, wherein in the target block, the stored user data is checked for errors in the column of storage cells, and errors are found in those cells. The correction data is programmed based on the data stored in these storage cells corresponding to that column.

4. The memory device of claim 3, wherein for the memory cells of a row containing erroneous bits and whose stored data cannot be changed by programming, a correct version of the data stored in the memory cells of that row is programmed into the memory cells of another row in the target block.

5. A method of operating a memory device, comprising: One of a plurality of storage blocks is selected as a target block to perform an error correction operation. The target block includes a plurality of storage units having multiple rows and multiple columns. The rows include at least one data row and at least one check row. The data stored in the storage units of the at least one data row is user data. The data stored in the storage units of the at least one check row is check code. The at least one check code stored in the storage units of each column is generated based on the user data stored in the storage units of the same column. Read these storage units of these columns of the target block column by column; The data stored in these storage units of these columns of the target block is transmitted to an error correction circuit; as well as The error correction circuit checks whether there are error bits in the user data stored in the storage cells of each column based on the at least one check code stored in each column, and corrects them to generate corrected data corresponding to the data stored in the storage cells of each column. Specifically, when performing a search operation on the target block, a search bias is not applied to at least one bit line corresponding to the at least one check row; or when performing a search operation on the target block, the current flowing out of at least one matching line corresponding to the at least one check row is not detected.

6. The operating method according to claim 5 further includes: The corrected data, which is stored in these storage cells corresponding to each column of the target block, is programmed into another storage block within these storage blocks.

7. The operating method according to claim 5 further includes: For the target block, the storage cells containing these user data that have error bits in the column are programmed based on the correction data stored in the storage cells corresponding to the column.

8. The method of operation according to claim 7, wherein for the storage cells of a row that have error bits and whose stored data cannot be changed by programming, a correct version of the data stored in the storage cells of that row is programmed into the storage cells of another row in the target block.

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