Memory and storage system comprising memory

Abstract

The present disclosure relates to memory and storage systems including memory. A storage system includes a plurality of memories, each memory including a plurality of data input terminals; and a memory controller configured to successively transmit a first codeword and a second codeword to the plurality of data input terminals of the plurality of memories during a write operation.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 316249, filed March 3, 2022, and U.S. Provisional Patent Application No. 63 / 427247, filed November 22, 2022. The disclosure of each of the foregoing applications is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to memory and storage systems including memory. Background Technology

[0004] In the early stages of the semiconductor memory device industry, wafers contained many perfectly good bare dies, meaning that semiconductor manufacturing processes could produce memory chips without defective memory cells. However, as the capacity of memory devices increased, manufacturing memory devices without any defective memory cells became difficult, and now it is practically impossible to manufacture memory devices without any defective memory cells. To address this problem, a repair method is being used that incorporates redundant memory cells into the memory device and replaces defective memory cells with redundant memory cells.

[0005] As another method, error correction circuits (ECC circuits) used to correct errors in the storage system are used to correct errors that occur in the storage cells as well as errors that occur during data transfer during read and write operations in the storage system. Summary of the Invention

[0006] Embodiments of the present invention relate to a technique for improving error correction efficiency in storage systems.

[0007] According to one embodiment of the present invention, a storage system includes: a plurality of memories, each memory including a plurality of data input terminals; and a memory controller configured to continuously transmit a first codeword and a second codeword to the plurality of data input terminals of the plurality of memories during a write operation.

[0008] According to another embodiment of the present invention, a memory includes: a plurality of long subword lines included in a Kth row, wherein K is an integer equal to or greater than 0; a plurality of first memory cells coupled to the plurality of long subword lines; a plurality of short subword lines included in the Kth row, wherein the number of short subword lines is less than the number of long subword lines; a plurality of second memory cells coupled to the plurality of short subword lines; and a memory error correction code generation circuit configured to generate memory error correction codes based on write data, wherein, when the Kth row is selected during a write operation, a portion of the second memory cells is configured to store the memory error correction codes therein, and a portion of the second memory cells and a portion of the first memory cells are configured to store the write data therein.

[0009] According to another embodiment of the present invention, a memory includes: a plurality of subword line drivers included in the Kth row, wherein K is an integer equal to or greater than 0; and a plurality of subword lines driven by the subword line drivers, wherein the plurality of subword lines include long subword lines and short subword lines.

[0010] According to one embodiment of the present invention, a storage system includes: K data rows of a storage cell, each data row being configured to store M bits of data therein; an error correction code (ECC) row of the storage cell being configured to store M bits of ECC therein, the M bits of ECC forming a block together with (K*M) bits of data; and a controller coupled to each data row and each ECC row via N paths, each path having an (M / N) bit width, and the controller being configured to: rearrange the (K*M) bits of data into a (K*M / 2) bit high-order data portion and a (K*M / 2) bit low-order data portion, for individual high-order data portions to be stored in a data row during a single write operation. The data segments and low-order data portions are ECC encoded to generate corresponding (M / 2) bit high-order ECC portions and (M / 2) bit low-order ECC portions constituting an M-bit ECC. The M-bit ECC is used to perform ECC decoding on the corresponding data segments and low-order data portions read from the data row during a single read operation, and to provide (M / (2*N)) high-order bits and (M / (2*N)) low-order bits to each of the data row and ECC row through each of the N paths, wherein the high-order bits have either high-order data portions or high-order ECC portions, wherein the low-order bits have either low-order data portions or low-order ECC portions, and wherein each of K, M, and N is a natural number of 1 or greater.

[0011] According to another embodiment of the invention, a memory includes: an error correction code (ECC) circuit configured to ECC-encode data stored in a row of storage cells to generate an ECC for ECC decoding of data read from the row; the row including one or more first groups of storage cells and one or more second groups of storage cells, and the row being configured to store and read blocks therein consisting of data and ECC; and a plurality of drivers, each driver being configured to drive storage cells in at least one of the first and second groups, wherein the number of storage cells in each group of the second group is less than the number of storage cells in each group of the first group. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a storage system according to an embodiment of the present invention.

[0013] Figure 2It is according to an embodiment of the present invention. Figure 1 A detailed diagram of the memory is shown.

[0014] Figure 3 An embodiment of the present invention is shown. Figure 2 The diagram shows the correspondence between regions in the memory and data transmission / reception blocks.

[0015] Figure 4 An embodiment of the invention is shown when... Figure 2 The diagram shows the correspondence between regions and data transmission / reception blocks when performing repair operations in the memory.

[0016] Figure 5 This illustrates an error in the data output from the memory when the memory is not repaired and the subword line driver is defective, and when a read operation is performed from the Kth row, according to an embodiment of the invention.

[0017] Figure 6 An embodiment of the present invention is shown where the memory, such as Figure 4 The fault condition shown is corrected when the subword line driver is defective and when a read operation is performed from the Kth row, the data output from the memory is incorrect.

[0018] Figure 7 This is a block diagram illustrating an embodiment of the present invention in which the system error correction code generation circuit generates system error correction codes by dividing codeword units into smaller units.

[0019] Figures 8A to 8D An embodiment according to the present invention is shown in which, when... Figure 7 When codewords are used as described in the example, the system error correction circuit can correct the data output from the memory.

[0020] Figure 9 This is according to another embodiment of the present invention. Figure 2 A detailed diagram of the cell array of the memory shown.

[0021] Figure 10 and Figure 11 This is a detailed diagram of a cell array according to another embodiment of the present invention. Detailed Implementation

[0022] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts, regardless of the accompanying drawings and embodiments.

[0023] Figure 1 This is a block diagram illustrating a storage system 100 according to an embodiment of the present invention. Figure 1 Only the parts directly related to data storage and error correction in storage system 100 are shown.

[0024] Reference Figure 1 The storage system 100 may include a memory controller 110 and memories 120_0 to 120_4.

[0025] The memory controller 110 can control operations such as read and write operations of the memories 120_0 to 120_4 according to requests from the host. The memory controller 110 may include a system error correction code generation circuit (i.e., a system ECC generation circuit) 111 for generating a system error correction code SYS_ECC during a write operation and a system error correction circuit 112 for correcting errors in the data DATA based on the system error correction code SYS_ECC during a read operation.

[0026] The system ECC generation circuit 111 can generate a system error correction code SYS_ECC to correct errors based on the data HOST_DATA transferred from the host during a write operation. Here, it is shown that the unit (i.e., block size) of the data HOST_DATA processed during a single write operation is 512 bits, and the system error correction code SYS_ECC has 128 bits. During a write operation, only the system error correction code SYS_ECC is generated, but no error correction operation is performed. Therefore, the data HOST_DATA transferred from the host and the data transferred from the memory controller 110 to the memories 120_0 to 120_4 can be the same.

[0027] The system error correction circuit 112 can correct errors in the data transmitted from memory 120_0 to 120_4 based on the system error correction code SYS_ECC transmitted from memory 120_0 to 120_4 during read operations.

[0028] Memory 120_0 to 120_4 can allocate and store data DATA and system error correction code SYS_ECC. Each of memories 120_0 to 120_3 can store 128 bits of information during a single write operation. Memories 120_0 to 120_3 can divide the 512 bits of data DATA into 128 bits and store the 128 bits, while memory 120_4 can store the 128 bits of system error correction code SYS_ECC. Even during a read operation, each of memories 120_0 to 120_4 can transfer 128 bits of information to memory controller 110.

[0029] During write or read operations, the unit (i.e., block size) of data transferred between memory controller 110 and memories 120_0 to 120_4 can be 640 (=512+128) bits.

[0030] Figure 2 An embodiment of the present invention is shown. Figure 1 The memory 120_0 is shown. Other memories 120_1 to 120_4 can also be used as shown. Figure 2 As shown in the diagram.

[0031] Reference Figure 2 The memory 120_0 may include data transmission / reception blocks DQ0 to DQ7, a memory error correction code generation circuit (i.e., a memory ECC generation circuit) 211, a memory error correction circuit 212, and a cell array 220.

[0032] Each of the data transfer / receive blocks DQ0 through DQ7 can transmit and receive data DATA from the memory controller 110 via data terminals 201 through 208. During a single read operation and a single write operation, each of the data transfer / receive blocks DQ0 through DQ7 can transmit and receive 16 bits of data DATA. That is, during a single read operation and a single write operation, 16 bits of data DATA can be serially transmitted and received via each of data terminals 201 through 208. The length of the serial data can be referred to as the burst length BL, and here, the burst length BL is 16 (BL = 16) because 16 bits of data are transmitted and received via one data terminal. Since the eight data transfer / receive blocks DQ0 through DQ7 transmit and receive 16 bits of data DATA at a time, the memory 120_0 is capable of transmitting and receiving 128 bits of data DATA at a time.

[0033] The memory ECC generation circuit 211 can generate an 8-bit memory error correction code MEM_ECC based on the 128-bit data DATA received through data transmission / reception blocks DQ0 to DQ7 during a write operation. The memory error correction code MEM_ECC is related to... Figure 1 The difference in the system error correction code SYS_ECC shown is that it is an error correction code used only within memory 120_0. During write operations, only memory error correction code MEM_ECC is generated, but no error correction operation is performed. Therefore, the data DATA input to memory ECC generation circuit 211 and the data DATA' output from memory ECC generation circuit 211 can be the same.

[0034] The memory error correction circuit 212 can correct errors in the data DATA' read from the cell array 220 based on the memory error correction code MEM_ECC read from the cell array 220 during a read operation. The error-corrected data DATA can be transmitted to the memory controller 110 via data transmission / reception blocks DQ0 to DQ7. The memory error correction code MEM_ECC can be used only for error correction of the data DATA' within the memory 120_0, and the memory error correction code MEM_ECC may not be transmitted to the memory controller 110.

[0035] Cell array 220 may include storage cells arranged in multiple rows and multiple columns. In cell array 220, 128 bits of data DATA' and 8 bits of memory error correction code MEM_ECC can be stored during a single read operation.

[0036] The diagram illustrates three rows of cell array 220 (rows (K-1), K, and K+1). Each row may include multiple sub-word lines (SWLs) and multiple sub-word line drivers 251 to 265 for driving the sub-word lines (SWLs). For example, row K may include nine sub-word lines (SWLK_1 to SWLK_9) and sub-word line drivers 256 to 260 for driving the sub-word lines (SWLK_1 to SWLK_9). Multiple memory cells may be coupled to each sub-word line (SWL).

[0037] In this diagram, H0 to H15, ECC, and RED may not represent constituent elements, but rather indicate the division of column regions. H0 can represent the left half of sub-line SWLK-1_1, SWLK_1, and SWLK+1_1; H1 can represent the right half of sub-line SWLK-1_1, SWLK_1, and SWLK+1_1; ECC can represent the left half of sub-line SWLK-1_5, SWLK_5, and SWLK+1_5; H8 can represent the right half of sub-line SWLK-1_5, SWLK_5, and SWLK+1_5; H15 can represent the left half of sub-line SWLK-1_9, SWLK_9, and SWLK+1_9; and RED can represent the right half of sub-line SWLK-1_9, SWLK_9, and SWLK+1_9.

[0038] Figure 3 An embodiment of the present invention is shown. Figure 2 The correspondence between regions H0 to H15, ECC, and RED in memory 120_0 and data transmission / reception blocks DQ0 to DQ7 is shown.

[0039] Reference Figure 3 It can be seen that region H0 corresponds to BL07 of data transmission / reception block DQ0, and region H1 corresponds to BL8F of data transmission / reception block DQ0. This means that of the 16 bits of data received by data transmission / reception block DQ0, the 8 bits corresponding to BL0 to BL7 can be stored in region H1, and of the data received by data transmission / reception block DQ0, the 8 bits corresponding to BL8 to BLF (where F = 15) can be stored in region H2. Specifically, when the Kth row is selected based on the row address, it can be said that the 8 bits of data received by data transmission / reception block DQ0 corresponding to BL0 to BL7 are stored in eight memory cells selected based on column address among multiple memory cells coupled to the left half of sub-word line SWLK_1, while the 8 bits of data received by data transmission / reception block DQ0 corresponding to BL8 to BLF are stored in eight memory cells selected based on column address among multiple memory cells coupled to the right half of sub-word line SWLK_1.

[0040] Similarly, region H2 can correspond to BL07 of data transmission / reception block DQ1, while region H3 can correspond to BL8F of data transmission / reception block DQ1. Other regions H3 to H15 can also correspond to data transmission / reception blocks DQ2 to DQ7.

[0041] The region ECC does not correspond to any data transmission / reception blocks DQ0 to DQ7 because the region ECC stores memory error correction code MEM_ECC, not data. Although the memory error correction code MEM_ECC is stored in cell array 220, it can only be used to correct errors within memory 120_0, and it may not be information output to or input from outside memory 120_0. Therefore, the region ECC does not correspond to any data transmission / reception blocks DQ0 to DQ7.

[0042] The RED region can be a redundant region used for repair. Therefore, when it is not repaired, the RED region does not correspond to any data transmission / reception blocks DQ0 to DQ7.

[0043] Figure 4 An embodiment of the invention is shown when... Figure 2 The diagram shows the correspondence between regions H0 to H16, ECC, and RED in memory 120_0 during repair operations and data transmission / reception blocks DQ0 to DQ7.

[0044] Reference Figure 4 The attached diagram, labeled "No Rep," indicates the correspondence between regions H0 to H15, ECC, and RED, and data transmission / reception blocks DQ0 to DQ7 when no repair operation is performed. In this case, it has the same... Figure 3 The same correspondence is shown.

[0045] Figure 4 The reference numeral "H0 fail" in the accompanying drawings indicates the correspondence between regions H1 to H15, ECC, and RED, and data transmission / reception blocks DQ0 to DQ7 when region H0 is determined to be defective and is repaired. In this case, region H0 is not used, and region H1 can be used instead of region H0, and region H2 can be used instead of region H1. Similarly, region RED can be used instead of region H15. In the case of H0 failure, the 8-bit data of BL07 received by data transmission / reception block DQ0 can be stored in region H1, and the 8-bit data of BL8F received by data transmission / reception block DQ3 can be stored in region ECC, the 8-bit memory error correction code MEM_ECC can be stored in region H8, and the 8-bit data of BL8F received by data transmission / reception block DQ7 can be stored in region RED.

[0046] Figure 4The reference numerals “H1 fail” to “H15 fail” in the attached figures indicate the correspondence between regions H0 to H15, ECC, and RED and data transmission / reception blocks DQ0 to DQ7 when regions H1 to H15 are determined to be defective and are repaired.

[0047] Figure 4 The region ECC indicates the correspondence between regions H0 to H15 and RED and data transmission / reception blocks DQ0 to DQ7 when region ECC is determined to be defective and repaired. It can be seen that regions ECC to H15 are replaced by regions H8 to RED. In this case, the 8-bit memory error correction code MEM_ECC can be stored in region H8, and the 8-bit data of BL07 received by data transmission / reception block DQ4 can be stored in region H9. Similarly, the 8-bit data of BL8F received by data transmission / reception block DQ7 can be stored in region RED.

[0048] Due to the system error correction circuit 112 of the memory controller 110 (see...) Figure 1 It uses the system error correction code SYS_ECC, which has a large number of bits, and therefore has high error correction capability. For example, the system error correction circuit 112 can correct eight data transmission / reception blocks DQ0 to DQ7 from memory 120_0 (see...). Figure 2 All data output from the two data transmission / reception blocks in the () are processed, even if errors exist.

[0049] Figure 5 This illustrates an error in the data DATA output from memory 120_0 when memory 120_0 is not repaired (No Rep) and subword line driver 257 is defective, and when a read operation is performed from line K, according to an embodiment of the present invention.

[0050] Because it is the sub-word line driver 257 of row K, errors may occur in regions H2, H3, H4, and H5 corresponding to this sub-word line driver when a read operation is performed from row K. Therefore, errors may occur in a total of 32 bits of data, including 16 bits of data BL0 to BL15 output from data transmission / reception block DQ1 corresponding to regions H2, H3, H4, and H5, and 16 bits of data BL0 to BL15 output from data transmission / reception block DQ2. Figure 5 Of the 128 bits of data shown, the 32 bits of colored data can represent erroneous data.

[0051] Despite Figure 5A 32-bit error has occurred, but since all the errors only occur in the data output from the two data transmission / reception blocks DQ1 and DQ2, that is, since the errors only occur in the data output from the two data terminals, the errors can be corrected by the system error correction circuit 112 of the memory controller 110.

[0052] Figure 6 This illustrates an embodiment of the invention where memory 120_0 is as follows: Figure 4 The H0 fault (H0fail) condition shown is repaired when the subword line driver 257 is defective, and when the data DATA output from memory 120_0 is faulty when a read operation is performed from the Kth line.

[0053] Because it is the sub-word line driver 257 of row K, errors may occur in regions H2, H3, H4, and H5 corresponding to this sub-word line driver when a read operation is performed from row K. In the case of a fault at H0, errors may occur in a total of 32 bits of data, since region H2 can correspond to 8 bits of data BL8 to BL15 output from data transmission / reception block DQ0, regions H3 and H4 can correspond to 16 bits of data BL0 to BL15 output from data transmission / reception block DQ2, and region H5 can correspond to 8 bits of data BL0 to BL7 output from data transmission / reception block DQ1. Figure 6 In the 128-bit data shown, the 32-bit colored data can represent erroneous data.

[0054] exist Figure 6 In this case, errors occur in the 8-bit data output from data transmission / reception block DQ0, the 8-bit data output from data transmission / reception block DQ1, and the 16-bit data output from data transmission / reception block DQ2. Figure 6 In the middle, due to errors in the data output from the three data transmission / reception blocks DQ0, DQ1, and DQ2, therefore... Figure 5 Unlike the case where the error only occurs in the data output from the two data transmission / reception blocks DQ1 and DQ2, the system error correction circuit 112 of the memory controller 110 may not correct the error. (The system error correction circuit 112 can only correct the error if an error occurs in both data terminals.)

[0055] When memory 120_0 is not repaired (see...) Figure 5The four regions H2, H3, H4, and H5 of a sub-word line driver 257 correspond to two data transmission / reception blocks DQ1 and DQ2. Therefore, even if the sub-word line driver 257 is defective, errors will only occur in the data output from the two data transmission / reception blocks DQ1 and DQ2. Thus, the system error correction circuit 112 is able to correct the errors. However, when the memory 120_0 is repaired (see...), Figure 6 This corresponds to four adjacent regions of a sub-word line driver 257, which in turn correspond to three data transmission / reception blocks DQ0, DQ1, and DQ2. Therefore, when the sub-word line driver 257 is defective, errors occur in the data output from the three data transmission / reception blocks DQ0, DQ1, and DQ2. This is beyond the error correction range of the system error correction circuit 112. Therefore, the errors cannot be corrected.

[0056] To address this issue, the system ECC generation circuit 111 and system error correction circuit 112 of the memory controller 110 can divide codeword units into smaller segments.

[0057] When the system ECC generation circuit 111 encodes the 512-bit data HOST_DATA to generate a 128-bit system error correction code and bundles 640 bits into a codeword, the system error correction circuit 112 can correct errors in the data output from two of the eight data transmission / reception blocks DQ0 to DQ7 of a memory 120_0. However, when the codeword unit becomes smaller, the system error correction circuit 112 can correct errors in a finer unit.

[0058] Figure 7 This is a block diagram illustrating an embodiment of the present invention in which the system ECC generation circuit 111 generates system error correction code SYS_ECC by dividing the codeword unit into smaller units.

[0059] The first data HOST_DATA_BL07 can represent 256 bits of data from the 512-bit data HOST_DATA that are to be transmitted as BL0 to BL7 from the data terminals of memory 120_0 to 120_3. Furthermore, the second data HOST_DATA_BL8F can represent 256 bits of data from the 512-bit data HOST_DATA that are to be transmitted as BL8 to BL15 from the data terminals of memory 120_0 to 120_3.

[0060] The system ECC generation circuit 111 can generate a 64-bit first system error correction code SYS_ECC_BL07 by encoding the 256-bit first data HOST_DATA_BL07. Furthermore, the system ECC generation circuit 111 can generate a 64-bit second system error correction code SYS_ECC_BL8F by encoding the 256-bit second data HOST_DATA_BL07.

[0061] During a write operation, a 320-bit first codeword CODEWORD_0, including the first system error correction code SYS_ECC_BL07 and the first data DATA_BL07, can be transmitted as BL0 to BL7 to 40 data terminals (40*8=320) of memory 120_0 to 120_4. Furthermore, during a write operation, a 320-bit second codeword CODEWORD_1, including the second system error correction code SYS_ECC_BL8F and the second data DATA_BL8F, can be transmitted as BL8 to BL15 to 40 data terminals (40*8=320) of memory 120_0 to 120_4.

[0062] During a read operation, the error correction operation of the system error correction circuit 112 can be performed independently for each of the codewords CODEWORD_0 and CODEWORD_1. The system error correction circuit 112 can correct errors in the first codeword CODEWORD_0 based on the first system error correction code SYS_ECC_BL07 in the first codeword CODEWORD_0, and correct errors in the second codeword CODEWORD_1 based on the second system error correction code SYS_ECC_BL8F in the second codeword CODEWORD_1.

[0063] The system error correction circuit 112 is capable of correcting errors in the data output from the two data transmission / reception blocks in a portion of the first codeword CODEWORD_0 in the data read from the memory 120_0, and is also capable of correcting errors in the data output from the two data transmission / reception blocks in a portion of the second codeword CODEWORD_1.

[0064] Figure 8A , Figure 8B , Figure 8C and Figure 8D It shows that when such Figure 7 When using codewords CODEWORD_0 and CODEWORD_1, the system error correction circuit 112 can correct the data output from memory 120_0.

[0065] Reference Figure 8AAlthough errors corresponding to the two data transmission / reception blocks DQ1 and DQ2 occur in the first codeword CODEWORD_0 and errors corresponding to the two data transmission / reception blocks DQ0 and DQ2 occur in the second codeword CODEWORD_1, these errors can be corrected by the system error correction circuit 112. This is because the error correction operation of the first codeword CODEWORD_0 and the error correction operation of the second codeword CODEWORD_1 are performed independently. Therefore, in Figure 6 In this case, the error in memory 120_0 can be corrected.

[0066] Figure 8B , Figure 8C and Figure 8D An example of an error mode that can be corrected by the system error correction circuit 112 is also shown. Even if an error corresponding to any block of the two data transmission / reception blocks occurs in the first codeword CODEWORD_0 and an error corresponding to any block of the two data transmission / reception blocks occurs in the second codeword CODEWORD_1, the error can still be corrected by the system error correction circuit 112.

[0067] Return to reference Figure 2 and Figure 3 When the subword line driver 258 of the Kth row of cell array 220 is defective and a read operation is performed in the Kth row, errors may occur in regions H6, H7, ECC, and H8. Since regions H6 and H7 correspond to data transmission / reception block DQ3 and region H8 corresponds to data transmission / reception block DQ4, errors may occur in the data output from data transmission / reception blocks DQ3 and DQ4. The memory error correction code MEM_ECC read from region ECC may not be output to the outside of memory 120_0, but can be used for error correction operations of memory error correction circuit 212. When the memory error correction code MEM_ECC read from this region contains a large number of errors, the memory error correction circuit 212 (which typically has low error correction capability) may miscorrect, and miscorrection may further increase the number of errors in the data output from memory 120_0. For example, in addition to errors in the data output from data transmission / reception blocks DQ3 and DQ4 caused by errors in regions H6, H7, and H8, errors may also occur in the data output from another data transmission / reception block (e.g., DQ6) due to miscorrection. In this case, the number of errors may exceed the error correction range of the system error correction circuit 112 of the memory controller 110, leading to a failure of the memory system 100.

[0068] In other words, when an error occurs in the ECC region of the memory error correction code MEM_ECC, the memory error correction circuit 212, which has low error correction capability, may miscorrect. Miscorrection may cause additional errors in unexpected locations. To address this issue, Figure 9 Another embodiment of the cell array 220 of memory 120_0 is shown.

[0069] Figure 9 Another embodiment of the invention is shown. Figure 2 The cell array 220 of the memory 120_0 shown.

[0070] Reference Figure 9 Cell array 220 may include storage cells arranged in multiple rows and multiple columns. During a single read operation, cell array 220 may include 128 bits of data DATA' and 8 bits of memory error correction code MEM_ECC.

[0071] This diagram illustrates three rows of cell array 220 (rows (K-1), K, and K+1). Each row may include multiple sub-word lines (SWLs) and multiple sub-word line drivers 951 to 966 for driving the sub-word lines (SWLs). For example, row K may include 10 sub-word lines (SWLK_1 to SWLK_10) and sub-word line drivers 956 to 961 for driving the sub-word lines (SWLK_1 to SWLK_10). Multiple memory cells may be coupled to each sub-word line (SWL).

[0072] exist Figure 9 In the cell array 220, unlike Figure 2 In the cell array 220, the sub-word lines SWL have different lengths. For example, the sub-word lines SWLK_1, SWLK_2, SWLK_3, SWLK_4, SWLK_7, SWLK_8, SWLK_9, and SWLK_10 in the Kth row can be long sub-word lines, while the sub-word lines SWLK_5 and SWLK_6 can be short sub-word lines.

[0073] The memory error correction code MEM_ECC can be stored in the region ECC. The memory error correction code MEM_ECC can also be stored solely in memory cells coupled to the short subword line. Most of the data DATA can be stored in memory cells coupled to the long subword line, while some data can be stored in memory cells coupled to the short subword line.

[0074] The following will describe as follows: Figure 9The advantages of the structure of the cell array 220 shown are as follows: When the subword line driver 958 of the Kth row is defective and a read operation is performed in the Kth row, errors may occur in regions H6, H7, and ECC. Since regions H6 and H7 correspond to data transmission / reception block DQ3, errors may occur in the data output from data transmission / reception block DQ3. Due to errors in the memory error correction code MEM_ECC read from region ECC, miscorrection may occur in the memory error correction circuit 212. However, even if errors occur in the data of another memory transmission / reception block (e.g., DQ5) due to miscorrection, since the number of data transmission / reception blocks (e.g., DQ3 and DQ5) where errors occur is 2, the errors can still be corrected by the system error correction circuit 112 of the memory controller 110.

[0075] The error correction code MEM_ECC is stored only in the memory cells connected to the short sub-word lines (SWLK-1_5, SWLK-1_6, SWLK_5, SWLK_6, SWLK+1_5, and SWLK+1_6), which prevents memory system 100 from malcorrecting errors by forming long sub-word lines SWLK-1_1 to SWLK-1_4, SWLK-1_7 to SWLK-1_10, SWLK_1 to SWLK_4, SWLK_7 to SWLK_10, and SWLK+1_6. The cell array 220 of cell array 220, consisting of cell arrays 1_1 to SWLK+1_4 and SWLK+1_7 to SWLK+1_10, and short sub-word lines SWLK-1_5, SWLK-1_6, SWLK_5, SWLK_6, SWLK+1_5, and SWLK+1_6, stores only the memory error correction code MEM_ECC in the memory cells coupled to the short sub-word lines SWLK-1_5, SWLK-1_6, SWLK_5, SWLK_6, SWLK+1_5, and SWLK+1_6.

[0076] like Figure 10 and Figure 11 As shown, it can be applied as follows Figure 9 The diagram shows the formation of long and short sub-word lines, replacing the length of the sub-word line SWL in the unified cell array 220. (Refer to...) Figure 10 and Figure 11 When long sub-word lines and short sub-word lines are arranged throughout the cell array 220, even if the cell array 220 is repaired and the arrangement of regions H0 to H15, ECC and RED, and data transmission / reception blocks DQ0 to DQ7 changes, it can still respond to changes more flexibly.

[0077] Reference Figure 10The cell array 220 may include long sub-word lines SWLK-1_1, SWLK-1_2, SWLK-1_4, SWLK-1_5, SWLK-1_6, SWLK-1_7, SWLK-1_9, SWLK-1_10, SWLK_1, SWLK_2, SWLK_4, SWLK_5, SWLK_6, SWLK_7, SWLK_9, SWLK_10, SWLK+1_1, SWLK+1_2, SWLK+1_4, SWLK+1_5, SWLK+1_6, SWLK+1_7, SWLK+1_9, and SWLK+1_10, as well as short sub-word lines SWLK-1_3, SWLK-1_8, SWLK_3, SWLK_8, SWLK+1_3, and SWLK+1_8. Some adjacent subword line drivers 1059 and 1060 may not include any subword lines. Subword line drivers 1059 and 1060 may drive only subword lines SWLK_5 and SWLK_6 in one direction. Furthermore, for some subword line drivers 1052, 1055, 1058, 1061, 1064, and 1067, the lengths of the left and right subword lines may be different.

[0078] Reference Figure 10 When long and short sub-word lines are arranged in many different positions in the cell array 220, it can cope with changes in correspondence caused by the repair of the cell array 220 and subsequent error correction.

[0079] Reference Figure 11 The cell array 220 may include long sub-word lines SWLK-1_1, SWLK-1_2, SWLK-1_3, SWLK-1_4, SWLK-1_6, SWLK-1_7, SWLK-1_8, SWLK-1_9, SWLK_1, SWLK_2, SWLK_3, SWLK_4, SWLK_6, SWLK_7, SWLK_8, SWLK_9, SWLK+1_1, SWLK+1_2, SWLK+1_3, SWLK+1_4, SWLK+1_6, SWLK+1_7, SWLK+1_8, and SWLK+1_9, as well as short sub-word lines SWLK-1_5, SWLK_5, and SWLK+1_5. Furthermore, for some sub-word drivers 1153, 1158, and 1163, the lengths of the sub-word lines on one side and the other side can be different. Figure 11 The RED region in the middle can be absent because Figure 11 This shows the case without redundancy.

[0080] Reference Figure 11When long and short sub-word lines are arranged in many different locations in the cell array 220, the possibility of error correction can be further increased even if defects are detected in the sub-word line driver and / or sub-word lines.

[0081] According to embodiments of the present invention, the efficiency of error correction in a storage system can be improved.

[0082] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A memory, comprising: The Kth row contains multiple long subword lines, where K is an integer equal to or greater than 0; Multiple first storage cells are coupled to the multiple long subword lines; The Kth row includes multiple short sub-word lines, the number of which is less than the number of long sub-word lines; Multiple second storage cells are coupled to the multiple short subword lines; as well as The memory error correction code generation circuit generates memory error correction codes based on the written data. When the Kth row is selected during a write operation, a portion of the second storage unit stores the memory error correction code therein, and a portion of the second storage unit and a portion of the first storage unit are configured to store the write data therein.

2. The memory according to claim 1, wherein, The number of bits of the written data stored in a portion of the second storage unit is less than the number of bits of the written data stored in a portion of the first storage unit.

3. The memory according to claim 1, wherein: A portion of the second memory cell is selected based on the column address to store the memory error correction code therein; as well as A portion of the first storage cell and a portion of the second storage cell are selected based on the column address to store the written data therein.

4. A memory, comprising: ECC circuitry encodes the data stored in rows of memory cells using ECC to generate ECC codes for ECC decoding of data read from said rows, where ECC stands for Error Correction Code. The row includes one or more first group storage units and one or more second group storage units, and blocks therein for storing and reading from there consisting of the data and the ECC, wherein the ECC is stored in a portion of the second group, and the data is stored in a portion of the first group and a portion of the second group; as well as Multiple drives, each drive driving the memory cells within at least one of the first and second groups. The number of storage units in each group of the second group is less than the number of storage units in each group of the first group.

Images