A manufacturing method of an isolation transformer circuit, an isolation driving circuit and a chip

Abstract

The embodiment of the application belongs to the technical field of integrated circuits, and relates to a manufacturing method of an isolated driving circuit, which comprises the following steps: depositing silicon dioxide on a substrate to form a silicon dioxide isolation layer; sputtering a metal film on the silicon dioxide isolation layer to form a first metal layer, and integrating wiring lines of an isolated transformer circuit in the first metal layer; depositing silicon dioxide on the first metal layer to form a silicon dioxide isolation layer; sputtering a metal film on the silicon dioxide isolation layer to form a second metal layer, and ion etching an input coil or an output coil of the isolated transformer circuit on the second metal layer; depositing silicon dioxide on the second metal layer to form a silicon dioxide isolation layer; sputtering a metal film on the silicon dioxide isolation layer to form a third metal layer, and ion etching an output coil or an input coil of the isolated transformer circuit on the third metal layer. The application further provides an isolated driving circuit and a chip. The technical scheme provided by the application can improve driving capacity, shorten transmission delay, and improve transmission speed.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a method for manufacturing an isolation transformer circuit, an isolation drive circuit, and a chip. Background Technology

[0002] Driven by emerging industries such as smart grids, mobile communications, and new energy vehicles, power electronics application systems require further improvements in system efficiency, miniaturization, and functionality. In particular, there is a demand for trade-offs between system equipment size, weight, power, and efficiency, as seen in applications such as server power management, battery chargers, and microinverters for solar power plants. To adapt to applications requiring high voltage, high temperature, high efficiency, and high power density, high-voltage integrated circuits (HVICs) have been developed.

[0003] HVIC is an integrated circuit product that converts MCU (Microcontroller Unit) signals into signals to drive IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). HVIC receives control signals from the MCU to drive subsequent IGBTs or MOSFETs, and also sends fault status detection signals back to the MCU. It is a key chip within an Intelligent Power Module (IPM).

[0004] However, the HVIC inside the current IPM uses a vertical PN junction and HVJT (High Voltage Junction Terminating) isolation, see [link to relevant documentation]. Figure 1 A to Figure 1 As shown in Figure C, the isolation voltage is insufficient to drive the IGBT or MOSFET.

[0005] In addition, HVIC currently uses pulse transformers to achieve isolated transmission of drive signals. The pulse transformer directly drives the MOSFET after fully coupling the PWM (Pulse Width Modulation) signal to the secondary side. The conduction time is limited by the saturation characteristics of the magnetic core, resulting in a large transmission delay and a slow transmission speed. Furthermore, due to the large parasitic capacitance of the MOSFET, the obtained drive signal is prone to waveform distortion. Summary of the Invention

[0006] The technical problem to be solved by the embodiments of this application is that the isolation drive capability is weak, and the isolation drive transmission delay is large and the transmission speed is slow in the related technology.

[0007] To address the aforementioned technical problems, this application provides a method for manufacturing an isolation transformer circuit, employing the following technical solution:

[0008] A first silicon dioxide isolation layer is formed by depositing a silicon dioxide dielectric on the substrate using plasma-enhanced chemical vapor deposition.

[0009] A metal film is sputtered onto the first silicon dioxide isolation layer to form a first metal layer, and the wiring of the isolation transformer circuit is integrated on the first metal layer.

[0010] A second silicon dioxide isolation layer is formed by depositing a silicon dioxide dielectric on the first metal layer using plasma-enhanced chemical vapor deposition.

[0011] A metal film is sputtered onto the second silicon dioxide isolation layer to form a second metal layer. The input coil or output coil of the isolation transformer circuit is ion etched onto the second metal layer. The port of the input coil or the output coil is connected to the wiring lines on the first metal layer through metal-filled vias.

[0012] A third silicon dioxide insulating layer is formed by depositing a silicon dioxide dielectric on the second metal layer using plasma-enhanced chemical vapor deposition.

[0013] A metal film is sputtered onto the third silicon dioxide isolation layer to form a third metal layer. The output coil or input coil of the isolation transformer circuit is ion etched onto the third metal layer, wherein the port of the output coil or input coil is a bonding region.

[0014] To address the aforementioned technical problems, this application provides an isolated driving circuit, employing the following technical solution:

[0015] The input stage circuit, the output stage circuit, and the isolation transformer circuit obtained by the method of manufacturing the isolation transformer circuit according to claim 1 are electrically connected to each other.

[0016] The input stage circuit is used to receive input signals, fault signals, and abnormal feedback signals from the output stage circuit. It modulates the input signals into valid input signals for the isolation transformer circuit and transmits the valid input signals to the output stage circuit through the isolation transformer circuit. It shuts off the output of the input stage circuit according to the fault signal and demodulates the received abnormal feedback signals.

[0017] The isolation transformer circuit is used to transmit the valid input signal to the output stage circuit, and to transmit the abnormal feedback signal to the input stage circuit;

[0018] The output stage circuit is used to demodulate the received valid input signal into a square wave signal and transmit the abnormal feedback signal to the input stage circuit through the isolation transformer circuit.

[0019] Furthermore, the input stage circuit includes a first ESD protection circuit, a first Schmitt trigger circuit, a first filter circuit, a first logic circuit, a first modulation circuit, a first demodulation circuit, and a fault feedback circuit, wherein:

[0020] The first ESD protection circuit is connected to the first Schmitt circuit to release the electrostatic current generated in the circuit.

[0021] The first Schmitt circuit is connected to the first filter circuit to filter out interference signals;

[0022] The first filter circuit is connected to the first logic circuit and is used to filter out voltage spikes in the input signal.

[0023] The first logic circuit is connected to the first modulation circuit, the first demodulation circuit, and the fault feedback circuit respectively, and is used to perform logical processing on the input signal, the abnormal feedback signal, and the fault signal, and to shut down all outputs of the input stage circuit according to the fault signal and the abnormal feedback signal.

[0024] The first modulation circuit is connected to the isolation transformer circuit and is used to modulate the input signal into an effective input signal for the isolation transformer circuit, and transmit the effective input signal to the isolation transformer circuit.

[0025] The first demodulation circuit is connected to the isolation transformer circuit and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit and feed it back to the first logic circuit.

[0026] The fault feedback circuit is used to output the fault signal through the fault output circuit and feed it back to the first logic circuit.

[0027] Furthermore, the input stage circuit also includes a second ESD protection circuit, an overcurrent protection circuit, and a second filter circuit;

[0028] The overcurrent protection circuit is connected to the fault feedback circuit through the second filter circuit. It is used to detect the voltage signal fed back by the external sampling circuit. When the voltage signal is greater than the reference voltage, it outputs an overcurrent protection signal and transmits the overcurrent protection signal to the second filter circuit.

[0029] The second ESD protection circuit is connected to the second filter circuit through the overcurrent protection circuit to release the electrostatic current generated in the circuit;

[0030] The second filtering circuit is used to filter out interference signals from the overcurrent protection signal and transmit the filtered overcurrent protection signal to the fault feedback circuit, wherein the overcurrent protection signal serves as a fault signal for the fault feedback circuit.

[0031] Furthermore, the output stage circuit includes a second demodulation circuit, a second modulation circuit, a third filter circuit, an undervoltage protection circuit, a second logic circuit, a drive and dead-time circuit, and an output drive circuit.

[0032] The second demodulation circuit is connected between the third filter circuit and the isolation transformer circuit, and is used to demodulate the received valid input signal into a square wave signal and send it to the fourth filter circuit.

[0033] The third filtering circuit is connected to the second logic circuit and is used to filter out the spike voltage signal of the square wave signal;

[0034] The undervoltage protection circuit is connected to the second logic circuit and is used to detect the power supply voltage of the output stage circuit. When the power supply voltage is lower than the second preset threshold, it transmits an undervoltage signal to the second logic circuit.

[0035] The second logic circuit is connected to the drive and dead-time circuit and is used to process the square wave signal and the undervoltage signal;

[0036] The drive and dead-time circuits are connected to the output drive circuit and to the power supply voltage, and are used to amplify the signal output by the second logic circuit to drive the output drive circuit and generate dead-time characteristics for the output drive circuit.

[0037] The second modulation circuit is connected between the second logic circuit and the isolation transformer circuit, and is used to transmit the abnormal feedback signal output by the second logic circuit to the input stage circuit.

[0038] Furthermore, the isolation transformer circuit includes a first isolation transformer and a second isolation transformer, the input coil includes a first input coil and a second input coil, and the output coil includes a first output coil and a second output coil;

[0039] The first isolation transformer includes a first input coil and a first output coil. The first input coil is connected to the input stage circuit, and the first output coil is connected to the output stage circuit. It is used to transmit the valid input signal to the output stage circuit in sequence through the first input coil and the first output coil.

[0040] The second isolation transformer includes a second input coil and a second output coil. The second input coil is connected to the output stage circuit, and the second output coil is connected to the input stage circuit. It is used to transmit the abnormal feedback signal to the input stage circuit in sequence through the second input coil and the second output coil.

[0041] Furthermore, the input stage circuit also includes a dead-time interlock circuit, a third ESD protection circuit, a second Schmitt circuit, a fourth filter circuit, a third modulation circuit, and a third demodulation circuit.

[0042] The dead-time interlock circuit is connected between the first filter circuit, the fourth filter circuit and the first logic circuit, and is used to output an interlock signal when at least two input signals are high level, and send the interlock signal to the first logic circuit.

[0043] The third ESD protection circuit is connected to the second Schmitt circuit and is used to release the electrostatic current generated in the circuit.

[0044] The second Schmitt circuit is connected to the fourth filter circuit to filter out interference signals;

[0045] The fourth filtering circuit is connected to the dead-time interlock circuit and is used to filter out input signal spike voltage.

[0046] The first logic circuit is connected to the third modulation circuit and the third demodulation circuit respectively, and is used to turn off the output corresponding to the input signal according to the interlock signal;

[0047] The third modulation circuit is connected to the isolation transformer circuit and is used to modulate the input signal into an effective input signal for the isolation transformer circuit, and transmit the effective input signal to the isolation transformer circuit.

[0048] The third demodulation circuit is connected to the isolation transformer circuit and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit and feed it back to the first logic circuit.

[0049] To address the aforementioned technical problems, this application also provides an isolation driver chip, employing the technical solution described below:

[0050] The input stage circuit and the output stage circuit of the isolation driving circuit are integrated on the substrate, and the wiring of the input stage circuit and the output stage circuit are encapsulated in the first metal layer.

[0051] The input stage circuit and the output stage circuit are connected to the isolation transformer circuit of the isolation drive circuit through the bonding region.

[0052] Furthermore, the substrate is an SOI substrate, and the top silicon layer of the SOI substrate is used to integrate the devices of the input stage circuit and the output stage circuit, with a silicon dioxide isolation region formed between the devices.

[0053] Furthermore, the avalanche breakdown voltage of the silicon dioxide isolation region is greater than twice the withstand voltage rating of the isolation driver chip; the avalanche breakdown voltage of the silicon dioxide layer is greater than twice the withstand voltage rating of the isolation driver chip.

[0054] Compared with the prior art, the embodiments of this application have the following main advantages:

[0055] The method for fabricating the isolation drive circuit provided in this application involves depositing a silicon dioxide dielectric on a substrate using plasma-enhanced chemical vapor deposition (PECVD) to form a first silicon dioxide isolation layer; sputtering a metal film onto the first silicon dioxide isolation layer to form a first metal layer, and integrating the wiring of the isolation transformer circuit onto the first metal layer; depositing a silicon dioxide dielectric on the first metal layer using PECVD to form a second silicon dioxide isolation layer; sputtering a metal film onto the second silicon dioxide isolation layer to form a second metal layer; and ion etching the input coil or output coil of the isolation transformer circuit onto the second metal layer. The port is connected to the wiring lines on the first metal layer through metal-filled vias; a silicon dioxide dielectric is deposited on the second metal layer using plasma-enhanced chemical vapor deposition to form a third silicon dioxide isolation layer; a metal film is sputtered on the third silicon dioxide isolation layer to form a third metal layer; the output coil or input coil of the isolation transformer circuit is ion-etched on the third metal layer, wherein the port of the output coil or input coil is a bonding region; by setting the input coil and output coil of the isolation transformer circuit on different metal layers, this application can produce an isolation transformer circuit with a larger isolation drive voltage, improve the driving capability, shorten the transmission delay, and increase the transmission speed. Attached Figure Description

[0056] To more clearly illustrate the solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the structure of an isolation driver chip in the prior art;

[0058] Figure 2 This is a schematic diagram of the input stage circuit of the isolation drive circuit of this application;

[0059] Figure 3 This is another schematic diagram of the input stage circuit of the isolated drive circuit of this application;

[0060] Figure 4 This is a schematic diagram of the output stage circuit of the isolation drive circuit of this application;

[0061] Figure 5 This is a schematic diagram of the isolation drive circuit of this application;

[0062] Figure 6 This is a schematic diagram of the substrate structure of the isolation driver chip of this application;

[0063] Figure 7 This is a schematic diagram of an isolation structure of the isolation driver chip of this application;

[0064] Figure 8 This is a schematic diagram of the structure of the third metal layer of the isolation driver chip in this application;

[0065] Figure 9 This is a schematic diagram of the structure of the second metal layer of the isolation driver chip of this application. Detailed Implementation

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0067] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0068] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0069] This application provides a method for manufacturing an isolation transformer circuit, including the following steps:

[0070] Step S10: A silicon dioxide dielectric is deposited on the substrate using plasma-enhanced chemical vapor deposition to form a first silicon dioxide isolation layer.

[0071] Step S20: Sputter a metal film onto the first silicon dioxide isolation layer to form a first metal layer, and integrate the wiring lines of the isolation transformer circuit onto the first metal layer.

[0072] Step S30: A second silicon dioxide isolation layer is formed by depositing a silicon dioxide dielectric on the first metal layer using plasma-enhanced chemical vapor deposition.

[0073] Step S40: Sputter a metal film onto the second silicon dioxide isolation layer to form a second metal layer. Ion etch the input coil or output coil of the isolation transformer circuit onto the second metal layer. The port of the input coil or output coil is connected to the wiring lines on the first metal layer through metal-filled vias.

[0074] In step S50, a silicon dioxide dielectric is deposited on the second metal layer using plasma-enhanced chemical vapor deposition to form a third silicon dioxide isolation layer.

[0075] Step S60: Sputter a metal film onto the third silicon dioxide isolation layer to form a third metal layer. Ion etch the output coil or input coil of the isolation transformer circuit onto the third metal layer, wherein the port of the output coil or input coil is a bonding region.

[0076] In this embodiment, the silicon dioxide dielectric layer is deposited using plasma enhanced chemical vapor deposition (PECVD). After depositing the silicon dioxide isolation layer, SOG (Spin On Glass) is used to flatten the surface of the deposited silicon dioxide isolation layer, and the solvent in the SOG is removed by heating.

[0077] It should be noted that when the spiral coil etched on the second metal layer is the input coil of the isolation transformer circuit, the one on the third metal layer is the output coil of the isolation transformer circuit; similarly, when the spiral coil etched on the second metal layer is the output coil of the isolation transformer circuit, the one on the third metal layer is the input coil of the isolation transformer circuit.

[0078] In step S40, the via (VIA) is formed by using photolithography to create a metal contact hole and filling it with metal; the bonding area in step S60 is also formed using photolithography.

[0079] The method for manufacturing the isolation transformer circuit provided in this application can produce an isolation transformer circuit with a larger isolation drive voltage, so as to provide a larger isolation drive capability.

[0080] Based on the above-described method for manufacturing an isolation transformer circuit, this application provides an isolation drive circuit, which includes an input stage circuit 10, an output stage circuit 30, and an isolation transformer circuit 20 manufactured using the method described above. The input stage circuit 10, the isolation transformer circuit 20, and the output stage circuit 30 are electrically connected.

[0081] The input stage circuit 10 is used to receive input signals, fault signals, and abnormal feedback signals from the output stage circuit 30. It modulates the input signal into a valid input signal for the isolation transformer circuit 20 and transmits the valid input signal to the output stage circuit 30 through the isolation transformer circuit 20. It controls the input stage circuit 10 to disconnect according to the fault signal and demodulates the received abnormal feedback signal.

[0082] The isolation transformer circuit 20 is used to transmit valid input signals to the output stage circuit 30 and to transmit abnormal feedback signals to the input stage circuit 10.

[0083] The output stage circuit 30 is used to demodulate the received valid input signal into a square wave signal and transmit the abnormal feedback signal to the input stage circuit 10 through the isolation transformer circuit 20.

[0084] It should be understood that the input stage circuit 10, the isolation transformer circuit 20, and the output stage circuit 30 are all integrated on the chip to form an isolation driver chip.

[0085] In this embodiment, see Figure 2 As shown, the input stage circuit 10 includes a first ESD protection circuit 101, a first Schmitt trigger circuit 102, a first filter circuit 103, a first logic circuit 104, a first modulation circuit 105, a first demodulation circuit 106, and a fault feedback circuit 107, wherein:

[0086] The first ESD protection circuit 101 is connected to the first Schmitt circuit 102 to release the electrostatic current generated in the circuit, thereby improving the circuit's resistance to ESD (Electro-Static discharge).

[0087] The first Schmitt circuit 102 is connected to the first filter circuit 103 and is used to filter out interference signals.

[0088] The first filter circuit 103 is connected to the first logic circuit 104 and is used to filter out voltage spikes in the input signal.

[0089] The first logic circuit 104 is connected to the first modulation circuit 105, the first demodulation circuit 106 and the fault feedback circuit 107 respectively, and is used to perform logical processing on the input signal, the abnormal feedback signal and the fault signal, and to shut down all outputs of the input stage circuit 10 according to the fault signal and the abnormal feedback signal.

[0090] The first modulation circuit 105 is connected to the isolation transformer circuit 20 and is used to modulate the input signal into an effective input signal of the isolation transformer circuit 20 and transmit the effective input signal to the isolation transformer circuit 20.

[0091] The first demodulation circuit 106 is connected to the isolation transformer circuit 20 and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit 30 and feed it back to the first logic circuit 104.

[0092] The fault feedback circuit 107 is used to output the fault signal through the fault output circuit 112 and feed it back to the first logic circuit 104.

[0093] The first ESD protection circuit 101 is connected to the input port INA, which can filter out ESD interference when the signal is input, and improve the circuit's resistance to ESD (Electro-Static discharge).

[0094] The Schmitt trigger circuit is a flip-flop. When the input voltage is higher than the positive threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output remains unchanged. This double-threshold action of the Schmitt trigger circuit is called hysteresis, which means it has a hysteresis characteristic and can be used to suppress interference.

[0095] The first modulation circuit 104 can modulate the input signal into an effective input signal for the isolation transformer circuit 20, thereby enabling the signal to be transmitted through the isolation transformer circuit 20 to the output stage circuit 30, and thus providing a drive signal.

[0096] When a fault signal, namely the FAULT signal, is present, the fault feedback circuit 107 will output the FAULT signal through the fault output circuit 112 and simultaneously feed the FAULT signal back to the first logic circuit 104, which will then shut down all outputs.

[0097] In some alternative implementations, the input stage circuit 10 may also include a second ESD protection circuit 108, an overcurrent protection circuit 109, and a second filter circuit 110.

[0098] The overcurrent protection circuit 109 is connected to the fault feedback circuit 107 through the second filter circuit 110. It is used to detect the voltage signal fed back by the external sampling circuit. When the voltage signal is greater than the reference voltage, it outputs an overcurrent protection signal and transmits the overcurrent protection signal to the second filter circuit 110.

[0099] The second ESD protection circuit 108 is connected to the second filter circuit 110 through the overcurrent protection circuit 109, and is used to release the electrostatic current generated in the circuit.

[0100] The second filter circuit 110 is used to filter out interference signals of the overcurrent protection signal and transmit the filtered overcurrent protection signal to the fault feedback circuit 107, wherein the overcurrent protection signal serves as the fault signal of the fault feedback circuit 107.

[0101] The second ESD protection circuit 108 is connected to the external sampling circuit through the input terminal ITRIP. The voltage signal of the external sampling circuit is transmitted to the second ESD protection circuit 108 through the input terminal ITRIP. After electrostatic discharge, it is transmitted to the overcurrent protection circuit 109 for detection. The overcurrent protection circuit 109 compares the voltage signal with the internal reference voltage. When the voltage signal is greater than the reference voltage, the overcurrent protection circuit 109 outputs an overcurrent protection signal to the first logic circuit 104 through the fault feedback circuit 107. At this time, the overcurrent protection signal is the fault signal. The fault feedback circuit 107 outputs the fault signal through the fault output circuit 112 and simultaneously shuts off all outputs through the first logic circuit 104.

[0102] In this embodiment, the input stage circuit 10 further includes a temperature detection circuit 111, which is connected to the fault feedback circuit 107 and is used to detect the temperature of the circuit. When the temperature is higher than a first preset threshold, an over-temperature protection signal is output to the fault feedback circuit 107, wherein the over-temperature protection signal serves as a fault signal for the fault feedback circuit 107.

[0103] Specifically, the temperature detection circuit 111 can detect the temperature of the chip and output different voltage signals. At the same time, when the chip temperature is higher than the first preset threshold (i.e. a certain limit value), the first logic circuit 104 shuts down all outputs.

[0104] In this embodiment, all outputs of the input stage circuit 10 are the output ports OUTA1 and OUTA2 connected to the first modulation circuit 105.

[0105] In this embodiment, the fault output circuit 112 includes an NMOS transistor, the source of which is grounded, the drain of which is connected to the output terminal FO, and the gate of which is connected to the fault feedback circuit 107. The fault feedback circuit 107 transmits the fault signal to the FO terminal through the NMOS transistor.

[0106] In this embodiment, the first filter capacitor 103, the second filter capacitor 110, and the third filter capacitor 116 can be filters.

[0107] See Figure 4 In this embodiment, the output stage circuit 30 includes a second demodulation circuit 301, a second modulation circuit 302, a third filter circuit 303, an undervoltage protection circuit 304, a second logic circuit 305, a drive and dead-time circuit 306, and an output drive circuit 307.

[0108] The second demodulation circuit 301 is connected between the third filter circuit 303 and the isolation transformer circuit 20, and is used to demodulate the received valid input signal into a square wave signal and send it to the third filter circuit 303.

[0109] The third filter circuit 303 is connected to the second logic circuit 305 and is used to filter out the spike voltage signal of the square wave signal.

[0110] The undervoltage protection circuit 304 is connected to the second logic circuit 305 and is used to detect the power supply voltage of the output stage circuit 30. When the power supply voltage is lower than the second preset threshold, it transmits an undervoltage signal to the second logic circuit 305.

[0111] The second logic circuit 305 is connected to the drive and dead-time circuit 306 and is used to process square wave signals and undervoltage signals.

[0112] The drive and dead-time circuit 306 is connected to the output drive circuit 307 and connected to the VB terminal of the power supply voltage. It is used to amplify the signal output by the second logic circuit 305 to drive the output drive circuit 307 and generate dead-time characteristics for the output drive circuit 307.

[0113] The second modulation circuit 302 is connected between the second logic circuit 305 and the isolation transformer circuit 20, and is used to transmit the abnormal feedback signal output by the second logic circuit 305 to the input stage circuit 10.

[0114] See Figure 4As shown, the output drive circuit 307 is connected in parallel across the VB and VS terminals of the power supply voltage. It includes output transistors D1 and D2 and integrated drive resistors R1 and R2. Both D1 and D2 are NMOS transistors. Specifically, the drain of D1 is connected to the VB terminal, the gate of D1 is connected to the drive and dead-time circuit 306, the source of D1 is connected to resistor R1, resistors R1 and R2 are connected in series to the drain of D2, the gate of D2 is connected to the drive and dead-time circuit 306, the source of D2 is connected to the VS terminal, and the common connection point of resistors R1 and R2 is connected to the drive and dead-time circuit 306.

[0115] The second demodulation circuit 301 demodulates the valid input signal transmitted from the isolation transformer circuit 20 into a square wave signal. The square wave signal is used as a drive signal and transmitted to the drive and dead-time circuit 306. After being output by the drive and dead-time circuit 306 to the common connection point of resistors R1 and R2, drive signals are distributed to D1 and D2 through resistors R1 and R2.

[0116] After the square wave signal is transmitted to the drive and dead-time circuit 306, it is amplified step by step to an order of magnitude sufficient to drive transistors D1 and D2, and then output to drive the output transistors D1 and D2. Simultaneously, the drive and dead-time circuit 306 can create a dead-time characteristic in the output transistors. When the drive signal simultaneously satisfies the conduction conditions of both output transistors D1 and D2, it controls them to turn off. The turn-off principle is "turn off first, then turn on," preventing simultaneous conduction of output transistors D1 and D2 and thus avoiding a short circuit.

[0117] The third filter circuit 303 is used to filter out spike voltage signals coupled from internal or external circuits. The undervoltage protection circuit 304 is used to detect the voltage across VB-VS. When the voltage is lower than the second preset threshold, the undervoltage protection circuit 304 activates, transmitting an undervoltage signal to the second logic circuit 305, thus shutting down the output signal of the output stage circuit 30. The second logic circuit 305 is used to synthesize and process the signal logic of the output stage circuit 30.

[0118] In this embodiment, when the output stage circuit 30 has a fault, the second logic circuit 305 generates an abnormal feedback signal and transmits it to the second modulation circuit 302. The second modulation circuit 302 modulates the abnormal feedback signal into a valid input signal of the isolation transformer circuit 20, which is then transmitted to the input stage circuit 10 through the isolation transformer circuit 20. After being demodulated by the first demodulation circuit 106 of the input stage circuit 10, the signal is transmitted to the first logic circuit 104, which then shuts off all outputs.

[0119] See Figure 5As shown, in this embodiment, the isolation transformer circuit 20 includes a first isolation transformer 201 and a second isolation transformer 202. The input coil includes a first input coil and a second input coil, and the output coil includes a first output coil and a second output coil. The first isolation transformer 201 includes a first input coil and a first output coil. The first input coil is connected to the input stage circuit 10, and the first output coil is connected to the output stage circuit 30, used to transmit valid input signals sequentially through the first input coil and the first output coil to the output stage circuit 30. The second isolation transformer 202 includes a second input coil and a second output coil. The second input coil is connected to the output stage circuit 30, and the second output coil is connected to the input stage circuit 10, used to transmit abnormal feedback signals sequentially through the second input coil and the second output coil to the input stage circuit 10.

[0120] The input terminals IN1 and IN2 of the first input coil of the first isolation transformer 201 are connected to the output terminals OUTA1 and OUTA2 of the first modulation circuit, and the output terminals OUT1 and OUT2 of the first output coil are connected to the input terminals IND1 and IND2 of the second demodulation circuit. The input terminals IN3 and IN4 of the second input coil of the second isolation transformer 202 are connected to the output terminals OUTM1 and OUTM2 of the second modulation circuit, and the output terminals OUT3 and OUT4 of the second output coil are connected to the input terminals INA1 and INA2 of the first demodulation circuit.

[0121] See Figures 7 to 9 As shown, in this embodiment, the isolation transformer circuit 20 uses integrated circuit technology to fabricate structures such as input coils, output coils, and magnetic cores on a chip. When the first input coil and the second input coil are disposed on the second metal layer 42, and the first output coil and the second output coil are disposed on the third metal layer 43, the input terminals IN1 and IN2 of the first input coil and the input terminals IN3 and IN4 of the second input coil are connected to the wiring lines of the first metal layer 41 through vias. The output terminals OUT1 and OUT2 of the first output coil and the output terminals OUT3 and OUT4 of the second output coil are bonding areas, which are connected to the wiring lines of the first metal layer 41 through the bonding areas. When the first input coil and the second input coil are disposed on the third metal layer 43, and the first output coil and the second output coil are disposed on the second metal layer 42, the input terminals IN1 and IN2 of the first input coil and the input terminals IN3 and IN4 of the second input coil are bonding areas, which are connected to the wiring lines of the first metal layer 41 through the bonding areas. The output terminals OUT1 and OUT2 of the first output coil and the output terminals OUT3 and OUT4 of the second output coil are connected to the wiring lines of the first metal layer 41 through vias.

[0122] In this embodiment, the coil of the isolation transformer can be a helical coil, see [reference]. Figure 8 and Figure 9 As shown, the spiral coils of the second metal layer 42 and the third metal layer 43 overlap to form electromagnetic coupling, so that the signal of the coil of the second metal layer 42 is coupled to the coil of the third metal layer 43, thus completing the isolated signal transmission.

[0123] It should be noted that the input coil and the output coil have an isolation capability of over 2000V.

[0124] In some alternative implementations, when the input stage circuit 10 is in dual-input port mode, see [reference needed]. Figure 3 As shown, the input ports are INA and INB. The input stage circuit 10 also includes a dead time interlock circuit 113, a third ESD protection circuit 114, a second Schmitt circuit 115, a fourth filter circuit 116, a third modulation circuit 117, and a third demodulation circuit 118.

[0125] Among them, the dead time interlock circuit 113 is connected between the first filter circuit 103, the fourth filter circuit 116 and the first logic circuit 104, and is used to output an interlock signal when at least two input signals are high level, and send the interlock signal to the first logic circuit 104.

[0126] The third ESD protection circuit 114 is connected to the second Schmitt circuit 115 to release the electrostatic current generated in the circuit.

[0127] The second Schmitt circuit 115 is connected to the fourth filter circuit 116 and is used to filter out interference signals.

[0128] The fourth filter circuit 116 is connected to the dead-time interlock circuit 113 and is used to filter out input signal spike voltage.

[0129] The first logic circuit 104 is connected to the third modulation circuit 117 and the third demodulation circuit 118 respectively, and is used to turn off the output corresponding to the input signal according to the interlock signal.

[0130] The third modulation circuit 117 is connected to the isolation transformer circuit 20 and is used to modulate the input signal into an effective input signal of the isolation transformer circuit 20 and transmit the effective input signal to the isolation transformer circuit.

[0131] The third demodulation circuit 118 is connected to the isolation transformer circuit 20 and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit 30 and feed it back to the first logic circuit 104.

[0132] When the input stage circuit 10 is in dual-input mode, in order to avoid the outputs corresponding to the two inputs being turned on at the same time and causing a short circuit, the two outputs of the input stage circuit 10 need to be interlocked by the dead time interlock circuit 113. The two outputs are output ports OUTA1 and OUTA2 output through the first modulation circuit 105 and output ports OUTB1 and OUTB2 output through the third modulation circuit 117.

[0133] Specifically, when both input signals are high, the dead time interlock circuit 113 outputs an interlock signal to the first logic circuit 104, which then turns off both outputs. The principle of turning off is "turn off first, then turn on". This prevents both outputs from being turned on at the same time. At the same time, the two signals will have a brief simultaneous turn-off time, which is the dead time.

[0134] In this embodiment, when the input stage circuit 10 is in dual-input mode, the isolation transformer circuit 20 is also a dual-isolation transformer circuit.

[0135] Specifically, when the input stage circuit 10 is in dual-input mode, the input ports are INA and INB respectively. The dual isolation transformer circuit 20 includes a first isolation transformer 201, a second isolation transformer 202, a third isolation transformer (not shown in the figure), and a fourth isolation transformer (not shown in the figure). The connection method corresponding to the input port INA is described in [reference needed]. Figure 5 As shown, the circuit connection method corresponding to the input port INB is as follows:

[0136] The input terminals IN5 and IN6 of the third input coil of the third isolation transformer are connected to the output terminals OUTB1 and OUTB2 of the third modulation circuit, respectively. The output terminals OUT5 and OUT6 of the third output coil are connected to the input terminals IND3 and IND4 of the fourth demodulation circuit, respectively. The input terminals IN7 and IN8 of the fourth input coil of the fourth isolation transformer are connected to the output terminals OUTM3 and OUTM4 of the second modulation circuit, respectively. The output terminals OUT7 and OUT8 of the second output coil are connected to the input terminals INB1 and INB2 of the first demodulation circuit, respectively.

[0137] In some alternative implementations, when the input stage circuit 10 is in multi-input port mode, i.e., with three or more input ports, the structure of the input stage circuit 10 is the same as that of the dual-input port circuit described above, except that the number of input ports is increased, and modulation and demodulation circuits are set up to match the number of input ports. Similarly, an isolation transformer circuit is set up to match the number of input ports.

[0138] The isolation drive circuit provided in this application provides an input stage circuit that modulates the input signal into an effective input signal for the isolation transformer circuit. This signal is then transmitted to the output stage circuit via the isolation transformer circuit and demodulated by the output stage circuit. This process avoids waveform distortion of the drive signal, improves drive capability, and also shortens transmission delay and increases transmission speed.

[0139] Based on the above-described isolation driver circuit, this application also provides an isolation driver chip, see [link to relevant documentation]. Figures 6 to 9 As shown, the chip includes a substrate 4 and the isolation drive circuit described above. The input stage circuit 10 and the output stage circuit 30 of the isolation drive circuit are integrated on the substrate 4, see [reference needed]. Figure 6 As shown, a first metal layer 41, a second metal layer 42, and a third metal layer 43 are sequentially disposed on the substrate 40. A silicon dioxide isolation layer 44 is located between the substrate 40, the first metal layer 41, the second metal layer 42, and the third metal layer 43. The silicon dioxide isolation layer 44 includes a first silicon dioxide isolation layer, a second silicon dioxide isolation layer, and a third silicon dioxide isolation layer. The wiring lines of the input stage circuit 10 and the output stage circuit 30 are encapsulated in the first metal layer 41, which is also referred to as the wiring layer.

[0140] The components of the isolation drive circuit include PMOS transistors, NMOS transistors, transistors, diodes, Zener diodes, resistors, and capacitors. High-voltage isolation is used between the components; oxygen injection isolation is used between high-voltage and low-voltage components, and between high-voltage components of different phases. A silicon dioxide isolation region is formed between the components, and a silicon dioxide isolation layer is used between the components and the substrate.

[0141] It should be noted that when the input stage circuit 10, isolation transformer circuit 20, and output stage circuit 30 of the isolation driver circuit are integrated on the same chip, the substrates are the same; when the input stage circuit 10, isolation transformer circuit 20, and output stage circuit 30 of the isolation driver circuit are integrated on different chips, the substrates are different. The number of substrates corresponds to the number of chips used in the isolation driver chip.

[0142] In this embodiment, the isolation driver chip can be a multi-chip (integrated circuit, IC) or a single-chip solution. When using a multi-chip solution, bonding wires are used to connect the bonding areas of the input stage circuit 10, the isolation transformer circuit 20, and the output stage circuit 30. When using a single-chip solution, bonding wires are used to connect the bonding area (PAD) of the isolation transformer circuit to the bonding area (PAD) of the input stage circuit or the output stage circuit.

[0143] In this embodiment, the isolation structure between devices and the isolation structure between device substrates can be designed and fabricated using SOI technology.

[0144] Specifically, the substrate is an SOI substrate, including a back substrate 401, a silicon dioxide layer 402, and a top silicon layer 403. The SOI substrate is fabricated using the SOI process, which involves introducing a buried oxide layer between the back substrate 401 and the top silicon layer 403. The buried oxide layer can be a silicon dioxide layer, used to isolate the back substrate 401 and the top silicon layer 403. The top silicon layer 403 is used for integrated circuit devices.

[0145] In some optional implementations of this embodiment, the avalanche breakdown voltage (i.e., the avalanche breakdown voltage between devices) of the silicon dioxide isolation region 404 is greater than twice the withstand voltage rating of the isolation driver chip; the avalanche breakdown voltage of the silicon dioxide layer 402 is greater than twice the withstand voltage rating of the isolation driver chip.

[0146] For example, when the HVIC isolation voltage is 1200V, the avalanche breakdown voltage between devices must be greater than 2400V; when the HVIC isolation voltage is 1700V, the avalanche breakdown voltage between devices must be greater than 3400V. When the IC isolation voltage is 1200V, the avalanche breakdown voltage of the silicon dioxide layer must be greater than 2400V; when the IC isolation voltage is 1700V, the avalanche breakdown voltage of the silicon dioxide layer must be greater than 3400V.

[0147] In this embodiment, the isolation spacing of the silicon dioxide isolation region between high-voltage devices and the isolation spacing of the silicon dioxide layer between the back substrate and the device can be selected through DOE (Design of Experiment) experiments to ensure that the withstand voltage is high enough without making the spacing too large and occupying too much chip area.

[0148] The isolation driver chip in this application embodiment can achieve isolation driving at 600V, 1200V or even higher voltages, and has the advantages of large driving capability and short transmission delay. At the same time, it adopts a chip-level isolation transformer to realize the miniaturization and integration of SiC MOSFET driving circuit. The SiC MOSFET isolation driver chip greatly reduces the size of SiC IPM.

[0149] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A method for manufacturing an isolation transformer circuit, characterized in that, Includes the following steps: A first silicon dioxide isolation layer is formed by depositing a silicon dioxide dielectric on a substrate using plasma-enhanced chemical vapor deposition. A metal film is sputtered onto the first silicon dioxide isolation layer to form a first metal layer, and the wiring of the isolation transformer circuit is integrated on the first metal layer. A second silicon dioxide isolation layer is formed by depositing a silicon dioxide dielectric on the first metal layer using plasma-enhanced chemical vapor deposition. A metal film is sputtered onto the second silicon dioxide isolation layer to form a second metal layer. The input coil or output coil of the isolation transformer circuit is ion etched onto the second metal layer. The port of the input coil or the output coil is connected to the wiring lines on the first metal layer through metal-filled vias. A third silicon dioxide insulating layer is formed by depositing a silicon dioxide dielectric on the second metal layer using plasma-enhanced chemical vapor deposition. A metal film is sputtered onto the third silicon dioxide isolation layer to form a third metal layer. The output coil or input coil of the isolation transformer circuit is ion etched onto the third metal layer, wherein the port of the output coil or input coil is a bonding region.

2. An isolated drive circuit, characterized in that, include: The input stage circuit, the output stage circuit, and the isolation transformer circuit obtained by the method of manufacturing the isolation transformer circuit according to claim 1 are electrically connected to each other. The input stage circuit is used to receive input signals, fault signals, and abnormal feedback signals from the output stage circuit. It modulates the input signals into valid input signals for the isolation transformer circuit and transmits the valid input signals to the output stage circuit through the isolation transformer circuit. It shuts off the output of the input stage circuit according to the fault signal and demodulates the received abnormal feedback signals. The isolation transformer circuit is used to transmit the valid input signal to the output stage circuit, and to transmit the abnormal feedback signal to the input stage circuit; The output stage circuit is used to demodulate the received valid input signal into a square wave signal and transmit the abnormal feedback signal to the input stage circuit through the isolation transformer circuit.

3. The isolated drive circuit according to claim 2, characterized in that, The input stage circuit includes a first ESD protection circuit, a first Schmitt trigger circuit, a first filter circuit, a first logic circuit, a first modulation circuit, a first demodulation circuit, and a fault feedback circuit, wherein: The first ESD protection circuit is connected to the first Schmitt circuit to release the electrostatic current generated in the circuit. The first Schmitt circuit is connected to the first filter circuit to filter out interference signals; The first filter circuit is connected to the first logic circuit and is used to filter out voltage spikes in the input signal. The first logic circuit is connected to the first modulation circuit, the first demodulation circuit, and the fault feedback circuit respectively, and is used to perform logical processing on the input signal, the abnormal feedback signal, and the fault signal, and to shut down all outputs of the input stage circuit according to the fault signal and the abnormal feedback signal. The first modulation circuit is connected to the isolation transformer circuit and is used to modulate the input signal into an effective input signal for the isolation transformer circuit, and transmit the effective input signal to the isolation transformer circuit. The first demodulation circuit is connected to the isolation transformer circuit and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit and feed it back to the first logic circuit. The fault feedback circuit is used to output the fault signal through the fault output circuit and feed it back to the first logic circuit.

4. The isolated drive circuit according to claim 3, characterized in that, The input stage circuit also includes a second ESD protection circuit, an overcurrent protection circuit, and a second filter circuit; The overcurrent protection circuit is connected to the fault feedback circuit through the second filter circuit. It is used to detect the voltage signal fed back by the external sampling circuit. When the voltage signal is greater than the reference voltage, it outputs an overcurrent protection signal and transmits the overcurrent protection signal to the second filter circuit. The second ESD protection circuit is connected to the second filter circuit through the overcurrent protection circuit to release the electrostatic current generated in the circuit; The second filtering circuit is used to filter out interference signals from the overcurrent protection signal and transmit the filtered overcurrent protection signal to the fault feedback circuit, wherein the overcurrent protection signal serves as a fault signal for the fault feedback circuit.

5. The isolated drive circuit according to claim 2, characterized in that, The output stage circuit includes a second demodulation circuit, a second modulation circuit, a third filter circuit, an undervoltage protection circuit, a second logic circuit, a drive and dead-time circuit, and an output drive circuit. The second demodulation circuit is connected between the third filter circuit and the isolation transformer circuit, and is used to demodulate the received valid input signal into a square wave signal and send it to the third filter circuit. The third filtering circuit is connected to the second logic circuit and is used to filter out the spike voltage signal of the square wave signal; The undervoltage protection circuit is connected to the second logic circuit and is used to detect the power supply voltage of the output stage circuit. When the power supply voltage is lower than the second preset threshold, it transmits an undervoltage signal to the second logic circuit. The second logic circuit is connected to the drive and dead-time circuit and is used to process the square wave signal and the undervoltage signal; The drive and dead-time circuits are connected to the output drive circuit and to the power supply voltage, and are used to amplify the signal output by the second logic circuit to drive the output drive circuit and generate dead-time characteristics for the output drive circuit. The second modulation circuit is connected between the second logic circuit and the isolation transformer circuit, and is used to transmit the abnormal feedback signal output by the second logic circuit to the input stage circuit.

6. The isolated drive circuit according to claim 2, characterized in that, The isolation transformer circuit includes a first isolation transformer and a second isolation transformer, the input coil includes a first input coil and a second input coil, and the output coil includes a first output coil and a second output coil; The first isolation transformer includes a first input coil and a first output coil. The first input coil is connected to the input stage circuit, and the first output coil is connected to the output stage circuit. It is used to transmit the valid input signal to the output stage circuit in sequence through the first input coil and the first output coil. The second isolation transformer includes a second input coil and a second output coil. The second input coil is connected to the output stage circuit, and the second output coil is connected to the input stage circuit. It is used to transmit the abnormal feedback signal to the input stage circuit in sequence through the second input coil and the second output coil.

7. The isolated drive circuit according to claim 3, characterized in that, The input stage circuit also includes a dead-time interlock circuit, a third ESD protection circuit, a second Schmitt circuit, a fourth filter circuit, a third modulation circuit, and a third demodulation circuit. The dead-time interlock circuit is connected between the first filter circuit, the fourth filter circuit and the first logic circuit, and is used to output an interlock signal when at least two input signals are high level, and send the interlock signal to the first logic circuit. The third ESD protection circuit is connected to the second Schmitt circuit and is used to release the electrostatic current generated in the circuit. The second Schmitt circuit is connected to the fourth filter circuit to filter out interference signals; The fourth filtering circuit is connected to the dead-time interlock circuit and is used to filter out input signal spike voltage. The first logic circuit is connected to the third modulation circuit and the third demodulation circuit respectively, and is used to turn off the output corresponding to the input signal according to the interlock signal; The third modulation circuit is connected to the isolation transformer circuit and is used to modulate the input signal into an effective input signal for the isolation transformer circuit, and transmit the effective input signal to the isolation transformer circuit. The third demodulation circuit is connected to the isolation transformer circuit and is used to demodulate the abnormal feedback signal transmitted by the output stage circuit and feed it back to the first logic circuit.

8. An isolated driver chip, characterized in that, Includes a substrate and the isolation drive circuit according to any one of claims 2 to 7; The input stage circuit and the output stage circuit of the isolation driving circuit are integrated on the substrate, and the wiring of the input stage circuit and the output stage circuit are encapsulated in the first metal layer. The input stage circuit and the output stage circuit are connected to the isolation transformer circuit of the isolation drive circuit through the bonding region.

9. The isolation driver chip according to claim 8, characterized in that, The substrate is an SOI substrate, which includes a back substrate, a silicon dioxide layer, and a top silicon layer. The top silicon layer of the SOI substrate is used to integrate the devices of the input stage circuit and the output stage circuit, and a silicon dioxide isolation region is formed between the devices.

10. The isolation driver chip according to claim 9, characterized in that, The avalanche breakdown voltage of the silicon dioxide isolation region is greater than twice the withstand voltage rating of the isolation driver chip; the avalanche breakdown voltage of the silicon dioxide layer is greater than twice the withstand voltage rating of the isolation driver chip.

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