Multilayer ceramic capacitor and mounting structure of multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor and a mounting structure of a multilayer ceramic capacitor, which can improve low ESL characteristics. The multilayer ceramic capacitor includes a laminate and first to fourth external electrodes. A first internal electrode layer has a first opposing electrode portion opposite a second internal electrode layer, a first lead-out electrode portion extending from the first opposing electrode portion and leading out to a first end surface, and a second lead-out electrode portion extending from the first opposing electrode portion and leading out to a second end surface. The second internal electrode layer has a second opposing electrode portion opposite the first internal electrode layer, a third lead-out electrode portion extending from the second opposing electrode portion and leading out to a first side surface, and a fourth lead-out electrode portion extending from the second opposing electrode portion and leading out to a second side surface. The first and second lead-out electrode portions each have a first and second curved portion, respectively, by which a portion or all of the first and second lead-out electrode portions are curved to face either of a first main surface or a second main surface.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors and their mounting structures. Background Technology

[0002] Previously, three-terminal multilayer ceramic capacitors were known as decoupling capacitors used to stabilize the power supply voltage supplied to high-speed integrated circuit components (ICs).

[0003] Three-terminal multilayer ceramic capacitors typically have a ceramic body with a rectangular outer surface, which includes an upper and lower surface opposite each other in the thickness direction, two side surfaces opposite each other in the width direction, and two end surfaces opposite each other in the length direction.

[0004] Inside the ceramic body, multiple first internal electrodes and second internal electrodes are alternately arranged in the stacking direction. Furthermore, the two ends of the first internal electrodes extend in a direction orthogonal to the stacking direction and are exposed on both end faces of the ceramic body, where they are connected to external electrodes. Similarly, the two ends of the second internal electrodes extend in a direction orthogonal to the stacking direction and are exposed on a first side face and a second side face, where they are connected to external electrodes on both sides of the ceramic body (see, for example, Patent Document 1).

[0005] Prior art literature

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-201417 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] In order to obtain good performance of three-terminal multilayer ceramic capacitors, it is preferable to suppress the value of equivalent series inductance (hereinafter referred to as ESL) to a low level (hereinafter referred to as low ESL characteristic).

[0010] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor that can improve low ESL characteristics.

[0011] means for solving problems

[0012] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; a third external electrode disposed on the first side surface; and a fourth external electrode disposed on the second side surface, wherein the multilayer body has an inner layer portion with the plurality of internal electrode layers opposite to each other, the plurality of internal electrode layers having a first internal electrode layer and a second internal electrode layer, the first internal electrode layer having a first internal electrode layer and a second internal electrode layer opposite to the second internal electrode layer. The first internal electrode layer has a first opposing electrode portion, a first lead-out electrode portion extending from the first opposing electrode portion and leading to a first end face, and a second lead-out electrode portion extending from the first opposing electrode portion and leading to a second end face. The second internal electrode layer has a second opposing electrode portion opposite to the first internal electrode layer, a third lead-out electrode portion extending from the second opposing electrode portion and leading to a first side face, and a fourth lead-out electrode portion extending from the second opposing electrode portion and leading to a second side face. The first lead-out electrode portion has a first bending portion, and the second lead-out electrode portion has a second bending portion. Through the first bending portion, a portion or all of the first lead-out electrode portion is configured to face either the first main face or the second main face. Through the second bending portion, a portion or all of the second lead-out electrode portion is configured to face either the first main face or the second main face.

[0013] The three-terminal multilayer ceramic capacitor of the present invention has a first bent portion and a second bent portion in the first internal electrode layer. The first bent portion is used to configure part or all of the first lead electrode portion toward either the first main surface or the second main surface, and the second bent portion is used to configure part or all of the second lead electrode portion toward either the first main surface or the second main surface. As a result, compared with the prior art, the current path from the first internal electrode layer to the mounting substrate can be shortened.

[0014] This improves the low ESL characteristics of three-terminal multilayer ceramic capacitors.

[0015] Furthermore, the mounting structure of the multilayer ceramic capacitor of the present invention includes a mounting substrate and a multilayer ceramic capacitor mounted on the mounting substrate. The multilayer ceramic capacitor is the multilayer ceramic capacitor of the present invention. The mounting substrate has: a core material of the substrate; a first connecting conductor disposed on the core material and connected to a first external electrode; a second connecting conductor disposed on the core material and connected to a second external electrode; a third connecting conductor disposed on the core material and connected to a third external electrode; and a fourth connecting conductor disposed on the core material and connected to a fourth external electrode. The multilayer ceramic capacitor is mounted such that the first main surface or the second main surface faces the mounting substrate side, such that the distance between the first lead-out electrode portion and the second lead-out electrode portion extending to the first end surface and the second end surface closest to the first main surface or the second main surface and the mounting surface of the mounting substrate is the shortest distance.

[0016] Furthermore, the mounting structure of the three-terminal multilayer ceramic capacitor of the present invention directly reflects the various functions of the three-terminal multilayer ceramic capacitor of the present invention, and compared with the prior art, it can shorten the current path from the first internal electrode layer of the three-terminal multilayer ceramic capacitor to the mounting substrate. As a result, it achieves the effect of reflecting the various effects of the three-terminal multilayer ceramic capacitor of the present invention and improving the low ESL characteristics in the mounting structure of the three-terminal multilayer ceramic capacitor.

[0017] Invention Effects

[0018] According to the present invention, a multilayer ceramic capacitor capable of improving low ESL characteristics and a mounting structure for the multilayer ceramic capacitor can be provided.

[0019] The above-mentioned objects, other objects, features, and advantages of the present invention will become clearer from the following detailed description of the embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a perspective view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0021] Figure 2 This is a top view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0022] Figure 3 This is a front view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0023] Figure 4 yes Figure 1 A cross-sectional view at line IV-IV.

[0024] Figure 5 yes Figure 1 A cross-sectional view at line VV.

[0025] Figure 6 This is a top view showing the structure of the first internal electrode layer of a three-terminal type multilayer ceramic capacitor according to a first embodiment of the present invention.

[0026] Figure 7 This is a top view showing the structure of the second internal electrode layer of a three-terminal type multilayer ceramic capacitor according to a first embodiment of the present invention.

[0027] Figure 8 yes Figure 4 A cross-sectional view at line VIII-VIII.

[0028] Figure 9 (a) is shown Figure 4 The enlarged view of region R1 is a cross-sectional schematic diagram illustrating the function of the three-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 9 (b) is shown Figure 4 The enlarged view of region R2 is a cross-sectional schematic diagram illustrating the function of the three-terminal multilayer ceramic capacitor according to the first embodiment of the present invention.

[0029] Figure 10 This is a top view showing the structure of another example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0030] Figure 11 This is a top view showing the structure of another example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0031] Figure 12 This is a top view showing the structure of another example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0032] Figure 13 This is a cross-sectional view showing an example of the mounting structure of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0033] Figure 14 This is a cross-sectional view showing an example of the mounting structure of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention.

[0034] Figure 15 This is a perspective view showing an example of a three-terminal type multilayer ceramic capacitor according to a second embodiment of the present invention.

[0035] Figure 16 yes Figure 15 A cross-sectional view at line XVI-XVI.

[0036] Figure 17 yes Figure 15 A cross-sectional view along line XVII-XVII.

[0037] Figure 18 This is a top view showing the structure of the second internal electrode layer of a three-terminal type multilayer ceramic capacitor according to a second embodiment of the present invention.

[0038] Figure 19 (a) is shown Figure 17 The enlarged view of region R3 is a cross-sectional schematic diagram illustrating other functions of the three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. Figure 19 (b) is shown Figure 17 The enlarged view of region R4 is a cross-sectional schematic diagram illustrating other functions of the three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention.

[0039] Figure 20 This is a cross-sectional view showing an example of the mounting structure of a three-terminal type multilayer ceramic capacitor according to a second embodiment of the present invention.

[0040] Figure 21 This is a cross-sectional view showing the structure of a conventional three-terminal multilayer ceramic capacitor.

[0041] Explanation of reference numerals in the attached figures

[0042] 100, 200 three-terminal multilayer ceramic capacitors;

[0043] Mounting structure of 500 and 600 three-terminal multilayer ceramic capacitors;

[0044] 10-layer stack;

[0045] 10a First main face;

[0046] 10b Second main face;

[0047] 10c First side view;

[0048] 10d Second side view;

[0049] 10e First end face;

[0050] 10f Second end face;

[0051] 12. Dielectric layer;

[0052] 14. Inner layer;

[0053] 16a First main surface side outer layer;

[0054] 16b Second main surface outer layer;

[0055] 16c First side outer layer;

[0056] 16d Second side outer layer;

[0057] 16e First end face side outer layer;

[0058] 16f Second end face side outer layer;

[0059] 20. Internal electrode layer;

[0060] 21, 21a, 21b, 21c, 21d First internal electrode layer;

[0061] 23a, 23b, 23c, 23d First opposing electrode section;

[0062] 25a, 25b, 25c, 25d First end face side electrode section;

[0063] 27a, 27b, 27c, 27d Second end face side electrode section;

[0064] 22, 22a, 22b, 22c, 22d Second internal electrode layer;

[0065] 24a, 24b, 24c, 24d Second opposing electrode section;

[0066] 26a, 26b, 26c, 26d First side side electrode leads;

[0067] 28a, 28b, 28c, 22d Second side side electrode leads;

[0068] 29a First bend;

[0069] 29b Second bend;

[0070] 29c Third bend;

[0071] 29d Fourth bend;

[0072] 30 External electrodes;

[0073] 30a First external electrode;

[0074] 30b Second external electrode;

[0075] 30c Third external electrode;

[0076] 30d Fourth external electrode;

[0077] 32. Substrate electrode layer;

[0078] 32a First substrate electrode layer;

[0079] 32b Second base electrode layer;

[0080] 32c Third base electrode layer;

[0081] 32d Fourth base electrode layer;

[0082] 34. Coating layer;

[0083] 34a First plating layer;

[0084] 34b Second plating layer;

[0085] 34c Third plating layer;

[0086] 34d Fourth coating layer;

[0087] 36. Lower plating layer;

[0088] 36a First lower plating layer;

[0089] 36b Second lower plating layer;

[0090] 36c Third lower plating layer;

[0091] 36d Fourth lower plating layer;

[0092] 38. Top coating layer;

[0093] 38a First upper plating layer;

[0094] 38b Second upper coating layer;

[0095] 38c Third upper plating layer;

[0096] 38d Fourth upper coating layer;

[0097] 50 Mounting substrate;

[0098] 51 core material;

[0099] 51a Substrate-side mounting surface;

[0100] 52 Conductor pads;

[0101] 52a First conductor pad;

[0102] 52b Second conductor pad;

[0103] 52c Third conductor pad;

[0104] 52d Fourth conductor pad;

[0105] x indicates the stacking direction;

[0106] y represents the width direction;

[0107] z represents the length direction. Detailed Implementation

[0108] A. First Implementation Method

[0109] a. Three-terminal multilayer ceramic capacitor

[0110] As an example of a three-terminal multilayer ceramic capacitor according to the first embodiment of the present invention, a three-terminal multilayer ceramic capacitor 100 will be described.

[0111] Figure 1 This is a perspective view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 This is a top view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 This is a front view showing an example of a three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 4 yes Figure 1 A cross-sectional view at line IV-IV. Figure 5 yes Figure 1 A cross-sectional view at line VV.

[0112] like Figures 1 to 5 As shown, the three-terminal multilayer ceramic capacitor 100 includes a multilayer body 10 and an external electrode 30 disposed on the surface of the multilayer body 10.

[0113] The stack 10 is cuboid in shape and has multiple stacked dielectric layers 12 and multiple internal electrode layers 20 stacked on the dielectric layers 12. Each of the multiple internal electrode layers 20 is individually disposed on each of the dielectric layers 12. Therefore, the multiple internal electrode layers 20 are disposed between each of the stacked dielectric layers 12.

[0114] Furthermore, the laminate 10 has a first main surface 10a and a second main surface 10b facing each other, a first side surface 10c and a second side surface 10d connecting the first main surface 10a and the second main surface 10b and facing each other, and a first end surface 10e and a second end surface 10f connecting the first main surface 10a and the second main surface 10b and facing each other in a direction orthogonal to the first side surface 10c and the second side surface 10d. The corners and edges of the laminate 10 are rounded. It should be noted that a corner refers to the part where three adjacent surfaces of the laminate 10 intersect, and an edge is the part where two adjacent surfaces of the laminate 10 intersect.

[0115] The first main surface 10a and the second main surface 10b, the first side surface 10c and the second side surface 10d, and the first end surface 10e and the second end surface 10f may also have concave or convex shapes formed in all or part of them.

[0116] Here, the direction connecting the first main surface 10a and the second main surface 10b of the laminate 10 is defined as the lamination direction x; the direction connecting the first side surface 10c and the second side surface 10d, which is orthogonal to the lamination direction x, is defined as the width direction y; and the direction connecting the first end surface 10e and the second end surface 10f, which is orthogonal to both the lamination direction x and the width direction y, is defined as the length direction z. Furthermore, in the following description, regarding the three-terminal type laminated ceramic capacitor 100 including the laminate 10, the first external electrode 30a, and the second external electrode 30b, its dimension in the length direction z is referred to as the L dimension, its dimension in the lamination direction x is referred to as the T dimension, and its dimension in the width direction y is referred to as the W dimension. These terms will be used in the following description.

[0117] In the stack 10, multiple dielectric layers 12 and multiple internal electrode layers 20 are stacked along the stacking direction x.

[0118] The laminate 10 has an inner layer 14, which includes one or more dielectric layers 12 and multiple internal electrode layers 20 disposed on the dielectric layer 12. The internal electrode layers 20 have first internal electrode layers 21 extending to a first end face 10e and a second end face 10f, respectively, and second internal electrode layers 22 extending to a first side face 10c and a second side face 10d, respectively. In the inner layer 14, the multiple first internal electrode layers 21 and second internal electrode layers 22 are positioned opposite each other with respect to the dielectric layer 12, exhibiting the characteristics of a capacitor that stores charge.

[0119] The laminate 10 has a first main surface side outer layer 16a, which is located on the side of the first main surface 10a and is formed by a plurality of dielectric layers 12 located between the outermost surface of the inner layer 14 on the side of the first main surface 10a and the plane including the outermost surface.

[0120] Similarly, the laminate 10 has a second main surface side outer layer 16b, which is located on the side of the second main surface 10b and is formed by a plurality of dielectric layers 12 between the outermost surface of the inner layer 14 located on the side of the second main surface 10b and the plane including the outermost surface.

[0121] The laminate 10 has a first side outer layer 16c, which is located on the side of the first side 10c and is formed by a plurality of dielectric layers 12 located between the outermost surfaces of the inner layer 14 on the side of the first side 10c.

[0122] Similarly, the laminate 10 has a second side outer layer 16d located on the second side 10d side and formed by a plurality of dielectric layers 12 located between the outermost surfaces of the inner layer 14 on the second side 10d side.

[0123] The laminate 10 has a first end face side outer layer 16e, which is located on the first end face 10e side and is formed by a plurality of dielectric layers 12 located between the first main face side outer layer 16a and the second main face side outer layer 16b and between the outermost surfaces of the inner layer 14 on the first end face 10e side.

[0124] The laminate 10 has a second end face side outer layer 16f, which is located on the second end face 10f side and is formed by a plurality of dielectric layers 12 located between the first main face side outer layer 16a and the second main face side outer layer 16b and between the outermost surfaces of the inner layer 14 on the second end face 10f side.

[0125] The dimensions of the laminate 10 are not particularly limited.

[0126] The dielectric layer 12 can be formed, for example, from a dielectric material that is a ceramic material. Such a dielectric material can be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the aforementioned dielectric material is included as the main component, materials obtained by adding, for example, minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds in smaller amounts than the main component can be used, depending on the desired characteristics of the laminate 10.

[0127] The thickness of the dielectric layer 12 after firing is preferably 0.40 μm or more and 5.0 μm or less (e.g., 0.59 μm). The number of stacked dielectric layers 12 is preferably 30 or more and 2000 or less (e.g., 234). The number of dielectric layers 12 is the total number of dielectric layers 12 constituting the inner layer portion 14 and the number of dielectric layers 12 constituting the first main surface side outer layer portion 16a and the second main surface side outer layer portion 16b.

[0128] The laminate 10 has a plurality of first internal electrode layers 21 and a plurality of second internal electrode layers 22 as a plurality of internal electrode layers 20. The plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 are embedded in a manner that alternates at equal intervals along the lamination direction x of the laminate 10, separated by a dielectric layer 12.

[0129] It should be noted that, for the sake of simplicity, in the figures, it is assumed that the plurality of first internal electrode layers 21 have four first internal electrode layers 21a, 21b, 21c, and 21d arranged sequentially from top to bottom along the stacking direction x, and the plurality of second internal electrode layers 22 have four second internal electrode layers 22a, 22b, 22c, and 22d arranged sequentially from top to bottom along the stacking direction x. However, these are examples, and the number of first internal electrode layers 21 and second internal electrode layers 22 can be any number other than those described in the examples below.

[0130] The first internal electrode layer 21 is disposed on each of the plurality of dielectric layers 12 and is located inside the laminate 10.

[0131] The structure of the first internal electrode layer 21 will now be described. In the following description, the structure of the first internal electrode layer 21a and its associated electrode layers will be used as examples, but the first internal electrode layers 21b to 21d and their associated electrode layers also have the same structure.

[0132] like Figure 6 As shown, the first internal electrode layer 21a is approximately rectangular in shape when viewed in the stacking direction x, and includes: a first opposing electrode portion 23a opposite to the second internal electrode layer 22; an electrode portion 25a located on the left side along the length direction z of the first internal electrode layer 21a, extending from the first opposing electrode portion 23a toward the surface of the first end face 10e of the laminate 10 and exposed on the first end face side of the laminate 10; and an electrode portion 27a located on the right side along the length direction z of the first internal electrode layer 21a, extending from the first opposing electrode portion 23a toward the surface of the second end face 10f of the laminate 10 and exposed on the second end face side of the laminate 10. Therefore, the first internal electrode layer 21a is not exposed on the surfaces of the first side face 10c and the second side face 10d of the laminate 10.

[0133] Furthermore, in the first internal electrode layer 21a, the first end face side lead-out electrode portion 25a has a first bent portion 29a, and the second end face side lead-out electrode portion 27a has a second bent portion 29b.

[0134] Here, appropriate reference Figure 9 The display Figure 4 Enlarged views of the main parts of regions R1 and R2 are provided, illustrating the first curved portion 29a and the second curved portion 29b.

[0135] The first end face side lead-out electrode portion 25a is bent and configured to face the second main surface 10b via the first bending portion 29a.

[0136] The second end face side lead-out electrode portion 27a is bent and configured to face the second main surface 10b via the second bending portion 29b.

[0137] It should be noted that the first end face side lead-out electrode portion 25a can also be bent and configured to face the first main surface 10a by the first bending portion 29a, and the second end face side lead-out electrode portion 27a can also be bent and configured to face the first main surface 10a by the second bending portion 29b.

[0138] Therefore, when the three-terminal multilayer ceramic capacitor 100 is mounted on the mounting substrate, in the multilayer 10, the first end face side lead-out electrode portion 25a of the first internal electrode layer 21a is bent by the first bending portion 29a so that it faces downward along the stacking direction x relative to a plane orthogonal to the stacking direction x and toward the mounting surface of the mounting substrate for mounting the three-terminal multilayer ceramic capacitor 100.

[0139] Therefore, the connection point CN between the end of the first end face side lead-out electrode portion 25a and the first external electrode 30a is offset downward in the stacking direction x compared to the first bending portion 29a. Similarly, the other electrode layers located within the first end face side outer layer portion 16e also have first bending portions 29a, with the first opposing electrode portions 23b to 23d connecting the first internal electrode layers 21b to 21d and the first end face side lead-out electrode portions 25b to 25d of the first end face 10e. Thus, the bending is directed toward the mounting surface of the mounting substrate for mounting the three-terminal type multilayer ceramic capacitor 100.

[0140] Furthermore, when the three-terminal multilayer ceramic capacitor 100 is mounted on a mounting substrate, in the multilayer 10, the second end face side lead-out electrode portion 27a of the first internal electrode layer 21a is bent by the second bending portion 29b so that it faces downward along the stacking direction x relative to a plane orthogonal to the stacking direction x and toward the mounting surface of the mounting substrate for mounting the three-terminal multilayer ceramic capacitor 100.

[0141] Therefore, the connection point CN between the end of the second end face side lead-out electrode portion 27a and the second external electrode 30b is offset downward in the stacking direction x compared to the second bending portion 29b. Similarly, the other electrode layers located within the second end face side outer layer portion 16f also have second bending portions 29b, whereby the first opposing electrode portions 23b-23d connecting the first internal electrode layers 21b-21d and the second end face side lead-out electrode portions 27b-27d of the second end face 10f are bent toward the mounting surface of the mounting substrate for mounting the three-terminal type multilayer ceramic capacitor 100.

[0142] As a result, the total length of the first end face side lead-out electrode portion 25a and the second end face side lead-out electrode portion 27a, which are formed obliquely towards the mounting surface side of the mounting substrate of the capacitor through the first bending portion 29a and the second bending portion 29b, is maximized, and the current path from the first internal electrode layer 21a to 21d to the mounting substrate is formed with the shortest distance, thereby improving the low ESL characteristics of the three-terminal type multilayer ceramic capacitor 100.

[0143] Furthermore, the first curved portion 29a of the first inner electrode layers 21a to 21d is located on the inner layer 14 side at a position that is half the length z dimension between the outermost surface of the inner layer 14 on the first end face 10e and the first end face 10e side.

[0144] In addition, the second curved portion 29b of the first internal electrode layers 21a to 21d is located on the inner layer 14 side at a position that is half the length z dimension between the second end face 10f and the outermost surface of the inner layer 14 on the side of the second end face 10f.

[0145] Therefore, by bending the first end face side lead-out electrode portions 25a-25d and the second end face side lead-out electrode portions 27a-27d at an earlier stage, these lead-out electrode portions are led out to a position closer to the mounting surface of the mounting substrate, making it easier to achieve the above-mentioned effects of the present invention.

[0146] Therefore, as Figure 10 As shown, the first curved portion 29a is formed on the boundary La of the first end face side lead-out electrode portions 25a-25d and the second curved portion 29b is formed on the boundary Lb of the second end face side lead-out electrode portions 27a-27d. As long as the above conditions are met, they can be formed at any position on the first end face side lead-out electrode portions 25a-25d and the second end face side lead-out electrode portions 27a-27d respectively.

[0147] Furthermore, in the laminate 10, the following relationship exists between an adjacent pair of first internal electrode layers 21, a second internal electrode layer 22 located between them, and a dielectric layer 12 located between them.

[0148] That is, the thickness of the dielectric layer 12 located at half the length z dimension between the outermost surface of the inner layer portion 14 on the first end face 10e and the first end face 10e side, and located between adjacent first internal electrode layers 21 in the stacking direction x, is set as A1; the thickness of the dielectric layer located at half the length z dimension between the outermost surface of the inner layer portion 14 on the second end face 10f and the second end face 10f side, and located between adjacent first internal electrode layers 21 in the stacking direction x, is set as A2; the thickness of the dielectric layer 12 located in the central portion of the inner layer portion 14 and located between adjacent first internal electrode layers 21 and second internal electrode layers 22 in the stacking direction x is set as B; and the thickness of adjacent first internal electrode layers 21 or second internal electrode layers 22 in the stacking direction x located in the central portion of the inner layer portion 14 is set as C. At this time, the relationship is A1>2×B+C and A2>2×B+C.

[0149] Therefore, in the laminate 10, the first end face side lead-out electrode portions 25a to 25d disposed in the first end face side outer layer portion 16e and the second end face side lead-out electrode portions 27a to 27d disposed in the second end face side outer layer portion 16f can be inclined at a larger bending angle from the inner layer portion 14 toward the mounting surface side of the mounting substrate, and the above-mentioned effects of the present invention can be obtained more easily.

[0150] (Method for determining A1)

[0151] When the thickness of the dielectric layer 12 located at 1 / 2 of the length z dimension of the outer layer portion 16e on the first end face side and between adjacent first inner electrode layers 21 in the stacking direction x is set as A1, A1 is measured by the method shown below.

[0152] First, the cross-section of the three-terminal multilayer ceramic capacitor 100 is exposed. Specifically, grinding is performed until 1 / 2W of the three-terminal multilayer ceramic capacitor 100 is reached, and grinding is performed approximately parallel to the first side 10c or the second side 10d to expose the LT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the dielectric layer 12 located at 1 / 2 of the length z dimension of the outer layer portion 16e on the first end face side and between adjacent first internal electrode layers 21 in the stacking direction x. At this time, the thickness of 10 consecutive dielectric layers 12 located between adjacent first internal electrode layers 21 on the outer layer portion 16e on the first end face side, starting from the side closest to the first main surface 10a or the side closest to the second main surface 10b, is measured, and the averaged thickness is set as the dimension A1 of a three-terminal multilayer ceramic capacitor 100.

[0153] (Method for determining A2)

[0154] When the thickness of the dielectric layer 12 located at 1 / 2 of the length z dimension of the outer layer portion 16f on the second end face side and between adjacent first inner electrode layers 21 in the stacking direction x is set as A2, A2 is measured by the method shown below.

[0155] First, the cross-section of the three-terminal multilayer ceramic capacitor 100 is exposed. Specifically, grinding is performed until 1 / 2W of the three-terminal multilayer ceramic capacitor 100 is reached, and grinding is performed approximately parallel to the first side 10c or the second side 10d to expose the LT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the dielectric layer 12 located at 1 / 2 of the length z dimension of the outer layer portion 16f on the second end face side and between adjacent first internal electrode layers 21 in the stacking direction x. At this time, the thickness of 10 consecutive dielectric layers 12 located between adjacent first internal electrode layers 21 on the outer layer portion 16f on the second end face side is measured, starting from the side closest to the first main surface 10a or the side closest to the second main surface 10b. The average of these thicknesses is used to obtain the dimension A2 of a three-terminal multilayer ceramic capacitor 100.

[0156] (Method for determining B)

[0157] When the thickness of the dielectric layer 12 located in the central part of the inner layer 14 and located between the first inner electrode layer 21 and the second inner electrode layer 22 adjacent in the stacking direction x is defined as B, B is measured by the method shown below.

[0158] First, the cross-section of the three-terminal multilayer ceramic capacitor 100 is exposed. Specifically, grinding is performed until 1 / 2W of the three-terminal multilayer ceramic capacitor 100 is reached, and grinding is performed approximately parallel to the first side 10c or the second side 10d to expose the LT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the dielectric layer 12 located in the central part of the inner layer portion 14 between adjacent first internal electrode layers 21 and second internal electrode layers 22 in the stacking direction x. At this time, the thickness of 10 consecutive dielectric layers 12 located in the central part of the inner layer portion 14 between adjacent first internal electrode layers 21 and second internal electrode layers 22 in the stacking direction x is measured, and the average of these thicknesses is set as the dimension B of a three-terminal multilayer ceramic capacitor.

[0159] (Method for determining C)

[0160] When the thickness of the first inner electrode layer or the second inner electrode layer located in the central part of the inner layer and adjacent in the stacking direction is defined as C, C is measured by the method shown below.

[0161] First, the cross-section of the three-terminal multilayer ceramic capacitor 100 is exposed. Specifically, grinding is performed until 1 / 2W of the three-terminal multilayer ceramic capacitor 100 is reached, and grinding is performed approximately parallel to the first side 10c or the second side 10d to expose the LT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the first internal electrode layer 21 or the second internal electrode layer 22 adjacent in the lamination direction x at the center of the inner layer portion 14 in the ground cross-section. At this time, the thickness of 10 adjacent internal electrode layers of the first internal electrode layer 21 or the second internal electrode layer 22 is measured, and the averaged value of these values ​​is set as the dimension C of a three-terminal multilayer ceramic capacitor 100.

[0162] It should be noted that this describes the case where the first bending portion 29a and the second bending portion 29b of each of the first internal electrode layers 21 are all bent in the same direction. However, for a portion of the electrode layer constituting the first internal electrode layer 21, the bending portion of the present invention may also be a structure that bends in different directions.

[0163] Furthermore, while the above description illustrates the case where the first curved portion 29a and the second curved portion 29b have a single bending point, the bending point of the present invention can also be composed of multiple bending points. In addition, in this case, the curved portion can be configured to change the direction of the electrode portion extending from the (first and / or second) end face side midway.

[0164] Furthermore, in the above description, when viewed in a cross section (LT section) parallel to the first side surface 10c or the second side surface 10d, the angles of the first curved portion 29a and the second curved portion 29b may increase or decrease as they approach either the first main surface 10a or the second main surface 10b.

[0165] It should be noted that when the above-mentioned conditions of thickness A1, B and C are met, and the view is taken in a cross section (LT section) parallel to the first side surface 10c or the second side surface 10d, the angles of the plurality of first curved portions 29a of the laminate 10 can also be changed such that the angle of the first curved portion 29a located on the side closer to the second main surface 10b is larger or smaller.

[0166] Therefore, in the laminate 10, the first end face side lead-out electrode portions 25a to 25d disposed in the outer layer portion 16e on the first end face side are arranged to widen radially from the inner layer portion 14, and their mutual spacing is larger than the mutual spacing of the first opposing electrode portions 23a to 23d disposed in the inner layer portion 14.

[0167] When the conditions of thicknesses A2, B and C are met, and the observation is made in a cross section (LT section) parallel to the first side surface 10c or the second side surface 10d, if the thickness A2 is the same in the electrode portions 27a to 27d on the second end face side, the angles of the plurality of second curved portions 29b of the laminate 10 can also be varied such that the angle of the second curved portion 29b located on the side close to the second main surface 10b is larger or smaller.

[0168] Therefore, in the laminate 10, the second end face side lead-out electrode portions 27a to 27d disposed in the outer layer portion 16f on the second end face side are arranged to widen radially from the inner layer portion 14, and their mutual spacing is larger than the mutual spacing of the first opposing electrode portions 23a to 23d disposed in the inner layer portion 14.

[0169] The angle formed by the first opposing electrode portions 23a to 23d and the first end face side lead-out electrode portions 25a to 25d through the first bending portion 29a is preferably 0.1° or more and 40.0° or less.

[0170] The angle formed by the first opposing electrode portions 23a to 23d and the second end-face side lead-out electrode portions 27a to 27d through the second bending portion 29b is preferably 0.1° or more and 40.0° or less.

[0171] It should be noted that when observing in the stacking direction x, such as Figure 8 As shown, the first curved portion 29a is manifested as a pair of ridge portions KL formed by the intersecting first opposing electrode portion 23a and the first end face side lead-out electrode portion 25a.

[0172] Additionally, when observing in the stacking direction x, such as Figure 8 As shown, the second curved portion 29b appears as a pair of ridge portions KL formed by the intersecting first opposing electrode portion 23a and the second end face side lead-out electrode portion 27a.

[0173] Next, the shape of the first opposing electrode portion 23a of the first internal electrode layer 21a is not particularly limited, but as... Figure 6 As shown, it is preferably rectangular when viewed in the x-direction of the stacking process. However, it may have rounded corners when viewed in the x-direction of the stacking process, or the corners may be obliquely formed (conical) when viewed in the x-direction of the stacking process. Alternatively, it may be a conical shape that is obliquely oriented in any direction along the length direction when viewed in the x-direction of the stacking process.

[0174] The shapes of the first end face side lead-out electrode portion 25a and the second end face side lead-out electrode portion 27a of the first internal electrode layer 21a are not particularly limited, but such as Figure 6As shown, it is preferably rectangular when viewed in the x-direction of the stacking process. However, it may have rounded corners when viewed in the x-direction of the stacking process, or the corners may be obliquely formed (conical) when viewed in the x-direction of the stacking process. Alternatively, it may be a conical shape that is obliquely inclined in any direction along the length direction when viewed in the x-direction of the stacking process.

[0175] Furthermore, in the first internal electrode layer 21a, the first opposing electrode portion 23a, the first end face side lead-out electrode portion 25a, and the second end face side lead-out electrode portion 27a can be formed to have the same width, or they can be formed to have one of them being narrower.

[0176] Next, the structure of the second internal electrode layer 22 will be described. For example... Figure 7 As shown, the second internal electrode layer 22 has a roughly cross shape when viewed in the stacking direction x, and a flat plate shape when viewed in the length direction z and width direction y. Taking the second internal electrode layer 22a as an example, it has a second opposing electrode portion 22a1 opposite to the first opposing electrode portion 23a of the first internal electrode layer 21, a first side electrode portion 26a extending parallel from the second opposing electrode portion 24a to the surface of the first side surface 10c of the laminate 10, and a second side electrode portion 28a extending parallel from the second opposing electrode portion 24a to the surface of the second side surface 10d of the laminate 10.

[0177] Specifically, the second opposing electrode portion 24a is rectangular when viewed in the stacking direction x. The first side-exit electrode portion 26a is led out from the boundary Bc, which coincides with the edge of the second opposing electrode portion 24a near the first side 10c, and is exposed on the surface of the first side 10c of the laminate 10. The second side-exit electrode portion 28a is led out from the boundary Bd, which coincides with the edge of the second opposing electrode portion 24a near the second side 10d, and is exposed on the surface of the second side 10d of the laminate 10. Therefore, the second internal electrode layer 22 is not exposed on the surfaces of the first end face 10e and the second end face 10f of the laminate 10.

[0178] It should be noted that the four corners of the second opposing electrode portion 24a in the second internal electrode layer 22a are... Figure 7 The shape shown in the image is not chamfered, but it can also be a chamfered shape. The corners of the second opposing electrode portion 24a avoid overlapping with the corners of the opposing electrode portions of the first internal electrode layer, such as the first opposing electrode portion 23a of the first internal electrode layer 21, thus suppressing electric field concentration. As a result, insulation damage to the ceramic capacitor that may occur due to electric field concentration can be suppressed.

[0179] The shape of the second opposing electrode portion 24a of the second internal electrode layer 22a is not particularly limited, but it is preferably rectangular when viewed in the stacking direction x. However, it may have rounded corners when viewed in the stacking direction x, or the corners may be formed obliquely (conical) when viewed in the stacking direction x. Alternatively, it may be conical in shape that is obliquely oriented in any direction along the length direction when viewed in the stacking direction x.

[0180] The shapes of the first end face side lead-out electrode portion 25a and the second side side lead-out electrode portion 28a of the second internal electrode layer 22a are not particularly limited, but such as Figure 7 As shown, it is preferably rectangular when viewed in the x-direction of the stacking process. However, it may have rounded corners when viewed in the x-direction of the stacking process, or the corners may be obliquely formed (conical) when viewed in the x-direction of the stacking process. Alternatively, it may be a conical shape that is obliquely inclined in any direction along the length direction when viewed in the x-direction of the stacking process.

[0181] In the second internal electrode layer 22, the second opposing electrode portion 24a, the first end face side lead-out electrode portion 25a, and the second side side lead-out electrode portion 28a can be formed to have the same width, or they can be formed to have one of them being narrower.

[0182] The second internal electrode layers 22b, 22c, and 22d constituting the second internal electrode layer 22 also have the same structure as the second internal electrode layer 22a. That is, the second internal electrode layers 22b, 22c, and 22d each have second opposing electrode portions 24b, 24c, and 24d that are opposite to the first internal electrode layer 21. In addition, the second internal electrode layers 22b, 22c, and 22d each have first side electrode portions 26b, 26c, and 26d that are coplanarly extended from the second opposing electrode portions 24b, 24c, and 24d to the first end face 10e of the laminate 10. In addition, the second internal electrode layers 22b, 22c, and 22d each have second side electrode portions 28b, 28c, and 28d that are coplanarly extended from the second opposing electrode portions 24b, 24c, and 24d to the second end face 10f of the laminate.

[0183] The first internal electrode layer 21 and the second internal electrode layer 22 can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0184] The thickness of the first internal electrode layer 21 is not particularly limited, but is preferably, for example, 0.4 μm or more and 5.0 μm or less. The thickness of the second internal electrode layer 22 is not particularly limited, but is preferably, for example, 0.4 μm or more and 5.0 μm or less.

[0185] The number of the first internal electrode layer 21 and the second internal electrode layer 22 is not particularly limited, but it is preferably more than 30 and less than 2,000 in total.

[0186] The first internal electrode layer 21 and the second internal electrode layer 22 can be stacked alternately with the dielectric layer 12 in between, or the dielectric layer 12 with the second internal electrode layer 22 can be stacked after multiple dielectric layers 12 with the first internal electrode layer 21 disposed thereon are stacked. In this way, the stacking pattern of the first internal electrode layer 21 and the second internal electrode layer 22 can be changed according to the desired capacitance value in the three-terminal type multilayer ceramic capacitor 100.

[0187] like Figures 1 to 3 As shown, external electrodes 30 are disposed on the first side 10c and the second side 10d of the laminate 10, as well as on the first end face 10e and the second end face 10f.

[0188] The external electrode 30 in the three-terminal type multilayer ceramic capacitor 100 consists of four independent electrodes, configured to have a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0189] The first external electrode 30a is electrically connected to the first internal electrode layer 21 and is disposed on the surface of the first end face 10e. Furthermore, the first external electrode 30a extends from the first end face 10e of the laminate 10 along the contour of the laminate 10 and is disposed on a portion of the first main surface 10a, a portion of the second main surface 10b, a portion of the first side surface 10c, and a portion of the second side surface 10d. In this case, the first external electrode 30a is electrically connected to the electrode portions 25a-25d extending from the first end face of the first internal electrode layers 21a-21d.

[0190] The second external electrode 30b is electrically connected to the first internal electrode layer 21 and is disposed on the surface of the second end face 10f. Furthermore, the second external electrode 30b extends from the first end face 10e of the laminate 10 along the contour of the laminate 10 and is disposed on a portion of the first main surface 10a, a portion of the second main surface 10b, a portion of the first side surface 10c, and a portion of the second side surface 10d. In this case, the second external electrode 30b is electrically connected to the electrode portions 27a-27d extending from the second end face of the first internal electrode layers 21a-21d.

[0191] The third external electrode 30c is electrically connected to the second internal electrode layer 22 and is disposed on the surface of the first side surface 10c. Furthermore, the third external electrode 30c extends from the first side surface 10c of the laminate 10 along the contour of the laminate 10 and is disposed on a portion of the first main surface 10a and a portion of the second main surface 10b. In this case, the third external electrode 30c is electrically connected to the electrode portions 26a-26d extending from the first side surfaces of the second internal electrode layers 22a-22d.

[0192] The fourth external electrode 30d is electrically connected to the second internal electrode layer 22 and is disposed on the surface of the second side surface 10d. Furthermore, the fourth external electrode 30d extends from the second side surface 10d of the laminate 10 along the contour of the laminate 10 and is disposed on a portion of the first main surface 10a and a portion of the second main surface 10b. In this case, the fourth external electrode 30d is electrically connected to the electrode portions 28a-28d extending from the second side surfaces of the second internal electrode layers 22a-22d.

[0193] Within the laminate 10, as described above, the first opposing electrode portions 23a-23d of the first internal electrode layer 21 and the second opposing electrode portions 24a-24d of the second internal electrode layer 22 are respectively opposed to each other across the dielectric layer 12, serving as the inner layer portion 14. Thus, the laminate 10 functions as the main body of a capacitor that stores charge between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode layer 21 and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 22.

[0194] As an example of the internal structure of the external electrode 30, the external electrode 30 includes at least a base electrode layer 32 comprising metallic and ceramic components, and a plating layer 34. The plating layer 34 includes a lower plating layer 36 disposed on the surface of the base electrode layer 32. Furthermore, as in this embodiment, the plating layer 34 of the external electrode 30 preferably includes an upper plating layer 38 disposed on the surface of the lower plating layer 36.

[0195] The base electrode layer 32 includes a first base electrode layer 32a in the first external electrode 30a, a second base electrode layer 32b in the second external electrode 30b, a third base electrode layer 32c in the third external electrode 30c, and a fourth base electrode layer 32d in the fourth external electrode 30d.

[0196] The substrate electrode layer 32 preferably includes at least one selected from a sintered layer, a conductive resin layer, and a thin film layer. Hereinafter, the case where the substrate electrode layer 32 is a sintered layer will be described.

[0197] The sintered layer is obtained by applying a conductive paste containing glass components and a metal to the laminate 10 and then sintering it. The glass component of the sintered layer includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal of the sintered layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0198] The sintered layer can also be obtained by simultaneously firing a stacked sheet that forms the basis of the laminate 10 and applying a conductive paste to the stacked sheet, the stacked sheet having a first internal electrode layer 21, a second internal electrode layer 22, and a dielectric layer 12. Alternatively, the sintered layer can also be obtained by firing the stacked sheet to obtain the laminate 10, then applying a conductive paste to the laminate 10 and sintering it. It should be noted that when simultaneously firing the stacked sheet and applying the conductive paste to the stacked sheet, it is preferable to use a sintered layer in which a dielectric material is added instead of a glass component.

[0199] The sintered layer can be a single layer or multiple layers.

[0200] When the sintered layer is configured as a first external electrode 30a located on the first end face 10e, the thickness of the longitudinal direction z of the central portion in the stacking direction x is preferably, for example, 3 μm or more and 70 μm or less.

[0201] When the sintered layer is configured as a second external electrode 30b located on the second end face 10f, the thickness of the longitudinal direction z of the central portion in the stacking direction x is preferably, for example, 3 μm or more and 70 μm or less.

[0202] Furthermore, when the sintered layer is configured as part of the first external electrode 30a located in part of the first main surface 10a and part of the second main surface 10b, the thickness of the stacking direction x of the central portion in the length direction z is preferably, for example, 3 μm or more and 40 μm or less.

[0203] Furthermore, when the sintered layer is configured as part of the second external electrode 30b located in part of the first main surface 10a and part of the second main surface 10b, the thickness of the stacking direction x in the central part of the length direction z is preferably, for example, 3 μm or more and 40 μm or less.

[0204] Next, we will explain the case where the base electrode layer 32 is a conductive resin layer.

[0205] When the conductive resin layer is used as the base electrode layer 32, the conductive resin layer can also be configured to further cover the already formed sintered layer. Alternatively, it can be disposed directly on the laminate 10 without forming a sintered layer. In this case, the conductive resin layer can completely cover the sintered layer or cover a portion of the sintered layer.

[0206] The conductive resin layer is made of materials such as conductive particles and thermosetting resins. Because the conductive resin layer includes a thermosetting resin, it is more flexible than, for example, conductive layers comprising sintered products containing coatings or conductive pastes. Therefore, even when subjected to physical impact or thermal cycling-induced impact on the three-terminal multilayer ceramic capacitor 100, the conductive resin layer functions as a buffer layer, suppressing the formation of cracks in the three-terminal multilayer ceramic capacitor 100.

[0207] On the other hand, the conductive particles contained in the conductive resin layer are primarily responsible for the electrical conductivity of the conductive resin layer. Specifically, electrical pathways are formed within the conductive resin layer through the contact between conductive fillers.

[0208] Metal particles can be used as conductive particles contained in the conductive resin layer. Furthermore, Ag, Cu, Ni, Sn, Bi, or alloys containing all or part of them can be used as suitable metal particles.

[0209] Furthermore, conductive particles coated with Ag can also be used as conductive particles. In this case, Cu, Ni, Sn, Bi, or alloys containing them are preferred as the metal. The reason for using conductive particles coated with Ag as conductive particles is that Ag has the lowest resistivity among metals, making it suitable for electrode materials. Moreover, as a noble metal, it does not oxidize and has high weather resistance. Additionally, it allows for the use of a cheaper base metal while maintaining the aforementioned properties of Ag.

[0210] Furthermore, the metal included in the conductive resin layer can also be a metal that has undergone anti-oxidation treatment on Cu or Ni.

[0211] Furthermore, as a metal included in the conductive resin layer, metal powders coated with Sn, Ni, or Cu can also be used. When using metal powders coated with Sn, Ni, or Cu, Ag, Cu, Ni, Sn, Bi, or alloys thereof are preferably used as the base metal powder.

[0212] Next, the shape of the metal powder contained in the conductive resin layer can be spherical, flat, etc., but it is preferable to use a mixture of spherical and flat metal powder.

[0213] Next, as a suitable resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, with its excellent heat resistance, moisture resistance, and adhesion, is the most suitable resin.

[0214] Furthermore, the conductive resin layer preferably includes a curing agent in addition to a thermosetting resin. When using epoxy resin as the base thermosetting resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, reactive ester, and amide-imide compounds can be used as the curing agent.

[0215] Furthermore, the conductive resin layer can be formed from a single layer or from multiple layers.

[0216] Furthermore, the thickness of the conductive resin layer is preferably in the range of 10 μm or more and 150 μm or less at its thickest part.

[0217] Next, we will explain the case where the substrate electrode layer 32 is a thin film layer.

[0218] When the substrate electrode layer 32 is set as a thin film layer, the thin film layer is formed by the accumulation of metal particles to form a layer with an average thickness of less than 1 μm. In addition, the thin film layer is fabricated by a thin film formation method such as sputtering or vapor deposition.

[0219] Next, the coating layer 34 will be described.

[0220] The plating layer 34 includes a lower plating layer 36 and an upper plating layer 38 disposed on the surface of the lower plating layer 36.

[0221] The plating layer 34 includes a first plating layer 34a disposed on the surface of the first base electrode layer 32a, a second plating layer 34b disposed on the surface of the second base electrode layer 32b, a third plating layer 34c disposed on the surface of the third base electrode layer 32c, and a fourth plating layer 34d disposed on the surface of the fourth base electrode layer 32d.

[0222] The lower plating layer 36 includes a first lower plating layer 36a in the first external electrode 30a, a second lower plating layer 36b in the second external electrode 30b, a third lower plating layer 3632c in the third external electrode 30c, and a fourth lower plating layer 36d in the fourth external electrode 30d.

[0223] In addition, the upper plating layer 38 includes a first upper plating layer 38a in the first external electrode 30a, a second upper plating layer 38b in the second external electrode 30b, a third upper plating layer 38c in the third external electrode 30c, and a fourth upper plating layer 38d in the fourth external electrode 30d.

[0224] The lower plating layer 36 and the upper plating layer 38 may also have a common structure, for example, containing at least one metal selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. Preferably, the lower plating layer 36 is formed as a Ni plating layer and the upper plating layer 38 is formed as a Sn plating layer.

[0225] The Ni plating layer can suppress solder erosion of the base electrode layer 32 when the three-terminal multilayer ceramic capacitor 100 is mounted on the mounting substrate. In addition, the Sn plating layer can improve the wettability of the solder when the three-terminal multilayer ceramic capacitor 100 is mounted on the mounting substrate, which can facilitate mounting.

[0226] Regarding each lower plating layer 36 and each upper plating layer 38, the thickness of each layer is preferably 2 μm or more and 15 μm or less.

[0227] It should be noted that the base electrode layer 32 may not be provided, and the external electrode 30 may be formed solely by the plating layer.

[0228] The following describes a structure in which a plating layer is provided instead of a base electrode layer 32, which is not illustrated.

[0229] The first external electrode 30a and the second external electrode 30b may also be formed directly on the surface of the laminate 10 without a base electrode layer. That is, the three-terminal type laminated ceramic capacitor 100 may also have a structure that includes a plating layer electrically connected to the first internal electrode layer 21 or the second internal electrode layer 22.

[0230] With such a structure, a coating layer can also be formed after the catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0231] It should be noted that when a plating layer is formed directly on the laminate without setting a base electrode layer, it is possible to achieve a lower back thickness, i.e., thinner profile, corresponding to the reduction in the thickness of the base electrode layer, or to convert it into the thickness of the laminate, i.e., the thickness of the inner layer. Therefore, it is possible to increase the design freedom of the thickness of the laminate 10.

[0232] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 10 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode preferably each include, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn or an alloy containing such metal.

[0233] Furthermore, the lower plating electrode is preferably formed using Ni, which has solder resist properties, and the upper plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0234] Furthermore, for example, if the first inner electrode layer 21 and the second inner electrode layer 22 are formed using Ni, the lower plating electrode is preferably formed using Cu, which has good adhesion to Ni. It should be noted that the upper plating electrode can be formed as needed, and the first outer electrode 30a and the second outer electrode 30b can each be composed solely of the lower plating electrode. The plating layer can have the upper plating electrode as the outermost layer, or other plating electrodes can be further formed on the surface of the upper plating electrode.

[0235] Here, when the external electrode 30 is formed solely by a plating layer without providing a base electrode layer 32, the thickness of each layer of the plating layer provided without providing a base electrode layer 32 is preferably 1.0 μm or more and 15.0 μm or less.

[0236] Furthermore, the coating preferably does not contain glass. The metal content per unit volume of the coating is preferably 99% by volume or more.

[0237] It should be noted that the external electrode 30 may also be formed solely by the lower plating layer 36 and the upper plating layer 38 without the base electrode layer 32. That is, all or part of the first external electrode 30a to the fourth external electrode 30d constituting the external electrode 30 can be formed directly on the surface of the laminate 10 without the base electrode layer 32. In this case, the three-terminal type laminated ceramic capacitor 100 has a structure including a lower plating layer 36 that is directly electrically connected to the first internal electrode layer 21 and the second internal electrode layer 22, and an upper plating layer 38 disposed on the lower plating layer 36.

[0238] It should be noted that, in this structure, the lower plating layer 36 and the upper plating layer 38 preferably each comprise, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. The lower plating layer 36 is preferably formed using Ni, which has solder resist properties, and the upper plating layer 38 is preferably formed using Sn or Au, which have good solder wettability.

[0239] Alternatively, for example, if the first inner electrode layer 21 and the second inner electrode layer 22 are formed using Ni, the lower plating layer 36 is preferably formed using Cu, which has good adhesion to Ni. Furthermore, the upper plating layer 38 can be formed as needed, and the first to fourth outer electrodes may each be composed solely of the lower plating layer 36.

[0240] Furthermore, the outer electrode 30 may have the upper plating layer 38 as the outermost layer as in this embodiment, or other plating electrodes may be further formed on the surface of the upper plating layer 38.

[0241] The thickness of each of the lower plating layer 36 and the upper plating layer 38, which are configured without the base electrode layer 32, is preferably 1 μm or more and 15 μm or less.

[0242] Furthermore, the lower coating layer 36 and the upper coating layer 38 preferably do not contain glass in their compositions. Additionally, the metal content per unit volume of each of the lower coating layer 36 and the upper coating layer 38 is preferably 99% by volume or more.

[0243] The length direction z dimension of the three-terminal type multilayer ceramic capacitor 100, including the laminate 10, the first external electrode 30a and the second external electrode 30b, is set as dimension L. The stacking direction x dimension of the three-terminal type multilayer ceramic capacitor 100, including the laminate 10, the first external electrode 30a and the second external electrode 30b, is set as dimension T. The width direction y dimension of the three-terminal type multilayer ceramic capacitor 100, including the laminate 10, the first external electrode 30a and the second external electrode 30b, is set as dimension W.

[0244] Regarding the dimensions of the three-terminal multilayer ceramic capacitor 100, the length dimension L in the z-direction is 1.00 mm or more and 1.20 mm or less, the width dimension W in the y-direction is 0.50 mm or more and 0.70 mm or less, and the stacking dimension T in the x-direction is 0.30 mm or more and 0.39 mm or less. Furthermore, the dimensions of the three-terminal multilayer ceramic capacitor 100 can be measured using a microscope.

[0245] Here, in Figure 21 The image shows a conventional three-terminal multilayer ceramic capacitor 1.

[0246] Conventional three-terminal multilayer ceramic capacitors have a multilayer body 2, external electrodes 3a and 3b disposed on both ends of the multilayer body 2, and external electrodes 3c and 3d disposed on both sides of the multilayer body 2. Furthermore, inside the multilayer body 2, multiple first internal electrode layers 5 exposed on both ends and second internal electrode layers 6 exposed on both sides are alternately stacked and arranged with dielectric layers 4 in between.

[0247] The first end face side lead-out electrode 5a, which is configured as the first internal electrode layer 5, is led out straight to the first end face 2a, and the second end face side lead-out electrode 5b is led out straight to the second end face 2b.

[0248] In this case, the current path from the area where the first inner electrode layer 5 and the second inner electrode layer 6 face each other, i.e., the inner layer 7, to the mounting substrate (not shown), becomes the sum of the distance from the inner layer 7 to the connection point cn where the first end face electrode 5a connects to the external electrode 3a in the first end face 2a, and the distance from the connection point cn to the conductor pad on the mounting substrate (not shown).

[0249] In contrast, such as Figure 9 As shown in (a), in the case of the three-terminal multilayer ceramic capacitor 100 of the first embodiment of the present invention, the current path, that is, the current path from the inner layer 14 to the mounting substrate (not shown), is the sum of the distance from the first bent portion 29a to the connection point where the first end face side of the electrode portion 25a, which is inclined towards the conductor pad on the mounting substrate (not shown), connects to the first external electrode 30a, and the distance from the connection point CN to the conductor pad on the mounting substrate (not shown). Similarly, as Figure 9 As shown in (b), in the case of the three-terminal type multilayer ceramic capacitor 100 of the first embodiment of the present invention, the current path, that is, the current path from the inner layer 14 to the mounting substrate (not shown), is the sum of the distance from the second bend 29b to the connection point where the second end face side leads out electrode 27a and the second external electrode 30b are connected, which is inclined toward the conductor pad on the mounting substrate (not shown), and the distance from the connection point CN to the conductor pad on the mounting substrate (not shown).

[0250] Therefore, compared with existing examples, the first embodiment of the present invention can further shorten the current path.

[0251] Thus, in Figure 1 In the first internal electrode layers 21a-21d of the three-terminal type multilayer ceramic capacitor 100 shown, the first end face side lead-out electrode portions 25a-25d have a first bending portion 29a, and the second end face side lead-out electrode portions 27a-27d have a second bending portion 29b. Through the first bending portion 29a, a portion or all of the first end face side lead-out electrode portions 25a-25d are configured to face either the first main surface 10a or the second main surface 10b. Through the second bending portion 29b, a portion or all of the second end face side lead-out electrode portions 27a-27d are configured to face either the first main surface 10a or the second main surface 10b. As a result, compared with the prior art, the current path from the first internal electrode layers 21a-21d to the mounting substrate can be further shortened.

[0252] This improves the low ESL characteristics of the three-terminal multilayer ceramic capacitor 100.

[0253] As described above, in the first internal electrode layer 21a of the three-terminal stacked ceramic capacitor 100 of this embodiment, the first end face side lead-out electrode portion 25a has a first bent portion 29a, and the second end face side lead-out electrode portion 27a has a second bent portion 29b.

[0254] Furthermore, the first end face side lead-out electrode portion 25a is bent and configured to face the second main surface 10b via the first bending portion 29a, and the second end face side lead-out electrode portion 27a is bent and configured to face the second main surface 10b via the second bending portion 29b.

[0255] Therefore, as Figure 11 As shown, the first curved portion 29a and the second curved portion 29b can also be arranged in the first internal electrode layer 21, with the first opposing electrode portions 23a-23d and the first end-face side lead-out electrode portions 25a-25d and the second end-face side lead-out electrode portions 27a-27d being the same and equally spaced. In this case, in addition to the desired effect described above, the spacing between the first end-face side lead-out electrode portions 25a-25d and the second end-face side lead-out electrode portions 27a-27d can be made equal, suppressing quality deviations and obtaining stable low ESL characteristics.

[0256] In addition, such as Figure 12 As shown, the first bent portion 29a and the second bent portion 29b can also be in the first inner electrode layer 21 such that the spacing between the first end face side lead-out electrode portions 25a-25d and the second end face side lead-out electrode portions 27a-27d is smaller than the spacing between the first opposing electrode portions 23a-23d. In this case, in addition to the desired effect described above, the connection points of the first end face side lead-out electrode portions 25a-25d to the first outer electrode 30a, and the connection points of the second end face side lead-out electrode portions 27a-27d to the first outer electrode 30a, can be positioned closer to the mounting surface, further shortening the current path between the inner layer portion 14 and the mounting surface, and further improving the low ESL characteristics.

[0257] b. Mounting structure of three-terminal multilayer ceramic capacitors

[0258] Next, refer to Figure 13 and 14 The mounting structure of the three-terminal type multilayer ceramic capacitor according to the first embodiment of the present invention will be described.

[0259] like Figure 13 and Figure 14 As shown, the mounting structure 500 of the three-terminal multilayer ceramic capacitor of this embodiment includes the three-terminal multilayer ceramic capacitor 100 of the first embodiment and a mounting substrate 50. The mounting substrate 50 includes a substrate core 51 and conductor pads 52. The substrate core 51 is, for example, made of a substrate comprising materials or a ceramic substrate manufactured by sintering a sheet of material mixed with ceramic and glass, which is obtained by impregnating a substrate of a mixture of glass cloth (cloth) and glass nonwoven fabric with epoxy resin or polyimide resin. It should be noted that the substrate core 51 can be a single-layer substrate or a substrate composed of multiple layers.

[0260] The thickness of the core material 51 of the substrate is not particularly limited, but is preferably 200 μm or more and 800 μm or less.

[0261] One main surface of the core material 51 of the substrate constitutes a substrate-side mounting surface 51a, which is provided with conductor pads 52 and serves as the mounting surface of a three-terminal type multilayer ceramic capacitor 100.

[0262] The conductor pad 52 includes a first conductor pad 52a, a second conductor pad 52b, a third conductor pad 52c, and a fourth conductor pad 52d.

[0263] The first conductor pad 52a is a portion electrically and mechanically connected to the first external electrode 30a of the three-terminal multilayer ceramic capacitor 100 via a bonding material. The second conductor pad 52b is a portion electrically and mechanically connected to the second external electrode 30b of the three-terminal multilayer ceramic capacitor 100 via a bonding material. The third conductor pad 52c is a portion electrically and mechanically connected to the third external electrode 30c of the three-terminal multilayer ceramic capacitor 100 via a bonding material. The fourth conductor pad 52d is a portion electrically and mechanically connected to the fourth external electrode 30d of the three-terminal multilayer ceramic capacitor 100 via a bonding material.

[0264] It should be noted that the conductor pad 52 can also be disposed on the main surface opposite to the substrate-side mounting surface 51a of the core material 51 of the substrate.

[0265] The material of the conductor pad 52 is not particularly limited, but metals such as copper, gold, palladium, and platinum can be used. Furthermore, the thickness of the conductor pad 52, i.e., its dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less. For example, a high-heat-resistant epoxy adhesive can be used as the bonding material.

[0266] It should be noted that, in the above description, the mounting substrate 50 corresponds to the mounting substrate of the present invention. The core material 51 of the substrate corresponds to the core material of the substrate of the present invention. The mounting surface 51a of the substrate side corresponds to the mounting surface of the present invention. The plurality of conductor pads 52 correspond to the plurality of connecting conductors of the present invention. Wherein, the connecting conductors of the present invention, apart from the so-called pads, are any conductors disposed between the multilayer ceramic capacitor and the mounting substrate that can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0267] Figure 13 and Figure 14The mounting structure 500 of the three-terminal multilayer ceramic capacitor shown is mounted on the mounting substrate 50 such that the second main surface 10b of the three-terminal multilayer ceramic capacitor 100 faces the substrate-side mounting surface 51a. Thus, with the distance between the first end-face side lead-out electrode portions 25a-25d and the second end-face side lead-out electrode portions 27a-27d extending from the first end-face 10e and the second end-face 10f and the substrate-side mounting surface 51a of the mounting substrate 50 being minimized, electrical connection between the three-terminal multilayer ceramic capacitor 100 and the mounting substrate 50 is achieved.

[0268] therefore, Figure 13 and Figure 14 The mounting configuration 500 of the three-terminal multilayer ceramic capacitor shown directly reflects the various functions of the three-terminal multilayer ceramic capacitor 100 of the first embodiment of the present invention described above. Compared with conventional examples, it can shorten the current path from the first internal electrode layers 21a to 21d of the three-terminal multilayer ceramic capacitor 100 to the mounting substrate 50. As a result, it achieves the various effects of the three-terminal multilayer ceramic capacitor 100 of the first embodiment of the present invention and improves the low ESL characteristics in the mounting configuration of the three-terminal multilayer ceramic capacitor.

[0269] It should be noted that, in the above description, the second main surface 10b of the three-terminal multilayer ceramic capacitor 100 is mounted on the mounting substrate 50 such that the substrate-side mounting surface 51a faces the second main surface 10b. However, when the ends of the first end-face side lead-out electrode portions 25a-25d and the second end-face side lead-out electrode portions 27a-27d, which are led out from the first end-face 10e and the second end-face 10f respectively, are located near the first main surface 10a, that is, when the first end-face side lead-out electrode portions 25a-25d and the second end-face side lead-out electrode portions 27a-27d are bent toward the first main surface 10a by the first bending portion 29a and the second bending portion 29b of the first internal electrode layer 21, the first main surface 10a of the three-terminal multilayer ceramic capacitor 100 is mounted on the mounting substrate 50 such that the substrate-side mounting surface 51a faces the second main surface 10b. Thus, the same structure as when the second main surface 10b faces the substrate-side mounting surface 51a is achieved, reflecting the... Figure 1 The three-terminal type multilayer ceramic capacitor 100 shown has various effects.

[0270] c. Manufacturing method of three-terminal multilayer ceramic capacitor

[0271] Next, as a method for manufacturing a multilayer ceramic capacitor according to the first embodiment of the present invention, the method for manufacturing a three-terminal multilayer ceramic capacitor 100 according to the first embodiment will be described.

[0272] (Prepare)

[0273] First, prepare a dielectric sheet for the dielectric layer, a conductive paste for the internal electrode layer, and a dielectric paste for the dielectric layer. It should be noted that dielectric sheets with a first internal electrode layer, dielectric sheets with a second internal electrode layer, and dielectric sheets without an internal electrode layer are prepared respectively. The dielectric sheet, conductive paste, and dielectric paste each contain an adhesive and a solvent. The adhesive and solvent can also be known.

[0274] (Fabrication of laminated sheets)

[0275] Next, conductive paste is printed onto the dielectric sheet using methods such as screen printing, gravure printing, or printing with an inkjet printer, in a predetermined pattern corresponding to the shapes of the internal electrode layers. Thus, conductive paste is applied to the portion of the dielectric sheet that becomes the first internal electrode layer (hereinafter, such a dielectric sheet is referred to as the first coated dielectric sheet). Furthermore, conductive paste is applied to the portion of the dielectric sheet that becomes the second internal electrode layer (hereinafter, such a dielectric sheet is referred to as the second coated dielectric sheet).

[0276] Specifically, when applying a conductive paste for the internal electrode layer by screen printing, a screen for printing the first internal electrode layer and a screen for printing the second internal electrode layer are prepared respectively. A printing press capable of printing these two screens onto different dielectric sheets can be used to print the prescribed patterns corresponding to the internal electrode layers respectively.

[0277] Next, at the positions of the first end face side outer layer and the second end face side outer layer of the laminate, a conductive paste for the dielectric layer is applied to the portions of the second coated dielectric sheet that are not coated with the internal electrode layer, for example by screen printing, gravure printing, or printing using an inkjet printer. Specifically, refer to... Figure 7 The layout of the second internal electrode layer and the dielectric layer disposed thereon is shown. In the second coated dielectric sheet, the coating region ARa, located closer to the first end face than the first end face of the second counter electrode portion, is coated with a dielectric paste. Similarly, in the coating region ARb, located closer to the second end face than the second end face of the second counter electrode portion, in the second coated dielectric sheet, a dielectric paste is coated with a dielectric paste.

[0278] This increases the thickness of the coating area ARa on the first end face side relative to the portion corresponding to boundary Ba, and the thickness of the coating area ARb on the second end face side relative to the portion corresponding to boundary Bb, in the second coated dielectric sheet. The boundary Ba coincides with the end edge on the first end face side of the second counter electrode portion, and the boundary Bb coincides with the end edge on the second end face side of the second counter electrode portion.

[0279] Next, a predetermined number of outer layer dielectric sheets without the pattern of the internal electrode layer are stacked to form a portion on the second main surface side that becomes the outer layer portion on the second main surface side. Then, a first coated dielectric sheet with the pattern of the first internal electrode layer printed on it and a second coated dielectric sheet with the pattern of the second internal electrode layer printed on it are sequentially stacked on the portion that becomes the outer layer portion on the second main surface side, thereby forming the structure of the present invention, thereby forming a portion including an inner layer portion. On the portion including the inner layer portion, a predetermined number of outer layer dielectric sheets without the pattern of the internal electrode layer printed on it are stacked to form a portion on the first main surface side that becomes the outer layer portion on the first main surface side.

[0280] When forming the portion including the inner layer, when the first coated dielectric sheet is laminated onto the second coated dielectric sheet, the portions on both end faces of the first coated dielectric sheet are bent in the lamination direction x along the boundaries Ba and Bb on both end faces of the portion of the second coated dielectric sheet that becomes the second opposing electrode portion. As a result, portions corresponding to the first and second bent portions are formed in the first inner electrode layer of the laminate.

[0281] At this point, by configuring the structure to apply dielectric paste to all the second coated dielectric sheets constituting the laminate, the thickness of the portions coated with dielectric paste is greater than the thickness of the portions not coated with dielectric paste, and gradually increases according to the number of laminates. As a result, in Figure 9 In the completed laminated body shown, when the thickness of the first end face side outer layer and the second end face side outer layer is set to C, the thickness of the dielectric layer in the inner layer is set to B, the thickness of the dielectric layer formed by the above-mentioned dielectric paste, that is, the dielectric layer sandwiched by an adjacent pair of first end face side lead-out electrodes along the lamination direction x is set to A1, and the thickness of the dielectric layer sandwiched by an adjacent pair of second end face side lead-out electrodes along the lamination direction x is set to A2, the thicknesses A1, A2, B and C can have the relationship A1>2×B+C and A2>2×B+C.

[0282] Through the above processes, a laminated sheet is produced.

[0283] (Creating stacked blocks)

[0284] Next, a stacked block is made by pressing the stacked sheets along the stacking direction of the dielectric sheets using a hydrostatic press or other mechanisms.

[0285] (The creation of layered small pieces)

[0286] Multiple small laminated pieces are cut out by cutting the laminated blocks to a specified size. At this time, the corners and edges of the small laminated pieces can also be rounded by methods such as tumble grinding.

[0287] (Creating a layered body)

[0288] The laminate 10 is fabricated by firing the laminated sheets. The firing temperature is determined by the material of the dielectric sheet or the material of the internal electrode layer, but is preferably above 900°C and below 1400°C.

[0289] (Formation of external electrodes)

[0290] (The situation of the burnt-on layer)

[0291] In the following description, the base electrode layer is assumed to be formed by a sintered layer. When forming a sintered layer, a conductive paste comprising glass components and metal is applied, followed by a sintering process to form the base electrode layer. The sintering temperature is preferably 700°C or higher and 900°C or lower.

[0292] A third base electrode layer 31c of a third external electrode 30c and a fourth base electrode layer 32d of a fourth external electrode 30d are formed on the first side 10c and the second side 10d of the laminate 10. Various methods can be used to form the sintered layer. For example, a method of applying the sintered layer by extruding a conductive paste through a slit (so-called impregnation method) can be used. In this method, by increasing the amount of conductive paste extruded, the base electrode layer can be formed not only on the first side 10c and the second side 10d, but also on a portion of the first main surface 10a and a portion of the second main surface 10b.

[0293] Alternatively, a roll transfer method can be used to form the sintered layer. In the case of the roll transfer method, by increasing the pressing pressure during roll transfer, not only can the base electrode layer be formed on the first side surface 10c and the second side surface 10d, but the base electrode layer can also be formed on a portion of the first main surface 10a and a portion of the second main surface 10b.

[0294] Next, a first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first end face 10e and the second end face 10f of the laminate 10.

[0295] In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed by impregnation, respectively, extending not only to the first end face 10e and the second end face 10f, but also to a portion of the first main face 10a and a portion of the second main face 10b, as well as a portion of the first side face 10c and a portion of the second side face 10d.

[0296] The order of the calcination process is not limited to the above. The third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b can be calcined simultaneously, or the calcination can be performed on the side surface and the end surface respectively.

[0297] (In the case of conductive resin layers)

[0298] It should be noted that when the first base electrode layer 32a to the fourth base electrode layer 32d are formed from a conductive resin layer, they can be formed by the following method. The conductive resin layer can be formed on the surface of the sintered layer, or the sintered layer can be omitted, and the conductive resin layer can be directly formed onto the laminate 10 in the form of a monomer.

[0299] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the sintered layer or the laminate 10, and then heat-treating it at a temperature of 250°C or higher and 550°C or lower to heat-cure the resin. The atmosphere during this heat treatment is preferably N2. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably suppressed to 100 ppm or lower.

[0300] As a method for applying conductive resin paste, it can be similar to the method for forming a base electrode layer from a sintered layer, for example, by using a method of applying the conductive paste by extruding it from a slit or by a roller transfer method.

[0301] (In the case of thin film layers)

[0302] When the first base electrode layer 32a to the fourth base electrode layer 32d are formed from thin film layers, the formation is performed by covering the area other than the desired area where the external electrode 30 is to be formed using a mask or the like, and then performing a thin film formation method such as sputtering or vapor deposition on the exposed desired area. The third base electrode layer 32c formed from the thin film layer is a layer with metal particles deposited on it and a thickness of 1 μm or less.

[0303] (Production of the coating layer)

[0304] Finally, the first lower plating layer 36a to the fourth lower plating layer 36d and the first upper plating layer 38a to the fourth upper plating layer 38d are formed. It should be noted that the plating layer can be formed on the surface of the third base electrode layer 32c or directly onto the laminate 10. In this embodiment, the plating layer is formed on the surface of the first base electrode layer 32a to the fourth base electrode layer 32d. More specifically, a Ni plating layer is formed on the first base electrode layer 32a to the fourth base electrode layer 32d as the first lower plating layer 36a to the fourth lower plating layer 36d, and a Sn plating layer is formed on the surface of the Ni plating layer as the first upper plating layer 38a to the fourth upper plating layer 38d. During the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires pretreatment based on catalysts, etc., to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is generally preferred.

[0305] The three-terminal multilayer ceramic capacitor of the first embodiment is obtained as described above.

[0306] B. Second Implementation Method

[0307] a. Three-terminal multilayer ceramic capacitor

[0308] Next, the three-terminal type multilayer ceramic capacitor of the second embodiment of the present invention will be described.

[0309] Figure 15 This is a perspective view showing an example of a three-terminal type multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 16 yes Figure 15 A cross-sectional view at line XVI-XVI. Figure 17 yes Figure 15 A cross-sectional view along line XVII-XVII. Figure 18 This is a top view showing the structure of the second internal electrode layer of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention, corresponding to... Figure 7 Top view from the same orientation. Structures identical or equivalent to those in the first embodiment described above are labeled with the same markings. Detailed descriptions of structures and operations identical to those in the first embodiment are omitted.

[0310] The three-terminal multilayer ceramic capacitor 200 of this embodiment is characterized in that, in the three-terminal multilayer ceramic capacitor 100 of the first embodiment 1, the second internal electrode layer 22 has a different structure. That is, as shown in... Figure 16 and 17As shown, taking the second internal electrode layer 22a as an example, the three-terminal type multilayer ceramic capacitor 200 includes a second opposing electrode portion 24a opposite to the first internal electrode layer 21, a first side-side lead-out electrode portion 26a extending from the second opposing electrode portion 24a to the surface of the first side surface 10c of the multilayer body 10, and a second side-side lead-out electrode portion 28a extending from the second opposing electrode portion 24a to the surface of the second side surface 10d of the multilayer body 10.

[0311] Furthermore, in the second internal electrode layer 22a, the first side electrode portion 26a has a third bend 29c, and the second side electrode portion 28a has a fourth bend 29d.

[0312] Here, appropriate reference Figure 19 The display Figure 17 Enlarged views of the main parts of regions R3 and R4 are provided, and the third bend 29c and the fourth bend 29d are explained.

[0313] The first side-exit electrode portion 26a is bent and positioned toward the second main surface 10b via the third bend 29c.

[0314] The second side electrode section 28a is bent and positioned toward the second main surface 10b via the fourth bend 29d.

[0315] It should be noted that the first side lead-out electrode portion 26a can also be bent and configured to face the first main surface 10a via the third bending portion 29c, and the second side lead-out electrode portion 28a can also be bent and configured to face the first main surface 10a via the fourth bending portion 29d.

[0316] Therefore, when the three-terminal multilayer ceramic capacitor 200 is mounted on a mounting substrate, in the multilayer 10, the first side electrode portion 26a of the second internal electrode layer 22a is bent by the third bending portion 29c so that it faces downward along the stacking direction x relative to a plane orthogonal to the stacking direction x and toward the mounting surface of the mounting substrate for mounting the three-terminal multilayer ceramic capacitor 200.

[0317] Therefore, the connection point CN between the end of the first side-side lead-out electrode portion 26a and the third external electrode 30c is offset downward in the stacking direction x compared to the third bending portion 29c. Similarly, the other electrode layers located within the first side-side outer layer portion 16c also have third bending portions 29c, with the second opposing electrode portions 24b-24d connecting the second internal electrode layers 22b-22d and the first side-side lead-out electrode portions 26b-26d of the first side surface 10c. Thus, the bending is directed toward the mounting surface of the mounting substrate for mounting the three-terminal type multilayer ceramic capacitor 100.

[0318] Furthermore, when the three-terminal multilayer ceramic capacitor 200 is mounted on a mounting substrate, in the multilayer 10, the second side electrode portion 28a of the second internal electrode layer 22a is bent by the fourth bending portion 29d so that it faces downward along the stacking direction x relative to a plane orthogonal to the stacking direction x and toward the mounting surface of the mounting substrate for mounting the three-terminal multilayer ceramic capacitor 200.

[0319] Therefore, the connection point CN between the end of the second side-side lead-out electrode portion 28a and the fourth external electrode 30d is offset downward in the lamination direction x compared to the fourth bend 29d. Similarly, the other electrode layers located within the second side-side outer layer portion 16d also have a fourth bend 29d, with the second opposing electrode portions 24b-24d connecting the second internal electrode layers 22b-22d and the second side-side lead-out electrode portions 28b-28d of the second side surface 10d. Thus, the bend faces the mounting surface of the mounting substrate for mounting the three-terminal type multilayer ceramic capacitor 200.

[0320] As a result, the total length of the first side lead-out electrode portion 26a and the second side lead-out electrode portion 28a, which are formed obliquely towards the mounting surface of the mounting substrate of the capacitor through the third bending portion 29c and the fourth bending portion 29d, is maximized, and the current path from the second internal electrode layer 22a to 22d to the mounting substrate is formed with the shortest distance, thereby improving the low ESL characteristics of the three-terminal type multilayer ceramic capacitor 200.

[0321] Furthermore, the third curved portion 29c of the second inner electrode layers 22a to 22d is located on the inner layer 14 side at a position that is half the length z dimension between the outermost surface of the inner layer 14 on the first side 10c and the first side 10c side.

[0322] In addition, the fourth curved portion 29d of the second inner electrode layers 22a to 22d is located on the inner layer 14 side at a position that is half the length z dimension between the outermost surface of the inner layer 14 on the second side 10d and the second side 10d side.

[0323] Therefore, by bending the first side-side lead-out electrode portions 26a-26d and the second side-side lead-out electrode portions 28a-28d at an earlier stage, these lead-out electrode portions are led out to a position closer to the mounting surface of the mounting substrate, making it easier to achieve the above-mentioned effects of the present invention.

[0324] Furthermore, in the laminate 10, the following relationship exists between an adjacent pair of second internal electrode layers 22, a first internal electrode layer 21 located between them, and a dielectric layer 12 located between them.

[0325] That is, the thickness of the dielectric layer 12 located at half the width direction y between the outermost surfaces of the inner layer portion 14 on the first side 10c and the second inner electrode layer 22 adjacent in the stacking direction x is set as A3; the thickness of the dielectric layer 12 located at half the width direction y between the outermost surfaces of the inner layer portion 14 on the second side 10d and the first inner electrode layer 21 adjacent in the stacking direction x is set as A4; the thickness of the dielectric layer 12 located in the central portion of the inner layer portion 14 and located between the first inner electrode layer 21 and the second inner electrode layer 22 adjacent in the stacking direction x is set as B; and the thickness of the first inner electrode layer 21 or the second inner electrode layer 22 adjacent in the stacking direction x in the central portion of the inner layer portion 14 is set as C. At this time, the relationship is A3>2×B+C and A4>2×B+C.

[0326] Therefore, in the laminate 10, the first side-side lead-out electrode portions 26a to 26d disposed in the first side-side outer layer portion 16c and the second side-side lead-out electrode portions 28a to 28d disposed in the second side-side outer layer portion 16d can be inclined at a larger bending angle from the inner layer portion 14 toward the mounting surface side of the mounting substrate, and the above-mentioned effects of the present invention can be obtained more easily.

[0327] (Method for determining A3)

[0328] When the thickness of the dielectric layer 12 located at half the width direction y of the first side outer layer 16c and between adjacent second inner electrode layers 22 in the stacking direction x is set as A3, A3 is measured by the method shown below.

[0329] First, the cross-section of the three-terminal multilayer ceramic capacitor 200 is exposed. Specifically, grinding is performed until 1 / 2L of the three-terminal multilayer ceramic capacitor 200 is reached, and grinding is performed approximately parallel to the first end face 10e or the second end face 10f to expose the WT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the dielectric layer 12 located at 1 / 2 of the length z dimension of the outer layer portion 16c of the first side surface and between adjacent second internal electrode layers 22 in the stacking direction x. At this time, the thickness of 10 consecutive dielectric layers 12 located between adjacent second internal electrode layers 22 in the outer layer portion 16c of the first side surface is measured, starting from the side closest to the first main surface 10a or the side closest to the second main surface 10b. The average of these thicknesses is then used to determine the dimension A3 of a three-terminal multilayer ceramic capacitor 200.

[0330] (Method for determining A4)

[0331] When the thickness of the dielectric layer 12 located at half the width direction y of the second side outer layer 16d and between adjacent second inner electrode layers 22 in the stacking direction x is set as A4, A4 is measured by the method shown below.

[0332] First, the cross-section of the three-terminal multilayer ceramic capacitor 200 is exposed. Specifically, grinding is performed until 1 / 2L of the three-terminal multilayer ceramic capacitor 200 is reached, and grinding is performed approximately parallel to the first end face 10e or the second end face 10f to expose the WT cross-section. Next, a scanning electron microscope (SEM) is used to measure the thickness of the dielectric layer 12 located at 1 / 2 of the length dimension of the outer layer portion 16c on the first side side and between adjacent second internal electrode layers 22 in the stacking direction in the ground cross-section. At this time, the thickness of 10 consecutive dielectric layers 12 located between adjacent second internal electrode layers 22 from the outer layer portion 16d on the second side side, starting from the side closest to the first main surface 10a or the side closest to the second main surface 10b, is measured, and the average of these thicknesses is set as the dimension A4 of a three-terminal multilayer ceramic capacitor 200.

[0333] It should be noted that this describes the case where the first bending portion 29a and the second bending portion 29b of each of the first internal electrode layers 21 are all bent in the same direction. However, for a portion of the electrode layer constituting the first internal electrode layer 21, the bending portion of the present invention may also be a structure that bends in different directions.

[0334] Furthermore, in the above description, the case where the first curved portion 29a and the second curved portion 29b have a single curved point was described, but the curved point of the present invention may also be composed of multiple curved points.

[0335] Furthermore, in the above description, when viewed in a cross section (LT section) parallel to the first side surface 10c or the second side surface 10d, the angles of the first curved portion 29a and the second curved portion 29b may increase or decrease as they approach either the first main surface 10a or the second main surface 10b.

[0336] It should be noted that when the above conditions of thickness A3, B and C are met and the view is taken in a cross section (WT section) parallel to the first end face 10e or the second end face 10f, the angles of the multiple third bends 29c of the laminate 10 can also be changed such that the angle of the third bend 29c located on the side close to the second main face 10b is larger or smaller.

[0337] Therefore, in the laminate 10, the first side-side lead-out electrode portions 26a to 26d disposed within the first side-side outer layer portion 16c are arranged to expand radially from the inner layer portion 14, and their mutual spacing is larger than the mutual spacing of the second opposing electrode portions 24a to 24d disposed within the inner layer portion 14.

[0338] When the conditions of thicknesses A4, B and C are met, and the view is taken in a cross section (WT section) parallel to the first end face 10e or the second end face 10f, the angles of the plurality of fourth curved portions 29d of the laminate 10 can also be varied such that the angle of the second curved portion 29b located on the side close to the second main face 10b is larger or smaller.

[0339] Therefore, in the laminate 10, the second side-side lead-out electrode portions 28a to 28d disposed within the second side-side outer layer portion 16d are arranged to widen radially from the inner layer portion 14, and their mutual spacing is greater than that of the second opposing electrode portions 24a to 24d disposed within the inner layer portion 14.

[0340] The angle formed by the second opposing electrode portions 24a to 24d and the first side-side lead-out electrode portions 26a to 26d through the third bending portion 29c is preferably 0.1° or more and 40.0° or less.

[0341] The angle formed by the second opposing electrode portions 24a to 24d and the second side-side lead-out electrode portions 28a to 28d through the fourth bending portion 29d is preferably 0.1° or more and 40.0° or less.

[0342] It should be noted that when observing in the stacking direction x, such as Figure 18 As shown, the third curved portion 29c is manifested as a pair of ridge portions KL formed by the intersecting second opposing electrode portion 24a and the first side side lead-out electrode portion 26a.

[0343] Additionally, when observing in the stacking direction x, such as Figure 18 As shown, the fourth curved portion 29d is manifested as a pair of ridge portions KL formed by the intersecting second opposing electrode portion 24a and the second side side lead-out electrode portion 28a.

[0344] The three-terminal multilayer ceramic capacitor 200 of the second embodiment of the present invention, by having the above structure, not only has the effect of the three-terminal multilayer ceramic capacitor 100 of the first embodiment, but also has the same various effects based on the same function as the three-terminal multilayer ceramic capacitor 100 of the first embodiment.

[0345] That is, the three-terminal multilayer ceramic capacitor 100 of the second embodiment of the present invention forms a third bend 29c and a fourth bend 29d, such that the first side-side lead-out electrode portions 26a-26d and the second side-side lead-out electrode portions 28a-28d are inclined toward the mounting surface side of the mounting substrate of the three-terminal multilayer ceramic capacitor 200. Therefore, compared with the conventional example, the current path from the second inner electrode layers 22a-22d to the mounting substrate can be shortened. This further improves the low ESL characteristics of the three-terminal multilayer ceramic capacitor 200.

[0346] It should be noted that the various modifications of the first bent portion 29a and the second bent portion 29b of the three-terminal type multilayer ceramic capacitor 100 described in the first embodiment are also applied to the three-terminal type multilayer ceramic capacitor 200 of the second embodiment, and achieve the same effect as the modifications.

[0347] b. Mounting structure of three-terminal multilayer ceramic capacitors

[0348] Next, refer to Figure 20 The mounting structure of the three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention will be described. Specifically, regarding the mounting structure of the capacitor... Figure 14 The same or equivalent structures are marked with the same symbols. Detailed descriptions of structures and operations common to the third embodiment with reference to this figure are omitted.

[0349] like Figure 20 As shown, the mounting structure 600 of the three-terminal multilayer ceramic capacitor includes the three-terminal multilayer ceramic capacitor 200 of the second embodiment and the mounting substrate 50.

[0350] The mounting structure 600 of the three-terminal multilayer ceramic capacitor of the fourth embodiment of the present invention, having the structure described above, is mounted on the mounting substrate 50 such that the second main surface 10b of the three-terminal multilayer ceramic capacitor 200 faces the substrate-side mounting surface 51a. As a result, the electrical connection between the three-terminal multilayer ceramic capacitor 100 and the mounting substrate 50 is achieved when the distance between the first side-side lead-out electrode portions 26a-26d and the second side-side lead-out electrode portions 28a-28d extending from the first side-side and the second side-side 10d and the substrate-side mounting surface 51a of the mounting substrate 50 is minimized.

[0351] Therefore, the mounting structure 600 of the three-terminal multilayer ceramic capacitor of the first embodiment of the present invention directly reflects the various functions of the three-terminal multilayer ceramic capacitor 200 of the second embodiment of the present invention described above. That is, compared with the conventional example, the current path from the first internal electrode layers 21a to 21d and the second internal electrode layers 22a to 22d of the three-terminal multilayer ceramic capacitor 200 to the mounting substrate 50 can be shortened.

[0352] This results in various effects of the three-terminal multilayer ceramic capacitor 200 according to the second embodiment of the present invention and improves the low ESL characteristics in the mounting structure of the three-terminal multilayer ceramic capacitor.

[0353] It should be noted that, in the above description, the three-terminal multilayer ceramic capacitor 200 is mounted on the mounting substrate 50 with its second main surface 10b facing the substrate-side mounting surface 51a. However, when the ends of the first side-side electrode portions 26a-26d and the second side-side electrode portions 28a-28d extending from the first side surface 10c and the second side surface 10d are located near the first main surface 10a, that is, when the third bending portion 29c and the fourth bending portion 29d of the second internal electrode layer 22 are bent toward the first main surface 10a, the three-terminal multilayer ceramic capacitor 200 is mounted on the mounting substrate 50 with its first main surface 10a facing the substrate-side mounting surface 51a. This achieves the same structure as when the first main surface 10a is facing the substrate-side mounting surface 51a, and provides various effects reflecting the various effects of the three-terminal multilayer ceramic capacitor 200 of the second embodiment of the present invention.

[0354] c. Manufacturing method of three-terminal multilayer ceramic capacitor

[0355] Next, the manufacturing method of the three-terminal multilayer ceramic capacitor according to the second embodiment will be described. The difference between the manufacturing method of the three-terminal multilayer ceramic capacitor in this embodiment and the manufacturing method of the three-terminal multilayer ceramic capacitor in the first embodiment lies in the fabrication process of the multilayer wafer. Detailed descriptions of the remaining fabrication processes of the multilayer wafer, which are common to the manufacturing method of the multilayer ceramic capacitor in the first embodiment, and other fabrication processes are omitted.

[0356] The manufacturing process of the laminated sheets in the manufacturing method of the three-terminal type multilayer ceramic capacitor of the second embodiment is as follows.

[0357] In this embodiment, at the positions of the first and second side outer layers of the laminate, the conductive paste for the dielectric layer is applied to the portions of the first coated dielectric sheet that are not coated with the internal electrode layer, for example by screen printing, gravure printing, or printing using an inkjet printer. Specifically, refer to... Figure 18The layout of the first internal electrode layer and the dielectric layer disposed thereon is shown. In the first coated dielectric sheet, the coating region ARc, located closer to the first side edge than the first side edge of the first opposing electrode portion, is coated with a dielectric paste for the dielectric layer. Similarly, in the coating region ARd, located closer to the second side edge than the second side edge of the first opposing electrode portion, in the first coated dielectric sheet, a dielectric paste for the dielectric layer is coated.

[0358] This increases the thickness of the coating area ARc, which is closer to the first side side than the portion corresponding to boundary Bc, and the thickness of the coating area ARd, which is closer to the second side side than the portion corresponding to boundary Bd, in the first coated dielectric sheet. The boundary Bc coincides with the end edge of the first side side of the first counter electrode portion, and the boundary Bd coincides with the end edge of the second side side of the first counter electrode portion.

[0359] Next, a predetermined number of outer layer dielectric sheets without the pattern of the internal electrode layer are stacked to form a portion on the second main surface side that becomes the outer layer portion on the second main surface side. Then, a first coated dielectric sheet with the pattern of the first internal electrode layer printed on it and a second coated dielectric sheet with the pattern of the second internal electrode layer printed on it are sequentially stacked on the portion that becomes the outer layer portion on the second main surface side, thereby forming the structure of the present invention, thereby forming a portion including an inner layer portion. On the portion including the inner layer portion, a predetermined number of outer layer dielectric sheets without the pattern of the internal electrode layer printed on it are stacked to form a portion on the first main surface side that becomes the outer layer portion on the first main surface side.

[0360] When forming the portion including the inner layer, when the first coated dielectric sheet is laminated onto the second coated dielectric sheet, the two end portions of the first coated dielectric sheet are bent in the lamination direction x along the boundaries Ba and Bb located on the two end faces of the portion of the second coated dielectric sheet that becomes the second opposing electrode portion. As a result, a portion corresponding to the first bent portion and the second bent portion is formed in the first inner electrode layer of the laminate.

[0361] Furthermore, when forming the portion including the inner layer, when the first coated dielectric sheet is laminated onto the second coated dielectric sheet, portions on both sides of the second coated dielectric sheet are bent in the lamination direction x along the boundaries Bc and Bd of the portions on both sides of the first coated dielectric sheet that form the first opposing electrode portion. As a result, portions corresponding to the third and fourth bent portions are formed in the second inner electrode layer of the laminate.

[0362] At this point, by configuring the structure to apply dielectric paste to all the second coated dielectric sheets constituting the laminate, the thickness of the portions coated with dielectric paste is greater than the thickness of the portions not coated with dielectric paste, and gradually increases according to the number of laminates. As a result, in Figure 9 In the completed laminated body shown, when the thickness of the first end face side outer layer and the second end face side outer layer is set to C, the thickness of the dielectric layer in the inner layer is set to B, the thickness of the dielectric layer formed by the above-mentioned dielectric paste, that is, the dielectric layer sandwiched by an adjacent pair of first end face side lead-out electrodes along the lamination direction x is set to A1, and the thickness of the dielectric layer sandwiched by an adjacent pair of second end face side lead-out electrodes along the lamination direction x is set to A2, the thicknesses A1, A2, B and C can have the relationship A1>2×B+C and A2>2×B+C.

[0363] Furthermore, by configuring the structure to apply dielectric paste to all the first coated dielectric sheets constituting the laminate, the thickness of the portions coated with dielectric paste is greater than the thickness of the portions not coated with dielectric paste, and gradually increases with the number of laminates. As a result, in Figure 19 In the completed laminated body shown, when the thickness of the first or second inner electrode layer is set to C, the thickness of the dielectric layer in the inner layer is set to B, the thickness of the dielectric layer formed by the dielectric paste (i.e., the dielectric layer sandwiched by a pair of adjacent first side electrode portions along the lamination direction x) is set to A3, and the thickness of the dielectric layer sandwiched by a pair of adjacent second side electrode portions along the lamination direction x is set to A4, the thicknesses A1, A2, B, and C can have the relationship A3>2×B+C and A4>2×B+C.

[0364] As described above, a three-terminal multilayer ceramic capacitor of the second embodiment is obtained.

[0365] D. Experimental Example 1

[0366] According to the manufacturing method described above, the product is manufactured as follows: Figure 1 The ESL of the three-terminal multilayer ceramic capacitor shown was measured.

[0367] (a) Specifications of the sample in Experimental Example 1

[0368] As Experimental Example 1, a three-terminal multilayer ceramic capacitor with the following specifications was prepared. The specifications of the prepared sample are as follows.

[0369] • Dimensions (design values) of a three-terminal multilayer ceramic capacitor: L×W×T=1.136mm×0.632mm×0.361mm

[0370] • The main component of the dielectric layer is BaTiO3.

[0371] • Capacitance: 7.29μF

[0372] Rated voltage: 4V

[0373] • Dielectric layer thickness (thickness B): Refer to Table 1

[0374] • Electrode material of the first internal electrode layer: Ni

[0375] • Number of sheets in the first internal electrode layer: 117 sheets

[0376] • Thickness (C) of the first internal electrode layer: 0.56 μm

[0377] • The first end face side electrode section (total 117 sheets) and the second end face side electrode section (total 117 sheets) are formed with a first curved section and a second curved section that bend towards the mounting substrate when viewed in the width direction y.

[0378] In sample No. 1, the thickness of the dielectric layer located at half the length z dimension between the outermost surface of the inner layer portion of the first end face and the first end face side and located between adjacent first internal electrode layers in the stacking direction x is set as A1. The thickness of the dielectric layer located at half the length z dimension between the outermost surface of the inner layer portion of the second end face and the second end face side and located between adjacent first internal electrode layers in the stacking direction x is set as A2. The thickness of the dielectric layer located in the central portion of the inner layer portion and located between adjacent first internal electrode layers and second internal electrode layers 22 in the stacking direction x is set as B. The thickness of the first internal electrode layer or second internal electrode layer located in the central portion of the inner layer portion and located between adjacent first internal electrode layers and second internal electrode layers 22 in the stacking direction x is set as C. At this time, the relationship becomes A1>2×B+C and A2>2×B+C.

[0379] In sample number 2, for the thicknesses A1, A2, B and C mentioned above, the relationships are A1≈2×B+C and A2≈2×B+C.

[0380] In sample number 3, for the thicknesses A1, A2, B and C mentioned above, the relationship is A1<2×B+C and A2<2×B+C.

[0381] (b) Methods for measuring thicknesses A1, A2, B and C

[0382] The thicknesses of A, B, and C were measured as follows.

[0383] (Method for determining A1)

[0384] The thickness A1 of the dielectric layer located at 1 / 2 of the length dimension of the outer layer on the first end face side and between adjacent first inner electrode layers in the stacking direction was measured by the following method.

[0385] First, the cross-section of a three-terminal multilayer ceramic capacitor used as a test material is exposed. Specifically, grinding is performed until 1 / 2 W of the three-terminal multilayer ceramic capacitor is reached, roughly parallel to the side surface, to expose the LT cross-section. Next, using a scanning electron microscope (SEM), the thickness of the dielectric layer located at 1 / 2 of the length dimension of the outer layer on the first end face side and between adjacent first internal electrode layers in the stacking direction is measured. At this time, the thickness of 10 consecutive dielectric layers starting from the side closest to the first main face or the side closest to the second main face of the dielectric layer between adjacent first internal electrode layers on the outer layer on the first end face side is measured, and the average of these thicknesses is set as the dimension A1 of a three-terminal multilayer ceramic capacitor.

[0386] (Method for determining A2)

[0387] The thickness A2 of the dielectric layer located at 1 / 2 of the length dimension of the outer layer on the second end face side and between adjacent first inner electrode layers in the stacking direction was measured by the following method.

[0388] First, the cross-section of a three-terminal multilayer ceramic capacitor used as a test material is exposed. Specifically, grinding is performed until 1 / 2 W of the three-terminal multilayer ceramic capacitor is reached, grinding approximately parallel to the side surface, to expose the LT cross-section. Next, using a scanning electron microscope (SEM), the thickness of the dielectric layer located at 1 / 2 of the length dimension of the outer layer on the second end face side and between adjacent first internal electrode layers in the stacking direction is measured. At this time, the thickness of 10 consecutive dielectric layers starting from the outermost first main face side or the outermost second main face side of the dielectric layer between adjacent first internal electrode layers on the second end face side is measured, and the average of these thicknesses is set as the dimension A2 of a three-terminal multilayer ceramic capacitor.

[0389] (Method for determining B)

[0390] The thickness B of the dielectric layer located in the central part of the inner layer and between the first inner electrode layer and the second inner electrode layer that are adjacent in the stacking direction was measured by the following method.

[0391] That is, first, a cross-section of a three-terminal multilayer ceramic capacitor as a sample is exposed. Specifically, grinding is performed until reaching the 1 / 2W position of the three-terminal multilayer ceramic capacitor, and grinding is performed substantially parallel to the side surface to expose the LT cross-section. Subsequently, using a scanning electron microscope (SEM), the thickness of the dielectric layer located between the first internal electrode layer and the second internal electrode layer adjacent to each other in the lamination direction at the central portion of the inner layer in the ground cross-section was measured. At this time, the thicknesses of a total of 10 consecutive dielectric layers located at the central portion of the inner layer and between the first internal electrode layer and the second internal electrode layer adjacent in the lamination direction were measured, and the dimension obtained by averaging these thicknesses was defined as the dimension B of one three-terminal multilayer ceramic capacitor.

[0392] (Measurement Method for C)

[0393] The thickness C of the first internal electrode layer or the second internal electrode layer adjacent in the lamination direction located at the central portion of the inner layer was measured by the following method.

[0394] That is, first, a cross-section of the three-terminal multilayer ceramic capacitor is exposed. Specifically, grinding is performed until reaching the 1 / 2W position of the three-terminal multilayer ceramic capacitor, and grinding is performed substantially parallel to the side surface to expose the LT cross-section. Subsequently, using a scanning electron microscope (SEM), the thickness of the first internal electrode layer or the second internal electrode layer adjacent in the lamination direction at the central portion of the inner layer in the ground cross-section was measured. At this time, the thicknesses of a total of 10 adjacent internal electrode layers of the first internal electrode layer or the second internal electrode layer were measured, and the dimension obtained by averaging these thicknesses was defined as the dimension C of one three-terminal multilayer ceramic capacitor.

[0395] (c) Measurement Method for ESL

[0396] Each sample of each sample number in Experimental Example 1 was mounted on a mounting substrate having a mounting surface, thereby preparing circuit board samples. A voltage was applied to each external electrode via the pads of these circuit boards, and the ESL value was measured. Specifically, a voltage was applied to each external electrode, and the ESL value of each sample at a frequency of 100 MHz was measured using a network analyzer (manufactured by Agilent Technologies, model: E5071B). The number of samples for each sample number was 5 respectively. Furthermore, the ESL value of the samples of each sample number was calculated as the average value of the 5 samples. It should be noted that the acceptance criterion for qualified products is 110 pH or less.

[0397] (d) Results

[0398] Table 1 shows the ESL measurement results for the samples of Sample No. 1 to Sample No. 3.

[0399] [Table 1]

[0400]

[0401] According to the results in Table 1, in sample 1, when the thickness of the dielectric layer located at 1 / 2 of the length z dimension between the outermost surface of the inner layer portion on the first end face and the first end face side and located between adjacent first internal electrode layers in the stacking direction x is set as A1, the thickness of the dielectric layer located at 1 / 2 of the length z dimension between the outermost surface of the inner layer portion on the second end face and the second end face side and located between adjacent first internal electrode layers in the stacking direction x is set as A2, the thickness of the dielectric layer located in the central portion of the inner layer portion and located between adjacent first internal electrode layers and second internal electrode layers in the stacking direction x is set as B, and the thickness of the first internal electrode layer or second internal electrode layer located in the central portion of the inner layer portion and located between adjacent first internal electrode layers and second internal electrode layers in the stacking direction x is set as C, sample 1 meets the conditions A1>2×B+C and A2>2×B+C. Therefore, the best ESL of samples 1 to 3 is obtained.

[0402] Furthermore, when the end face electrode portions of samples 1 to 3 are all provided with bent portions, based on the ESR results of each sample from sample 1 to sample 3, it was confirmed that the relationship between "A1 and A2" and "2×B+C" can affect the ESL of the multilayer ceramic capacitor.

[0403] E. Experimental Example 2

[0404] Manufactured according to the above manufacturing method as follows: Figure 15 The ESL of the three-terminal multilayer ceramic capacitor shown was measured.

[0405] (a) Specifications of the sample in Experimental Example 2

[0406] As Experimental Example 2, a three-terminal multilayer ceramic capacitor with the following specifications was prepared. The specifications of the prepared sample are as follows.

[0407] • Dimensions (design values) of a three-terminal multilayer ceramic capacitor: L×W×T=1.136mm×0.632mm×0.361mm

[0408] • The main component of the dielectric layer is BaTiO3.

[0409] • Capacity: 7.29μF

[0410] Rated voltage: 4V

[0411] • Dielectric layer thickness (thickness B): Refer to Table 1

[0412] • Electrode material of the first internal electrode layer: Ni

[0413] • Number of sheets in the first internal electrode layer: 117 sheets

[0414] • Thickness (C) of the first internal electrode layer: 0.56 μm

[0415] Regarding the thickness of the dielectric layer between a pair of adjacent first end face side lead-out electrode portions (a total of 117 sheets), the thickness A1 on the first end face side is fixed at 1.94 μm, and the thickness A2 on the second end face side is fixed at 1.97 μm.

[0416] • The first end face side electrode section (total 117 sheets) and the second end face side electrode section (total 117 sheets) are formed with a first bent portion and a second bent portion that bend towards the mounting substrate when viewed in the width direction y. In addition, the first side side electrode section (total 117 sheets) and the second side side electrode section (total 117 sheets) are formed with a third bent portion and a fourth bent portion that bend towards the mounting substrate when viewed in the width direction y.

[0417] In sample 4, the thickness of the dielectric layer 12 located at half the width direction y between the outermost surfaces of the inner layer 14 on the first side 10c and the first side 10c side, and located between adjacent second internal electrode layers 22 in the stacking direction x, is set as A3. The thickness of the dielectric layer 12 located at half the width direction y between the outermost surfaces of the inner layer 14 on the second side 10d and the second side 10d side, and located between adjacent first internal electrode layers 21 in the stacking direction x, is set as A4. The thickness of the dielectric layer 12 located in the central part of the inner layer 14 and located between adjacent first internal electrode layers 21 and second internal electrode layers 22 in the stacking direction x is set as B. The thickness of the first internal electrode layer 21 or second internal electrode layer 22 located in the central part of the inner layer 14 and located between adjacent first internal electrode layers 21 and second internal electrode layers 22 in the stacking direction x is set as C. Thus, A3>2×B+C and A4>2×B+C.

[0418] In sample number 5, for the aforementioned thicknesses A3, A4, B, and C, the relationships are A3≈2×B+C and A4≈2×B+C.

[0419] In sample number 6, for the aforementioned thicknesses A3, A4, B, and C, the relationship becomes A3 < 2 × B + C and A4 < 2 × B + C.

[0420] (b) Methods for measuring thicknesses A3 and A4

[0421] The thicknesses of A3 and A4 were measured as follows. It should be noted that the measurement methods for thicknesses A1, A2, B, and C are the same as those described in Experimental Example 1.

[0422] (Method for determining A3)

[0423] The thickness A3 of the dielectric layer located at 1 / 2 of the width dimension of the outer layer of the first side surface and between adjacent second inner electrode layers in the stacking direction was measured by the following method.

[0424] First, the cross-section of the three-terminal multilayer ceramic capacitor is exposed. Specifically, grinding is performed until 1 / 2L of the three-terminal multilayer ceramic capacitor, roughly parallel to the end face, to expose the WT cross-section. Next, using a scanning electron microscope (SEM), the thickness of the dielectric layer located at 1 / 2 of the length dimension of the outer layer of the first side surface and between adjacent second inner electrode layers in the stacking direction is measured. At this time, the thickness of 10 consecutive dielectric layers starting from the outermost side of the first side surface and between adjacent second inner electrode layers is measured, and the average of these thicknesses is set as the dimension A3 of a three-terminal multilayer ceramic capacitor.

[0425] (Method for determining A4)

[0426] The thickness A4 of the dielectric layer located at 1 / 2 of the width dimension of the outer layer of the second side and between adjacent second inner electrode layers in the stacking direction was measured by the following method.

[0427] First, the cross-section of the three-terminal multilayer ceramic capacitor is exposed. Specifically, grinding is performed until 1 / 2L of the three-terminal multilayer ceramic capacitor, roughly parallel to the end face, to expose the WT cross-section. Next, using a scanning electron microscope (SEM), the thickness of the dielectric layer located at 1 / 2 of the length dimension of the outer layer of the first side surface and between adjacent second inner electrode layers in the stacking direction is measured. At this time, the thickness of 10 consecutive dielectric layers starting from the side closest to the first main surface or the side closest to the second main surface of the dielectric layer between adjacent second inner electrode layers on the outer layer of the second side surface is measured, and the average of these thicknesses is set as the dimension A4 of a three-terminal multilayer ceramic capacitor.

[0428] (c) Methods for determining ESL

[0429] Samples of each test piece number in Experimental Example 2 were respectively mounted on a mounting substrate having a mounting surface to prepare samples of circuit substrates. A voltage was applied to each external electrode via the pads of these circuit substrates, and the ESL value was measured. Specifically, a voltage was applied to each external electrode, and the ESL value of each sample at a frequency of 100 MHz was measured using a network analyzer (manufactured by Agilent, model: E5071B). The number of samples for each test piece number was 5, respectively. Moreover, the ESL value of the sample of each test piece number was calculated as the average value of 5 samples. It should be noted that the criterion for determining a qualified product is 110 pH or less.

[0430] (d) Results

[0431] Table 2 shows the ESL measurement results of samples from test piece number 4 to test piece number 6.

[0432] [Table 2]

[0433]

[0434] According to the results in Table 2, for the sample of test piece number 6, when A1 is defined as the thickness of a dielectric layer between adjacent first internal electrode layers in the lamination direction x at a position that is 1 / 2 of the dimension in the length direction z between the first end surface and the outermost surface of the inner layer portion on the first end surface side; A2 is defined as the thickness of a dielectric layer between adjacent first internal electrode layers in the lamination direction x at a position that is 1 / 2 of the dimension in the length direction z between the second end surface and the outermost surface of the inner layer portion on the second end surface side; B is defined as the thickness of a dielectric layer between a first internal electrode layer and a second internal electrode layer adjacent in the lamination direction x at the central part of the inner layer portion; C is defined as the thickness of the first internal electrode layer or the second internal electrode layer adjacent in the lamination direction x at the central part of the inner layer portion; the sample of test piece number 1 satisfies the conditions of A1>2×B+C and A2>2×B+C. Furthermore, when A3 is defined as the thickness of a dielectric layer between adjacent second internal electrode layers in the lamination direction x at a position that is 1 / 2 of the dimension in the width direction y between the first side surface 10c and the outermost surface of the inner layer portion 14 on the first side surface side; A4 is defined as the thickness of a dielectric layer between adjacent first internal electrode layers in the lamination direction x at a position that is 1 / 2 of the dimension in the width direction y between the second side surface and the outermost surface of the inner layer portion on the second side surface side; B is defined as the thickness of a dielectric layer between a first internal electrode layer and a second internal electrode layer adjacent in the lamination direction x at the central part of the inner layer portion; C is defined as the thickness of the first internal electrode layer or the second internal electrode layer adjacent in the lamination direction x at the central part of the inner layer portion, it satisfies the conditions of A3>2×B+C and A4>2×B+C. Therefore, the best ESL among the samples from test piece number 1 to test piece number 6 is obtained.

[0435] Furthermore, when the end face electrode portions of samples 1 to 3 are all provided with bent portions and the side face electrode portions are also provided with bent portions, based on the ESR results of samples 4 to 6, it was confirmed that the relationship between “A3 and A4” and “2×B+C” can affect the ESL of the multilayer ceramic capacitor.

[0436] It should be noted that, as described above, the embodiments of the present invention are disclosed in the description, but the present invention is not limited thereto.

[0437] Furthermore, the first end face side lead-out electrode portions 25a to 25d of the first internal electrode layers 21a to 21d and the second end face side lead-out electrode portions 27a to 27d can be either one of the sets having a curved portion.

[0438] Similarly, the first side electrode portion 26a-26d of the second internal electrode layer 22a-22d and the second side electrode portion 28a-28d can be either one of the groups having a curved portion.

[0439] Furthermore, regarding the group of first end face side lead-out electrode portions 25a to 25d of the first internal electrode layers 21a to 21d and the group of second end face side lead-out electrode portions 27a to 27d, each may have a bent portion as a part of the lead-out electrode portion included in the group.

[0440] Similarly, regarding the group of first side-side lead-out electrode portions 26a-26d and the group of second side-side lead-out electrode portions 28a-28d of the second internal electrode layers 22a-22d, each of the lead-out electrode portions included in the group may have a bent portion.

[0441] Thus, the bending portion of the present invention can be formed in all or part of the plurality of internal electrode layers in the laminate as bending toward the mounting surface for connecting the external electrode between the boundary between the opposing electrode portion and the lead-out electrode portion and the lead-out electrode portion, without being limited by other specific structures.

[0442] As described above, various changes can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or configuration without departing from the technical concept and scope of the invention, and these changes are also included in the invention.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction and the width direction. A first external electrode is disposed on the first end face; A second external electrode is disposed on the second end face; A third external electrode is disposed on the first side surface; and A fourth external electrode is disposed on the second side. in, The laminate has an inner layer portion with the plurality of internal electrode layers facing each other. The plurality of internal electrode layers have a first internal electrode layer and a second internal electrode layer. The first internal electrode layer has a first opposing electrode portion opposite to the second internal electrode layer, a first lead-out electrode portion extending from the first opposing electrode portion and extending toward the first end face, and a second lead-out electrode portion extending from the first opposing electrode portion and extending toward the second end face. The second internal electrode layer has a second opposing electrode portion opposite to the first internal electrode layer, a third lead-out electrode portion extending from the second opposing electrode portion and extending toward the first side, and a fourth lead-out electrode portion extending from the second opposing electrode portion and extending toward the second side. The first lead-out electrode portion has a first bent portion. The second lead-out electrode portion has a second bent portion. The first bending portion allows part or all of the first lead-out electrode portion to be bent and positioned facing the second main surface. The second bending portion allows part or all of the second lead-out electrode portion to be bent and positioned toward the second main surface. The end of the first lead-out electrode portion that is exposed on the first end face and connected to the first external electrode is located further towards the second main surface in the stacking direction than the first curved portion. The end of the second lead-out electrode portion that is exposed on the second end face and connected to the second external electrode is located in the stacking direction closer to the second main surface than the second curved portion.

2. The multilayer ceramic capacitor according to claim 1, wherein, The first curved portion is located on the inner layer side at a position that is half the length of the inner layer portion between the first end face and the outermost surface of the inner layer portion on the first end face side. The second curved portion is located on the inner layer side at a position that is half the length of the inner layer portion between the second end face and the outermost surface of the inner layer portion on the side of the second end face.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, Let A1 be the thickness of the dielectric layer located at half the length of the inner layer portion between the first end face and the outermost surface of the first end face side, and located between adjacent first inner electrode layers in the stacking direction. The thickness of the dielectric layer located at half the length of the outermost surface of the inner layer between the second end face and the second end face side, and located between adjacent first inner electrode layers in the stacking direction, is defined as A2. Let the thickness of the dielectric layer located in the central part of the inner layer and between the first inner electrode layer and the second inner electrode layer adjacent in the stacking direction be B. The thickness of the first internal electrode layer or the second internal electrode layer adjacent to each other in the stacking direction at the center of the inner layer is defined as C. At this point, the relationship is A1 > 2 × B + C and A2 > 2 × B + C.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The third lead-out electrode portion has a third curved portion. The fourth lead-out electrode section has a fourth bend. The third bending portion allows part or all of the third lead-out electrode portion to be bent and positioned facing either the first main surface or the second main surface. The fourth bending portion allows part or all of the fourth lead-out electrode portion to be bent and configured to face either the first main surface or the second main surface.

5. The multilayer ceramic capacitor according to claim 4, wherein, The third curved portion is located on the inner layer side at a position that is half the width dimension between the outermost surface of the inner layer portion and the first side side. The fourth curved portion is located on the inner layer side at a position that is half the width dimension between the outermost surface of the inner layer portion and the second side side.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The thickness of the dielectric layer located at half the width dimension between the outermost surfaces of the inner layer portion of the first side and the first side side, and located between adjacent second inner electrode layers in the stacking direction, is defined as A3. The thickness of the dielectric layer located at half the width dimension between the outermost surfaces of the inner layer portion of the second side and the second side side, and located between adjacent first inner electrode layers in the stacking direction, is defined as A4. Let the thickness of the dielectric layer located in the central portion of the inner layer and situated between the first inner electrode layer and the second inner electrode layer adjacent in the stacking direction be defined as B. The thickness of the first internal electrode layer or the second internal electrode layer adjacent to each other in the stacking direction at the center of the inner layer is defined as C. At this point, the relationship is A3 > 2 × B + C and A4 > 2 × B + C.

7. A mounting structure for a multilayer ceramic capacitor, comprising: Mounting substrate; and Multilayer ceramic capacitor mounted on the mounting substrate The laminated ceramic capacitor is the laminated ceramic capacitor according to any one of claims 1 to 3. The mounting base plate has: The core material of the substrate; A first connecting conductor is disposed on the core material and connected to the first external electrode; A second connecting conductor is disposed on the core and connected to the second external electrode; A third connecting conductor is disposed on the core material and connected to the third external electrode; as well as A fourth connecting conductor is disposed on the core material and connected to the fourth external electrode. The multilayer ceramic capacitor is mounted such that the second main surface faces the mounting substrate, such that the distance between the end of the first lead electrode portion exposed on the first end face and connected to the first external electrode and the end of the second lead electrode portion exposed on the second end face and connected to the second external electrode and the mounting surface of the mounting substrate is the shortest distance.

8. The mounting structure of the multilayer ceramic capacitor according to claim 7, wherein, The laminated ceramic capacitor is the laminated ceramic capacitor according to any one of claims 4 to 6. The multilayer ceramic capacitor is mounted such that the second main surface faces the mounting substrate, such that the distance between the end of the third lead electrode portion exposed on the first side and connected to the third external electrode and the end of the fourth lead electrode portion exposed on the second side and connected to the fourth external electrode and the mounting surface of the mounting substrate is the shortest distance.

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