Semiconductor structure and manufacturing method

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The method includes: providing an initial semiconductor structure, the initial semiconductor structure including a substrate and a polysilicon layer; forming a first mask layer on the initial semiconductor structure, the first mask layer having a first ion implantation window defining the gate location of a first transistor; performing a first ion implantation process to adjust the work function of the gate of the first transistor through the first ion implantation window to form the semiconductor structure. The semiconductor structure manufacturing method provided by this disclosure enables work function adjustment of the transistor gate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] With the rapid development of VLSI technology, the size of MOS (Metal Oxide Semiconductor) transistors is constantly decreasing, typically including reducing the channel length of MOS transistors and thinning the gate oxide layer to achieve faster device speeds.

[0003] MOS transistors can be classified into P-type MOS transistors and N-type MOS transistors based on the type of conductive channel. Because NMOS and PMOS have different threshold voltages, they require different work function regulation layers.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0007] An initial semiconductor structure is provided, the initial semiconductor structure comprising a substrate and a polycrystalline silicon layer;

[0008] A first mask layer is formed on the initial semiconductor structure, the first mask layer having a first ion implantation window, the first ion implantation window defining the gate location of the first transistor;

[0009] A first ion implantation process is performed, in which the work function of the gate of the first transistor is adjusted through the first ion implantation window to form a semiconductor structure.

[0010] In one exemplary embodiment of this disclosure, the semiconductor structure further comprises an insulating oxide layer formed between the substrate and the polysilicon layer.

[0011] In one exemplary embodiment of this disclosure, after performing the first ion implantation process, the manufacturing method further includes:

[0012] The first mask layer is removed using a first solvent to form the semiconductor structure, wherein the first solvent is a mixed aqueous solution of ammonia and hydrogen peroxide.

[0013] In one exemplary embodiment of this disclosure, the concentration of ammonia in the first solvent is in a first range, the concentration of hydrogen peroxide is in a second range, and the concentration of water is in a third range, wherein the third range is greater than the second range, and the second range is greater than the first range.

[0014] In one exemplary embodiment of this disclosure, the ratio of the concentration of water to the sum of the concentrations of ammonia and hydrogen peroxide in the first solvent is greater than 5.

[0015] In one exemplary embodiment of this disclosure, removing the first mask layer using a first solvent includes:

[0016] The first mask layer is removed simultaneously using a first solvent and a second solvent, wherein the second solvent is a mixed aqueous solution of sulfuric acid and hydrogen peroxide.

[0017] In one exemplary embodiment of this disclosure, the first mask layer is cleaned multiple times with the first solvent.

[0018] In one exemplary embodiment of this disclosure, the temperature during the cleaning of the first mask layer with the first solvent is 25°C to 30°C.

[0019] In one exemplary embodiment of this disclosure, the time for cleaning the first mask layer with the first solvent is 30s to 150s.

[0020] In one exemplary embodiment of this disclosure, after removing the first mask layer with a first solvent and before forming the semiconductor structure, the manufacturing method further includes:

[0021] A second mask layer is formed on the initial semiconductor structure, the second mask layer having a second ion implantation window, the second ion implantation window defining the gate location of the second transistor;

[0022] A second ion implantation process is performed, and the work function of the gate of the second transistor is adjusted through the second ion implantation window;

[0023] After the second ion implantation process, the second mask layer is removed using the first solvent.

[0024] In one exemplary embodiment of this disclosure, the first transistor is of the opposite type to the second transistor, corresponding to the implanted ion type of the first ion implantation process being opposite to the implanted ion type of the second ion implantation process.

[0025] In one exemplary embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the first ion implanted ion includes B ions, and the second ion implanted ion includes AS / P ions.

[0026] In one exemplary embodiment of this disclosure, the first transistor is an N-type transistor, the second transistor is a P-type transistor, the first ion implanted ions include AS / P ions, and the second ion implanted ions include B ions.

[0027] According to another aspect of the present disclosure, a semiconductor structure is provided, including a substrate and a polysilicon layer, wherein the polysilicon layer is processed by the manufacturing method described above to obtain the semiconductor structure.

[0028] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0029] An insulating oxide layer is located between the substrate and the polycrystalline silicon layer.

[0030] The semiconductor structure manufacturing method disclosed herein forms a semiconductor structure by forming a first mask layer with a first ion implantation window on an initial semiconductor structure, defining the gate position of a first transistor through the first ion implantation window, and then adjusting the work function of the gate of the first transistor through the first ion implantation window to form a semiconductor structure, thereby realizing the adjustment of the gate work function of the transistor.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0033] Figure 1 A schematic diagram illustrating the adjustment relationship between the on-state current and the off-state current, provided for one embodiment of this disclosure;

[0034] Figure 2 A schematic diagram illustrating the relationship between threshold voltage and drain-source current adjustment in one embodiment of this disclosure;

[0035] Figure 3 A schematic diagram illustrating the relationship between threshold voltage and off-state current adjustment in one embodiment of this disclosure;

[0036] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0037] Figure 5 A schematic diagram of a semiconductor structure provided in one embodiment of this disclosure;

[0038] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor structure according to another embodiment of this disclosure;

[0039] Figure 7 A flowchart illustrating a method for manufacturing a semiconductor structure according to yet another embodiment of this disclosure;

[0040] Figure 8 This is a schematic diagram comparing the EOT before and after semiconductor structure optimization, provided as an embodiment of the present disclosure.

[0041] Figure 9 This is a schematic diagram comparing VT / IDS / IOFF before and after semiconductor structure optimization, as provided in one embodiment of this disclosure. Detailed Implementation

[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0043] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0044] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0045] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0046] Due to the combined influence of various factors, the channel of a MOS transistor cannot actually be completely pinched off during operation; that is, the drain current ID of a MOS transistor cannot reach a true zero state. Therefore, in practical applications, when the drain current of a MOS transistor is very close to zero, the voltage difference between the gate and source of the transistor is considered to be the pinch-off voltage, and the resulting drain current is called the off-state current Ioff. Conversely, for NMOS transistors, the drain current generated when the drive voltage VGS is greater than 0 and VGS is a multiple (not less than 1) of the pinch-off voltage is called the on-state current Ion; for PMOS transistors, the drain current generated when VGS is less than 0 and the absolute value of VGS is a multiple (not less than 1) of the pinch-off voltage is also called the on-state current Ion. The off-state current Ioff is actually the drain current of the transistor. The smaller the off-state current, the lower the power consumption of the transistor. Therefore, for MOS transistors, generally, the larger the switching current ratio Ion / Ioff, the lower the power consumption and the faster the transistor. Therefore, it is necessary to increase the switching current ratio Ion / Ioff of the transistor.

[0047] like Figures 1-3 As shown, punctuation 1 represents the electrical performance of the semiconductor device without adjustment. The horizontal axis represents the on-state current ION, and the vertical axis represents the off-state current IOFF. Punctuation 2 represents the electrical performance of the new semiconductor device formed by traditional adjustment methods, mainly achieved by adjusting LDD (shallow doping of the drain region), halo (high doping of the source end of the channel region), and channel concentration. It can be seen that while increasing ION (on-state current), the drain current IOFF (off-state current) is also increased, and the threshold voltage VT is reduced. This is because the effects of these adjustments on ION / IOFF / VT are synchronous inside and near the channel. It is impossible to increase ION while keeping VT / IOFF unchanged. A higher IOFF means increased power consumption, and a lower VT means a lower device turn-on voltage, making it easier to be turned on falsely.

[0048] The embodiments of this disclosure first provide a method for manufacturing a semiconductor structure, such as... Figure 4 As shown, the manufacturing method includes:

[0049] Step S100: Provide an initial semiconductor structure, which includes a substrate and a polysilicon layer;

[0050] Step S200: A first mask layer is formed on the initial semiconductor structure. The first mask layer has a first ion implantation window, which defines the gate location of the first transistor.

[0051] Step S300: Perform the first ion implantation process, and adjust the work function of the gate of the first transistor through the first ion implantation window to form a semiconductor structure.

[0052] The semiconductor structure manufacturing method disclosed herein forms a semiconductor structure by forming a first mask layer with a first ion implantation window on an initial semiconductor structure, defining the gate position of a first transistor through the first ion implantation window, and then adjusting the work function of the gate of the first transistor through the first ion implantation window to form a semiconductor structure, thereby realizing the adjustment of the gate work function of the transistor.

[0053] The steps of the semiconductor structure manufacturing method provided in this disclosure will now be described in detail.

[0054] In step S100, an initial semiconductor structure is provided, which includes a substrate and a polysilicon layer.

[0055] Specifically, an initial semiconductor structure is provided, such as Figure 5 As shown, the semiconductor structure includes a substrate 10 and a polycrystalline silicon layer 30. The substrate 10 is a semiconductor material, including but not limited to a single-crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate. In addition, when the semiconductor substrate is a single-crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate. Furthermore, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

[0056] like Figure 5 As shown, a shallow trench isolation structure (STI) 110 is formed on the substrate 10. The semiconductor substrate can be isolated using shallow trench isolation technology. Shallow trench isolation trenches are formed on the semiconductor substrate, with a depth of, for example, 20 nm to 40 nm. The shallow trench isolation structure is then formed in the etched shallow trench isolation trenches using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition techniques. The shallow trench isolation structure isolates multiple active regions. The material of the shallow trench isolation structure can include insulating materials such as silicon nitride or silicon oxide. As an example, the active regions contain the source / drain and channel regions (not shown) of a MOS device. The MOS device also includes a gate, with the source and drain located on opposite sides of the gate.

[0057] like Figure 5As shown, an insulating oxide layer 20 is further provided between the polysilicon layer 30 and the substrate 10. The insulating oxide layer 20 is used to achieve electrical insulation between the polysilicon layer 30 and the substrate 10. The material of the insulating oxide layer 20 may be, for example, a high dielectric constant material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, or other suitable insulating materials (e.g., organic polymer compounds) or combinations thereof. The insulating oxide layer 20 may be formed by, for example, physical vapor deposition, chemical vapor deposition, spin coating, or a combination thereof.

[0058] The polysilicon layer 30 can serve as the gate of a semiconductor device. Early on, aluminum was widely used as the preferred gate material for MOS (Metal-Oxide-Semiconductor) devices. The MOS fabrication process begins with the definition and doping of the source and drain regions. Then, a gate mask is used to define the gate oxide region, thus forming the aluminum gate. A major drawback of this manufacturing process is that if the gate mask is misaligned, it generates parasitic overlapping input capacitances Cgd and Cgs. Since these capacitances are feedback capacitances, Cgd is more detrimental. Due to Miller capacitance, the switching speed of the transistor is reduced.

[0059] One method to address gate mask misalignment is the so-called "self-aligned gate process." This process first creates the gate region, then uses ion implantation to create the drain and source regions. A thin gate oxide layer acts as a mask for the doping process, preventing further doping under the gate region (channel). Therefore, this process allows the gate to be self-aligned relative to the source and drain regions. Consequently, the source and drain regions do not extend under the gate. The doping process for the drain and source regions requires ultra-high temperature annealing (typically >8000°C). If aluminum is used as the gate material, it will melt at such a high temperature. This is because aluminum's melting point is approximately 660°C. However, if polysilicon is used as the gate material, it will not melt. Therefore, self-alignment of the polysilicon gate is possible. In the case of an aluminum gate, this is impossible, leading to high Cgd and Cgs. Therefore, polysilicon is now widely used as the gate material in most semiconductor devices.

[0060] The source, drain, and gate are connected to the test terminal via contact plugs and wires, respectively, to receive test voltage and current, and to output operating voltage and current.

[0061] In this process, word line trenches (not shown in the figure) can be formed in the region between two adjacent shallow trench isolation structures on the substrate 10 using anisotropic etching. Metal word lines can be formed within the word line trenches by chemical vapor deposition, physical vapor deposition, or other methods. The conductive material forming the word lines includes one or a combination of tungsten, titanium, nickel, aluminum, titanium oxide, and titanium nitride. Other conductive materials may be selected by those skilled in the art, and this disclosure does not limit this selection.

[0062] In step S200, a first mask layer is formed on the initial semiconductor structure. The first mask layer has a first ion implantation window, which defines the gate location of the first transistor.

[0063] Specifically, such as Figure 5 As shown, a first mask material layer, such as photoresist, is deposited on an initial semiconductor structure. Then, a patterned first mask layer 40 is formed by exposing and developing the photoresist, such that the patterned first mask layer 40 has a first ion implantation window, which defines the gate location of the first transistor. The photoresist can be either positive or negative.

[0064] In step S300, a first ion implantation process is performed, in which the work function of the gate of the first transistor is adjusted through the first ion implantation window to form a semiconductor structure.

[0065] Specifically, undoped polysilicon has a very high resistivity, approximately 10⁸ Ω / cm. Therefore, doping methods for polysilicon reduce its resistance. In addition, to adjust the threshold voltage of semiconductor devices, different types of ion implantation are performed on polysilicon to reduce the work function difference between the metal gate and the semiconductor substrate.

[0066] In one embodiment of this disclosure, such as Figure 5 As shown, an N-type polysilicon layer is formed by ion implantation of the polysilicon layer 30 according to the first ion implantation window, which serves as the gate of the N-type transistor. The dopant particles implanted into the polysilicon layer 30 are, for example, at least one of phosphorus (P) or arsenic (As), and the doping concentration can be 10¹³ atom / cm³. 2 -1016 atom / cm 2 The resistivity per unit area of ​​the polysilicon gate can be further adjusted by regulating the doping concentration; the higher the doping concentration, the lower the resistivity per unit area of ​​the polysilicon gate. When the photoresist does not cover the gate region of the N-type transistor, i.e., the N-type polysilicon layer (N-POLY) is open, P / As atoms will precipitate during subsequent photoresist washing, leading to the polysilicon gate depletion effect (when the doping concentration of polysilicon is limited, there is a voltage drop across it, resulting in an electric field inside the polysilicon gate. This makes electrons / holes near the insulating oxide interface easily attracted to the polysilicon gate side, causing a depletion layer near the insulating oxide interface and increasing the equivalent insulating layer thickness (EOT) of the semiconductor device).

[0067] In another embodiment of this disclosure, a P-type polysilicon layer is formed by ion implantation of the polysilicon layer 30 according to a first ion implantation window, serving as the gate of a P-type transistor. The dopant particles used for ion implantation of the polysilicon layer 30 are, for example, boron (B), and the doping concentration can be 10¹³ atoms / cm².2 -1016 atom / cm 2 The resistivity per unit area of ​​the polysilicon gate can be further adjusted by regulating the doping concentration; the higher the doping concentration, the lower the resistivity per unit area of ​​the polysilicon gate. When the photoresist does not cover the gate region of the P-type transistor, i.e., the P-type polysilicon layer (P-POLY) is open, boron atoms will precipitate during subsequent photoresist washing, leading to the polysilicon gate depletion effect.

[0068] Specifically, after the first ion implantation process, such as Figure 6 As shown, the manufacturing method further includes step S400: removing the first mask layer using a first solvent to form a semiconductor structure.

[0069] After the first ion implantation process is completed on the polysilicon layer 30, the photoresist (first mask layer 40) on the initial semiconductor structure is cleaned with a first solvent to form the semiconductor structure. The first solvent (APM solvent) is a mixed aqueous solution of ammonia (NH4OH) and hydrogen peroxide (H2O2).

[0070] The concentrations of ammonia are in the first range, hydrogen peroxide in the second range, and water in the third range, with the third range being greater than the second range, and the second range being greater than the first range. By improving the ratio of the above solutions, the deposition of implanted ions in polysilicon can be reduced, the polysilicon gate depletion effect can be reduced, the equivalent oxide layer thickness can be reduced, and the ion deposition loss of polysilicon can also reduce the resistance of polysilicon. By shortening the process time and improving the ratio of the above solutions, the thickness loss of the polysilicon layer can be reduced by about 1.5 nm compared to the conventional process, that is, the thickness of the polysilicon layer is increased by 1.5 nm compared to the conventional process. Since the thickness of the polysilicon layer is inversely proportional to the sheet resistance (ρ (resistivity) = R*a (width)*t (thickness) / b (length)), the performance of the device is thus optimized.

[0071] In the first solvent, the ratio of the concentration of water to the sum of the concentrations of ammonia and hydrogen peroxide is greater than 5. Preferably, the molar ratio of ammonia (NH4OH), hydrogen peroxide (H2O2) to water (H2O) is 1:1 to 10:50 to 100, such as 1:1:50, 1:5:70, 1:10:100, etc., which will not be listed here in this disclosure.

[0072] Specifically, removing the first mask layer using the first solvent includes: simultaneously removing the first mask layer using the first solvent and the second solvent. The second solvent (SPM solvent) is a mixed aqueous solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), which can be used to simultaneously clean the photoresist (first mask layer) on the initial semiconductor structure by mixing the first solvent and the second solvent.

[0073] In one embodiment of this disclosure, cleaning the photoresist on an initial semiconductor structure with a first solvent (and a second solvent) includes: feeding the initial semiconductor structure into a spin coating apparatus and having a vacuum chuck adsorb the back side of the initial semiconductor structure away from the photoresist; spraying the first solvent (and the second solvent) onto the photoresist; rotating the initial semiconductor structure so that the first solvent covers the surface of the photoresist and is then ejected; stopping the rotation of the initial semiconductor structure and removing it from the spin coating apparatus.

[0074] In another embodiment of this disclosure, cleaning the photoresist on the initial semiconductor structure with a first solvent (and a second solvent) includes: spraying the first solvent (and a second solvent) onto the photoresist surface; and cleaning the photoresist using ultrasonic cleaning.

[0075] In another embodiment of this disclosure, the photoresist on the initial semiconductor structure is cleaned with a first solvent (and a second solvent). The manufacturing method further includes: removing part of the photoresist by plasma ashing and / or wet cleaning, and then cleaning the remaining photoresist with the first solvent and the second solvent.

[0076] The photoresist is cleaned using a first solvent (and a second solvent), and the cleaning process is repeated multiple times to improve the cleaning effect.

[0077] The time for cleaning the photoresist with the first solvent (and the second solvent) is 30s to 150s, for example, 30s, 50s, 70s, 100s, 130s, 150s, etc., which are not listed here. Of course, the cleaning time for the photoresist can also be less than 30s or greater than 150s, and this disclosure does not limit it. By controlling the cleaning time and reducing the reaction time between polysilicon and the first solvent (second solvent), the reaction of doped ions, B ions and / or AS / P ions in polysilicon with the first solvent (second solvent) can be reduced, thereby reducing the formation of the polysilicon gate depletion effect, reducing the EOT of the device with this semiconductor structure and thus improving the ION.

[0078] The photoresist is cleaned using a first solvent (and a second solvent) at a temperature of 25°C to 30°C, such as 25°C, 26°C, 27°C, 28°C, 29°C, and 30°C, which will not be listed here. Of course, the temperature for cleaning the photoresist can also be less than 25°C or greater than 30°C, and this disclosure does not impose any restrictions on this.

[0079] Lowering the temperature of the photoresist cleaning process reduces the reaction of implanted ions in the polysilicon layer, thereby reducing the formation of depletion regions. This results in a decrease in EOT (excess ion charge) and an improvement in ION (intensity interference) in devices with this semiconductor structure. Given the sensitivity of EOT to VT / IDS / IOFF, and considering that EOT is highly sensitive to current while VT and IOFF are very weak, reducing even minute amounts of B or P deposition will only improve ION, offering more precise control compared to improvements achieved through ion implantation.

[0080] This disclosure improves ION performance by controlling the cleaning method after gate work function adjustment. Firstly, it primarily reduces the electrical thickness of the oxide layer by decreasing the deposition of P and B in the polysilicon layer, thereby improving ION without affecting VT and IOFF; such as Figure 8 As shown, the horizontal axis "Initial" represents an unoptimized wafer, and "Optimized" represents an optimized wafer manufactured using the method disclosed herein; the vertical axis represents the EOT value of NMOS, in units of... It can be seen that the EOT of NMOS before optimization is The optimized NMOS EOT is The optimized wafer has a significantly reduced EOT.

[0081] Secondly, this disclosure reduces poly loss by adjusting and decreasing the concentration of the clean liquid, and reduces the diffusion and precipitation of P or B in the poly by lowering the reaction temperature of the clean, achieving the following technical effects: Figure 1 As shown in point 3, while significantly increasing the on-state current ION, it avoids excessively increasing the off-state current IOFF; for example... Figure 2 As shown in point 3, the drain-source current IDS is significantly increased while ensuring that the threshold voltage VT does not decrease or remains essentially unchanged; Figure 3 As shown in point 3, while ensuring that the threshold voltage VT is reduced or not reduced at all, the off-state current IOFF is avoided from being pulled up; as Figure 9 As shown, the horizontal axis "Initial" represents the unoptimized wafer, and "Optimized" represents the optimized wafer using the manufacturing method of this application; the vertical axis, from top to bottom, represents VT / IDS / IOFF. It can be seen that the VT of the NMOS does not change significantly before and after optimization, while IDS increases relatively after optimization using the manufacturing method of this application, and IOFF decreases relatively after optimization. This achieves the goal of increasing ION independently while avoiding VT / IOFF spikes, thus improving the device's on / off ratio.

[0082] Specifically, after cleaning the photoresist with the first solvent and before forming the semiconductor structure, such as Figure 7As shown, the manufacturing method further includes step S500: forming a second mask layer on the initial semiconductor structure, the second mask layer having a second ion implantation window, the second ion implantation window defining the gate position of the second transistor; performing a second ion implantation process, adjusting the work function of the gate of the second transistor through the second ion implantation window.

[0083] After removing the first mask layer, a second mask material layer is deposited on the initial semiconductor structure. The second mask material layer is, for example, a photoresist material. Then, a patterned photoresist layer is formed by exposure and development to form a second mask layer with a second ion implantation window. Ion implantation is performed on the exposed area of ​​the polysilicon layer according to the second ion implantation window to form, for example, a P-type polysilicon layer as the gate of a P-type transistor.

[0084] Specifically, after the second ion implantation process and before the formation of the semiconductor structure, such as Figure 7 As shown, the manufacturing method further includes step S600, removing the second mask layer using a first solvent.

[0085] The photoresist covering the second region is removed by cleaning with a first solvent to form a semiconductor structure. The specific process steps for cleaning the second mask layer are the same as those for cleaning the first mask layer, and the beneficial effects are the same as those for cleaning the first mask layer, so they will not be repeated here.

[0086] In one embodiment of this disclosure, the dopant ion implanted into the polysilicon layer in the second ion implantation is, for example, boron (B), with a doping concentration of 10¹³ atoms / cm². 2 -1016 atom / cm 2 The resistivity per unit area of ​​the polysilicon gate can be further adjusted by regulating the doping concentration; the higher the doping concentration, the lower the resistivity per unit area of ​​the polysilicon gate.

[0087] In another embodiment of this disclosure, the dopant ions implanted in the second ion implantation of the polysilicon layer are, for example, at least one of phosphorus (P) or arsenic (As), and the doping concentration may be 10¹³ atoms / cm². 2 -1016 atom / cm 2 The resistivity per unit area of ​​the polysilicon gate can be further adjusted by regulating the doping concentration; the higher the doping concentration, the lower the resistivity per unit area of ​​the polysilicon gate.

[0088] In this process, the implanted ion type in the first ion implantation process is opposite to that in the second ion implantation process, and the first transistor is of the opposite type to the second transistor.

[0089] Embodiments of this disclosure also provide a semiconductor structure, including a substrate and a polysilicon layer, wherein the polysilicon layer is processed by the manufacturing method described above to obtain the semiconductor structure.

[0090] The semiconductor structure further includes an insulating oxide layer located between the substrate and the polysilicon layer. The insulating oxide layer provides electrical insulation between the polysilicon layer and the substrate. The insulating oxide layer may be made of high-dielectric-constant materials such as silicon oxide, silicon oxynitride, silicon nitride, or hafnium oxide, or other suitable insulating materials, or combinations thereof. The insulating oxide layer may be formed using methods such as physical vapor deposition, chemical vapor deposition, spin coating, or combinations thereof.

[0091] The semiconductor structure with a polysilicon gate provided in this disclosure can be applied to, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), or junction field-effect transistors (JFETs). The transistors including the semiconductor structure of this disclosure can be applied in semiconductor memories, such as computing memories (e.g., DRAM, SRAM, DDR3 SDRAM, DDR2 SDRAM, DDRSDRAM, etc.), consumer memories (e.g., DDR3 SDRAM, DDR2 SDRAM, DDRSDRAM, SDR SDRAM, etc.), graphics memories (e.g., DDR3 SDRAM, GDDR3 SDRAM, GDDR4 SDRAM, GDDR5 SDRAM, etc.), mobile memories, etc. Its beneficial effects are described above with reference to the semiconductor structure description and will not be repeated here.

[0092] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0093] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: An initial semiconductor structure is provided, the initial semiconductor structure comprising a substrate and a polycrystalline silicon layer; A first mask layer is formed on the initial semiconductor structure, the first mask layer having a first ion implantation window, the first ion implantation window defining the gate location of the first transistor; A first ion implantation process is performed, in which the work function of the gate of the first transistor is adjusted through the first ion implantation window to form a semiconductor structure; After performing the first ion implantation process, the manufacturing method further includes: The first mask layer is removed using a first solvent to form the semiconductor structure, wherein the first solvent is a mixed aqueous solution of ammonia and hydrogen peroxide; in the first solvent, the concentration of ammonia is in a first range, the concentration of hydrogen peroxide is in a second range, and the concentration of water is in a third range, wherein the third range is greater than the second range, and the second range is greater than the first range.

2. The manufacturing method according to claim 1, characterized in that, The semiconductor structure also has an insulating oxide layer formed between the substrate and the polysilicon layer.

3. The manufacturing method according to claim 1, characterized in that, In the first solvent, the ratio of the concentration of water to the sum of the concentrations of ammonia and hydrogen peroxide is greater than 5.

4. The manufacturing method according to claim 1, characterized in that, The step of removing the first mask layer using the first solvent includes: The first mask layer is removed simultaneously using a first solvent and a second solvent, wherein the second solvent is a mixed aqueous solution of sulfuric acid and hydrogen peroxide.

5. The manufacturing method according to claim 1, characterized in that, The first mask layer is cleaned multiple times with the first solvent.

6. The manufacturing method according to claim 1, characterized in that, The temperature during the cleaning of the first mask layer with the first solvent is 25℃~30℃.

7. The manufacturing method according to claim 1, characterized in that, The time for cleaning the first mask layer with the first solvent is 30s to 150s.

8. The manufacturing method according to claim 1, characterized in that, After removing the first mask layer with the first solvent and before forming the semiconductor structure, the manufacturing method further includes: A second mask layer is formed on the initial semiconductor structure, the second mask layer having a second ion implantation window, the second ion implantation window defining the gate location of the second transistor; A second ion implantation process is performed, and the work function of the gate of the second transistor is adjusted through the second ion implantation window; After the second ion implantation process, the second mask layer is removed using the first solvent.

9. The manufacturing method according to claim 8, characterized in that, The first transistor is of the opposite type to the second transistor, corresponding to the implanted ion type in the first ion implantation process being opposite to the implanted ion type in the second ion implantation process.

10. The manufacturing method according to claim 9, characterized in that, The first transistor is a P-type transistor, the second transistor is an N-type transistor, the first ion implanted includes B ions, and the second ion implanted includes As / P ions.

11. The manufacturing method according to claim 9, characterized in that, The first transistor is an N-type transistor, the second transistor is a P-type transistor, the first ion implanted ions include As / P ions, and the second ion implanted ions include B ions.

12. A semiconductor structure, characterized in that, The semiconductor structure comprises a substrate and a polysilicon layer, wherein the polysilicon layer is processed by the manufacturing method according to any one of claims 1-11 to obtain the semiconductor structure.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes: An insulating oxide layer is located between the substrate and the polycrystalline silicon layer.

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