Semiconductor structure and method of forming the same, method of manufacturing dynamic random access memory

Abstract

The application provides a semiconductor structure and a forming method thereof, and a manufacturing method of a dynamic random memory. The forming method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprises a center region and a boundary region, the boundary region is located at the periphery of the center region and is adjacent to the center region, the upper surface of the substrate has a first dielectric layer, the first dielectric layer has a plurality of holes, the bottom of the holes exposes the substrate, and the holes are filled with a second dielectric layer; etching part of the second dielectric layer to form a groove between the first dielectric layer; forming a barrier layer on the groove of the boundary region; and removing the remaining second dielectric layer of the center region by wet etching. The above technical scheme forms a stepped interface on the upper surfaces of the first dielectric layer and the second dielectric layer, avoids the corrosion liquid from penetrating into the boundary region to cause damage to the semiconductor structure when wet etching is subsequently performed, and improves the yield of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to semiconductor structures and methods for forming them, and methods for manufacturing dynamic random access memory. Background Technology

[0002] Dynamic random access memory (DRAM) includes an array of memory regions for storing data and a peripheral circuit region. The array of memory regions is composed of memory cells, each of which includes a metal-oxide-semiconductor transistor (MOSFET) and a capacitor structure. As chip integration becomes increasingly sophisticated, the density requirements for circuit patterns also increase, leading to a continuous shrinking of the device's critical dimensions.

[0003] However, due to the poor adhesion between the photoresist and the semiconductor material interface, when wet etching semiconductor materials is used, the etching solution will penetrate into the adjacent area along the boundary of the photoresist, making the boundary area of ​​the metal oxide semiconductor transistor and capacitor structure in the memory cell unstable, resulting in a short circuit between the active area and the capacitor structure, which further affects the yield of dynamic random access memory.

[0004] Therefore, preventing the etching solution from penetrating into adjacent areas along the boundaries of the photoresist is a technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide a semiconductor structure and a method for forming the same, and a method for manufacturing dynamic random access memory, so as to avoid the impact on the yield of dynamic random access memory when using wet etching of semiconductor materials because the etching solution penetrates into the adjacent area along the boundary of the photoresist.

[0006] To address the aforementioned problems, this disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region, the upper surface of the substrate having a first dielectric layer, the first dielectric layer having a plurality of holes, the bottom of the holes exposing the substrate, the holes being filled with a second dielectric layer; etching a portion of the second dielectric layer to form a groove between the first dielectric layers; forming a barrier layer on the groove in the boundary region; and removing the remaining second dielectric layer in the central region by wet etching.

[0007] In some embodiments, forming a barrier layer on the groove in the boundary region includes: covering the substrate with a barrier layer; and removing the barrier layer in the central region.

[0008] In some embodiments, after removing the remaining second dielectric layer in the central region, the method further includes: removing the barrier layer in the boundary region; and depositing a protective layer in the boundary region.

[0009] In some embodiments, the first dielectric layer is a silicon nitride layer.

[0010] In some embodiments, the second dielectric layer is a silicon oxide layer.

[0011] In some embodiments, the barrier layer is a photoresist layer.

[0012] In some embodiments, the protective layer is a silicon nitride layer.

[0013] In some embodiments, the height of the groove is 5 to 50 nanometers.

[0014] This disclosure also provides a method for manufacturing a dynamic random access memory (DRAM), comprising: forming a memory cell region and a logic circuit region; the forming of the memory cell region comprising: providing a substrate, the substrate comprising a central region and a boundary region, the boundary region being located outside and adjacent to the central region; forming an array of memory node contact structures on the upper surface of the substrate, the memory node contact structures comprising an effective contact hole located in the central region and a dummy contact hole located in the boundary region; forming a contact layer located within the effective contact hole and a second dielectric layer located within the dummy contact hole.

[0015] In some embodiments, the step of forming an array of storage node contact holes on the upper surface of the substrate includes: forming a first dielectric layer on the substrate; forming a plurality of holes in the first dielectric layer, wherein the bottom of the holes exposes the substrate.

[0016] In some embodiments, the step of forming a contact layer within the effective contact hole and a dielectric layer within the dummy contact hole includes: filling a second dielectric layer in the storage node contact structure; etching a portion of the second dielectric layer to form a groove between the first dielectric layers; forming a barrier layer within the dummy contact hole, the barrier layer being located on the second dielectric layer; and etching the remaining second dielectric layer within the effective contact hole to form the contact layer.

[0017] In some embodiments, the method of manufacturing the dynamic random access memory further includes depositing a protective layer on a second dielectric layer in the boundary region.

[0018] This disclosure also provides a semiconductor structure, comprising: a substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region, and an array of memory node contact structures on the upper surface of the substrate; the memory node contact structures including an effective contact hole located in the central region and a dummy contact hole located in the boundary region; a contact layer located within the effective contact hole; and a second dielectric layer and a protective layer located within the dummy contact hole.

[0019] In some embodiments, the protective layer is located above the second dielectric layer and does not extend beyond the top surface of the dummy contact hole.

[0020] In some embodiments, the thickness of the protective layer is 1 to 4 nanometers.

[0021] The above technical solution forms a groove between the first dielectric layer by etching the second dielectric layer, so that there is a height difference between the first dielectric layer and the second dielectric layer and a stepped interface is formed on the upper surface of the first dielectric layer and the second dielectric layer. This avoids the corrosion solution from penetrating into the boundary area and causing damage to the semiconductor structure when wet etching is used in subsequent processes, thereby improving the yield of the semiconductor structure.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the specific embodiments of this disclosure, the drawings used in the specific embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0025] Figure 2 This is a schematic diagram of a substrate according to an embodiment of the present disclosure.

[0026] Figure 3 This is a schematic diagram of a groove formed in one embodiment of the present disclosure.

[0027] Figure 4 This is a schematic diagram of the formation of a barrier layer in one embodiment of the present disclosure.

[0028] Figure 5 This is a schematic diagram of a barrier layer in one embodiment of the present disclosure.

[0029] Figure 6 This is a schematic diagram of removing the blocking layer in the central region according to an embodiment of the present disclosure.

[0030] Figure 7 This is a schematic diagram of the remaining second dielectric layer after removing the central region in one embodiment of the present disclosure.

[0031] Figure 8 This is a schematic diagram of removing the barrier layer in the boundary region according to an embodiment of the present disclosure.

[0032] Figure 9 This is a schematic diagram of a protective layer deposited in the boundary region according to an embodiment of the present disclosure.

[0033] Figure 10 This is a schematic diagram of a storage cell area formed in one embodiment of the present disclosure.

[0034] Figure 11 This is a schematic diagram of the storage node contact structure in one embodiment of the present disclosure.

[0035] Figure 12 This is a schematic diagram of the contact structure of the storage nodes arranged in an array according to one embodiment of the present disclosure.

[0036] Figure 13 This is a schematic diagram of a contact layer located within the effective contact hole and a second dielectric layer located within the dummy contact hole in one embodiment of the present disclosure.

[0037] Figure 14 This is a schematic diagram of filling a second dielectric layer in the storage node contact structure according to an embodiment of the present disclosure.

[0038] Figure 15 This is a schematic diagram of a groove formed in one embodiment of the present disclosure.

[0039] Figure 16 This is a schematic diagram of the formation of a barrier layer in one embodiment of the present disclosure.

[0040] Figure 17 This is a schematic diagram of the formation of a contact layer in one embodiment of the present disclosure.

[0041] Figure 18 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure. Detailed Implementation

[0042] The technical solutions of the specific embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described specific embodiments are only a part of the specific embodiments of this disclosure, and not all of them. Based on the specific embodiments in this disclosure, all other specific embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] To address the problem in existing technologies where wet etching of semiconductor materials affects the yield of dynamic random access memory (DRAM) due to the etchant penetrating into adjacent areas along the boundaries of the photoresist, this disclosure provides a semiconductor structure and its formation method, as well as a method for manufacturing DRAM.

[0044] The method for forming a semiconductor structure provided in the specific embodiments of this disclosure will be described below. Figure 1 This is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of this disclosure. Please refer to the following. Figure 1 The method for forming the semiconductor structure includes: step S101, providing a substrate, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region, the upper surface of the substrate having a first dielectric layer, the first dielectric layer having a plurality of holes, the bottom of the holes exposing the substrate, and the holes being filled with a second dielectric layer; step S102, etching a portion of the second dielectric layer to form a groove between the first dielectric layers; step S103, forming a barrier layer on the groove in the boundary region; step S104, removing the remaining second dielectric layer in the central region by wet etching.

[0045] Please continue reading below. Figure 1 Step S101: Provide a substrate, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region, the upper surface of the substrate having a first dielectric layer, the first dielectric layer having a plurality of holes, the bottom of the holes exposing the substrate, the holes being filled with a second dielectric layer.

[0046] Figure 2 This is a schematic diagram of a substrate according to an embodiment of this disclosure. Please refer to the following. Figure 2 A substrate 1 is provided, the substrate 1 including a central region A1 and a boundary region A2, the boundary region A2 being located around and adjacent to the central region A1. In some embodiments, a first dielectric layer 21 is deposited on the upper surface of the substrate 1 using a self-aligned dual-patterning lithography technique, a portion of the first dielectric layer 21 is etched to form a plurality of holes 3, the bottom of the holes 3 exposing the substrate 1, and a second dielectric layer 22 is filled in the holes. In this embodiment, the substrate is silicon, the first dielectric layer 21 is a silicon nitride layer, and the second dielectric layer 22 is an oxide layer. In other embodiments, the substrate material may be single-crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other III-V group compounds.

[0047] Please continue reading below. Figure 1 In step S102, a portion of the second dielectric layer is etched to form a groove between the first dielectric layers. Figure 3 This is a schematic diagram of a groove formed in one embodiment of the present disclosure. Please refer to the following: Figure 3A portion of the second dielectric layer 22 is etched away using dry etching or wet etching to form a groove 4 between the first dielectric layers 21, so that the first dielectric layer 21 and the second dielectric layer 22 have a certain height difference. For example, the second dielectric layer 22 is etched towards the substrate direction by 5 to 50 nm to form an interface where the first dielectric layer 21 is higher than the second dielectric layer 22, and the height of the groove 4 is 5 to 50 nm.

[0048] Please continue reading below. Figure 1 Step S103: A barrier layer is formed on the groove in the boundary region. Figure 4 This is a schematic diagram of the formation of a barrier layer in one embodiment of this disclosure. Please refer to the following. Figure 4 The process of forming a barrier layer on the groove in the boundary region includes: step S401, covering the substrate with a barrier layer; and step S402, removing the barrier layer in the central region. Figure 5 This is a schematic diagram of a barrier layer in one embodiment of this disclosure. Please refer to the following: Figure 5 In this embodiment, a spin-coating method is used to allow the photoresist to enter the groove 4 and form the barrier layer 5. Figure 6 This is a schematic diagram of removing the blocking layer in the central region according to an embodiment of this disclosure. Please refer to the following: Figure 6 In this embodiment, the barrier layer 5 in the central region A1 is removed by developing. Since the groove 4 is formed in step S102, after the barrier layer 5 is covered on the substrate, a stepped interface 6 is formed between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22.

[0049] Please continue reading below. Figure 1 Step S104: Remove the remaining second dielectric layer in the central region by wet etching. Figure 7 This is a schematic diagram of the remaining second dielectric layer after removing the central region in one embodiment of this disclosure. Please refer to the following: Figure 7 The remaining second dielectric layer 22 of the central region A1 is removed by wet etching. At this time, the remaining barrier layer 5 completely covers the top surface of the boundary region A2. Since the barrier layer 5 forms a stepped interface 6 with the first dielectric layer 21 and the second dielectric layer 22, compared with a vertical interface, the etching solution is less likely to penetrate into the boundary region A2 through the stepped interface 6 during the process of removing the remaining second dielectric layer 22 of the central region A1 by wet etching, thus avoiding damage to the boundary region A2.

[0050] Please continue reading below. Figure 1In some other embodiments, the method for forming the semiconductor structure further includes, after step S104, removing the remaining second dielectric layer in the central region: step S105, removing the barrier layer in the boundary region; and step S106, depositing a protective layer in the boundary region. Figure 8 This is a schematic diagram of removing the barrier layer in the boundary region according to an embodiment of this disclosure. Please refer to the following: Figure 8 Remove the barrier layer 6 of the boundary region A2 to expose the second dielectric layer 22 of the boundary region A2. Figure 9 This is a schematic diagram of a protective layer deposited in the boundary region according to an embodiment of this disclosure. Please refer to the following: Figure 9 In this embodiment, silicon nitride is deposited on the upper surface of the second dielectric layer 22 in the boundary region A2 by atomic deposition technology to form the protective layer 7. In some embodiments, the thickness of the protective layer 7 is 1 to 4 nm to avoid damage to the second dielectric layer 22 in the boundary region A2 during subsequent wet cleaning, thereby affecting the conductivity and stability of the semiconductor structure.

[0051] The above technical solution forms a groove 4 between the first dielectric layer 21 by etching the second dielectric layer 22, so that there is a height difference between the first dielectric layer 21 and the second dielectric layer 22. After covering the substrate with a barrier layer 5, a stepped interface 6 is formed between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22. This makes it difficult for the etching solution to penetrate into the boundary region A2 through the stepped interface 6 during the process of removing the remaining second dielectric layer 22 in the central region A1 by wet etching, thus avoiding damage to the boundary region A2 and improving the yield of the semiconductor structure during the manufacturing process.

[0052] The manufacturing method of the dynamic random access memory (DRAM) provided in this disclosure is described below. The manufacturing method of the DRAM includes: forming a memory cell area and a logic circuit area. Figure 10 This is a schematic diagram of a storage cell area formed in one embodiment of this disclosure. Please refer to the following: Figure 10 The formation of the memory cell region includes: step S111, providing a substrate, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region; step S112, forming an array of memory node contact structures on the upper surface of the substrate, the memory node contact structures including effective contact holes located in the central region and dummy contact holes located in the boundary region; step S113, forming a contact layer located in the effective contact holes and a second dielectric layer located in the dummy contact holes.

[0053] Figure 2 This is a schematic diagram of a substrate according to an embodiment of this disclosure. Please refer to the following. Figure 2A substrate 1 is provided, the substrate 1 includes a central region A1 and a boundary region A2, the boundary region A2 is located outside the central region A1 and adjacent to the central region A1.

[0054] Please continue reading below. Figure 10 In step S112, an array of storage node contact structures is formed on the upper surface of the substrate. The storage node contact structures include effective contact holes located in the central region and dummy contact holes located in the boundary region. Figure 11 This is a schematic diagram of the storage node contact structure in one embodiment of this disclosure. Please refer to the following: Figure 11 A silicon oxide layer 12, a silicon nitride layer 13, and a silicon oxide layer 14 are sequentially deposited on a single-crystal silicon layer 11. A metal layer 15 is embedded in the silicon oxide layer 14. An array of initial memory node contact structures 16 is formed on the metal layer 15. An initial contact layer 17, which is a silicon nitride layer, is then covered on the initial memory node contact structures 16 and the silicon oxide layer 14. The substrate 1 includes: a single-crystal silicon layer 11, a silicon oxide layer 12, a silicon nitride layer 13, a silicon oxide layer 14, a metal layer 15, an initial memory node contact structure 16, and an initial contact layer 17. Figure 12 This is a schematic diagram of the contact structure of the storage nodes arranged in an array according to one embodiment of this disclosure. Please refer to the following: Figure 11 The step of forming an array of memory node contact holes on the upper surface of the substrate includes: step S121, forming a first dielectric layer on the substrate; step S122, forming a plurality of holes in the first dielectric layer, the bottom of the holes exposing the substrate. In this embodiment, a first dielectric layer 21 is formed on the initial contact layer 17. The first dielectric layer 21 is a silicon nitride layer. A portion of the silicon nitride layer is etched so that the remaining silicon nitride layer overlaps with the initial memory node contact structure 16, and a plurality of holes 3 (illustrated in the figure) are formed in the first dielectric layer 21. Figure 2 The bottom of the hole 3 exposes the initial contact layer 17 of the substrate 1. Through the above steps, an effective contact hole 81 located in the central region A1 and a dummy contact hole 82 located in the boundary region A2 are formed.

[0055] Please continue reading below. Figure 10 Step S113: A contact layer located in the effective contact hole and a second dielectric layer located in the dummy contact hole are formed. Figure 13 This is a schematic diagram of a contact layer located within the effective contact hole and a second dielectric layer located within the dummy contact hole, according to an embodiment of this disclosure. Please refer to the following: Figure 13The steps of forming a contact layer located within the effective contact hole and a dielectric layer located within the dummy contact hole include: step S131, filling a second dielectric layer in the storage node contact structure; step S132, etching a portion of the second dielectric layer to form a groove between the first dielectric layers; step S133, forming a barrier layer within the dummy contact hole, the barrier layer being located on the second dielectric layer; and step S134, etching the remaining second dielectric layer within the effective contact hole to form the contact layer.

[0056] Figure 14 This is a schematic diagram of filling a second dielectric layer in the storage node contact structure according to an embodiment of this disclosure. Please refer to the following: Figure 14 A second dielectric layer 22, which is an oxide layer, is filled into the hole 3 of the storage node contact structure. Figure 15 This is a schematic diagram of a groove formed in one embodiment of the present disclosure. Please refer to the following: Figure 15 The oxide layer is etched to form a groove 4 between the first dielectric layers, so that the upper surface of the first dielectric layer 21 is higher than the upper surface of the second dielectric layer 22. Figure 16 This is a schematic diagram of the formation of a barrier layer in one embodiment of this disclosure. Please refer to the following: Figure 16 Photoresist is spin-coated onto the first dielectric layer 21 and the second dielectric layer 22, allowing the photoresist to enter the groove 4. Then, the photoresist in the effective contact hole 81 is removed, leaving the remaining photoresist to form a barrier layer 5 in the dummy contact hole 82. At this time, the contact surface between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22 is a stepped interface. Figure 17 This is a schematic diagram of the formation of a contact layer in one embodiment of this disclosure. Please refer to the following: Figure 17 The remaining second dielectric layer 22 within the effective contact hole is etched to form a contact layer 9 located within the effective contact hole 81. Since the remaining barrier layer 5 completely covers the top surface of the boundary region A2, and since a stepped interface 6 is formed between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22, compared to a vertical interface, the etching solution is less likely to penetrate into the boundary region A2 through the stepped interface 6 during the wet etching process to remove the remaining second dielectric layer 22 of the central region A1, thus avoiding damage to the boundary region A2.

[0057] Please continue reading below. Figure 10 In some embodiments, the method of manufacturing the dynamic random access memory further includes depositing a protective layer on the second dielectric layer in the boundary region. In some embodiments, the barrier layer 5 within the dummy contact hole 82 is removed, and a silicon nitride layer is deposited as a protective layer 7 on the second dielectric layer 22 within the dummy contact hole 82 (illustrated in...). Figure 18The thickness of the protective layer 7 is set according to the height of the groove 4. For example, when the depth of the groove 4 formed in step S132 is 5 to 50 nanometers, the thickness of the protective layer 7 can be 1 to 4 nanometers so that the protective layer 7 does not exceed the height of the dummy contact hole 82.

[0058] The above technical solution forms a groove 4 between the first dielectric layers 21 by etching the second dielectric layer 22, creating a height difference between the first dielectric layer 21 and the second dielectric layer 22. After covering the substrate with a barrier layer 5, a stepped interface 6 is formed between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22. This prevents the etching solution from easily penetrating into the dummy contact hole 82 through the stepped interface 6 during the wet etching process to remove the remaining second dielectric layer 22 in the effective contact hole 81. This avoids the dummy contact hole 82 adjacent to the effective region A1 from being etched by the etching solution during the removal of the remaining second dielectric layer 22 in the effective contact hole 81 due to poor adhesion between the barrier layer 5 and the first dielectric layer 21 and the second dielectric layer 22, thereby improving the yield of the semiconductor structure during manufacturing.

[0059] Corresponding to the specific implementation of the above method, this disclosure also provides a semiconductor structure. Figure 18 This is a schematic diagram of a semiconductor structure according to an embodiment of this disclosure. Please refer to the following: Figure 18 The semiconductor structure includes: a substrate 1, which includes a central region A1 and a boundary region A2, wherein the boundary region A2 is located outside and adjacent to the central region A1, and the upper surface of the substrate 1 has an array of memory node contact structures; the memory node contact structures include an effective contact hole 81 located in the central region and a dummy contact hole 82 located in the boundary region; a contact layer 9 located within the effective contact hole 81; a second dielectric layer 22 and a protective layer 7 located within the dummy contact hole 82. The protective layer 7 is located above the second dielectric layer and does not exceed the top surface of the dummy contact hole 82. In this embodiment, the thickness of the protective layer 7 is 1–4 nanometers; in other embodiments, the thickness of the protective layer 7 can be set according to the height of the groove in the above method.

[0060] In this embodiment, the substrate 1 includes: a single-crystal silicon layer 11, a silicon oxide layer 12, a silicon nitride layer 13, a silicon oxide layer 14, a metal layer 15, an initial memory node contact structure 16, and an initial contact layer 17.

[0061] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region, the upper surface of the substrate having a first dielectric layer having a plurality of holes, the bottom of the holes exposing the substrate, and the holes being filled with a second dielectric layer; Etch portions of the second dielectric layer to form grooves between the first dielectric layers; A barrier layer is formed on the groove in the boundary region, wherein a stepped interface is formed between the barrier layer and the first dielectric layer and the second dielectric layer; The remaining second dielectric layer in the central region is removed by wet etching. The method further includes, after removing the remaining second dielectric layer in the central region: Remove the blocking layer in the boundary region; A protective layer is deposited in the boundary region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The formation of the barrier layer on the groove in the boundary region includes: A barrier layer is covered on the substrate; Remove the blocking layer in the central region.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The first dielectric layer is a silicon nitride layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The second dielectric layer is a silicon oxide layer.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The barrier layer is a photoresist layer.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The protective layer is a silicon nitride layer.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The height of the groove is 5-50 nanometers.

8. A method for manufacturing a dynamic random access memory, characterized in that, include: This forms a memory cell area and a logic circuit area; The forming of the storage cell area includes: A substrate is provided, the substrate including a central region and a boundary region, the boundary region being located outside and adjacent to the central region; An array of memory node contact structures is formed on the upper surface of the substrate. The memory node contact structures include effective contact holes located in the central region and dummy contact holes located in the boundary regions. A contact layer is formed within the effective contact hole, and a second dielectric layer is formed within the dummy contact hole. The step of forming an array of storage node contact holes on the upper surface of the substrate includes: A first dielectric layer is formed on the substrate; A plurality of holes are formed in the first dielectric layer, the bottom of the holes exposing the substrate; A second dielectric layer is filled into the storage node contact structure; Etch portions of the second dielectric layer to form grooves between the first dielectric layers; A barrier layer is formed within the dummy contact hole. The barrier layer is located on the second dielectric layer, and a stepped interface is formed between the barrier layer and the first dielectric layer and the second dielectric layer. The remaining second dielectric layer within the effective contact hole is etched to form the contact layer; Remove the blocking layer in the boundary region; A protective layer is deposited in the boundary region.

9. The method for manufacturing a dynamic random access memory according to claim 8, characterized in that, Also includes: A protective layer is deposited on the second medium layer in the boundary region.

10. A semiconductor structure, characterized in that, include: The substrate includes a central region and a boundary region, the boundary region being located outside and adjacent to the central region, and the upper surface of the substrate having an array of storage node contact structures. The storage node contact structure includes an effective contact hole located in the central region and a dummy contact hole located in the boundary region; The contact layer is located within the effective contact hole; The second dielectric layer and the protective layer are located within the dummy contact hole. The protective layer is located above the second dielectric layer and does not extend beyond the top surface of the dummy contact hole. A stepped interface is formed between the protective layer, the second dielectric layer, and the sidewall of the dummy contact hole.

11. The semiconductor structure according to claim 10, characterized in that, The thickness of the protective layer is 1-4 nanometers.

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