Package structure and packaging method for reducing transmission loss

Abstract

The present application relates to a package structure and a package method for reducing transmission loss. The package structure comprises a package substrate for interconnecting with a chip package; a first network transmission path or a second network transmission path is configured for power transmission between the chip and the package substrate, and the second network transmission path or the first network transmission path is configured for signal transmission between the chip and the package substrate; the first network transmission path and the second network transmission path are configured to be independent of each other, so that the power transmission path and the signal transmission path between the chip and the package substrate are isolated from each other; and the first network transmission path is configured between the active surface of the chip and the active surface of the package substrate, so as to shorten the transmission distance of the first network transmission path. The present application can effectively reduce the transmission loss of power transmission or signal transmission, improve the decoupling performance, and improve the power integrity.

Description

Technical Field

[0001] This invention relates to a packaging structure and packaging method, and more particularly to a packaging structure and packaging method for reducing transmission loss. Background Technology

[0002] In traditional WB (Wire Bond) packaging, the chip pads are connected to the gold fingers on the front of the substrate via gold or copper wires, passing through vias and circuits inside the substrate, and then connected to the PCB (Print Circuit Board) via solder balls on the bottom of the substrate to achieve connection with the VRM (Voltage Regulator Module).

[0003] The functional networks of a chip can generally be divided into signal networks and power networks. In the prior art, the transmission paths of signal networks and power networks are mixed together on the substrate and accompany each other. Therefore, the transmission path of the signal network will affect the transmission path of the power network, which will lead to the following shortcomings:

[0004] 1) The more signals in the signal network, the more wiring space is required. The more layers in the substrate, the thicker the substrate will become, which in turn will lead to a longer power network transmission path and an increased voltage drop during power transmission.

[0005] 2) From the perspective of signal integrity, high-speed signals require a complete reference plane as a return path, which leads to an increase in the number of substrate layers, a thicker substrate, a longer power transmission path, and an increased voltage drop.

[0006] 3) For WB packaging, the minimum arc height and shortest line length requirements of the WB line body will limit the further shortening of the power transmission path.

[0007] In summary, in packages with power networks and signal networks, effectively reducing the impact of the signal network on the power network, and reducing power transmission loss within the power network or signal transmission loss within the signal network are urgent technical challenges that need to be addressed. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a packaging structure and packaging method that reduces transmission loss. This reduces the impact of the signal network on the power network, shortens the power or signal transmission path, and effectively reduces the power or signal transmission loss.

[0009] According to the technical solution provided by the present invention, the packaging structure for reducing transmission loss includes:

[0010] A package substrate for interconnection with a chip package;

[0011] A chip package includes at least one chip with an active surface. The active surface includes a first interface and a second interface, which are independent of each other. The first interface and the second interface of the active surface are respectively connected to the active surface of the package substrate via a first network transmission path and a second network transmission path.

[0012] The first network transmission path is configured for power transmission between the chip and the package substrate, and the second network transmission path is configured for signal transmission between the chip and the package substrate; or, the second network transmission path is configured for power transmission between the chip and the package substrate, and the first network transmission path is configured for signal transmission between the chip and the package substrate.

[0013] The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and signal transmission path between the chip and the package substrate are isolated from each other.

[0014] The first network transmission path is located between the active surface of the chip and the active surface of the package substrate, so as to shorten the transmission distance of the first network transmission path.

[0015] The chip package further includes a package substrate adapted to the chip, wherein,

[0016] The chip is mounted on the package substrate, and the active surface of the chip is opposite to the active surface of the package substrate.

[0017] The chip is located between the active surface of the package substrate and the package base.

[0018] The second network transmission path includes a first sub-path for connecting the second interface to the package substrate and a second sub-path for connecting the second network transmission to the active surface of the package substrate via the package substrate.

[0019] The package substrate includes an internal circuit layer located within the package substrate, wherein...

[0020] The first sub-path of the second network transmission is adapted and connected to the second sub-path of the second network transmission through the circuit layer inside the substrate.

[0021] For the first network transmission path, it includes:

[0022] The first interface lead-out unit is used to lead out the first interface on the active surface of the chip toward the active surface of the packaging substrate.

[0023] An active surface contact connection unit is electrically connected to the active surface contact of the packaging substrate, so that the first interface is adapted to be connected to the active surface of the packaging substrate via the first interface lead-out unit and the active surface contact connection unit.

[0024] For the first network transmission path, it also includes:

[0025] The first interface connection unit is used to adapt and connect the first interface lead-out unit and the active surface contact connection unit, wherein...

[0026] The first interface connection unit leads the first interface lead-out unit toward the active surface of the packaging substrate, and the first interface lead-out unit is electrically connected to the active surface contact connection unit through the first interface connection unit.

[0027] or,

[0028] The first interface connection unit leads the first interface lead-out unit toward the active surface of the package substrate, and rearranges the lead-out state of the first interface lead-out unit toward the active surface of the package substrate so that after the rearrangement, the first interface lead-out unit is electrically connected to the active surface contact connection unit via the first interface connection unit.

[0029] The first interface includes several ground pads and several functional pads for the first interface.

[0030] The first interface lead-out unit includes a first interface ground pad lead-out body for leading out the ground pads of the first interface and a first interface functional pad lead-out body for leading out the functional pads of the first interface, wherein...

[0031] Both the ground pad lead-out of the first interface and the functional pad lead-out of the first interface are embedded in the molding layer used to encapsulate the chip on the package substrate.

[0032] The first network transmission path configured for power transmission also includes decoupling capacitors, wherein,

[0033] The decoupling capacitor is located on the first interface connection unit and is connected to the first interface adapter through the first interface connection unit and the first interface lead-out unit to be configured to form a series connection between the ground pad of the first interface and the corresponding first interface functional pad.

[0034] The first interface connection unit includes an insulating dielectric layer and a plurality of interconnecting structural components distributed within the insulating dielectric layer; wherein,

[0035] The internal interconnect structure component leads the first interface lead-out unit toward the active surface of the packaging substrate;

[0036] or,

[0037] The internal structure component rearranges the first interface lead-out unit to the active surface of the packaging substrate and leads it out to the active surface of the packaging substrate.

[0038] The active surface contact connection unit includes several active surface contact connectors located on an insulating dielectric layer, wherein a corresponding internal interconnect structure component is adapted to be electrically connected to the active surface of the package substrate through an active surface contact connector.

[0039] The second network transmission second sub-path includes several second network transmission second sub-path lines formed by wire bonding process or several metal pins for connecting and supporting the package substrate;

[0040] Among them, for the second sub-path of the second network transmission based on the metal pins, the connection between the package substrate and the second sub-path of the second network transmission includes a pluggable connection.

[0041] For the second sub-path of the second network transmission formed based on the second sub-path line body of the second network transmission, a second sub-path protection body for protecting the second sub-path of the second network transmission is formed by dispensing adhesive.

[0042] A shielding layer is disposed on the substrate of the package, wherein...

[0043] The shielding layer and the chip are located on opposite sides of the package substrate;

[0044] The projection of the shielding layer toward the chip covers the area where the chip is located.

[0045] A packaging method for reducing transmission loss packaging structure, used to fabricate the packaging structure, wherein the packaging method includes:

[0046] A chip package and a package substrate are provided, and the chip package and the package substrate are aligned and interconnected.

[0047] The chip package includes at least one chip with an active surface. The active surface includes a first interface and a second interface, which are independent of each other. The first and second interfaces of the active surface are respectively connected to the active surface of the package substrate via a first network transmission path and a second network transmission path.

[0048] The first network transmission path is configured for power transmission between the chip and the package substrate, and the second network transmission path is configured for signal transmission between the chip and the package substrate; or, the second network transmission path is configured for power transmission between the chip and the package substrate, and the first network transmission path is configured for signal transmission between the chip and the package substrate.

[0049] The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and signal transmission path between the chip and the package substrate are isolated from each other.

[0050] The first network transmission path is located between the active surface of the chip and the active surface of the package substrate to shorten the transmission distance of the first network transmission path.

[0051] Advantages of this invention:

[0052] By making the first network transmission path and the second network transmission path independent of each other, and configuring the first network transmission path to be located between the active surface of the chip and the active surface of the package substrate, the influence of the signal transmission path on the power transmission path can be reduced, and the power transmission loss or signal transmission loss can be reduced. At the same time, since the first network transmission path does not pass through the package substrate, the thickness and size of the package substrate can be reduced, and the complexity of the package substrate can be reduced.

[0053] The chip is mounted on the front side of the package substrate, and a shielding layer is provided on the back side of the package substrate. The shielding layer can shield the chip from electromagnetic interference, improving the stability and reliability of the chip during operation. At the same time, the active surface of the chip is opposite to the active surface of the package substrate, which can further reduce the distance of the first network transmission path and reduce power transmission loss.

[0054] When the first interface is brought out, the first interface lead-out unit can be formed by one of the following processes: TMV process, wire bonding process or micro bump process. At this time, the first interface ground pad lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit can effectively shorten the interconnect length and further reduce power transmission loss or signal transmission loss.

[0055] After the ground pad lead-out body and the functional pad lead-out body of the first interface are led out and rearranged through the first interface connection unit, in addition to effectively providing process space for fabricating active surface contact connection units, it can also realize the placement and connection of decoupling capacitors, which can improve the decoupling effect.

[0056] When the second sub-path of the second network is formed based on the metal pins, a pluggable connection can be formed between it and the package substrate, which improves the convenience of maintenance. Since the height of the metal pins is less than the length of the bonding wire and the diameter of the metal pins is greater than the diameter of the bonding wire, it is beneficial to improve the reliability of signal transmission. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of an embodiment of an existing first network transmission path and a second network transmission path.

[0058] Figures 2-8 This diagram illustrates the specific implementation steps of the first packaging method of the present invention, wherein...

[0059] Figure 2 This is a schematic diagram of the chip being mounted on the front side of the package substrate according to the present invention.

[0060] Figure 3 This is a schematic diagram of the chip after it has been encapsulated using a molding layer according to the present invention.

[0061] Figure 4 This is a schematic diagram of the first interface lead-out unit fabricated using the TMV process of the present invention.

[0062] Figure 5 This is a schematic diagram of the first interface connection unit and the active surface after contacting the first connector, prepared according to the present invention.

[0063] Figure 6 This is a schematic diagram of the present invention after the active surface contact first connector is aligned and interconnected with the packaging substrate.

[0064] Figure 7 This is a schematic diagram of the second network transmission second sub-path obtained according to the present invention.

[0065] Figure 8 This is a schematic diagram of the second network transmission second sub-path protection body prepared according to the present invention.

[0066] Figures 9-14 This diagram illustrates the specific implementation steps of the second packaging method of the present invention, wherein...

[0067] Figure 9 This is a schematic diagram of the first interface lead-out unit fabricated using wire bonding technology and then encapsulated using a molding layer, according to the present invention.

[0068] Figure 10 This is a schematic diagram of the thinning of the molding layer according to the present invention.

[0069] Figure 11 This is a schematic diagram of the first interface connection unit and the active surface after contacting the first connector, prepared according to the present invention.

[0070] Figure 12 This is a schematic diagram of the present invention after the active surface contact first connector is aligned and interconnected with the packaging substrate.

[0071] Figure 13 This is a schematic diagram of the second network transmission second sub-path obtained according to the present invention.

[0072] Figure 14 This is a schematic diagram of the second network transmission second sub-path protection body prepared according to the present invention.

[0073] Figures 15-20 This is a diagram illustrating the specific implementation steps of the third packaging method of the present invention, wherein,

[0074] Figure 15 This is a schematic diagram of the first interface lead-out unit formed based on pre-prepared microbumps according to the present invention.

[0075] Figure 16 This is a schematic diagram of the first interface lead-out unit and the chip after being encapsulated using a molding layer according to the present invention.

[0076] Figure 17 This is a schematic diagram of the thinning of the molding layer according to the present invention.

[0077] Figure 18 This is a schematic diagram of the first interface connection unit and the active surface after contacting the first connector, prepared according to the present invention.

[0078] Figure 19 This is a schematic diagram of the present invention after the active surface contact first connector is aligned and interconnected with the packaging substrate.

[0079] Figure 20 This is a schematic diagram of the second network transmission second sub-path protection body prepared according to the present invention.

[0080] Figures 21-22 This is a diagram illustrating the specific implementation steps of the fourth packaging method of the present invention, wherein,

[0081] Figure 21 This is a schematic diagram of the fabrication of metal pins on the packaging substrate according to the present invention.

[0082] Figure 22 This is a schematic diagram of the present invention after the metal pins support the package substrate and form a second network to transmit the second sub-path.

[0083] Figure 23 This is another embodiment of the present invention in which the first network transmission path is configured between the active surface of the chip and the active surface of the package substrate.

[0084] Explanation of reference numerals in the attached diagram: 1-PCB board, 2-chip substrate, 3-chip, 4-molded package, 5-power management module, 6-decoupling capacitor, 7-chip substrate solder ball, 8-signal wire bonding wire, 9-power wire bonding wire, 10-package substrate, 11-package substrate, 12-shielding layer, 13-first line of the second sub-path of the second network transmission, 14-second line of the second sub-path of the second network transmission, 15-molded package, 16-first interface connection unit, 17-first line of the first sub-path of the second network transmission, 18-second line of the first sub-path of the second network transmission, 19-power ground Pad, 20-Power pad, 21-Power / ground pad TMV connector, 22-Power pad TMV connector, 23-Active surface contact connector, 24-Second network transmission second sub-path protection body, 25-Power / ground pad wire bonding connector, 26-Power pad wire bonding connector, 27-Power / ground pad micro-bump connector, 28-Power pad micro-bump connector, 29-First metal pin, 30-Signal interface signal pad, 31-Second metal pin, 32-Third metal pin, 33-Signal interface ground pad, 34-Signal interface connection unit. Detailed Implementation

[0085] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0086] Figure 1 An embodiment of an existing packaging structure is shown in the figure. Figure 1 In the process, chip 3 is placed on top of PCB board 1. Chip 3 is mounted on chip substrate 2. The power interface of chip 3 is adapted to chip substrate 2 through power wire bonding wire 9. The signal interface of chip 3 is adapted to chip substrate 2 through signal wire bonding wire 8. The power interface and signal interface are interconnected with PCB board 1 through chip substrate 2 and chip substrate solder balls 7.

[0087] Figure 1 In this configuration, a power management module 5 is installed on PCB board 1. The power management module 5 manages the power supply to chip 3 via PCB board 1. Figure 1 As can be seen, both the power interface and the signal interface are interconnected with the PCB board 1 through the chip substrate 2 and the chip substrate solder balls 7. At this time, the power network transmission path of the power network and the signal network transmission path of the signal network are coupled with the chip substrate 2. As can be seen from the above description, the signal network transmission path will affect the power network transmission path.

[0088] also, Figure 1 In the process, the decoupling capacitor 6 is disposed on the chip substrate 2 and is located on the same side of the chip substrate 2 as the chip 3. However, the distance between the two is too large, which cannot guarantee the integrity of the power supply when supplying power to the chip 3. Figure 1In the process, the chip 3, decoupling capacitor 6, signal wire bonding wire 8 and power wire bonding wire 9 are encapsulated on the chip substrate 2 by the encapsulation body 4. The chip 3 is on top of the PCB board 1 and is arranged in a positive orientation.

[0089] To effectively reduce power transmission or signal transmission losses, in one embodiment of the present invention, the packaging structure for reducing transmission losses includes:

[0090] The package substrate 10 is used for interconnection with a chip package;

[0091] The chip package includes at least one chip 3 with an active chip surface. The active chip surface includes a first interface and a second interface, which are independent of each other. The first interface and the second interface of the active chip surface are respectively adapted and connected to the active surface of the package substrate 10 through a first network transmission path and a second network transmission path.

[0092] The first network transmission path is configured for power transmission between chip 3 and package substrate 10, and the second network transmission path is configured for signal transmission between chip 3 and package substrate 10; or, the second network transmission path is configured for power transmission between chip 3 and package substrate 10, and the first network transmission path is configured for signal transmission between chip 3 and package substrate 10.

[0093] The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and the signal transmission path between the chip 3 and the package substrate 10 are isolated from each other.

[0094] The first network transmission path is located between the active surface of the chip and the active surface of the package substrate, so as to shorten the transmission distance of the first network transmission path.

[0095] In specific implementation, the encapsulation substrate 10 can be adopted Figure 1 The specific form of the PCB board 1 and the packaging substrate 10 can be selected as needed, specifically to provide power to the chip package and implement signal transmission management. Providing power specifically refers to providing the power required for the chip 3 to operate within the chip package. Signal transmission management can include signal conversion, filtering, amplification, and other management methods. The specific forms of providing power and signal transmission management can be selected according to the actual application scenario.

[0096] The chip package includes at least one chip 3, which has an active chip surface, such as the front side of the chip 3. The active chip surface of the chip 3 generally includes a first interface and a second interface. The specific form of the chip 3 and the distribution of the first and second interfaces on the active chip surface of the chip 3 can be selected according to the actual application scenario to meet the actual application scenario requirements.

[0097] Generally, on the active surface of a chip, the first interface and the second interface can be respectively located in a power network or a signal network. When the first interface or the second interface is located in a power network, its type is a power interface; when the first interface or the second interface is located in a signal network, its type is a signal interface. Specifically, when the first interface is a power interface, the second interface is a signal interface; or, when the first interface is a signal interface, the second interface is a power interface.

[0098] The first interface includes several ground pads and several functional pads. The second interface includes several ground pads and several functional pads. Specifically, when the first interface is a power interface, the ground pad is power ground pad 19 and the functional pad is power pad 20. When the second interface is a signal interface, the ground pad is signal interface ground pad 33 and the functional pad is signal interface signal pad 30. Similarly, the implementation where the first interface is a signal interface and the second interface is a power interface can be obtained. Please refer to the above description for details, and no specific examples will be given here.

[0099] For the first interface, the number of ground pads and functional pads can be determined based on the type of chip 3, etc., to meet the requirements of the actual application scenario. Similarly, for the second interface, the number of ground pads and functional pads can be selected and determined according to the actual application scenario.

[0100] When the active surface of chip 3 has both a first interface and a second interface, in order to interconnect with the package substrate 10, a first network transmission path and a second network transmission path need to be prepared. The first interface is adapted and connected to the active surface of the package substrate 10 through the first network transmission path to establish a power network or a signal network. The second interface is adapted and connected to the active surface of the package substrate 10 through the second network transmission path to establish a power network or a signal network.

[0101] After being adapted and connected to the packaging substrate 10 via the first network transmission path and the second network transmission path, the first network transmission path can be configured for power transmission or signal transmission depending on the type of the first interface. In this case, the second network transmission path can be used for either signal transmission or power transmission. Specifically, when the first interface is a power interface, the first network transmission path is configured for power transmission; when the first interface is a signal interface, the first network transmission path is configured for signal transmission. Similarly, the corresponding configuration of the second network transmission path when the second interface is a signal interface or a power interface can be obtained. Please refer to the above description for details; specific examples will not be provided here.

[0102] In one embodiment of the present invention, the first network transmission path and the second network transmission path are configured to be independent of each other, specifically meaning that they do not go through similar [paths / processes]. Figure 1 The coupling form of the chip substrate 2. After the first network transmission path and the second network transmission path are independent of each other, the power network transmission path is not affected by the signal network transmission path.

[0103] To reduce transmission loss, for the independent first and second network transmission paths, the first network transmission path can be configured between the active surface of the chip and the active surface of the package substrate. By configuring the first network transmission path between these two surfaces, the distance of the configured transmission path can be shortened, thereby reducing transmission loss. In this case, when the first network transmission path is used for power transmission, power transmission loss can be reduced; when the first network transmission path is used for signal transmission, signal transmission loss can be reduced.

[0104] In practice, when the first network transmission path is located between the active surface of the chip and the active surface of the package substrate, it is generally necessary to configure the first network transmission path as a vertical interconnect, a near-vertical interconnect, or other form that can effectively shorten the transmission path distance, so as to minimize transmission loss.

[0105] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0106] In one embodiment of the present invention, the chip package further includes a package substrate 11 adapted to the chip 3, the package substrate 11 serving the same purpose as... Figure 1 The chip substrate 2 serves the same purpose. Specifically, the package substrate 11 includes an internal circuit layer located within the package substrate 11.

[0107] In one embodiment of the present invention, the chip 3 is mounted on the package substrate 11, and the active surface of the chip 3 is opposite to the active surface of the package substrate 10.

[0108] Chip 3 is located between the package substrate 11 and the active surface of the package substrate 10. Optionally, the active surfaces of the package substrate 11, chip 3, and package substrate 10 are parallel to each other.

[0109] Specifically, chip 3 is generally mounted on the package substrate 11, such as on one side of the package substrate 11 in the thickness direction. The active surface of the package substrate is specifically a surface of the package substrate 10, such as... Figure 8 , Figure 14 , Figure 20 and Figure 22 The upper surface of the packaging substrate 10. In order to further shorten the length of the first network transmission path, the chip 3 is inverted and placed above the packaging substrate 10. At this time, the active surface of the chip 3 is opposite to the active surface of the packaging substrate 10, and the first interface and the second interface on the active surface of the chip are close to the active surface of the packaging substrate 10.

[0110] The package substrate 11 is located on one passive surface of the chip 3, such as... Figure 8 , Figure 14 , Figure 20 and Figure 22 As shown, the package substrate 11 is located above the chip 3. In order to improve the reliability of the connection between the chip 3 and the package substrate 11, the chip 3 needs to be encapsulated on the package substrate 11 using a molding compound 15.

[0111] As can be seen from the above explanation, Figure 1 In the present invention, both the first network transmission path and the second network transmission path pass through the chip substrate 2. However, in the embodiment of the present invention, when the first network transmission path is configured between the active surface of the chip and the active surface of the package substrate, the package substrate 11 is located above the first network transmission path. In this case, the first network transmission path does not pass through the package substrate 11. Therefore, for the layout of the package substrate 11, only the transmission of the signal network or the transmission of the power network needs to be considered. This can reduce the number of layers of the package substrate 11, reduce the thickness of the package substrate 11, and reduce the size of the package substrate 11 relative to the chip substrate 2, since the layout space of the power network or the signal network can be omitted.

[0112] In one embodiment of the present invention, the second network transmission path may be configured to pass through the package substrate 11. The second network transmission path may include a second network transmission first sub-path that connects the second interface to the package substrate 11 and a second network transmission second sub-path that connects the package substrate 11 to the package base 10. The first and second network transmission sub-paths will be described in detail below.

[0113] In specific implementation, the first sub-path of the second network transmission is electrically connected to the second sub-path of the second network transmission through the circuit layer inside the substrate. At this time, the second interface achieves electrical connection with the active surface of the package substrate through the first sub-path of the second network transmission, the circuit layer inside the substrate, and the second sub-path of the second network transmission. Specifically, the specific form of the package substrate 11, the circuit layer inside the package substrate 11, and the connection based on the circuit layer inside the substrate is determined to meet the actual transmission purpose.

[0114] In one embodiment of the present invention, the first network transmission path includes:

[0115] The first interface lead-out unit is used to lead out the first interface on the active surface of the chip toward the active surface of the packaging substrate.

[0116] An active surface contact connection unit is electrically connected to the active surface contact of the package substrate, so that the first interface of the active surface of the chip is adapted to be connected to the active surface of the package substrate through the first interface lead-out unit and the active surface contact connection unit.

[0117] When the active surface of chip 3 is opposite to the active surface of the packaging substrate 10, the first network transmission path generally includes at least a first interface lead-out unit and an active surface contact connection unit. The following is a detailed explanation of the situation of the first interface lead-out unit and the active surface contact connection unit.

[0118] For a chip 3, both the first interface and the second interface are located on the active surface of the chip 3. After the chip 3 is encapsulated by the molding layer 15, the molding layer 15 will encapsulate the first interface and the second interface. At this time, in order to form the required first network transmission path, the first interface needs to be brought out by the first interface lead-out unit.

[0119] Based on the above-described form of the first interface, an embodiment of the first interface lead-out unit can be obtained. Specifically, the first interface lead-out unit includes a first interface ground pad lead-out body for leading out the ground pads of the first interface and a first interface functional pad lead-out body for leading out the functional pads of the first interface.

[0120] Figures 2-22The figure illustrates some embodiments where the first interface is a power interface and the first network transmission path is used for power transmission. In the figure, the power ground pad 19 is the ground pad of the first interface, and the power pad 20 is the functional pad of the first interface. When the first interface is brought out, it specifically means that the power ground pad 19 and the power pad 20 are brought out simultaneously so as to interconnect with the active surface of the package substrate 10.

[0121] Figure 23 The diagram illustrates an embodiment where the first interface is a signal interface and the first network transmission path is used for signal transmission. In the diagram, the signal interface ground pad 33 is the ground pad of the first interface, and the signal interface signal pad 30 is the function pad of the first interface. Bringing out the first interface specifically means bringing out both the signal interface ground pad 33 and the signal interface signal pad 30 simultaneously.

[0122] In the above embodiments, the specific details of the ground pad and functional pad of the second interface within the second interface can be found in the above description, and will not be illustrated here.

[0123] When the first interface ground pad and the first interface functional pad are brought out using the first interface lead-out unit, in one embodiment of the present invention, the lead-out is preferably perpendicular to the active surface of the package substrate 10. Therefore, the first interface lead-out unit generally includes a plurality of first interface ground pad leads and a plurality of first interface functional pad leads. The number of first interface ground pad leads is sufficient to bring out the first interface ground pads. The number of first interface functional pad leads is sufficient to bring out the first interface functional pads. Optionally, the number of first interface functional pad leads is set to be consistent with the number of first interface functional pads. For example, when the first interface is a power interface, the power ground pad 19 is brought out using the first interface ground pad leads, and the power pad 20 is brought out using the first interface functional pad leads.

[0124] In one embodiment of the present invention, the first interface lead-out unit, the first interface ground pad lead-out body, and the first interface functional pad lead-out body are prepared and formed using the same process step, wherein,

[0125] The ground pad lead-out of the first interface and the functional pad lead-out of the first interface are prepared and formed based on one of the following processes: TMV process, wire bonding process or micro bump process, and embedded in the molding layer 15.

[0126] The following sections will provide a detailed description of the fabrication methods and processes based on TMV technology, wire bonding technology, or microbump technology. Of course, the fabrication process may not be limited to those listed; the specific process should be designed to produce the required first interface ground pads and first interface functional pads.

[0127] Of course, in practice, the ground pads and functional pads of the first interface can be fabricated using different processes, depending on the specific requirements. Using the same process improves process consistency and enhances the stability and reliability of the packaging process.

[0128] After the first interface is brought out through the first interface lead-out unit, an active surface contact connection unit can be prepared. The first interface is adapted and connected to the active surface of the packaging substrate through the first interface lead-out unit and the active surface contact connection unit, that is, the interconnection between the first interface and the active surface of the packaging substrate is realized.

[0129] Optionally, a first interface connection unit 16 may be provided on the first interface lead-out unit.

[0130] In one embodiment of the present invention, the first interface connection unit 16 is used to adapt and connect the first interface lead-out unit and the active surface contact connection unit, wherein,

[0131] The first interface connection unit 16 leads the first interface lead-out unit toward the active surface of the packaging substrate, and the first interface lead-out unit is electrically connected to the active surface contact connection unit through the first interface connection unit 16.

[0132] or,

[0133] The first interface connection unit 16 leads the first interface lead-out unit toward the active surface of the package substrate and rearranges the lead-out state of the first interface lead-out unit toward the active surface of the package substrate so that, after the rearrangement, the first interface lead-out unit is electrically connected to the active surface contact connection unit via the first interface connection unit 16.

[0134] The main difference between the two methods is whether the first interface connection unit 16 has the function of rearranging the lead-out state of the first interface lead-out unit to the active surface of the packaging substrate.

[0135] When the first interface ground pad is led out vertically to the active surface of the package substrate via the first interface ground pad lead-out body and the first interface functional pad is led out vertically via the first interface functional pad lead-out body, there may be a situation where the spacing between adjacent lead-out bodies is insufficient, failing to meet the minimum spacing requirement for fabricating the active surface contact connection unit. In this case, in order to set up the active surface contact connection unit and achieve alignment and interconnection with the package substrate 10, it is necessary to lead out the first interface lead-out unit towards the active surface of the package substrate via the first interface connection unit 16, and rearrange the lead-out state of the first interface lead-out unit towards the active surface of the package substrate to meet the minimum spacing requirement for fabricating the active surface contact connection unit. When the spacing between adjacent lead-out bodies is sufficient, the first interface connection unit 16 can simply lead out the first interface lead-out unit towards the active surface of the package substrate.

[0136] The first interface connection unit 16 is generally located between the first interface lead-out unit and the active surface contact connection unit.

[0137] In specific implementation, the first interface connection unit 16 includes an insulating dielectric layer and a plurality of interconnecting structural components distributed within the insulating dielectric layer; wherein...

[0138] The first interface lead-out unit is led out towards the active surface of the packaging substrate through the internal structural component.

[0139] Alternatively, when it is necessary to rearrange the first interface lead-out unit to the active surface of the packaging substrate through the first interface connection unit 16 to meet the minimum spacing of the active surface contact connection unit, the inner connection structure component rearranges the first interface lead-out unit to the active surface of the packaging substrate and leads it to the active surface of the packaging substrate.

[0140] Figure 8 , Figure 14 , Figure 20 and Figure 22 The packaging structures shown all illustrate embodiments of the first interface connection unit 16. In the figures, the first interface connection unit 16 includes an insulating dielectric layer and interconnect structure components distributed within the insulating dielectric layer. The interconnect structure components generally include ground pad interconnect structures and functional pad interconnect structures located within the insulating dielectric layer. The insulating dielectric layer, ground pad interconnect structures, and functional pad interconnect structures can be fabricated using techniques commonly used in this field, such as RDL (ReDistribution Layer) technology. The specific method and process of fabricating the first interface connection unit 16 using RDL technology can be consistent with techniques commonly used in this field.

[0141] In specific implementation, the functional pad interconnection structure and the first interface functional pad lead-out body can be in one-to-one correspondence. The specific correspondence is based on meeting the interconnection requirements between the first interface functional pad lead-out body and the active surface of the package substrate. When rearranging the lead-out state of the first interface lead-out unit, in one embodiment of the present invention, it specifically refers to using one or more functional pad interconnection structures to lead out the first interface functional pad lead-out body, or leading out the first interface functional pad lead-out body and rearranging the lead-out state of the corresponding first interface functional pad lead-out body. Of course, the ground pad interconnection structure can also be used simultaneously to lead out the first interface ground pad lead-out body, or lead out the first interface functional pad lead-out body and rearrange the lead-out state of the corresponding first interface ground pad lead-out body.

[0142] After rearranging the lead-out states of the first interface using functional pad interconnect structures and / or ground pad interconnect structures, the distance between adjacent functional pad interconnect structures exposed on the insulating dielectric layer is generally greater than the distance between the corresponding first interface functional pad leads; or, the distance between adjacent functional pad interconnect structures and ground pad interconnect structures exposed on the insulating dielectric layer is greater than the corresponding distance between the first interface ground pad leads and the first interface functional pad leads; or, the distance between adjacent ground pad interconnect structures exposed on the insulating dielectric layer is generally greater than the distance between the corresponding first interface ground pad leads. This provides space for fabricating active surface contact connection units on the insulating dielectric layer.

[0143] An active surface contact connection unit may generally include several active surface contact connectors 23. An active surface contact connector 23 is used to electrically connect the corresponding first interface ground pad lead-out or first interface functional pad lead-out to the active surface of the package substrate, thereby achieving interconnection between the first interface corresponding to the active surface contact connector 23 and the active surface of the package substrate through the corresponding first interface ground pad lead-out or first interface functional pad lead-out, the active surface contact connector 23, and the active surface of the package substrate.

[0144] Alternatively, when a first interface connection unit 16 is provided, an active surface contact connector 23 is used to electrically connect the corresponding ground pad interconnect structure or functional pad interconnect structure to the active surface of the package substrate. This enables interconnection between the first interface corresponding to the active surface contact connector 23 and the active surface of the package substrate through the corresponding first interface ground pad lead-out / first interface functional pad lead-out, ground pad interconnect structure / functional pad interconnect structure, active surface contact connector 23, and the active surface of the package substrate. The active surface contact connector 23 can generally be based on pads and solder balls formed by a ball-mounting process. Of course, it can also be formed using other processes. The specific choice can be made according to the needs of the application.

[0145] As explained above, the interconnection between the active surface contact connection unit and the active surface of the package substrate will differ depending on the type of the first interface. As described above, the active surface contact connection unit generally includes several active surface contact connectors 23. When the first interface is a power interface, the active surface contact connectors 23 are electrically connected to the functional pad interconnection structure within the first interface connection unit 16, thereby achieving interconnection between the first interface and the active surface of the package substrate through the first interface lead-out body within the first interface lead-out unit, the functional pad interconnection structure within the first interface connection unit 16, the active surface contact connectors 23 within the active surface contact connection unit, and the active surface of the package substrate; or the active surface contact connectors 23 are electrically connected to the first interface functional pad lead-out body within the first interface lead-out unit, thereby achieving interconnection between the first interface and the active surface of the package substrate through the first interface functional pad lead-out body, the active surface contact connectors 23 within the active surface contact connection unit, and the active surface of the package substrate.

[0146] When the first interface is a signal interface, the active surface contact connector 23 in the active surface contact connection unit is electrically connected to the ground pad interconnection structure and the functional pad interconnection structure in the first interface connection unit 16, so as to realize the interconnection of the first interface with the active surface of the package substrate through the first interface lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit, the ground pad interconnection structure and the functional pad interconnection structure in the first interface connection unit 16, and the active surface contact connector 23 in the active surface contact connection unit; or the active surface contact connector 23 in the active surface contact connection unit is connected to the first interface ground pad lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit, so as to realize the interconnection of the first interface with the active surface of the package substrate through the first interface ground pad lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit, and the active surface contact connector 23 in the active surface contact connection unit.

[0147] In one embodiment of the present invention, the first network transmission path configured for power transmission further includes a decoupling capacitor 6, wherein...

[0148] The decoupling capacitor 6 is located on the first interface connection unit 16 and is connected to the first interface adapter through the first interface connection unit 16 and the first interface lead-out unit to form a series connection between the ground pad of the first interface and the corresponding first interface functional pad.

[0149] When the first network transmission data is used for power transmission, decoupling capacitor 6 can also be set. Figure 8 , Figure 14 , Figure 20 and Figure 22In the illustrated packaging structure, the decoupling capacitor 6 is disposed on the first interface connection unit 16. Specifically, "disposal" means that the decoupling capacitor 6 is placed on the insulating dielectric layer. Optionally, the decoupling capacitor 6 and the active surface contact connection unit are located on the same surface of the insulating dielectric layer. The decoupling capacitor 6 can adopt a commonly used form. To achieve decoupling, the decoupling capacitor 6 generally needs to be connected in series between the first interface ground pad and the corresponding first interface functional pad. That is, the two ports of the decoupling capacitor 6 are electrically connected to the first interface ground pad and the first interface functional pad, respectively. The electrical connection state between the decoupling capacitor 6 and the first interface ground pad and the first interface functional pad is specifically determined to meet the decoupling purpose required by using the decoupling capacitor 6.

[0150] When the decoupling capacitor 6 is mounted on the insulating dielectric layer, one port of the decoupling capacitor 6 is electrically connected to the first interface ground pad through the ground pad interconnection structure and the first interface ground pad lead-out corresponding to the ground pad interconnection structure. The other port of the decoupling capacitor 6 is electrically connected to the first interface functional pad through the functional pad interconnection structure and the first interface functional pad lead-out corresponding to the functional pad interconnection structure.

[0151] and Figure 1 Compared to the packaging structure shown, the present invention, based on the distribution of the decoupling capacitor 6 and the electrical connection state with the ground pad and the functional pad of the first interface within the first interface, can reduce the connection distance, improve the decoupling effect, and improve the integrity of power supply network.

[0152] As explained above, when the first interface is a signal interface, the first network transmission path is used to implement signal transmission. In this case, such as... Figure 23 As shown, it is not necessary to set a decoupling capacitor 6 on the first interface connection unit 16.

[0153] In one embodiment of the present invention, a shielding layer 12 is provided on the package substrate 11, wherein,

[0154] The shielding layer 12 and the chip 3 are located on the two sides of the package substrate 11, and the shielding layer 12 corresponds to the chip 3 mounted on the package substrate 11.

[0155] The projection of the shielding layer 12 toward the chip 3 covers the area where the chip 3 is located, that is, the chip 3 falls within the projection range of the shielding layer 12 toward the chip 3.

[0156] Figure 8 , Figure 14 , Figure 20 and Figure 22In this embodiment, a shielding layer 12 is also provided on the back side of the package substrate 11. The shielding layer 12 can be prepared using shielding processes commonly used in this technical field, and the shielding layer 12 covers the back side of the package substrate 11. In order to improve the shielding effect, generally, the projection of the shielding layer 12 toward the chip 3 covers the area where the chip 3 is located, and the area of ​​the shielding layer 12 is greater than or equal to the area of ​​the chip 3. That is, when the shielding layer 12 is projected toward the chip 3, the chip 3 is located within the projection range of the shielding layer 12.

[0157] In specific implementation, since the chip 3 is inverted above the package substrate 10, that is, the back side of the package substrate 11 faces upwards, and the shielding layer 12 is prepared on the back side of the package substrate 11, when external electromagnetic signals propagate in the direction of the chip 3, the shielding layer 12 can be used to achieve a better electromagnetic shielding effect and provide good EMI (Electromagnetic Interference) protection for the chip 3.

[0158] In one embodiment of the present invention, the second sub-path of the second network transmission includes a plurality of second sub-path lines formed by wire bonding process or a plurality of metal pins for connecting and supporting the package substrate, wherein,

[0159] When the second sub-path of the second network is transmitted based on the metal pins, the metal pins are perpendicular to the active surface of the package substrate 10.

[0160] Figure 2 , Figure 8 , Figure 14 , Figure 20 and Figure 22 The diagram illustrates some embodiments where the second interface is a signal interface. When the second interface is a signal interface, the specific details can be found in the above description. Therefore, as can be seen from the above description, the ground pad of the second interface can be formed through the ground pad 33, and the signal pad of the second interface can be formed through the signal pad 30. In the diagram, the distribution areas of the signal pad 30 and the ground pad 33 are located outside the distribution areas of the power ground pad 19 and the power pad 20. Of course, the distribution of the second interface ground pad and the second interface functional pad on the active surface of the chip can be selected and set according to actual needs, and will not be listed and described in detail here.

[0161] Based on the aforementioned second interface form, the second network transmission first sub-path generally includes several second network transmission first sub-path first lines 17 and several second network transmission first sub-path second lines 18. The second network transmission first sub-path first lines 17 and second network transmission first sub-path second lines 18 can be fabricated using a wire bonding process. The signal interface signal pads 30 are adapted to the front side of the package substrate 11 via the second network transmission first sub-path first lines 17, and the signal interface ground pads 33 are adapted to the front side of the package substrate 11 via the second network transmission first sub-path second lines 18. Adapting to the package substrate 11 specifically means that after connection to the package substrate 11, the signal transmission via the package substrate 11 can be satisfied. The specific adaptation connection can be consistent with existing methods, based on the requirement of satisfying the formation of a first network transmission path via the package substrate 11.

[0162] Generally, after the second network transmission first sub-path is prepared, the chip 3 is encapsulated, that is, the second network transmission first sub-path is generally encapsulated by the encapsulation layer 15. At this time, the encapsulation layer 15 can protect the second network transmission first sub-path and improve the stability and reliability of the connection between the second network transmission first sub-path and the package substrate 11.

[0163] For the second sub-path of the second network transmission, it generally needs to be prepared or formed after or simultaneously with the alignment and interconnection between the chip package and the package substrate 10 using the active surface contact connector 23. In specific implementations, the second sub-path of the second network transmission can be prepared or formed using different technical means, such as... Figure 8 , Figure 14 and Figure 20 The example shown is prepared based on a wire bonding process. Figure 22 An embodiment based on metal pin formation is shown in the figure.

[0164] Figure 8 , Figure 14 and Figure 20 In the packaging structure shown, the second network transmission second sub-path includes several second network transmission second sub-path first lines 13 and several second network transmission second sub-path second lines 14. The second network transmission second sub-path first lines 13 and second network transmission second sub-path second lines 14 are fabricated based on wire bonding technology. One end of the second network transmission second sub-path first line 13 is electrically connected to the back side of the package substrate 11, and the other end of the second network transmission second sub-path first line 13 is electrically connected to the active surface of the package substrate 10. The connection of the second network transmission second sub-path second lines 14 can be referred to the description of the second network transmission second sub-path first line 13, and the specific connection should be based on the ability to form a second network transmission path.

[0165] In one embodiment of the present invention, a second network transmission second sub-path protection body 24 is formed by dispensing adhesive to protect the second network transmission second sub-path formed based on the second network transmission second sub-path line body.

[0166] After the first wire body 13 and the second wire body 14 of the second sub-path of the second network transmission are fabricated using a wire bonding process, the protective body 24 of the second sub-path of the second network transmission can be fabricated using a dispensing process, such as... Figure 8 , Figure 14 and Figure 20 In the scenario shown, the second network transmission second sub-path protector 24 is used to wrap the first line 13 and the second line 14 of the second network transmission second sub-path. The method and process of forming the second network transmission second sub-path protector 24 using a dispensing process can be consistent with existing methods, specifically designed to wrap the first line 13 and the second line 14 of the second network transmission second sub-path. In this case, the second network transmission second sub-path protector 24 can also provide support for the chip package, further improving the stability and reliability of the chip package on the package substrate 10.

[0167] When a second sub-path for transmission is formed based on metal pins, it is generally necessary to pre-set metal pins on the package substrate 10. The metal pins are generally perpendicular to and distributed on the active surface of the package substrate. When the active surface contact connection unit is aligned and interconnected with the package substrate 10, the package substrate 11 is simultaneously aligned and electrically connected with the metal pins on the active surface of the package substrate. That is, the metal pins can be used to support the package substrate 11 and also to achieve electrical connection between the package substrate 11 and the active surface of the package substrate 10.

[0168] Figure 22 As shown, three pairs of metal pins are provided on the active surface of the package substrate 10, such as a first metal pin 29, a second metal pin 31, and a third metal pin 32 being provided on the active surface of the package substrate.

[0169] In specific implementation, the number of metal pins on the active surface of the package substrate can be selected according to actual needs, so as to meet the requirements of supporting the package substrate 11 and electrically connecting with the package substrate 11 to ultimately form the second network transmission second sub-path.

[0170] In one embodiment of the present invention, for the second sub-path of the second network transmission formed based on metal pins, the connection between the package substrate 11 and the second sub-path of the second network transmission includes a pluggable connection.

[0171] Specifically, the pluggable design refers to the ability to plug and unplug between the package substrate 11 and the metal pins. When a pluggable design is used, the package substrate 11 or the package base 10 can be replaced. Generally, the height of the metal pins is less than the length of the first line 13 of the second sub-path of the second network transmission, and the diameter of the metal pins is greater than the diameter of the first line 13 of the second sub-path of the second network transmission, which is beneficial to improving the integrity of signal transmission.

[0172] Regarding the above-described packaging structure, in one embodiment of the present invention, a packaging method for reducing transmission loss is provided for fabricating the packaging structure, wherein the packaging method includes:

[0173] A chip package and a package substrate 10 are provided, and the chip package and the package substrate 10 are aligned and interconnected.

[0174] The chip package includes at least one chip 3 with an active chip surface. The active chip surface includes a first interface and a second interface, which are independent of each other. The first interface and the second interface of the active chip surface are respectively adapted and connected to the active surface of the package substrate through a first network transmission path and a second network transmission path.

[0175] The first network transmission path is configured for power transmission between chip 3 and package substrate 10, and the second network transmission path is configured for signal transmission between chip 3 and package substrate 10; or, the second network transmission path is configured for power transmission between chip 3 and package substrate 10, and the first network transmission path is configured for signal transmission between chip 3 and package substrate 10.

[0176] The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and the signal transmission path between the chip 3 and the package substrate 10 are isolated from each other.

[0177] The first network transmission path is located between the active surface of the chip and the active surface of the package substrate to shorten the transmission distance of the first network transmission path.

[0178] As can be seen from the above description, on the active surface of the chip, the first interface and the second interface can be respectively set in the power network or the signal network. When the first interface or the second interface is set in the power network, its type is a power interface. When the first interface or the second interface is set in the signal network, its type is a signal interface. Specifically, when the type of the first interface is a power interface, the type of the second interface is a signal interface; or, when the type of the first interface is a signal interface, the type of the second interface is a power interface.

[0179] The following section provides a detailed description of the fabrication process of the provided chip package.

[0180] In one embodiment of the present invention, the chip package is prepared by a process including:

[0181] Chip 3 is mounted on the front side of the package substrate 11;

[0182] A first interface lead-out unit and a second network transmission first sub-path are prepared. The first interface lead-out unit and the second network transmission first sub-path are both embedded in the molding layer 15. The chip 3 is molded onto the front side of the package substrate 11 through the molding layer 15, and the first interface ground pad lead-out body and the first interface function pad lead-out body in the first interface lead-out unit are exposed from the end face of the molding layer 15.

[0183] Active surface contact connection units are fabricated on the molding layer 15. Specifically, a number of active surface contact connectors 23 are fabricated based on the ball-mounting process. The active surface contact connectors 23 can achieve corresponding electrical connections with the power pads 20.

[0184] Optionally, before fabricating the active surface contact connection unit, a first interface connection unit 16 covering the molding layer 15 is first fabricated, and the first interface ground pad lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit are led out through the first interface lead-out unit 16, or the lead-out state in the first interface lead-out unit is rearranged.

[0185] An active surface contact connection unit is fabricated on the first interface connection unit 16.

[0186] As explained above, the first interface includes several ground pads and several functional pads; the second interface includes several ground pads and several functional pads. Specifically, when the first interface is a power interface, the ground pad is power ground pad 19, and the functional pad is power pad 20; when the second interface is a signal interface, the ground pad is signal interface ground pad 33, and the functional pad is signal interface signal pad 30. Similarly, the implementation where the first interface is a signal interface and the second interface is a power interface can be obtained.

[0187] Based on the type of the first interface, a corresponding first interface lead-out unit is fabricated, which includes a first interface ground pad lead-out body for leading out the ground pads of the first interface and a first interface functional pad lead-out body for leading out the functional pads of the first interface. As can be seen from the above description, the first interface ground pad lead-out body and the first interface functional pad lead-out body are fabricated using the same process steps to fabricate the first interface lead-out unit.

[0188] The first interface ground pad lead-out and the first interface functional pad lead-out are prepared based on one of the following processes: TMV (through mold via) process, wire bonding process or micro bump process, and embedded in the molding layer 15.

[0189] The following details the process of using different fabrication processes for the ground pad lead-out of the first interface and the functional pad lead-out of the first interface to finally form a chip package.

[0190] Figure 2 In this configuration, to mount chip 3 onto the front side of the package substrate 11, the second interface and the first interface are located on the front side of chip 3. Furthermore, in... Figure 2 In the process, a shielding layer 12 is formed on the back side of the package substrate 11. The shielding layer 12 can be formed after the chip 3 is mounted on the package substrate 11, or the shielding layer 12 can be formed first. The specific process sequence can be selected as needed.

[0191] Figures 3-5 The above describes a fabrication process for a chip package, specifically an embodiment of forming a first interface ground pad lead-out and a first interface functional pad lead-out based on TMV. Specifically:

[0192] Figure 3 In this process, a second network transmission first sub-path is prepared based on wire bonding technology, and a molding layer 15 is prepared after the second network transmission first sub-path is prepared. At this time, the molding layer 15 molds the second network transmission first sub-path on the front side of the package substrate 11. The specific details of the second network transmission first sub-path can be found in the above description.

[0193] When the first interface is a power interface Figure 4 In this process, grooves are cut into the aforementioned molding layer 15, such as using laser technology, so that the power ground pads 19 and 20 of the power network are exposed through the grooves. Metal is filled into the grooves to form power ground pad lead-out TMV connectors 21 and 22, respectively. The power ground pad lead-out TMV connectors 22 are electrically connected to the corresponding power pads 20, and the power ground pad lead-out TMV connectors 21 are electrically connected to the corresponding power ground pads 19.

[0194] At this time, a first interface ground pad is formed by leading out the TMV connector 21 through the power ground pad, and a first interface function pad is formed by leading out the TMV connector 22 through the power pad. Thus, the power ground pad 19 is led out through the TMV connector 21 through the power ground pad, and the corresponding power pad 20 is led out through the TMV connector 22 through the power pad.

[0195] Figure 5In the process, the first interface connection unit 16 is fabricated using the RDL process, and the first interface connection unit 16 is used to rearrange the lead-out distribution of the TMV connector 22 from the power pad.

[0196] After forming the first interface connection unit, several active surface contact connectors 23 are prepared based on the ball-planting process. The active surface contact connectors 23 can realize corresponding electrical connections with the power pads 20.

[0197] When the first interface is a power interface Figures 9-11 This is a fabrication process for a chip package, specifically an embodiment of forming a first interface ground pad lead-out and a first interface functional pad lead-out based on a wire bonding process. Specifically:

[0198] Figure 9 In the process, after chip 3 is mounted on package substrate 11, a second network transmission first sub-path is prepared using wire bonding process, and power ground pad lead-out wire connectors 25 and power pad lead-out wire connectors 26 are prepared based on wire bonding process. The power ground pad lead-out wire connectors 25 are distributed on power ground pad 19, and the power pad lead-out wire connectors 26 are vertically distributed on the corresponding power pad 20.

[0199] At this time, a first interface ground pad is formed by leading out the power ground pad through the wire bonding connector 25, and a first interface functional pad is formed by leading out the power pad through the wire bonding connector 26. Thus, the power ground pad 19 is led out through the power ground pad leading out the wire bonding connector 25, and the corresponding power pad 20 is led out through the power pad leading out the wire bonding connector 26.

[0200] The process conditions and procedures for fabricating the second network transmission first sub-path, the power ground pad lead-out wire bond connector 25, and the power pad lead-out wire bond connector 26 using wire bonding technology are consistent with existing technologies.

[0201] Subsequently, a molding process is used to prepare a molding layer 15, which molds the second network transmission first sub-path, the power ground pad lead-out wire connector 25, and the power pad lead-out wire connector 26. The molding layer 15 can completely encapsulate the power ground pad lead-out wire connector 25 and the power pad lead-out wire connector 26.

[0202] Figure 10 In the process, the molding layer 15 is thinned so that the corresponding ends of the power ground pad lead-out wire connector 25 and the power pad lead-out wire connector 26 are exposed.

[0203] Figure 11 In this process, the first interface connection unit 16 is fabricated using the RDL process. The details of the first interface connection unit 16 can be found in the description above. Figure 5 The TMV connector 22, which is connected to a power pad in the middle, has a different layout than the previous version. Figure 11 The first interface connection unit 16 mainly realizes the rearrangement of the lead-out distribution of the wire bonding connector 26 from the power pad. After the first interface connection unit is formed, the active surface contact connector 23 can be fabricated based on the ball-mounting process, as detailed in the above description.

[0204] When the first interface is a power interface Figures 15-18 This is a fabrication process for a chip package, specifically an embodiment of forming a first interface ground pad lead-out and a first interface functional pad lead-out based on a microbump process.

[0205] Figure 15 In the process, after the chip 3 is mounted on the package substrate 11, microbump units are fabricated on the power network of the chip 3, so as to form power ground pad lead-out microbump connectors 27 and power pad lead-out microbump connectors 28 respectively using the fabricated microbumps. The power ground pad lead-out microbump connectors 27 are distributed on the power ground pad 19, and the power pad lead-out microbump connectors 28 are distributed on the corresponding power pad 20.

[0206] Microbumps can be prepared using techniques commonly used in this field. Microbumps can be columnar, blocky, or other shapes, and can form the same or similar shapes and distributions as the TMV process and wire bonding process.

[0207] At this time, a first interface ground pad is formed by leading out a microbump connector 27 from the power ground pad, and a first interface functional pad is formed by leading out a microbump connector 28 from the power pad. Thus, the power ground pad 19 is led out through the microbump connector 27 from the power ground pad, and the corresponding power pad 20 is led out through the microbump connector 28 from the power pad.

[0208] Figure 16 In the process of preparing the first sub-path of the signal transmission network, a molding process is used to form a molding layer 15, which encapsulates the first sub-path of the second network transmission, the power and ground pad lead-out microbump connector 27, and the power pad lead-out microbump connector 28.

[0209] Figure 17 In this process, the molding layer 15 is thinned using techniques commonly used in this field, so that the power ground pad lead-out microbump connector 27 and the power pad lead-out microbump connector 28 are exposed at their respective ends away from the chip 3 after thinning.

[0210] Figure 18 In this process, the first interface connection unit is fabricated using the RDL process. The details of the first interface connection unit can be found in the description above. Figure 18 The first interface connection unit 16 mainly realizes the rearrangement of the distribution of the micro-bump connector 28 leading out from a power pad, and after the rearrangement, the active surface contact connector 23 can be fabricated based on the ball-mounting process after the first interface connection unit is formed. The fabrication of the active surface contact connector 23 and the corresponding connection state can be referred to the above description.

[0211] In practical implementation, when based on microbumps, on the one hand, the height of the microbump (commonly 60μm-90μm) is smaller than the interconnect length (commonly 1mm-2mm) when using wire bonding in traditional solutions; on the other hand, the diameter of the bump (commonly 60μm-100μm) is larger than the wire diameter (commonly 18μm-25μm) when using wire bonding in traditional solutions. Therefore, when the first interface lead-out unit prepared based on microbumps is used for power transmission, the power loss is smaller.

[0212] The above diagram illustrates the process when the first interface is a power interface. When the first interface is a signal interface, the specific process can be found in the above description, and will not be illustrated here.

[0213] In the above-described manufacturing process, after the first interface connection unit 16 is prepared, when the power interface needs to be decoupled, the decoupling capacitor 6 needs to be attached to the first interface connection unit 16. The function and connection method of the decoupling capacitor 6 can be referred to the above description.

[0214] The above describes the fabrication process of the chip package in detail. After the chip package is fabricated, it needs to be interconnected with the package substrate 10. Specifically, the interconnection between the chip package and the package substrate 10 includes:

[0215] The chip 3 is disposed upside down above the active surface of the packaging substrate 10, wherein the chip 3 is located between the packaging substrate 11 and the packaging substrate 10.

[0216] Align the active surface contact connection unit with the package substrate 10, and interconnect the active surface of the package substrate 10 with the active surface of the package substrate 10 to enable the first interface of the chip 3 to be adapted and connected to the package substrate 10.

[0217] Based on the second sub-path of the formed second network, the second interface of chip 3 is adapted and connected to the package substrate 10.

[0218] Based on the above chip package, it can be seen that when interconnecting with the package substrate 10, the chip 3 needs to be inverted first, that is, the active surface of the chip 3 is opposite to the active surface of the package substrate 10. At this time, the active surface contact connection unit is adjacent to the active surface of the package substrate 10.

[0219] After inverting chip 3, at least align the active surface contact connection unit with the package substrate 10. Then, align and interconnect the active surface contact connection unit with the active surface of the package substrate 10. At this time, by aligning and interconnecting the active surface contact connection unit with the active surface of the package substrate 10, the first interface of the chip can be adapted and connected to the active surface of the package substrate 10, thus forming the required first network transmission path, such as... Figure 6 , Figure 12 and Figure 19 As shown.

[0220] As can be seen from the above description, different implementation methods can be used for the second sub-path of the second network transmission. When different implementation methods are used, the process steps for forming the second sub-path of the second network transmission will be different.

[0221] Figure 7 and Figure 13 In this process, after the active surface contact connector 23 is aligned and interconnected with the active surface of the encapsulation substrate 10, a second network transmission second sub-path is fabricated using a wire bonding process. As described above, the second network transmission second sub-path includes a first line 13 and a second line 14. The two ends of the first line 13 and the second line 14 are respectively connected to the active surfaces of the encapsulation substrate 11 and the encapsulation substrate 10, specifically to meet the requirements for forming a second network transmission path.

[0222] Figure 8 , Figure 14 and Figure 20 In this process, a second network transmission second sub-path protector 24 is prepared by dispensing to protect the second network transmission second sub-path. The specific details of the second network transmission second sub-path protector 24 can be found in the above description and will not be repeated here.

[0223] Another way to prepare the second sub-path of the second network transmission is, as follows: Figure 21 and Figure 22As shown, several metal pins are pre-formed on the active surface of the package substrate 10. While the active surface contact connector 23 is aligned and interconnected with the package substrate 10, the metal pins on the package substrate 10 are aligned and interconnected with the package body substrate 11. At this time, the metal pins form a second network to transmit a second sub-path. The metal pins and the package body substrate 11 can be connected in a pluggable manner.

[0224] Since metal pins generally have high rigidity, using metal pins to support and interconnect the package substrate 11 eliminates the need for a protective structure to protect the metal pins. As explained above, using metal pins to form the second sub-path of the second network transmission enables a pluggable connection between the package substrate 11 and the second sub-path of the second network transmission, improving maintenance convenience.

[0225] Of course, in specific implementation, the second network transmission second sub-path can also take other forms, specifically based on the ability to achieve the adaptation connection between the package substrate 11 and the package base 10, and to form the required second network transmission second sub-path.

[0226] Figure 23 The illustration shows an embodiment where the first interface is a signal interface. Compared to the first network transmission path transmitting power, in this embodiment, the first network transmission path is configured for signal transmission, and the first network transmission path also includes a first interface lead-out unit and an active surface contact connection unit. Optionally, it also includes a first interface connection unit 16 disposed between the first interface lead-out unit and the active surface contact connection unit. Figure 23 The signal interface connection unit 34 in the middle forms the first interface connection unit 16.

[0227] As described above, the signal interface connection unit 34 generally includes an insulating dielectric layer and several interconnect structures distributed within the insulating dielectric layer. These interconnect structures may include ground pad interconnect structures and functional pad interconnect structures located within the insulating dielectric layer. The insulating dielectric layer and interconnect structures can generally be fabricated using the RDL process. The insulating dielectric layer covers the molding compound 15, and the connection and fit between the interconnect structures and the first interface lead-out unit can be referred to the above description.

[0228] After the signal interface connection unit 34 is fabricated, an active surface contact connection unit can be fabricated on the insulating dielectric layer of the signal interface connection unit 34. The fabrication method of the active surface contact connection unit, the connection and fit between the active surface contact connection unit and the signal interface connection unit 34, and the connection and fit between the active surface contact connection unit and the active surface of the package substrate can all refer to the above description. After the signal interface connection unit 34 is fabricated, an adapter electrical connection is made between the active surface contact connection unit and the signal interface connection unit 34, and ultimately, the interconnection between the first interface and the active surface of the package substrate can be achieved through the active surface contact connection unit.

[0229] Figure 23 In the embodiment, the second interface is a power interface. In this case, the second network transmission path includes a first sub-path of power network transmission and a second sub-path of power network transmission. Therefore, the first sub-path of power network transmission is the same as the first sub-path of second network transmission, and the second sub-path of power network transmission is the same as the second sub-path of second network transmission. Thus, the specific details of the first sub-path of power network transmission and the second sub-path of power network transmission can be found in the above description, and will not be repeated here.

[0230] Figure 23 In the figure, the shielding layer 12 is not shown; in addition, the decoupling capacitor 6 connected to the second interface adapter is also not shown.

[0231] In summary, this invention makes the first network transmission path and the second network transmission path independent of each other. When the first network transmission path is configured to be located between the active surface of the chip and the active surface of the package substrate, the influence of the signal transmission path on the power transmission path can be reduced, and the power transmission loss or signal transmission loss can be reduced. At the same time, since the first network transmission path does not pass through the package substrate 11, the thickness and size of the package substrate 11 can be reduced, and the complexity of the package substrate 11 can be reduced.

[0232] Chip 3 is mounted on the front side of the package substrate 11, and a shielding layer 12 is provided on the back side of the package substrate 11. The shielding layer 12 can shield the chip 3 from electromagnetic interference, thereby improving the stability and reliability of the chip 3 during operation. At the same time, when the chip 3 is inverted, the distance of the first network transmission path can be further reduced, thereby reducing power transmission loss.

[0233] When the first interface is brought out, the first interface lead-out unit can be formed by one of the following processes: TMV process, wire bonding process or micro bump process. At this time, the first interface ground pad lead-out body and the first interface functional pad lead-out body in the first interface lead-out unit can effectively shorten the interconnect length and further reduce power transmission loss or signal transmission loss.

[0234] After the first interface ground pad lead-out body and the first interface functional pad lead-out body are led out and rearranged by the first interface connection unit 16, in addition to effectively providing process space for fabricating active surface contact connection units, it can also realize the placement and connection of decoupling capacitor 6, which can improve the decoupling effect.

[0235] When the second sub-path of the second network is formed based on the metal pins, a pluggable connection can be formed between it and the package substrate 11, which improves the convenience of maintenance. Since the height of the metal pins is less than the length of the bonding wire and the diameter of the metal pins is greater than the diameter of the bonding wire, it is beneficial to improve the reliability of signal transmission.

Claims

1. A packaging structure for reducing transmission loss, characterized in that, The packaging structure includes: A package substrate for interconnection with a chip package; A chip package includes at least one chip with an active surface. The active surface includes a first interface and a second interface, which are independent of each other. The first interface and the second interface of the active surface are respectively connected to the active surface of the package substrate via a first network transmission path and a second network transmission path. The first network transmission path is configured for power transmission between the chip and the package substrate, and the second network transmission path is configured for signal transmission between the chip and the package substrate; or, the second network transmission path is configured for power transmission between the chip and the package substrate, and the first network transmission path is configured for signal transmission between the chip and the package substrate. The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and signal transmission path between the chip and the package substrate are isolated from each other. The first network transmission path is located between the active surface of the chip and the active surface of the package substrate, so as to shorten the transmission distance of the first network transmission path. The chip package further includes a package substrate adapted to the chip, wherein, The chip is mounted on the package substrate, and the active surface of the chip is opposite to the active surface of the package substrate. The chip is located between the active surface of the package substrate and the package base. The second network transmission path includes a first sub-path for connecting the second interface to the package substrate and a second sub-path for connecting the second network transmission to the active surface of the package substrate via the package substrate. The package substrate includes an internal circuit layer located within the package substrate, wherein... The first sub-path of the second network transmission is adapted and connected to the second sub-path of the second network transmission through the circuit layer in the substrate. For the first network transmission path, it includes: The first interface lead-out unit is used to lead out the first interface on the active surface of the chip toward the active surface of the packaging substrate. An active surface contact connection unit is electrically connected to the active surface contact of the packaging substrate, so that the first interface is adapted to be connected to the active surface of the packaging substrate via the first interface lead-out unit and the active surface contact connection unit.

2. The packaging structure for reducing transmission loss according to claim 1, characterized in that, For the first network transmission path, it also includes: The first interface connection unit is used to adapt and connect the first interface lead-out unit and the active surface contact connection unit, wherein... The first interface connection unit leads the first interface lead-out unit toward the active surface of the packaging substrate, and the first interface lead-out unit is electrically connected to the active surface contact connection unit through the first interface connection unit. or, The first interface connection unit leads the first interface lead-out unit toward the active surface of the package substrate, and rearranges the lead-out state of the first interface lead-out unit toward the active surface of the package substrate so that after the rearrangement, the first interface lead-out unit is electrically connected to the active surface contact connection unit via the first interface connection unit.

3. The packaging structure for reducing transmission loss according to claim 2, characterized in that, The first interface includes several ground pads and several functional pads for the first interface. The first interface lead-out unit includes a first interface ground pad lead-out body for leading out the ground pads of the first interface and a first interface functional pad lead-out body for leading out the functional pads of the first interface, wherein... Both the ground pad lead-out of the first interface and the functional pad lead-out of the first interface are embedded in the molding layer used to encapsulate the chip on the package substrate.

4. The packaging structure for reducing transmission loss according to claim 3, characterized in that, The first network transmission path configured for power transmission also includes decoupling capacitors, wherein, The decoupling capacitor is located on the first interface connection unit and is connected to the first interface adapter through the first interface connection unit and the first interface lead-out unit to be configured to form a series connection between the ground pad of the first interface and the corresponding first interface functional pad.

5. The packaging structure for reducing transmission loss according to claim 2, characterized in that, The first interface connection unit includes an insulating dielectric layer and a plurality of interconnecting structural components distributed within the insulating dielectric layer; wherein, The internal interconnect structure component leads the first interface lead-out unit toward the active surface of the packaging substrate; or, The internal structure component rearranges the first interface lead-out unit to the active surface of the packaging substrate and leads it out to the active surface of the packaging substrate. The active surface contact connection unit includes several active surface contact connectors located on an insulating dielectric layer, wherein a corresponding internal interconnect structure component is adapted to be electrically connected to the active surface of the package substrate through an active surface contact connector.

6. The packaging structure for reducing transmission loss according to claim 1, characterized in that, The second network transmission second sub-path includes several second network transmission second sub-path lines formed by wire bonding process or several metal pins for connecting and supporting the package substrate; Among them, for the second sub-path of the second network transmission based on the metal pins, the connection between the package substrate and the second sub-path of the second network transmission includes a pluggable connection.

7. The packaging structure for reducing transmission loss according to claim 6, characterized in that, For the second sub-path of the second network transmission formed based on the second sub-path line body of the second network transmission, a second sub-path protection body for protecting the second sub-path of the second network transmission is formed by dispensing adhesive.

8. The packaging structure for reducing transmission loss according to claim 1, characterized in that, A shielding layer is disposed on the substrate of the package, wherein... The shielding layer and the chip are located on opposite sides of the package substrate; The projection of the shielding layer toward the chip covers the area where the chip is located.

9. A packaging method for a packaging structure to reduce transmission loss, characterized in that, For preparing the packaging structure according to any one of claims 1-8, wherein the packaging method comprises: A chip package and a package substrate are provided, and the chip package and the package substrate are aligned and interconnected. The chip package includes at least one chip with an active surface. The active surface includes a first interface and a second interface, which are independent of each other. The first and second interfaces of the active surface are respectively connected to the active surface of the package substrate via a first network transmission path and a second network transmission path. The first network transmission path is configured for power transmission between the chip and the package substrate, and the second network transmission path is configured for signal transmission between the chip and the package substrate; or, the second network transmission path is configured for power transmission between the chip and the package substrate, and the first network transmission path is configured for signal transmission between the chip and the package substrate. The first network transmission path and the second network transmission path are configured to be independent of each other so that the power transmission path and signal transmission path between the chip and the package substrate are isolated from each other. The first network transmission path is located between the active surface of the chip and the active surface of the package substrate to shorten the transmission distance of the first network transmission path.

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