Semiconductor structure and semiconductor structure manufacturing method

Abstract

A semiconductor structure includes an active interposer layer, a first stacked wafer module, and a second stacked wafer module. The active interposer layer includes a substrate, a first control circuit located in a first control region of the substrate, a second control circuit located in a second control region of the substrate, and a communication circuit connecting the first and second control circuits. The first stacked wafer module is vertically stacked in the first control region of the active interposer layer, and the second stacked wafer module is vertically stacked in the second control region of the active interposer layer to integrate and package multiple components. Furthermore, a method for manufacturing a semiconductor structure is also disclosed herein.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] The statements herein are provided only as background information in relation to the present invention and do not necessarily constitute prior art.

[0003] With the increasing density of electronic components, the development of three-dimensional circuit routing schemes has begun. In recent years, through-silicon via (TSV) technology, which connects upper and lower electronic components, has flourished. The process of forming a TSV can begin from the surface of the upper electronic component. The completion of the TSV structure enables electrical connection between the circuit interconnects of the upper and lower electronic components and allows for the reception of external signals.

[0004] Furthermore, with the advancement of the electronics industry, the demand for high-performance, high-speed, and miniaturized electronic components continues to increase. To meet this demand, packaging technologies have recently been developed that can encapsulate multiple semiconductor wafers in a single package.

[0005] Due to the rapid increase in market demand for portable electronic devices in recent years, there is a need to further reduce the size and weight of electronic components in portable electronic devices. Therefore, there is a need to develop a packaging technology that can reduce the size of electronic components to integrate multiple components into a single package. Summary of the Invention

[0006] This summary is intended to provide a simplified overview of the invention to enable the reader to gain a basic understanding of its contents. It is not a complete summary of the invention and is not intended to identify key / critical elements of the embodiments or define the scope of the invention.

[0007] One object of this invention is to provide a semiconductor structure and a method for manufacturing the semiconductor structure. This semiconductor structure includes an active interposer layer, a first stacked wafer module, and a second stacked wafer module. The active interposer layer includes a substrate, a first control circuit located in a first control region of the substrate, a second control circuit located in a second control region of the substrate, and a communication circuit connected between the first and second control circuits. The first stacked wafer module is vertically stacked in the first control region of the active interposer layer, and the second stacked wafer module is vertically stacked in the second control region of the active interposer layer.

[0008] In some embodiments, the first stacked chip module includes a plurality of first stacked chips, vertically stacked in a first control region of an active interposer layer. The first stacked chips include dynamic random access memory (DRAM).

[0009] In some embodiments, the second stacked chip module includes a plurality of second stacked chips vertically stacked in a second control region of an active interposer layer. The second stacked chips include NAND flash memory.

[0010] In some embodiments, the active interposer also includes a plurality of through silicon vias (TSVs) formed by a via middle process.

[0011] In some embodiments, the semiconductor structure further includes a non-active interposer layer, on which the active interposer layer is bonded.

[0012] In some embodiments, the semiconductor structure further includes a logic wafer bonded to a non-active interposer layer.

[0013] In some embodiments, the logic chip includes a central processing unit (CPU), a graphics processing unit (GPU), or a field-programmable gate array (FPGA).

[0014] In some embodiments, the first stacked wafer module and the second stacked wafer module are configured in parallel with the logic wafer.

[0015] According to another aspect of the present invention, a semiconductor structure manufacturing method includes providing an active interposer layer, wherein the active interposer layer includes a substrate, a first control circuit located in a first control region of the substrate, a second control circuit located in a second control region of the substrate, and a communication circuit connected between the first control circuit and the second control circuit; vertically bonding a first stacked wafer module in the first control region of the active interposer layer; and vertically bonding a second stacked wafer module in the second control region of the active interposer layer.

[0016] In some embodiments, the semiconductor structure manufacturing method further includes vertically stacking a plurality of first stacked wafers in a first control region of an active interposer to form a first stacked wafer module. The first stacked wafers include dynamic random access memory (DRAM).

[0017] In some embodiments, the semiconductor structure manufacturing method further includes vertically stacking a plurality of second stacked wafers in a second control region of an active interposer to form a second stacked wafer module. The second stacked wafers include NAND flash memory.

[0018] In some embodiments, the active interposer also includes a plurality of through silicon vias (TSVs) formed by a via middle process.

[0019] In some embodiments, the semiconductor structure manufacturing method further includes dicing an active interposer layer to form a plurality of integrated memory wafers.

[0020] In some embodiments, the semiconductor structure manufacturing method further includes bonding a logic wafer and at least one integrated memory wafer on a non-active interposer layer.

[0021] In some embodiments, the logic chip includes a central processing unit (CPU), a graphics processing unit (GPU), or a field-programmable gate array (FPGA).

[0022] In some embodiments, the first stacked wafer module and the second stacked wafer module are configured in parallel with the logic wafer.

[0023] Therefore, in the semiconductor structure and semiconductor structure manufacturing method disclosed in this invention, dynamic random access memory (DRAM) and flash memory (NAND) chips are bonded to an active interposer layer to form an integrated memory chip. Furthermore, the logic chip and the integrated memory chip can be bonded to a non-active interposer layer, and both the DRAM and flash memory chips are disposed on and adjacent to one side of the logic chip to reduce the length of the communication circuitry between them. Attached Figure Description

[0024] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0025] Figures 1A to 7 This is a schematic cross-sectional view of a semiconductor structure at an intermediate stage of a semiconductor structure manufacturing method according to some embodiments of the present invention.

[0026] Figure 8This is a schematic diagram illustrating the manufacturing process of a semiconductor structure manufacturing method according to some embodiments of the present invention. Detailed Implementation

[0027] The following detailed description provides examples in conjunction with the accompanying drawings. However, the provided examples are not intended to limit the scope of the invention, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements, producing a device with equivalent functionality, is within the scope of this invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0028] Furthermore, unless otherwise specified, the terms used throughout this specification and claims generally have their ordinary meaning in the context of this art, the disclosure herein, and the specific content. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

[0029] In the embodiments and claims, unless otherwise specified in the text, "a" and "the" may refer to a single or multiple entities. The numbers used in the steps are only for illustrative purposes and are not intended to limit the order or implementation method.

[0030] Secondly, the terms “contains,” “includes,” “has,” “contains,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0031] See Figures 1A to 8 ,in, Figures 1A to 7 This is a cross-sectional schematic diagram of an intermediate stage in a semiconductor structure manufacturing process. Figure 8 This is a schematic diagram of the manufacturing process for semiconductor structure fabrication.

[0032] like Figure 8 As shown, the semiconductor structure manufacturing method 500 includes the following steps. First, in step 510, an active interposer layer 110 is provided, and also see... Figure 1A as well as Figure 1B . Figure 1A This is a cross-sectional schematic diagram of the active intermediary layer 110, and Figure 1B This is a top-down schematic diagram of the active intermediary layer 110.

[0033] In some embodiments, the active interposer layer 110 includes a substrate 112, a first control circuit 111 located in a first control region 101 of the substrate 112, a second control circuit 116 located in a second control region 102 of the substrate 112, and a communication circuit 115 connected between the first control circuit 111 and the second control circuit 116. The first control circuit 111, the second control circuit 116, and the communication circuit 115 are embedded in the substrate 112. Furthermore, a plurality of solder pads 113 are formed on the substrate 112 and located in the first control region 101, and a plurality of solder pads 114 are formed on the substrate 112 and located in the second control region 102.

[0034] In some embodiments, the active interposer 110 further includes a plurality of through-silicon vias (TSVs) 117 formed by a via middle process.

[0035] Step 520: A plurality of first stacked wafers 132 and a plurality of second stacked wafers 142 are vertically stacked on the active interposer layer 110 using a hybrid bonding process, to respectively form a first stacked wafer module 130 vertically located on the first control region 101 and a second stacked wafer module 140 vertically located on the second control region 102. See also... Figure 2 and Figure 3 In addition, the first control circuit 111 is used to control the first stacked chip 132, the second control circuit 116 is used to control the second stacked chip 142, and the communication circuit 115 in the active interposer layer 110 is used to communicate between the first stacked chip 132 and the second stacked chip 142.

[0036] In some embodiments, the hybrid bonding process further includes plasma treatment prior to bonding the first stacked wafer 132, the second stacked wafer 142, and the active interposer 110. Furthermore, the first stacked wafer 132, the second stacked wafer 142, and the active interposer 110 are bonded at a temperature below 400 degrees Celsius, preferably below 300 degrees Celsius. In some embodiments, the bumps and pads of the first stacked wafer 132, the second stacked wafer 142, and the active interposer 110 are bonded at 250 degrees Celsius. In some embodiments, the bumps and pads are formed of copper (Cu), tin-silver (SnAg), gold (Au), and nickel (Ni), all without departing from the spirit and scope of the invention.

[0037] Step 530: The first stacked wafer 132 and the second stacked wafer 142 are molded onto the active interposer layer 110 using molding resin 160, for example, using epoxy resin. See also... Figure 4 .

[0038] Step 540: The molding resin 160 is polished to reduce the thickness of the semiconductor structure 100. Furthermore, in step 550, the back side of the active interposer 110 is processed using a wafer-level backside process, and bumps 150 are formed on the back side of the active interposer 110. See also... Figure 5 .

[0039] In step 560, the semiconductor structure 100 is diced to form a plurality of integrated memory chips. In some embodiments, the first stacked chip 132 is dynamic random access memory (DRAM), and the second stacked chip 142 is NAND flash memory. Therefore, the semiconductor structure 100 is diced into a plurality of integrated memory chips, such as integrated memory chip 230, while also referring to... Figure 6 Each integrated memory chip contains at least one DRAM chip and at least one NAND flash memory chip.

[0040] Therefore, the semiconductor structure 100 includes an active interposer 110, a first stacked wafer module 130, and a second stacked wafer module 140. The active interposer 110 includes a substrate 112, a first control circuit 111 located in a first control region 101 of the substrate 112, a second control circuit 116 located in a second control region 102 of the substrate 112, and a communication circuit 115 connected between the first control circuit 111 and the second control circuit 116. The first stacked wafer module 130 is vertically stacked in the first control region 101 of the active interposer 110, and the second stacked wafer module 140 is vertically stacked in the second control region 102 of the active interposer 110. The first stacked wafer module 130 includes a plurality of first stacked wafers 132 vertically stacked in the first control region 101 of the active interposer 110, and the first stacked wafers are dynamic random access memory (DRAM) wafers. The second stacked chip module 140 includes a plurality of second stacked chips 142 vertically stacked on the second control region 102 of the active interposer layer 110, wherein the second stacked chips are NAND flash memory chips. The active interposer layer 110 includes a plurality of through-silicon vias (TSVs) formed using a via middle process.

[0041] In addition, steps 570 to 600, and also refer to Figure 6In step 570, at least one integrated memory chip 230, formed in steps 510 to 560, and a logic chip 220 are bonded to an inactive interposer 210. Therefore, both the active interposer 110 and the logic chip 220 are bonded to the inactive interposer 210. Furthermore, the inactive interposer 210 does not have active control circuitry or components formed therein.

[0042] Step 580: The integrated memory chip 230 and logic chip 220 are molded onto the non-active interposer layer 210. Step 590: Molding resin 260 is applied. Step 600: The back side of the non-active interposer layer 210 is processed using a wafer-level back-side processing technology, and bumps 250 are formed on the back side of the non-active interposer layer 210.

[0043] In some embodiments, the logic chip 220 is a central processing unit (CPU), a graphics processing unit (GPU), or a field-programmable gate array (FPGA) chip.

[0044] Therefore, the semiconductor structure 200 also includes a non-active interposer 210 and a logic chip 220, while the active interposer 110 and the logic chip 220 are bonded to the non-active interposer 210.

[0045] Further reading Figure 7 In some embodiments, the semiconductor structure 300 includes a passive interposer 310, an integrated memory chip 330, and a logic chip 320. The integrated memory chip 330 and the logic chip 320 are bonded and molded onto the passive interposer 210. Notably, the first stacked chip module 130 and the second stacked chip module 140 of the integrated memory chip 330 are arranged in parallel with the logic chip 220. See also Figure 6 as well as Figure 7 , Figure 7 The integrated memory chip 330 rotates the integrated memory chip 230 by 90 degrees and is bonded to the non-active interposer layer 210.

[0046] In other words, both the first stacked chip module 130 and the second stacked chip module 140 of the integrated memory chip 330 are disposed on and adjacent to one side of the logic chip 220 to reduce the length of the communication circuit between the first stacked chip module 130 and the logic chip 220, and the length of the communication circuit between the second stacked chip module 140 and the logic chip 220. Therefore, there is no second stacked chip module 140 located between the first stacked chip module 130 and the logic chip 220, and there is no first stacked chip module 130 located between the second stacked chip module 140 and the logic chip 220.

[0047] In view of this, the semiconductor structure and semiconductor structure manufacturing method disclosed in this invention, wherein dynamic random access memory (DRAM) and flash memory (NAND) chips are bonded on an active interposer to form an integrated memory chip. Furthermore, the logic chip and the integrated memory chip can be bonded on a non-active interposer, and both the DRAM and flash memory chips are disposed on and adjacent to one side of the logic chip to reduce the length of the communication circuitry between them.

[0048] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Any simple equivalent variations and modifications made in accordance with the claims and description of the invention are still within the scope of this patent. Furthermore, no embodiment or claim of the present invention needs to achieve all the objectives, advantages, or features disclosed in the invention. In addition, the abstract and headings are merely for assisting in patent document searches and are not intended to limit the scope of the invention. Moreover, the terms "first," "second," etc., used in this specification or claims are only used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements.

[0049] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0050] [Symbol Explanation]

[0051] 100: Semiconductor Structure

[0052] 101: First Control Zone

[0053] 102: Second Control Zone

[0054] 110: Active Intermediary Layer

[0055] 111: First control circuit

[0056] 112: Substrate

[0057] 113: Solder pad

[0058] 114: Solder pad

[0059] 115: Communication Circuits

[0060] 116: Second control circuit

[0061] 117: Through-silicon vias

[0062] 130: First stacked chip module

[0063] 132: First stacked wafer

[0064] 140: Second stacked chip module

[0065] 142: Second stacked wafer

[0066] 150: Bump

[0067] 160: Molding resin

[0068] 200: Semiconductor Structure

[0069] 210: Non-active mediation layer

[0070] 220: Logic chip

[0071] 230: Integrated memory chip

[0072] 250: Bump

[0073] 260: Molding resin

[0074] 300: Semiconductor Structure

[0075] 310: Non-active intermediary layer

[0076] 320: Logic chip

[0077] 330: Integrated memory chip

[0078] 500: Semiconductor Structure Manufacturing Methods

[0079] 510~600: Steps.

Claims

1. A semiconductor structure, characterized in that, Include: An active intermediary layer includes a substrate, a first control circuit located in a first control area of ​​the substrate, a second control circuit located in a second control area of ​​the substrate, and a communication circuit connected between the first control circuit and the second control circuit. A first stacked chip module is vertically stacked in the first control area of ​​the active interposer layer; The second stacked chip module is vertically stacked in the second control area of ​​the active interposer layer; A non-active mediation layer, on which the active mediation layer is joined; as well as A logic chip is bonded on the non-active interposer layer. The first stacked chip module and the second stacked chip module are both disposed on and adjacent to one side of the logic chip, and there is no second stacked chip module between the first stacked chip module and the logic chip, and no first stacked chip module between the second stacked chip module and the logic chip, so as to reduce the length of the communication circuit between the first stacked chip module and the logic chip, and the length of the communication circuit between the second stacked chip module and the logic chip.

2. The semiconductor structure according to claim 1, wherein the first stacked wafer module comprises a plurality of first stacked wafers, vertically stacked in the first control region of the active interposer layer.

3. The semiconductor structure of claim 2, wherein the first stacked wafers comprise dynamic random access memory.

4. The semiconductor structure of claim 3, wherein the second stacked wafer module comprises a plurality of second stacked wafers vertically stacked in the second control region of the active interposer layer.

5. The semiconductor structure of claim 4, wherein the second stacked wafers comprise flash memory.

6. The semiconductor structure according to claim 1, wherein the active interposer further comprises a plurality of silicon vias formed by a via intermediate process.

7. The semiconductor structure of claim 1, wherein the logic chip comprises a central processing unit, a graphics chip, or a field-programmable gate array.

8. The semiconductor structure of claim 1, wherein the first stacked wafer module and the second stacked wafer module are configured in parallel with the logic wafer.

9. A method for manufacturing a semiconductor structure, characterized in that, Include: An active intermediary layer is provided, wherein the active intermediary layer includes a substrate, a first control circuit located in a first control area of ​​the substrate, a second control circuit located in a second control area of ​​the substrate, and a communication circuit connected between the first control circuit and the second control circuit. The first stacked wafer module is vertically bonded to the first control area of ​​the active interposer layer; The second stacked wafer module is vertically bonded to the second control area of ​​the active interposer layer; The active interposer layer is cut to form a plurality of integrated memory chips; as well as A logic chip and at least one integrated memory chip are bonded on a non-active interposer layer, wherein the first stacked chip module and the second stacked chip module are both disposed on and adjacent to one side of the logic chip, and no second stacked chip module is located between the first stacked chip module and the logic chip, and no first stacked chip module is located between the second stacked chip module and the logic chip, so as to reduce the length of the communication circuit between the first stacked chip module and the logic chip, and the length of the communication circuit between the second stacked chip module and the logic chip.

10. The semiconductor structure manufacturing method according to claim 9, wherein, Also includes: A plurality of first stacked wafers are vertically stacked in the first control area of ​​the active interposer layer to form the first stacked wafer module.

11. The semiconductor structure manufacturing method of claim 10, wherein the first stacked wafers comprise dynamic random access memory.

12. The semiconductor structure manufacturing method according to claim 11, wherein, Also includes: A plurality of second stacked wafers are vertically stacked in the second control area of ​​the active interposer layer to form the second stacked wafer module.

13. The semiconductor structure manufacturing method of claim 12, wherein the second stacked wafer comprises flash memory.

14. The semiconductor structure manufacturing method according to claim 9, wherein the active interposer further comprises a plurality of silicon vias formed by a through-hole intermediate process.

15. The semiconductor structure manufacturing method according to claim 9, wherein the logic wafer comprises a central processing unit, a graphics chip, or a field-programmable gate array.

16. The semiconductor structure manufacturing method of claim 9, wherein the first stacked wafer module and the second stacked wafer module are configured in parallel with the logic wafer.

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