A gallium nitride power circuit module package structure

Abstract

The application discloses a kind of cascade gallium nitride power circuit module package structures, comprising: two double-sided copper-clad ceramic substrates forming package body, at least one first cascade gallium nitride power circuit and at least one second cascade gallium nitride power circuit;First cascade gallium nitride power circuit is connected with the pad and copper column of two double-sided copper-clad ceramic substrates using silver sintering;Second cascade gallium nitride power circuit is connected with the pad and copper column of two double-sided copper-clad ceramic substrates using silver sintering.The gallium nitride chip of the present application, MOSFET chip is cooled by double-sided copper-clad ceramic substrate at top and bottom, and the performance and life of module can be improved.The present application is interconnected by pad, copper column, MOSFET chip and gallium nitride chip, reduces a series of parasitic parameters caused by aluminum bonding wire interconnection, reduces the power consumption of device, and improves the reliability of device.

Description

Technical Field

[0001] This invention belongs to the field of gallium nitride power device technology, specifically relating to a cascaded gallium nitride power circuit module packaging structure. Background Technology

[0002] In recent years, gallium nitride (GaN) power devices have attracted widespread attention in high-frequency, high-efficiency, and high-power-density applications such as new energy power generation and electric vehicles due to their advantages of wide bandgap, high electron mobility, and high electron velocity. However, the relatively low current rating of existing gallium nitride high electron mobility transistors (HEMTs) limits their use in high-power applications. Parallel connection of GaN Cascode device modules can improve current handling capabilities, meeting the development demands for high power density, high frequency, and integration.

[0003] Traditional GaN cascode device packaging presents two main problems. First, conventional packaging connects the drain and source of the Si MOSFET to the source and gate of the depletion-mode GaN HEMT via wire bonding. Wire bonding introduces significant parasitic parameters, and the asymmetry of these parameters between parallel GaN devices can lead to current imbalances and loop currents. When the power device is turned off, the parasitic inductance can cause turn-off voltage spikes and oscillations, increasing device losses and potentially even causing avalanche breakdown failure of the low-voltage Si MOSFET. Second, traditional packaging relies on single-sided heat dissipation. The GaN chip is soldered onto a copper-clad substrate, and heat is dissipated through the substrate. However, the top of the device is constrained by the molding compound, resulting in high thermal resistance and poor heat dissipation. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a cascaded gallium nitride power circuit module packaging structure. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A cascaded gallium nitride power circuit module packaging structure includes: two double-sided copper-clad ceramic substrates forming a package, at least one first cascaded gallium nitride power circuit, and at least one second cascaded gallium nitride power circuit;

[0006] The two double-sided copper-clad ceramic substrates have their surfaces facing each other;

[0007] The first cascaded gallium nitride power circuit includes: four depletion-mode first gallium nitride chips and one enhancement-mode first MOSFET chip;

[0008] The first cascaded gallium nitride power circuit is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering.

[0009] The second cascaded gallium nitride power circuit includes four depletion-mode second gallium nitride chips and one enhancement-mode second MOSFET chip;

[0010] The second cascaded gallium nitride power circuit is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering.

[0011] The pads of the two double-sided copper-clad ceramic substrates are connected by the copper pillars.

[0012] In one embodiment of the present invention, the four first gallium nitride chips are connected in parallel and interconnected with the first MOSFET chip;

[0013] The first gallium nitride chip is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering.

[0014] The first MOSFET chip is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering.

[0015] The four second gallium nitride chips are connected in parallel and interconnected with the second MOSFET chip;

[0016] The second gallium nitride chip is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering.

[0017] The second MOSFET chip is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering.

[0018] In one embodiment of the present invention, the two double-sided copper-clad ceramic substrates are a first double-sided copper-clad ceramic substrate and a second double-sided copper-clad ceramic substrate; the copper pillar includes: a first sub-copper pillar and a second sub-copper pillar;

[0019] The substrate of the first gallium nitride chip and the source and gate of the first MOSFET chip are all connected to the pads of the first double-sided copper-clad ceramic substrate.

[0020] The source, gate, and drain of the first gallium nitride chip, as well as the drain of the first MOSFET chip, are all connected to the pads of the second double-sided copper-clad ceramic substrate.

[0021] The first copper pillar is connected to the pads of the first double-sided copper-clad ceramic substrate and the pads of the second double-sided copper-clad ceramic substrate.

[0022] The second copper pillar is connected to the pads of the first double-sided copper-clad ceramic substrate and the pads of the second double-sided copper-clad ceramic substrate.

[0023] In one embodiment of the present invention, the pads of the first double-sided copper-clad ceramic substrate include: a first pad, a third pad, and a fourth pad.

[0024] The substrate of the first gallium nitride chip is connected to the first pad;

[0025] The source of the first MOSFET chip is connected to the first pad, and the gate of the first MOSFET chip is connected to the fourth pad.

[0026] The third pad is connected to the first sub-copper pillar, and the first pad is connected to the second sub-copper pillar.

[0027] In one embodiment of the present invention, the pads of the second double-sided copper-clad ceramic substrate include: a sixth pad, an eighth pad, a tenth pad, an eleventh pad, and a twelfth pad.

[0028] The gates of the four first gallium nitride chips are connected in sequence and connected to the tenth pad, the eleventh pad and the twelfth pad;

[0029] The source of the first gallium nitride chip and the drain of the first MOSFET chip are both connected to the sixth pad;

[0030] The drain of the first gallium nitride chip is connected to the eighth pad;

[0031] The tenth pad, the eleventh pad, and the twelfth pad are connected to the second sub-copper pillar, and the eighth pad is connected to the first sub-copper pillar.

[0032] In one embodiment of the present invention, the copper pillar further includes a third sub-copper pillar and a fourth sub-copper pillar;

[0033] The substrate of the second gallium nitride chip and the source and gate of the second MOSFET chip are all connected to the pads of the second double-sided copper-clad ceramic substrate.

[0034] The source, gate, and drain of the second gallium nitride chip, as well as the drain of the second MOSFET chip, are all connected to the pads of the second double-sided copper-clad ceramic substrate.

[0035] The third copper pillar is connected to the pads of the first double-sided copper-clad ceramic substrate and the pads of the second double-sided copper-clad ceramic substrate.

[0036] The fourth copper pillar is connected to the pads of the first double-sided copper-clad ceramic substrate and the pads of the second double-sided copper-clad ceramic substrate.

[0037] In one embodiment of the present invention, the pads of the first double-sided copper-clad ceramic substrate further include: a second pad and a fifth pad;

[0038] The substrate of the second gallium nitride chip is connected to the second pad;

[0039] The source of the second MOSFET chip is connected to the second pad, and the gate of the second MOSFET chip is connected to the fifth pad;

[0040] The third sub-copper pillar is connected to the first pad, and the second pad is connected to the fourth sub-copper pillar.

[0041] In one embodiment of the present invention, the pads of the second double-sided copper-clad ceramic substrate further include: a seventh pad, a ninth pad, a thirteenth pad, a fourteenth pad, and a fifteenth pad;

[0042] The gates of the four second gallium nitride chips are connected in sequence and connected to the thirteenth, fourteenth, and fifteenth pads;

[0043] The source of the second gallium nitride chip and the drain of the second MOSFET chip are both connected to the seventh pad;

[0044] The drain of the second gallium nitride chip is connected to the ninth pad;

[0045] The thirteenth, fourteenth, and fifteenth pads are connected to the fourth sub-copper pillar, and the ninth pad is connected to the third sub-copper pillar.

[0046] In one embodiment of the present invention, the number of the first cascaded gallium nitride power circuit is one, and the number of the second cascaded gallium nitride power circuit is one.

[0047] In one embodiment of the present invention, the substrate of the first gallium nitride chip and the source electrode of the first MOSFET chip are at the same potential;

[0048] The substrate of the second gallium nitride chip is at the same potential as the source electrode of the second MOSFET chip.

[0049] The beneficial effects of this invention are:

[0050] 1. The present invention uses double-sided copper-clad ceramic substrates at the bottom and top, respectively, and directly connects them to the power circuit. The gallium nitride chip and MOSFET chip are cooled through the double-sided copper-clad ceramic substrates at the top and bottom, which can realize double-sided heat dissipation at the top and bottom of the module, reduce the efficiency reduction and device degradation caused by high temperature operation of the device, and improve the performance and life of the module.

[0051] 2. This invention uses pads and copper pillars to interconnect MOSFET chips and gallium nitride chips. Direct interconnection via pads and copper pillars reduces a series of parasitic parameters caused by aluminum bonding wire interconnection, lowers device power consumption, improves device reliability, and further enhances system power density in high-frequency applications.

[0052] 3. This invention connects the source of the MOSFET chip and the substrate of the gallium nitride chip to the same pad using silver sintering, avoiding the influence of floating potential of the GaN chip substrate. After connecting the source of the MOSFET chip and the substrate of the gallium nitride chip to the same potential, the trapped electrons in the substrate can be effectively reduced in the off state, and the release of trapped electrons in the substrate can be reduced in the on state, resulting in a more stable dynamic on-resistance of the device.

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0054] Figure 1 A three-dimensional structural diagram of a cascaded gallium nitride power circuit module packaging structure provided in an embodiment of the present invention;

[0055] Figure 2 A top view schematic diagram of a cascaded gallium nitride power circuit module packaging structure provided in an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the circuit arrangement on the first double-sided copper-clad ceramic substrate provided in an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the circuit arrangement on the second double-sided copper-clad ceramic substrate provided in an embodiment of the present invention;

[0058] Figure 5 A circuit diagram of a half-bridge module provided in an embodiment of the present invention;

[0059] Figure 6 This is a schematic diagram of the packaging structure of a half-bridge module provided in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram of the process for packaging a cascaded gallium nitride half-bridge module according to an embodiment of the present invention.

[0061] Explanation of reference numerals in the attached figures:

[0062] 100 - First double-sided copper-clad ceramic substrate; 200 - Second double-sided copper-clad ceramic substrate;

[0063] 110 - First gallium nitride chip; 111 - Gate of the first gallium nitride chip; 112 - Source of the first gallium nitride chip; 113 - Drain of the first gallium nitride chip; 120 - First MOSFET chip; 121 - Source of the first MOSFET chip; 122 - Gate of the first MOSFET chip; 123 - Drain of the first MOSFET chip;

[0064] 210 - Second gallium nitride chip; 211 - Gate of the second gallium nitride chip; 212 - Source of the second gallium nitride chip; 213 - Drain of the second gallium nitride chip; 220 - Second MOSFET chip; 221 - Source of the second MOSFET chip; 222 - Gate of the second MOSFET chip; 223 - Drain of the second MOSFET chip;

[0065] a - First copper pillar; b - Second copper pillar; c - Third copper pillar; d - Fourth copper pillar;

[0066] 1-First pad; 2-Second pad; 3-Third pad; 4-Fourth pad; 5-Fifth pad; 6-Sixth pad; 7-Seventh pad; 8-Eighth pad; 9-Ninth pad; 10-Tenth pad; 11-Eleventh pad; 12-Twelfth pad; 13-Thirteenth pad; 14-Fourteenth pad; 15-Fifteenth pad. Detailed Implementation

[0067] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0068] Example 1

[0069] like Figure 1 As shown, a cascaded gallium nitride power circuit module packaging structure includes: two double-sided copper-clad ceramic substrates forming the package, at least one first cascaded gallium nitride power circuit and at least one second cascaded gallium nitride power circuit; the surfaces of the two double-sided copper-clad ceramic substrates are arranged opposite to each other.

[0070] Each first cascaded gallium nitride power circuit includes: four depletion-mode first gallium nitride chips 110 and one enhancement-mode first MOSFET chip 120; the four first gallium nitride chips 110 are connected in parallel and interconnected with the first MOSFET chip 120; the first gallium nitride chips 110 are connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering; the first MOSFET chip 120 is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering.

[0071] Each second-cascaded gallium nitride power circuit includes four depletion-mode second gallium nitride chips 210 and one enhancement-mode second MOSFET chip 220; the four depletion-mode first gallium nitride chips 110 and the four depletion-mode second gallium nitride chips 210 are the same chip, and the enhancement-mode first MOSFET chip 120 and the enhancement-mode second MOSFET chip 220 are the same chip.

[0072] Four second gallium nitride chips 210 are connected in parallel and interconnected with the second MOSFET chip 220; the second gallium nitride chips 210 are connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering; the second MOSFET chip 220 is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering.

[0073] In this embodiment, double-sided copper-clad ceramic substrates are used at the bottom and top, respectively, and are directly connected to the power circuit. The gallium nitride (GaN) chip and MOSFET chip are cooled through the double-sided copper-clad ceramic substrates at the top and bottom, achieving double-sided heat dissipation at the top and bottom of the module. This reduces efficiency reduction and device degradation caused by high-temperature operation, improving module performance and lifespan. Simultaneously, the MOSFET chip and GaN chip are interconnected via pads and copper pillars. This direct interconnection reduces a series of parasitic parameters introduced by aluminum bonding wire interconnection, lowering device power consumption, improving device reliability, and further increasing system power density in high-frequency applications.

[0074] The package is a fully filled plastic encapsulation process used to encapsulate the soldered circuit modules. There can be multiple first-stage gallium nitride power circuits. The ceramic material of the double-sided copper-clad ceramic substrate is alumina, and the pads are copper sheets printed on the double-sided copper-clad ceramic substrate.

[0075] Specifically, the two double-sided copper-clad ceramic substrates are a first double-sided copper-clad ceramic substrate 100 and a second double-sided copper-clad ceramic substrate 200; the copper pillars include: a first sub-copper pillar a and a second sub-copper pillar b;

[0076] The substrate of the first gallium nitride chip 110 and the source 121 and gate of the first MOSFET chip are all connected to the pads of the first double-sided copper-clad ceramic substrate 100; the source 112, gate and drain of the first gallium nitride chip and the drain 123 of the first MOSFET chip are all connected to the pads of the second double-sided copper-clad ceramic substrate 200.

[0077] The first sub-copper pillar a is connected to the pads of the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200; the second sub-copper pillar b is connected to the pads of the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200.

[0078] Furthermore, the copper pillar also includes a third sub-copper pillar c and a fourth sub-copper pillar d;

[0079] The substrate of the second gallium nitride chip 210 and the source 221 and gate of the second MOSFET chip are all connected to the pads of the second double-sided copper-clad ceramic substrate 200; the source 212, gate and drain of the second gallium nitride chip and the drain 223 of the second MOSFET chip are all connected to the pads of the second double-sided copper-clad ceramic substrate 200.

[0080] The third copper pillar c is connected to the pads of the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200; the fourth copper pillar d is connected to the pads of the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200.

[0081] The first double-sided copper-clad ceramic substrate 100 is the bottom of the packaging structure, and the second double-sided copper-clad ceramic substrate 200 is the top of the packaging structure.

[0082] Preferably, when the number of the first cascaded gallium nitride power circuit is one and the number of the second cascaded gallium nitride power circuit is one, eight gallium nitride chips and two MOSFET chips are integrated in the same package to form a gallium nitride half-bridge module composed of two cascaded gallium nitride power circuits. The gallium nitride half-bridge module is provided with bottom and top heat dissipation through a double-sided copper-clad ceramic substrate to reduce the circuit parasitic parameters caused by interconnection.

[0083] Example 2

[0084] like Figure 3 and Figure 4 As shown, based on Embodiment 1, this embodiment further defines the pads of the first double-sided copper-clad ceramic substrate 100, including: first pad 1, third pad 3 and fourth pad 4;

[0085] The substrate of the first gallium nitride chip 110 is connected to the first pad 1;

[0086] The source 121 of the first MOSFET chip is connected to the first pad 1, and the gate 122 of the first MOSFET chip is connected to the fourth pad 4.

[0087] The third pad 3 is connected to the first sub-copper pillar a, and the first pad 1 is connected to the second sub-copper pillar b.

[0088] In this embodiment, the chip and the pad are connected by silver sintering, and the sub-copper pillar and the pad are connected by silver sintering. The source 121 of the first MOSFET chip and the substrate of the first gallium nitride chip 110 are connected to the first pad 1. By connecting the source of the MOSFET chip and the substrate of the gallium nitride chip to the same potential, the influence of the floating potential of the GaN chip substrate is avoided. In the off state, the trapped electrons in the substrate can be effectively reduced. In the on state, the release of trapped electrons in the substrate can also be reduced, and the device has a more stable dynamic on-resistance.

[0089] The first gallium nitride chip 110 has two gates at one end and a source between the two gates, and a drain at the other end. The first MOSFET chip 120 has a drain on one side and a source and a gate on the other side. The four first gallium nitride chips 110 are arranged in two rows and two columns, adjacent to each other. The first MOSFET chip 120 is located at the edge of the first pad 1. The third pad 3 and the fourth pad 4 are located on opposite sides of the first pad 1.

[0090] Furthermore, the pads of the second double-sided copper-clad ceramic substrate 200 include: the sixth pad 6, the eighth pad 8, the tenth pad 10, the eleventh pad 11, and the twelfth pad 12.

[0091] The gates 111 of the four first gallium nitride chips are connected in sequence and connected to the tenth pad 10, the eleventh pad 11 and the twelfth pad 12. Specifically, the gates of the four first gallium nitride chips 110 are connected in pairs. One gate of each first gallium nitride chip 110 is connected to the eleventh pad 11, and the remaining two gates located in the same row are connected to one pad. Two gates are connected to the tenth pad 10, and the other two gates are connected to the twelfth pad 12.

[0092] The source 112 of the four first gallium nitride chips and the drain 123 of the first MOSFET chip are all connected to the sixth pad 6; the drain 113 of the four first gallium nitride chips are all connected to the eighth pad 8.

[0093] The tenth pad 10, the eleventh pad 11 and the twelfth pad 12 are connected to the second sub-copper pillar b, and the eighth pad 8 is connected to the first sub-copper pillar a.

[0094] like Figure 3 and Figure 4 As shown in the figure, there is one first-stage gallium nitride power circuit and one second-stage gallium nitride power circuit. Furthermore, the pads of the first double-sided copper-clad ceramic substrate 100 also include: a second pad 2 and a fifth pad 5.

[0095] The substrate of the second gallium nitride chip 210 is connected to the second pad 2; the source 221 of the second MOSFET chip is connected to the second pad 2, and the gate 222 of the second MOSFET chip is connected to the fifth pad 5; the third sub-copper pillar c is connected to the first pad 1, and the second pad 2 is connected to the fourth sub-copper pillar d.

[0096] The four depletion-mode second gallium nitride (GaN) chips 210 and the four depletion-mode first GaN chips 110 are arranged in the same position. The first MOSFET chip 120 and the second MOSFET chip 220 are arranged in the same way. The four second GaN chips 210 are arranged in two rows and two columns, adjacent to each other. The second MOSFET chip 220 is located at the edge of the second pad 2. The fourth pad 4 and the fifth pad 5 are located on the same side.

[0097] Furthermore, the pads of the second double-sided copper-clad ceramic substrate 200 also include: the seventh pad 7, the ninth pad 9, the thirteenth pad 13, the fourteenth pad 14, and the fifteenth pad 15.

[0098] The gates 211 of the four second gallium nitride chips are connected in sequence and connected to the thirteenth pad 13, the fourteenth pad 14 and the fifteenth pad 15. Specifically, the gates of the four second gallium nitride chips 210 are connected in pairs. One gate of each second gallium nitride chip 210 is connected to the fourteenth pad 14, and the remaining two gates located in the same row are connected to one pad. Two gates are connected to the thirteenth pad 13, and the other two gates are connected to the fifteenth pad 15.

[0099] The sources 212 of the four second gallium nitride chips and the drains 223 of the second MOSFET chip are all connected to the seventh pad 7; the drains 213 of the four second gallium nitride chips are connected to the ninth pad 9.

[0100] The thirteenth pad 13, the fourteenth pad 14, and the fifteenth pad 15 are connected to the fourth sub-copper pillar d, and the ninth pad 9 is connected to the third sub-copper pillar c.

[0101] Furthermore, such as Figure 2 and Figure 5 As shown, the half-bridge module in this embodiment has seven pin ports: Drain (Vdc+), Midpoint, Source (Vdc-), Gate1, Kelvin Source1, Gate2, and Kelvin Source2. Pin Drain (Vdc+) is interconnected with the third pad 3, pin Midpoint with the first pad 1, pin Source (Vdc-) with the second pad 2, pin Kelvin Source1 with the first pad 1, pin Gate1 with the fourth pad 4, pin Kelvin Source2 with the second pad 2, and pin Gate2 with the fifth pad 5.

[0102] Preferred, such as Figure 6 As shown, heat sinks can be added to the top or bottom surface of the above-mentioned package (the outer surfaces of the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200) to further improve the heat dissipation effect.

[0103] Example 3

[0104] like Figure 7 As shown, this embodiment of the invention also provides a packaging method for a cascaded gallium nitride half-bridge module, used to fabricate a half-bridge module including the chip of Embodiment 2, comprising the following steps:

[0105] Step 1: Print the first double-sided copper-clad ceramic substrate 100 and the second double-sided copper-clad ceramic substrate 200 according to the pad structure of Embodiment 3.

[0106] Step two, chip mounting. Nano silver solder paste is used as the solder. The individual chips are connected to the first double-sided copper-clad ceramic substrate 100 using a silver sintering process. Compared with traditional solder, silver sintering significantly improves mechanical strength and density. Furthermore, because it is a solid-phase connection, it forms a dense connection layer with interatomic diffusion. Therefore, its electrical and thermal conductivity efficiency and performance are significantly improved compared to solder.

[0107] Step 3, full-fill plastic encapsulation process, using thermally conductive epoxy resin material to encapsulate the package from Step 2.

[0108] Step four, laser drilling: Laser drilling is used to cut the epoxy resin material to make electrical connections.

[0109] Step 5: Connect the printed second double-sided copper-clad ceramic substrate 200 using a silver sintering process.

[0110] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0111] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0112] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0113] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0114] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0115] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A cascaded gallium nitride power circuit module packaging structure, characterized in that, include: The package consists of two double-sided copper-clad ceramic substrates, at least one first-cascaded gallium nitride power circuit, and at least one second-cascaded gallium nitride power circuit. The two double-sided copper-clad ceramic substrates have their surfaces facing each other; The first cascaded gallium nitride power circuit includes: four depletion-mode first gallium nitride chips (110) and one enhancement-mode first MOSFET chip (120); The first cascaded gallium nitride power circuit is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering. The second cascaded gallium nitride power circuit includes four depletion-mode second gallium nitride chips (210) and one enhancement-mode second MOSFET chip (220); The second cascaded gallium nitride power circuit is connected to the pads and copper pillars of the two double-sided copper-clad ceramic substrates by silver sintering. The pads of the two double-sided copper-clad ceramic substrates are connected by the copper pillars.

2. The cascaded gallium nitride power circuit module packaging structure according to claim 1, characterized in that, The four first gallium nitride chips (110) are connected in parallel and interconnected with the first MOSFET chip (120); The first gallium nitride chip (110) is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering; The first MOSFET chip (120) is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering; The four second gallium nitride chips (210) are connected in parallel and interconnected with the second MOSFET chip (220); The second gallium nitride chip (210) is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering; The second MOSFET chip (220) is connected to the pads and copper pillars of two double-sided copper-clad ceramic substrates by silver sintering.

3. The cascaded gallium nitride power circuit module packaging structure according to claim 1, characterized in that, The two double-sided copper-clad ceramic substrates are a first double-sided copper-clad ceramic substrate (100) and a second double-sided copper-clad ceramic substrate (200); the copper pillars include: a first sub-copper pillar (a) and a second sub-copper pillar (b); The substrate of the first gallium nitride chip (110) and the source (121) and gate of the first MOSFET chip are all connected to the pads of the first double-sided copper-clad ceramic substrate (100). The source (112), gate, and drain of the first gallium nitride chip, as well as the drain (123) of the first MOSFET chip, are all connected to the pads of the second double-sided copper-clad ceramic substrate (200). The first sub-copper pillar (a) is connected to the pads of the first double-sided copper-clad ceramic substrate (100) and the pads of the second double-sided copper-clad ceramic substrate (200); The second sub-copper pillar (b) is connected to the pads of the first double-sided copper-clad ceramic substrate (100) and the pads of the second double-sided copper-clad ceramic substrate (200).

4. The cascaded gallium nitride power circuit module packaging structure according to claim 3, characterized in that, The pads of the first double-sided copper-clad ceramic substrate (100) include: a first pad (1), a third pad (3) and a fourth pad (4); The substrate of the first gallium nitride chip (110) is connected to the first pad (1); The source (121) of the first MOSFET chip is connected to the first pad (1), and the gate (122) of the first MOSFET chip is connected to the fourth pad (4). The third pad (3) is connected to the first sub-copper pillar (a), and the first pad (1) is connected to the second sub-copper pillar (b).

5. The cascaded gallium nitride power circuit module packaging structure according to claim 4, characterized in that, The pads of the second double-sided copper-clad ceramic substrate (200) include: a sixth pad (6), an eighth pad (8), a tenth pad (10), an eleventh pad (11), and a twelfth pad (12); The gates (111) of the four first gallium nitride chips are connected in sequence and connected to the tenth pad (10), the eleventh pad (11) and the twelfth pad (12); The source (112) of the first gallium nitride chip and the drain (123) of the first MOSFET chip are both connected to the sixth pad (6); The drain (113) of the first gallium nitride chip is connected to the eighth pad (8); The tenth pad (10), the eleventh pad (11) and the twelfth pad (12) are connected to the second sub-copper pillar (b), and the eighth pad (8) is connected to the first sub-copper pillar (a).

6. The cascaded gallium nitride power circuit module packaging structure according to claim 3, characterized in that, The copper pillar also includes a third sub-copper pillar (c) and a fourth sub-copper pillar (d); The substrate of the second gallium nitride chip (210) and the source (221) and gate of the second MOSFET chip are all connected to the pads of the second double-sided copper-clad ceramic substrate (200); The source (212), gate, and drain of the second gallium nitride chip, as well as the drain (223) of the second MOSFET chip, are all connected to the pads of the second double-sided copper-clad ceramic substrate (200). The third sub-copper pillar (c) is connected to the pads of the first double-sided copper-clad ceramic substrate (100) and the pads of the second double-sided copper-clad ceramic substrate (200); The fourth copper pillar (d) is connected to the pads of the first double-sided copper-clad ceramic substrate (100) and the pads of the second double-sided copper-clad ceramic substrate (200).

7. The cascaded gallium nitride power circuit module packaging structure according to claim 6, characterized in that, The pads of the first double-sided copper-clad ceramic substrate (100) further include: a second pad (2) and a fifth pad (5); The substrate of the second gallium nitride chip (210) is connected to the second pad (2); The source (221) of the second MOSFET chip is connected to the second pad (2), and the gate (222) of the second MOSFET chip is connected to the fifth pad (5); The third sub-copper pillar (c) is connected to the first pad (1) of the first double-sided copper-clad ceramic substrate (100), and the second pad (2) is connected to the fourth sub-copper pillar (d).

8. The cascaded gallium nitride power circuit module packaging structure according to claim 7, characterized in that, The pads of the second double-sided copper-clad ceramic substrate (200) also include: the seventh pad (7), the ninth pad (9), the thirteenth pad (13), the fourteenth pad (14), and the fifteenth pad (15); The gates (211) of the four second gallium nitride chips are connected in sequence and connected to the thirteenth pad (13), the fourteenth pad (14) and the fifteenth pad (15); The source (212) of the second gallium nitride chip and the drain (223) of the second MOSFET chip are both connected to the seventh pad (7); The drain (213) of the second gallium nitride chip is connected to the ninth pad (9); The thirteenth pad (13), the fourteenth pad (14), and the fifteenth pad (15) are connected to the fourth sub-copper pillar (d), and the ninth pad (9) is connected to the third sub-copper pillar (c).

9. The cascaded gallium nitride power circuit module packaging structure according to claim 1, characterized in that, The number of the first cascaded gallium nitride power circuit is one, and the number of the second cascaded gallium nitride power circuit is one.

10. The cascaded gallium nitride power circuit module packaging structure according to claim 1, characterized in that, The substrate of the first gallium nitride chip (110) and the source electrode of the first MOSFET chip (120) are at the same potential; The substrate of the second gallium nitride chip (210) and the source electrode of the second MOSFET chip (220) are at the same potential.

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