Semiconductor structure layout and semiconductor structure

Abstract

The application provides a semiconductor structure layout and a semiconductor structure. In the semiconductor structure layout, at least two first contact hole patterns are provided, and the first contact hole patterns are connected in parallel. When a defect occurs in one of the first contact hole patterns, the remaining first contact hole patterns can still be used, thereby greatly improving the reliability of the semiconductor structure. Similarly, at least two second contact hole patterns and at least two third contact hole patterns are provided, and the second contact hole patterns and the third contact hole patterns are connected in parallel, thereby greatly improving the reliability of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a semiconductor structure layout and semiconductor structure. Background Technology

[0002] As microprocessor design grows larger, memory occupies a significant portion of the chip area. Furthermore, with advancements in manufacturing processes, the proportion of memory within the chip will continue to increase. Therefore, designing high-density memory can reduce chip area to some extent, thereby lowering costs. However, with increasing memory density, existing semiconductor architectures suffer from low reliability and cannot meet the demands. Summary of the Invention

[0003] This application provides a semiconductor layout and semiconductor structure that can improve the reliability of the semiconductor structure.

[0004] One embodiment of this application provides a semiconductor structure layout, comprising: a first active region pattern; a first gate pattern, a second gate pattern, a third gate pattern, and a fourth gate pattern, spaced apart along a first direction and extending along a second direction, and overlapping the first active region pattern; a first connecting pattern for connecting the second gate pattern and the third gate pattern in parallel; a second connecting pattern for connecting the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel, disposed on the side of the first gate pattern away from the second gate pattern, and each first contact hole pattern overlapping the first active region pattern; at least two second contact hole patterns arranged in parallel, disposed between the second gate pattern and the third gate pattern, and each second contact hole pattern overlapping the first active region pattern; at least two third contact hole patterns arranged in parallel, disposed on the side of the fourth gate pattern away from the third gate pattern, and each third contact hole pattern overlapping the first active region pattern.

[0005] In one embodiment, the first contact hole pattern, the second contact hole pattern, and the third contact hole pattern are all spaced apart along the second direction.

[0006] In one embodiment, in the second direction, the first connecting pattern and the second connecting pattern are respectively disposed on both sides of the first active region pattern.

[0007] In one embodiment, a fourth contact hole pattern is also included, wherein at least two parallel fourth contact hole patterns overlap with the first connection pattern.

[0008] In one embodiment, the two fourth contact hole patterns are respectively disposed at one end of the second gate pattern and the third gate pattern.

[0009] In one embodiment, a fifth contact hole pattern is also included, wherein at least two parallel fifth contact hole patterns overlap with the second connection pattern.

[0010] In one embodiment, the two fifth contact hole patterns are respectively disposed at one end of the first gate pattern and the fourth gate pattern.

[0011] In one embodiment, it further includes: a second active region pattern, which is spaced apart from the first active region pattern in the second direction; a fifth gate pattern and a sixth gate pattern, which are spaced apart along the first direction and both extend along the second direction and overlap with the second active region pattern; the second connecting pattern is also used to connect the fifth gate pattern and the sixth gate pattern in parallel.

[0012] In one embodiment, in the second direction, the third gate pattern is spaced apart from the fifth gate pattern, and the fourth gate pattern is spaced apart from the sixth gate pattern.

[0013] In one embodiment, the method further includes: at least two parallel sixth contact hole patterns disposed on the side of the fifth gate pattern away from the sixth gate pattern and overlapping with the second active region pattern; at least two parallel seventh contact hole patterns disposed between the fifth gate pattern and the sixth gate pattern and overlapping with the second active region pattern; and at least two parallel eighth contact hole patterns disposed on the side of the sixth gate pattern away from the fifth gate pattern and overlapping with the second active region pattern.

[0014] In one embodiment, the sixth contact hole pattern is spaced apart along the second direction, the seventh contact hole pattern is spaced apart along the second direction, and the eighth contact hole pattern is spaced apart along the second direction. In the second direction, the sixth contact hole pattern and the seventh contact hole pattern are staggered at a predetermined distance, and the seventh contact hole pattern and the eighth contact hole pattern are staggered at a predetermined distance.

[0015] In one embodiment, it further includes: a seventh gate pattern and an eighth gate pattern, which are spaced apart along the first direction and both extend along the second direction and overlap with the second active region pattern. In the second direction, the first gate pattern and the seventh gate pattern are spaced apart, and the second gate pattern and the eighth gate pattern are spaced apart; a third connecting pattern is connected to the seventh gate pattern; and a fourth connecting pattern is connected to the eighth gate pattern.

[0016] In one embodiment, the system further includes: at least two parallel ninth contact hole patterns disposed on the side of the seventh gate pattern away from the eighth gate pattern and overlapping with the second active region pattern; and at least two parallel tenth contact hole patterns disposed between the seventh gate pattern and the eighth gate pattern and overlapping with the second active region pattern.

[0017] In one embodiment, the system further includes: a third active region pattern, which is spaced apart from the second active region pattern in the second direction; a ninth gate pattern, a tenth gate pattern, an eleventh gate pattern, and a twelfth gate pattern, which are spaced apart along the first direction and extend along the second direction, and overlap with the third active region pattern; the fourth connecting pattern is also used to connect the ninth gate pattern, the tenth gate pattern, the eleventh gate pattern, and the twelfth gate pattern in parallel.

[0018] In one embodiment, the method further includes: at least one eleventh contact hole pattern disposed on the side of the ninth gate pattern away from the tenth gate pattern and overlapping with the third active region pattern; at least two parallel twelfth contact hole patterns disposed between the ninth gate pattern and the tenth gate pattern and overlapping with the third active region pattern; at least one thirteenth contact hole pattern disposed between the tenth gate pattern and the eleventh gate pattern and overlapping with the third active region pattern; at least two parallel fourteenth contact hole patterns disposed between the eleventh gate pattern and the twelfth gate pattern and overlapping with the third active region pattern; and at least one fifteenth contact hole pattern disposed on the side of the twelfth gate pattern away from the eleventh gate pattern and overlapping with the third active region pattern.

[0019] In one embodiment, the number of the twelfth contact hole patterns is greater than the number of the eleventh contact hole patterns.

[0020] In one embodiment, the number of the fourteenth contact hole patterns is greater than the number of the fifteenth contact hole patterns.

[0021] Another aspect of this application embodiment provides a semiconductor structure fabricated according to the above-described semiconductor layout.

[0022] In the semiconductor structure layout provided in this application embodiment, at least two first contact hole patterns are provided, and these first contact hole patterns are arranged in parallel. When one of the first contact hole patterns is defective, the remaining first contact hole patterns can still be used, greatly improving the reliability of the semiconductor structure. Similarly, at least two second and three contact hole patterns are provided, and they are arranged in parallel, which greatly improves the reliability of the semiconductor structure. Attached Figure Description

[0023] Figure 1A This is a schematic diagram of a dynamic random access memory.

[0024] Figure 1B yes Figure 1A A magnified view of the portion shown in the dashed box A;

[0025] Figure 1C This is a schematic diagram of the read / write conversion circuit unit;

[0026] Figure 2 This is a semiconductor structure layout provided in the first embodiment of this application;

[0027] Figure 3 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the first embodiment of this application;

[0028] Figure 4 This is a semiconductor structure layout provided in the second embodiment of this application;

[0029] Figure 5 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the second embodiment of this application;

[0030] Figure 6 This is a semiconductor structure layout provided in the third embodiment of this application;

[0031] Figure 7 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the third embodiment of this application. Detailed Implementation

[0032] The following detailed description, with reference to the accompanying drawings, illustrates the semiconductor structure layout and embodiments thereof provided in this application.

[0033] Please see Figure 1A This is a schematic diagram of a dynamic random access memory (DRAM). The DRAM includes a memory array, a sensitive amplifier array Fsa, a row decoding and control circuit XDEC, a column decoding and control circuit YDEC, a read amplifier circuit SSA for the Gdata & Gdata# signals, and a write driver circuit.

[0034] Figure 1B for Figure 1AThe enlarged view of the area shown in the dashed box A illustrates how, when a word line WL is selected (controlled by XDEC decoding), data is transmitted to the upper and lower sensitive amplifier arrays. After amplification by these arrays, the data is written back to the memory cell of the memory array connected to the selected word line. When data needs to be modified or rewritten, the YDEC column decoder selects the corresponding sensitive amplifier array position. Data is transmitted from a set of Gdata&Gdata# through the local read / write conversion circuit (lrwap) to a set of Ldata&Ldata#, and then written to the corresponding sensitive amplifier array and the memory cell of the connected memory array. When reading data, the data transmission direction is reversed. The YDEC column decoder selects the corresponding sensitive amplifier array position, data is transmitted to a set of Ldata&Ldata#, then transmitted by the local read / write conversion circuit (lrwap) to a set of Gdata&Gdata#, and finally amplified and output by the read amplifier circuit SSA.

[0035] The read / write conversion circuit (LRWAP) includes multiple read / write conversion circuit units. Figure 1C This is a schematic diagram of a read / write conversion circuit unit. Each read / write conversion circuit unit includes a read circuit 100, a local amplifier unit 110, and a write circuit 120.

[0036] This application provides a semiconductor structure layout for implementing read / write conversion circuit functions. The semiconductor structure obtained using this semiconductor structure layout has high reliability.

[0037] Figure 2 This is a semiconductor structure layout provided in the first embodiment of this application. Figure 3 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the first embodiment of this application. The circuit is an example of a write conversion circuit used by Ldat / Ldat#.

[0038] Please see Figure 3 The circuit includes a first NMOS transistor MN1 and a second NMOS transistor MN2. The first terminal of the first NMOS transistor MN1 is connected to Ldat#, and the second terminal of the first NMOS transistor MN1 is connected to the first terminal of the second NMOS transistor MN2. The control terminal of the first NMOS transistor MN1 is controlled by Gdat, and the second terminal of the second NMOS transistor MN2 is grounded. The control terminal of the second NMOS transistor MN2 is controlled by the write drive signal Wr.

[0039] The semiconductor structure layout forms the pattern of the first NMOS transistor MN1 and the second NMOS transistor MN2. Please refer to [link / reference]. Figure 2The semiconductor structure layout includes a first active region pattern AA1, a first gate pattern G1, a second gate pattern G2, a third gate pattern G3, a fourth gate pattern G4, a first connection pattern M1, a second connection pattern M2, a first contact hole pattern T1, a second contact hole pattern T2, and a third contact hole pattern T3.

[0040] The first gate pattern G1, the second gate pattern G2, the third gate pattern G3, and the fourth gate pattern G4 are spaced apart along a first direction and all extend along a second direction. In this embodiment, the first direction is perpendicular to the second direction. The first direction can be a direction parallel to the bit lines of the semiconductor structure, and the second direction can be a direction perpendicular to the bit lines of the semiconductor structure, that is, the second direction can be a direction parallel to the word lines of the semiconductor structure. The first gate pattern G1, the second gate pattern G2, the third gate pattern G3, and the fourth gate pattern G4 all overlap with the first active region pattern AA1.

[0041] The second connection pattern M2 is used to connect the first gate pattern G1 and the fourth gate pattern G4 in parallel. The first gate pattern G1, the fourth gate pattern G4 and the first active region pattern AA1 constitute the first NMOS transistor MN1 pattern.

[0042] The first connection pattern M1 is used to connect the second gate pattern G2 and the third gate pattern G3 in parallel. The second gate pattern G2, the third gate pattern G3 and the first active region pattern AA1 together constitute the second NMOS transistor MN2 pattern.

[0043] At least two first contact hole patterns T1 are arranged in parallel on the side of the first gate pattern G1 away from the second gate pattern G2, and each first contact hole pattern T1 overlaps with the first active region pattern AA1. As an example, in this embodiment, based on the lengths of the first gate pattern G1 and the first active region pattern AA1, the semiconductor structure layout includes three first contact hole patterns T1 arranged in parallel, which can both avoid mutual interference between adjacent first contact hole patterns T1 and provide as many parallel first contact hole patterns T1 as possible.

[0044] At least two second contact hole patterns T2 are connected in parallel between the second gate pattern G2 and the third gate pattern G3, and each second contact hole pattern T2 overlaps with the first active region pattern AA1. In this embodiment, the semiconductor structure layout includes three second contact hole patterns T2 connected in parallel.

[0045] At least two third contact hole patterns T3 are arranged in parallel on the side of the fourth gate pattern G4 away from the third gate pattern G3, and each third contact hole pattern T3 overlaps with the first active region pattern AA1. In this embodiment, the semiconductor structure layout includes three third contact hole patterns T3 arranged in parallel. The third contact hole pattern T3 corresponds to... Figure 2Terminal A of the first NMOS transistor MN1.

[0046] In this embodiment, the first gate pattern G1 and the second gate pattern G2 are connected in series, the third gate pattern G3 and the fourth gate pattern G4 are connected in series, and the first contact hole pattern T1 and the third contact hole pattern T3 correspond to each other. Figure 2 The A terminal of the first NMOS transistor MN1 corresponds to the second contact hole pattern T2. Figure 2 The C-terminal of the second NMOS transistor MN2, the region between the first gate pattern G1 and the second gate pattern G2, and the region between the third gate pattern G3 and the fourth gate pattern G4, corresponds to the common terminal B of the first NMOS transistor MN1 and the second NMOS transistor MN2. No contact hole patterns are provided in the layout region corresponding to terminal B. This is because the semiconductor structure layout provided in this embodiment allows the potential of terminal B to be limited by terminals A and C, thus providing predictability. Therefore, the layout region corresponding to terminal B does not need to be provided with dedicated contact hole patterns to limit the potential. Since terminal A corresponds to the edge regions on both sides of the first active region, its potential is not predictable. Therefore, contact holes are needed to limit it; that is, the first contact hole pattern T1 and the third contact hole pattern T3 need to be provided in the edge regions on both sides of the first active region pattern AA1.

[0047] Because the contact hole patterns located on both sides of the same gate pattern are mutually constrained, including the spacing between the contact hole patterns in the second direction (which must be greater than or equal to a preset distance), the first contact hole pattern T1 is constrained by the contact hole pattern in region B1 (i.e., the layout region corresponding to end B) on the other side of the first gate pattern G1. The second contact hole pattern T2 is constrained by the contact hole patterns in region B1 (i.e., the layout region corresponding to end B) on the other side of the second gate pattern G2 and region B2 (i.e., the layout region corresponding to end B) on the other side of the third gate pattern G3. The third contact hole pattern T3 will... Limited by the contact hole pattern in region B2 (i.e., the layout region corresponding to B end) on the other side of the first gate pattern G1, and in the semiconductor structure layout provided in this application embodiment, regions B1 and B2 (i.e., the layout region corresponding to B end) are not provided with contact hole patterns. Therefore, the arrangement of the first contact hole pattern T1, the second contact hole pattern T2 and the third contact hole pattern T3 in the second direction is only limited by a preset distance, so that within the length of the first active region pattern AA1, multiple first contact hole patterns T1, second contact hole patterns T2 and third contact hole patterns T3 can be arranged at a preset distance interval.

[0048] As the integration density of semiconductor structures increases and process dimensions gradually shrink, contact holes become smaller and smaller. Defects in these contact holes increasingly lead to performance degradation in semiconductor structures, affecting both performance and yield. In this embodiment, at least two first contact hole patterns T1 are provided, and these patterns are connected in parallel. When one of the first contact hole patterns T1 is defective, the remaining patterns can still be used, significantly improving the reliability of the semiconductor structure. Similarly, at least two second contact hole patterns T2 and three third contact hole patterns T3 are provided, and they are connected in parallel, further enhancing the reliability of the semiconductor structure.

[0049] In this embodiment, multiple first contact hole patterns T1, multiple second contact hole patterns T2, and multiple third contact hole patterns T3 are all spaced apart along a second direction. In this embodiment, along a first direction, the first contact hole patterns T1 are aligned with the second contact hole patterns T2 and the third contact hole patterns T3. In another embodiment, along the first direction, the first contact hole patterns T1 are staggered from the second contact hole patterns T2 and the third contact hole patterns T3. In this embodiment, the number of first contact hole patterns T1 is the same as the number of second contact hole patterns T2 and the number of third contact hole patterns T3. In other embodiments, the number of first contact hole patterns T1 may be partially the same as the number of second contact hole patterns T2 and the number of third contact hole patterns T3, or they may be completely different.

[0050] In some embodiments, in the second direction, the first connecting pattern M1 and the second connecting pattern M2 are respectively disposed on opposite sides of the first active region pattern AA1.

[0051] In some embodiments, the semiconductor layout further includes a fourth contact hole pattern T4, with at least two parallel fourth contact hole patterns T4 overlapping the first connection pattern M1. In this embodiment, the semiconductor layout further includes two fourth contact hole patterns T4, which are respectively disposed at one end of the second gate pattern G2 and the third gate pattern G3. Since at least two fourth contact hole patterns T4 are provided and arranged in parallel, if one of the fourth contact hole patterns T4 is defective, the remaining fourth contact hole patterns T4 can still be used, greatly improving the reliability of the semiconductor structure.

[0052] In some embodiments, the semiconductor layout further includes a fifth contact hole pattern T5, with at least two parallel fifth contact hole patterns T5 overlapping the second connection pattern M2. In this embodiment, the two fifth contact hole patterns T5 are respectively disposed at one end of the first gate pattern G1 and the fourth gate pattern G4. Since at least two fifth contact hole patterns T5 are provided and arranged in parallel, if one of the fifth contact hole patterns T5 is defective, the remaining fifth contact hole patterns T5 can still be used, greatly improving the reliability of the semiconductor structure.

[0053] Please continue reading. Figure 3 The circuit also includes a third NMOS transistor MN3. The first terminal of the third NMOS transistor MN3 is connected to Ldat, and the second terminal of the third NMOS transistor MN3 is connected to the control terminal of the first NMOS transistor MN1 to provide the Gdat signal. The control terminal of the third NMOS transistor MN3 is controlled by the write drive signal Wr.

[0054] Please continue reading. Figure 2 In this embodiment, the semiconductor structure layout also includes a second active region pattern AA2, a fifth gate pattern G5, and a sixth gate pattern G6.

[0055] The second active region pattern AA2 is disposed at an interval or side-by-side with the first active region pattern AA1 in the second direction. The fifth gate pattern G5 and the sixth gate pattern G6 are disposed at an interval along the first direction and both extend along the second direction. The fifth gate pattern G5 and the sixth gate pattern G6 overlap with the second active region pattern AA2.

[0056] In one embodiment, in the second direction, the third gate pattern G3 and the fifth gate pattern G5 are arranged at intervals or side by side, and the fourth gate pattern G4 and the sixth gate pattern G6 are arranged at intervals or side by side. Correspondingly, the fourth gate pattern G4 and the fifth gate pattern G5 are staggered, the third gate pattern G3 and the sixth gate pattern G6 are staggered, and the fifth gate pattern G5 and the sixth gate pattern G6 are staggered relative to the first gate pattern G1 and the second gate pattern G2.

[0057] The second connection pattern M2 is also used to connect the fifth gate pattern G5 and the sixth gate pattern G6 in parallel. The fifth gate pattern G5, the sixth gate pattern G6, and the second active region pattern AA2 constitute the third NMOS transistor pattern MN3.

[0058] In some embodiments, the semiconductor layout further includes at least two parallel-connected sixth contact hole patterns T6, disposed on the side of the fifth gate pattern G5 away from the sixth gate pattern G6, and overlapping with the second active region pattern AA2. The sixth contact hole patterns T6 are spaced apart along a second direction. For example, in this embodiment, two sixth contact hole patterns T6 are schematically illustrated.

[0059] In some embodiments, the semiconductor layout further includes at least two parallelly arranged seventh contact hole patterns T7, which are disposed between the fifth gate pattern G5 and the sixth gate pattern G6 and overlap with the second active region pattern AA2. The seventh contact hole patterns T7 are spaced apart along a second direction. For example, in this embodiment, two seventh contact hole patterns T7 are schematically shown.

[0060] In some embodiments, the semiconductor layout further includes at least two parallelly arranged eighth contact hole patterns T8, which are disposed on the side of the sixth gate pattern G6 away from the fifth gate pattern G5 and overlap with the second active region pattern AA2. The eighth contact hole patterns T8 are spaced apart along a second direction. For example, in this embodiment, two eighth contact hole patterns T8 are schematically shown.

[0061] In this embodiment, in the second direction, the sixth contact hole pattern T6 and the seventh contact hole pattern T7 are staggered at a predetermined distance, and the seventh contact hole pattern T7 and the eighth contact hole pattern T8 are staggered at a predetermined distance. The predetermined distance needs to satisfy the following conditions: no contact hole pattern is affected by other contact hole patterns, and the parasitic capacitance and parasitic inductance between adjacent contact hole patterns are less than a preset value.

[0062] The semiconductor structure layout provided in the first embodiment of this application can achieve... Figure 3 The write conversion circuit shown is used by Ldat / Ldat#.

[0063] Based on the semiconductor structure layout shown in the first embodiment, the second embodiment of this application also provides a semiconductor structure layout. Figure 4 This is a semiconductor structure layout provided in the second embodiment of this application. Figure 5 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the second embodiment of this application. The circuit is a partial circuit example of a local amplifier used by Ldat / Ldat#.

[0064] Please see Figure 5In this embodiment, the circuit includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor NM6. The first terminal of the fourth NMOS transistor MN4 is connected to Ldat#, and the second terminal of the fourth NMOS transistor MN4 is connected to the first terminal of the sixth NMOS transistor NM6. The control terminal of the fourth NMOS transistor MN4 is controlled by Ldat. The first terminal of the fifth NMOS transistor MN5 is connected to Ldat, and the second terminal of the fifth NMOS transistor MN5 is connected to the first terminal of the sixth NMOS transistor NM6. The control terminal of the fifth NMOS transistor MN5 is controlled by Ldat#. The second terminal of the sixth NMOS transistor NM6 is grounded, and the control terminal of the sixth NMOS transistor NM6 is controlled by the read enable signal RdEn.

[0065] In the second embodiment, the semiconductor structure layout includes a seventh gate pattern G7, an eighth gate pattern G8, a third connection pattern M3, and a fourth connection pattern M4. The seventh gate pattern G7 and the eighth gate pattern G8 are spaced apart along a first direction and both extend along a second direction. The seventh gate pattern G7 and the eighth gate pattern G8 overlap with the second active region pattern AA2. In the second direction, the first gate pattern G1 is spaced apart from the seventh gate pattern G7, and the second gate pattern G2 is spaced apart from the eighth gate pattern G8. In the first direction, the seventh gate pattern G7, the eighth gate pattern G8, the fifth gate pattern G5, and the sixth gate pattern G6 are spaced apart. The third connection pattern M3 is connected to the seventh gate pattern G7. The seventh gate pattern G7 and the second active region pattern AA2 constitute the fourth NMOS transistor MN4 pattern. The fourth connection pattern M4 is connected to the eighth gate pattern G8. The eighth gate pattern G8 and the second active region pattern AA2 constitute the fifth NMOS transistor MN5 pattern.

[0066] In some embodiments, at least two parallel ninth contact hole patterns T9 are disposed on the side of the seventh gate pattern G7 away from the eighth gate pattern G8 and overlap with the second active region pattern AA2. In this embodiment, the semiconductor structure layout includes two parallel ninth contact hole patterns T9, which are spaced apart along a second direction.

[0067] In some embodiments, at least two parallel-connected tenth contact hole patterns T10 are disposed between the seventh gate pattern G7 and the eighth gate pattern G8, and overlap with the second active region pattern AA2. In this embodiment, the semiconductor structure layout includes two parallel-connected tenth contact hole patterns T10, which are spaced apart along a second direction. In a first direction, the ninth contact hole pattern T9 and the tenth contact hole pattern T10 are staggered.

[0068] In this embodiment, the semiconductor structure layout also includes a fourth active region pattern AA4 and a thirteenth gate pattern G13. The fourth active region pattern AA4 and the second active region pattern AA2 are spaced apart in the second direction. The thirteenth gate pattern G13 extends along the second direction and overlaps with the fourth active region pattern AA4. A fifth connecting pattern M5 connects to the thirteenth gate pattern G13. The thirteenth gate pattern G13 and the fourth active region pattern AA4 constitute a sixth NMOS transistor NM6 pattern, and the fifth connecting pattern M5 is used to receive the read enable signal RdEn.

[0069] In the second embodiment, the semiconductor structure layout can be formed Figure 3 The write conversion circuit shown is for use with Ldat / Ldat# and Figure 5 The circuitry shown is a portion of the local amplifier used by Ldat / Ldat#.

[0070] Based on the semiconductor structure layout shown in the second embodiment, the third embodiment of this application also provides a semiconductor structure layout. Figure 6 This is a semiconductor structure layout provided in the third embodiment of this application. Figure 7 This is a circuit diagram of a semiconductor structure formed by the semiconductor structure layout provided in the third embodiment of this application. The circuit is an example of a circuit that converts Ldat / Ldat# to Gdat / Gdat# when reading.

[0071] Please see Figure 7 In this embodiment, the circuit includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8. The first terminal of the seventh NMOS transistor MN7 is connected to Gdat, and the second terminal of the seventh NMOS transistor MN7 is connected to the first terminal of the eighth NMOS transistor MN8. The control terminal of the seventh NMOS transistor MN7 is controlled by Ldat#. The second terminal of the eighth NMOS transistor MN8 is grounded, and the control terminal of the eighth NMOS transistor MN8 is controlled by the read enable signal RdEn.

[0072] In the third embodiment, the semiconductor structure layout includes a third active region pattern AA3, a ninth gate pattern G9, a tenth gate pattern G10, an eleventh gate pattern G11, and a twelfth gate pattern G12.

[0073] In the second direction, the third active region pattern AA3 is disposed at an interval from the second active region pattern AA2. In this embodiment, the third active region pattern AA3 is disposed between the second active region pattern AA2 and the fourth active region pattern AA4. The ninth gate pattern G9, the tenth gate pattern G10, the eleventh gate pattern G11, and the twelfth gate pattern G12 are disposed at intervals along the first direction and all extend along the second direction. The ninth gate pattern G9, the tenth gate pattern G10, the eleventh gate pattern G11, and the twelfth gate pattern G12 overlap with the third active region pattern AA3.

[0074] In one embodiment, in the second direction, the seventh gate pattern G7, the ninth gate pattern G9 and the thirteenth gate pattern G13 are spaced apart, the eighth gate pattern G8 and the tenth gate pattern G10 are spaced apart, the fifth gate pattern G5 and the eleventh gate pattern G12 are spaced apart, and the sixth gate pattern G6 and the twelfth gate pattern G11 are spaced apart.

[0075] The fourth connection pattern M4 is also used to connect the ninth gate pattern G9, the tenth gate pattern G10, the eleventh gate pattern G11, and the twelfth gate pattern G12 in parallel. The ninth gate pattern G9, the tenth gate pattern G10, the eleventh gate pattern G11, the twelfth gate pattern G12, and the third active region pattern AA3 constitute the seventh NMOS transistor pattern MN7.

[0076] In some embodiments, the semiconductor structure layout further includes an eleventh contact hole pattern T11, a twelfth contact hole pattern T12, a thirteenth contact hole pattern T13, a fourteenth contact hole pattern T14, and a fifteenth contact hole pattern T15.

[0077] At least one eleventh contact hole pattern T11 is disposed on the side of the ninth gate pattern G9 away from the tenth gate pattern G10, and overlaps with the third active region pattern AA3. In this embodiment, only one eleventh contact hole pattern T11 is schematically shown.

[0078] At least two parallel twelfth contact hole patterns T12 are disposed between the ninth gate pattern G9 and the tenth gate pattern G10, and overlap with the third active region pattern AA3. In this embodiment, only two twelfth contact hole patterns T12 are schematically shown.

[0079] Since the eleventh contact hole pattern T11 and the twelfth contact hole pattern T12 are respectively located on both sides of the ninth gate pattern G9, their arrangement restricts each other. Furthermore, since the function of the eleventh contact hole pattern T11 is to limit the potential, its number only needs to meet the requirements. Therefore, in this embodiment, reducing the number of eleventh contact hole patterns T11 allows for a corresponding increase in the number of twelfth contact hole patterns T12. The twelfth contact hole patterns T12 are used to connect the source terminal of the transistor, and their number is greater than that of the eleventh contact hole patterns T11, allowing the source terminal to have more contact holes arranged in parallel, thus meeting the source terminal's current transmission requirements.

[0080] At least one thirteenth contact hole pattern T13 is disposed between the tenth gate pattern G10 and the eleventh gate pattern G11, and overlaps with the third active region pattern AA3. In this embodiment, only one thirteenth contact hole pattern T13 is schematically shown.

[0081] At least two parallel-connected fourteenth contact hole patterns T14 are disposed between the eleventh gate pattern G11 and the twelfth gate pattern G12, and overlap with the third active region pattern AA3. In this embodiment, only two fourteenth contact hole patterns T14 are schematically shown.

[0082] At least one fifteenth contact hole pattern T15 is disposed on the side of the twelfth gate pattern G12 away from the eleventh gate pattern G11, and overlaps with the third active region pattern AA3. In this embodiment, only one fifteenth contact hole pattern T15 is schematically shown.

[0083] Since the fourteenth contact hole pattern T14 and the fifteenth contact hole pattern T15 are located on opposite sides of the twelfth gate pattern G12, their arrangement restricts each other. Furthermore, since the function of the fifteenth contact hole pattern T15 is to limit the potential, its number only needs to meet the requirements. Therefore, in this embodiment, reducing the number of fifteenth contact hole patterns T15 allows for a corresponding increase in the number of fourteenth contact hole patterns T14. The fourteenth contact hole pattern T14 provides the source terminal connection of the transistor, and its number is greater than that of the fifteenth contact hole patterns T15, allowing the source terminal to have more contact holes arranged in parallel, thus meeting the source terminal's current transmission requirements.

[0084] In this embodiment, the semiconductor structure layout further includes a fourteenth gate pattern G14, a fifteenth gate pattern G15, and a sixteenth gate pattern G16. The fourteenth gate pattern G14, the fifteenth gate pattern G15, and the sixteenth gate pattern G16 are spaced apart along a first direction and all extend along a second direction. The fourteenth gate pattern G14, the fifteenth gate pattern G15, and the sixteenth gate pattern G16 overlap with the fourth active region pattern AA4. In this embodiment, in the second direction, the tenth gate pattern G10 and the fourteenth gate pattern G14 are spaced apart, the eleventh gate pattern G11 and the fifteenth gate pattern G15 are spaced apart, and the twelfth gate pattern G12 and the sixteenth gate pattern G16 are spaced apart.

[0085] The fifth connection pattern M5 is also connected to the fourteenth gate pattern G14, the fifteenth gate pattern G15, and the sixteenth gate pattern G16. The fourteenth gate pattern G14, the fifteenth gate pattern G15, the sixteenth gate pattern G16, and the fourth active region pattern AA4 constitute the eighth NMOS transistor MN8.

[0086] The semiconductor structure layout provided in the third embodiment of this application can form Figure 3 The write conversion circuit shown is used by Ldat / Ldat#. Figure 5 The circuit diagram shown is part of the local amplifier used by Ldat / Ldat#. Figure 7 The circuit shown converts Ldat / Ldat# to Gdat / Gdat# for reading.

[0087] Another aspect of this application embodiment also provides a semiconductor structure. The semiconductor structure is fabricated according to the above-described semiconductor layout. The semiconductor structure can be provided with multiple contact holes connected in parallel. When one contact hole is defective, the remaining contact hole can still be used, which greatly improves the reliability of the semiconductor structure.

[0088] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A semiconductor structure layout, characterized in that, include: First active region graphic; The first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are spaced apart along the first direction and all extend along the second direction, and overlap with the first active region pattern. A first connection pattern is used to connect the second gate pattern and the third gate pattern in parallel; The second connection pattern is used to connect the first gate pattern and the fourth gate pattern in parallel; At least two first contact hole patterns are arranged in parallel and disposed on the side of the first gate pattern away from the second gate pattern, and each first contact hole pattern overlaps with the first active region pattern. At least two second contact hole patterns are arranged in parallel and disposed between the second gate pattern and the third gate pattern, and each second contact hole pattern overlaps with the first active region pattern; At least two third contact hole patterns are arranged in parallel and disposed on the side of the fourth gate pattern away from the third gate pattern, and each of the third contact hole patterns overlaps with the first active region pattern.

2. The semiconductor structure layout according to claim 1, characterized in that, The first contact hole pattern, the second contact hole pattern, and the third contact hole pattern are all spaced apart along the second direction.

3. The semiconductor structure layout according to claim 1, characterized in that, In the second direction, the first connecting pattern and the second connecting pattern are respectively disposed on both sides of the first active region pattern.

4. The semiconductor structure layout according to claim 1, characterized in that, It also includes a fourth contact hole pattern, wherein at least two of the fourth contact hole patterns connected in parallel overlap with the first connection pattern.

5. The semiconductor structure layout according to claim 4, characterized in that, The two fourth contact hole patterns are respectively disposed at one end of the second gate pattern and the third gate pattern.

6. The semiconductor structure layout according to claim 1, characterized in that, It also includes a fifth contact hole pattern, wherein at least two of the fifth contact hole patterns connected in parallel overlap with the second connection pattern.

7. The semiconductor structure layout according to claim 6, characterized in that, The two fifth contact hole patterns are respectively disposed at one end of the first gate pattern and the fourth gate pattern.

8. The semiconductor structure layout according to claim 1, characterized in that, Also includes: The second active region pattern is spaced apart from the first active region pattern in the second direction; The fifth gate pattern and the sixth gate pattern are spaced apart along the first direction and both extend along the second direction, and overlap with the second active region pattern. The second connecting pattern is also used to connect the fifth gate pattern and the sixth gate pattern in parallel.

9. The semiconductor structure layout according to claim 8, characterized in that, In the second direction, the third gate pattern is spaced apart from the fifth gate pattern, and the fourth gate pattern is spaced apart from the sixth gate pattern.

10. The semiconductor structure layout according to claim 9, characterized in that, Also includes: At least two sixth contact hole patterns arranged in parallel are disposed on the side of the fifth gate pattern away from the sixth gate pattern and overlap with the second active region pattern; At least two seventh contact hole patterns arranged in parallel are disposed between the fifth gate pattern and the sixth gate pattern, and overlap with the second active region pattern; At least two eighth contact hole patterns arranged in parallel are disposed on the side of the sixth gate pattern away from the fifth gate pattern and overlap with the second active region pattern.

11. The semiconductor structure layout according to claim 10, characterized in that, The sixth contact hole pattern is spaced apart along the second direction, the seventh contact hole pattern is spaced apart along the second direction, and the eighth contact hole pattern is spaced apart along the second direction. In the second direction, the sixth contact hole pattern and the seventh contact hole pattern are staggered at a set distance, and the seventh contact hole pattern and the eighth contact hole pattern are staggered at a set distance.

12. The semiconductor structure layout according to claim 8, characterized in that, Also includes: The seventh gate pattern and the eighth gate pattern are spaced apart along the first direction and both extend along the second direction and overlap with the second active region pattern. In the second direction, the first gate pattern and the seventh gate pattern are spaced apart, and the second gate pattern and the eighth gate pattern are spaced apart. The third connection pattern is connected to the seventh gate pattern; The fourth connection pattern is connected to the eighth gate pattern.

13. The semiconductor structure layout according to claim 12, characterized in that, Also includes: At least two ninth contact hole patterns arranged in parallel are disposed on the side of the seventh gate pattern away from the eighth gate pattern and overlap with the second active region pattern; At least two parallel tenth contact hole patterns are disposed between the seventh gate pattern and the eighth gate pattern, and overlap with the second active region pattern.

14. The semiconductor structure layout according to claim 12, characterized in that, Also includes: The third active region pattern is spaced apart from the second active region pattern in the second direction; The ninth, tenth, eleventh, and twelfth gate patterns are spaced apart along the first direction and extend along the second direction, and overlap with the third active region pattern. The fourth connecting pattern is also used to connect the ninth, tenth, eleventh, and twelfth gate patterns in parallel.

15. The semiconductor structure layout according to claim 14, characterized in that, Also includes: At least one eleventh contact hole pattern is disposed on the side of the ninth gate pattern away from the tenth gate pattern and overlaps with the third active region pattern; At least two parallel twelfth contact hole patterns are disposed between the ninth gate pattern and the tenth gate pattern, and overlap with the third active region pattern; At least one thirteenth contact hole pattern is disposed between the tenth gate pattern and the eleventh gate pattern, and overlaps with the third active region pattern; At least two parallel fourteenth contact hole patterns are disposed between the eleventh gate pattern and the twelfth gate pattern, and overlap with the third active region pattern; At least one fifteenth contact hole pattern is disposed on the side of the twelfth gate pattern away from the eleventh gate pattern and overlaps with the third active region pattern.

16. The semiconductor structure layout according to claim 15, characterized in that, The number of the twelfth contact hole pattern is greater than the number of the eleventh contact hole pattern.

17. The semiconductor structure layout according to claim 15, characterized in that, The number of the fourteenth contact hole pattern is greater than the number of the fifteenth contact hole pattern.

18. A semiconductor structure, fabricated according to the semiconductor structure layout of any one of claims 1 to 17.

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