Transistor structure and method of manufacturing the same

Abstract

The present disclosure provides a transistor structure and a method for manufacturing the same. The structure comprises: a substrate; a gate structure disposed on the substrate and having a first gate portion, a second gate portion and a third gate portion arranged in sequence in a direction perpendicular to and away from the substrate; a first channel disposed on the substrate and surrounding an outer surface of the first gate portion; a first source-drain layer disposed on the substrate and connected to both sides opposite to the first channel; an isolation layer covering the first channel and the first source-drain layer and surrounding an outer surface of the second gate portion; a second channel disposed on the isolation layer and surrounding an outer surface of the third gate portion; a second source-drain layer disposed on the isolation layer and connected to both sides opposite to the second channel; the first gate portion, the first channel and the first source-drain layer form a first transistor, and the third gate portion, the second channel and the second source-drain layer form a second transistor, wherein one of them is an N-type transistor and the other is a P-type transistor. The present disclosure can reduce the footprint of the transistor structure by half.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a transistor structure and its fabrication method. Background Technology

[0002] As semiconductor technology matures and integrated circuits shrink, the channel length in transistors becomes shorter, increasing the likelihood of short-channel effects. To address this issue, a vertical annular channel (CAA) structure is employed, where the channel surrounds the gate in the transistor. This provides more stringent control over charge carriers within the channel, mitigating the short-channel effect.

[0003] However, the channel-all-around structure is generally used in CMOS (Complementary Metal Oxide Semiconductor), which includes N-type transistors (…).

[0004] N-type metal oxidide semiconductor (NMOS) and P-type transistor (P-type metal oxidide semiconductor (PMOS)). To date, the CMOS technology standard has placed NMOS and PMOS side by side in the horizontal direction, which occupies a large area and is not conducive to further increasing density.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a transistor structure and its fabrication method, which can halve the footprint of N-type and P-type transistors and double their density.

[0007] This disclosure provides a transistor structure including a substrate, a gate structure, a first channel, a first source-drain layer, an isolation layer, a second channel, and a second source-drain layer. The gate structure is disposed on the substrate and, in a direction perpendicular to and away from the substrate, has a first gate portion, a second gate portion, and a third gate portion arranged sequentially. The first channel is disposed on the substrate and surrounds the outer surface of the first gate portion. The first source-drain layer is disposed on the substrate and connected to opposite sides of the first channel. The isolation layer covers the first channel and the first source-drain layer and surrounds the outer surface of the second gate portion. The second channel is disposed on the isolation layer and surrounds the outer surface of the third gate portion. The second source-drain layer is disposed on the isolation layer and connected to opposite sides of the second channel. The first gate portion, the first channel, and the first source-drain layer of the gate structure constitute a first transistor, and the third gate portion, the second channel, and the second source-drain layer of the gate structure constitute a second transistor. One of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.

[0008] This disclosure also provides a method for fabricating a transistor structure, comprising: providing a substrate; forming a first gate portion, a first channel surrounding the first gate portion, and first source-drain layers located on opposite sides of the first channel on the substrate to form a first transistor; forming an isolation layer having a first via on the first channel and the first source-drain layers, the first via corresponding to the first gate portion in a vertical direction; forming a second gate portion in the first via; forming a third gate portion on the second gate portion, and forming a second channel surrounding the third gate portion and second source-drain layers located on opposite sides of the second channel on the isolation layer to form a second transistor; wherein, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor.

[0009] As can be seen from the above technical solutions, the transistor structure of this disclosure embodiment has the following beneficial effects:

[0010] In this embodiment of the present disclosure, the first transistor and the second transistor are distributed in the vertical direction and share the same gate structure, which avoids placing the first transistor and the second transistor side by side in the horizontal direction, reduces the footprint by half, doubles the density of the transistor structure, and improves the electrical performance of the transistor structure. Attached Figure Description

[0011] Figure 1 This is a top view of a transistor structure in which a first insulating layer is formed on a substrate and a first trench is formed in the first insulating layer, as shown in some embodiments of this disclosure;

[0012] Figure 2a and Figure 2b They are respectively Figure 1 Sectional views along AA and BB;

[0013] Figure 3 This is a top view of a transistor structure in which a first polysilicon layer is formed in a first trench and the first polysilicon layer is doped, as shown in some embodiments of this disclosure.

[0014] Figure 4a and Figure 4b They are respectively Figure 3 Sectional views along AA and BB;

[0015] Figure 5 This is a top view of a transistor structure having an initial mask layer with an initial via pattern formed on a first insulating layer, as shown in some embodiments of this disclosure.

[0016] Figure 6a and Figure 6b They are respectively Figure 5 Sectional views along AA and BB;

[0017] Figure 7 This is a top view of a transistor structure with an initial via formed after patterning a first doped polysilicon layer and a first insulating layer, as shown in some embodiments of this disclosure.

[0018] Figure 8a and Figure 8b They are respectively Figure 7 Sectional views along AA and BB;

[0019] Figure 9 This is a top view of a transistor structure in which a second polysilicon layer and a first gate dielectric layer are sequentially formed on the inner wall of an initial via, as shown in some embodiments of this disclosure;

[0020] Figure 10a and Figure 10b They are respectively Figure 9 Sectional views along AA and BB;

[0021] Figure 11 This is a top view of a transistor structure in which a first source / drain layer and a first channel are formed by heat treatment of a first doped polysilicon layer and a second polysilicon layer, respectively, according to some embodiments of the present disclosure.

[0022] Figure 12a and Figure 12b They are respectively Figure 11 Sectional views along AA and BB;

[0023] Figure 13 This is a top view of a transistor structure in which a first gate is formed in an initial via, as shown in some embodiments of this disclosure;

[0024] Figure 14a and Figure 14b They are respectively Figure 13 Sectional views along AA and BB;

[0025] Figure 15 This is a top view of a transistor structure forming an isolation layer, as shown in some embodiments of this disclosure;

[0026] Figure 16a and Figure 16b They are respectively Figure 15 Sectional views along AA and BB;

[0027] Figure 17 This is a top view of a transistor structure forming a first mask layer with a first via pattern, as shown in some embodiments of this disclosure;

[0028] Figure 18a and Figure 18b They are respectively Figure 17 Sectional views along AA and BB;

[0029] Figure 19 This is a top view of a transistor structure in which a first via is formed in an isolation layer, as shown in some embodiments of this disclosure;

[0030] Figure 20a and Figure 20b They are respectively Figure 19 Sectional views along AA and BB;

[0031] Figure 21 This is a top view of a transistor structure in which a second gate dielectric layer is formed in a first via, as shown in some embodiments of this disclosure;

[0032] Figure 22a and Figure 22b They are respectively Figure 21 Sectional views along AA and BB;

[0033] Figure 23 This is a top view of a transistor structure in which a second gate is formed in a first via, as shown in some embodiments of this disclosure;

[0034] Figure 24a and Figure 24b They are respectively Figure 23 Sectional views along AA and BB;

[0035] Figure 25 This is a top view of a transistor structure showing the formation of a second insulating layer and a second mask layer having a second trench pattern formed on the second insulating layer, as illustrated in some embodiments of this disclosure.

[0036] Figure 26a and Figure 26b They are respectively Figure 25 Sectional views along AA and BB;

[0037] Figure 27 This is a top view of a transistor structure in which a second trench is formed in a second insulating layer, as shown in some embodiments of this disclosure;

[0038] Figure 28a and Figure 28b They are respectively Figure 27 Sectional views along AA and BB;

[0039] Figure 29 This is a top view of a transistor structure in which a third polysilicon layer is filled in a second trench and the third polysilicon layer is doped, as shown in some embodiments of this disclosure.

[0040] Figure 30a and Figure 30b They are respectively Figure 29 Sectional views along AA and BB;

[0041] Figure 31 This is a top view of a transistor structure in which a third mask layer with a second via pattern is formed on a second insulating layer, as shown in some embodiments of this disclosure.

[0042] Figure 32a and Figure 32b They are respectively Figure 31 Sectional views along AA and BB;

[0043] Figure 33 This is a top view of a transistor structure in which a patterned third doped polysilicon layer and a second insulating layer form a second via, as shown in some embodiments of this disclosure.

[0044] Figure 34a and Figure 34b They are respectively Figure 33 Sectional views along AA and BB;

[0045] Figure 35 This is a top view of a transistor structure in which a fourth polysilicon layer and a third gate dielectric layer are sequentially formed on the inner wall of a second via, as shown in some embodiments of this disclosure.

[0046] Figure 36a and Figure 36b They are respectively Figure 35 Sectional views along AA and BB;

[0047] Figure 37 This is a top view of a transistor structure in which a third gate is filled in a second via, as shown in some embodiments of this disclosure;

[0048] Figure 38a and Figure 38b They are respectively Figure 37 Sectional views along AA and BB;

[0049] Figure 39 This is a top view of a transistor structure in which a third doped polysilicon layer and a fourth polysilicon layer are thermally processed to form a second source / drain layer and a second channel, respectively, according to some embodiments of this disclosure.

[0050] Figure 40a and Figure 40b They are respectively Figure 39 Sectional views along AA and BB;

[0051] Figure 41 This is a flowchart illustrating a method for fabricating a transistor structure according to some embodiments of this disclosure.

[0052] Explanation of reference numerals in the attached figures:

[0053] 1. Substrate; 2. First insulating layer; 201. First trench; 3. First polysilicon layer; 301. First doped polysilicon layer; 302. First source / drain layer; 4. Initial mask layer; 5. Initial via; 6. Second polysilicon layer; 601. First channel; 7. Isolation layer; 8. First mask layer; 9. First via; 10. Second insulating layer; 1001. Second trench; 11. Second mask layer; 12. Third polysilicon layer; 1201. Third doped polysilicon layer; 1202. 13. Second source / drain layer; 14. Third mask layer; 15. Second via; 16. Fourth polysilicon layer; 17. Second channel; 20. Gate structure; 21. First gate portion; 211. First gate dielectric layer; 212. First gate; 22. Second gate portion; 221. Second gate dielectric layer; 222. Second gate; 23. Third gate portion; 231. Third gate dielectric layer; 232. Third gate; X1. First horizontal direction; X2. Second horizontal direction; Y. Vertical direction. Detailed Implementation

[0054] The flowcharts shown in the accompanying drawings of this disclosure are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the actual situation.

[0055] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0056] As the size of integrated circuits continues to shrink, the length of the channels in transistors is also shortening, making them more susceptible to short-channel effects. Short-channel effects reduce the gate's control over the channel, making it more difficult to pinch off the channel with the gate voltage. This increases the likelihood of subthreshold leakage, thereby reducing the transistor's electrical performance.

[0057] In CMOS, a channel-around-gate structure can mitigate the short-channel effect. CMOS includes NMOS and PMOS, but all CMOS technologies place NMOS and PMOS side by side on a horizontal plane, resulting in a large footprint and hindering further density improvements.

[0058] Based on the above, this disclosure provides a transistor structure that enables N-type transistors (NMOS) and P-type transistors (PMOS) to share a single gate. These transistors are distributed in the vertical Y-direction, thereby reducing the footprint and increasing the transistor layout density. The PMOS and NMOS transistors are arranged on the same vertical plane, sharing the same gate and using separate channels isolated by an isolation layer, allowing the gate to control the operation of different types of transistors. Specifically, the operation of the PMOS and NMOS is controlled by adjusting the voltages at each terminal, such as the gate, source, and drain.

[0059] Specifically, such as Figures 39 to 40b As shown, the transistor structure of this embodiment includes a substrate 1, a gate structure 20, a first channel 601, a first source-drain layer 302, an isolation layer 7, a second channel 1501, and a second source-drain layer 1202. The first gate portion 21, the first channel 601, and the first source-drain layer 302 of the gate structure 20 constitute a first transistor, and the third gate portion 23, the second channel 1501, and the second source-drain layer 1202 of the gate structure 20 constitute a second transistor. The first transistor and the second transistor are distributed in a direction perpendicular to the substrate 1 and are separated by the isolation layer 7.

[0060] The transistor structure of the embodiments of this disclosure will be described in detail below.

[0061] In this embodiment, the substrate 1 can be made of silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, silicon-on-insulator, or germanium-on-insulator, etc. The substrate 1 can also be doped with certain dopant particles to change the electrical parameters according to design requirements.

[0062] Shallow trench isolation is formed on substrate 1, and active regions are provided between the shallow trench isolations. Word line structures and bit line structures (not shown in the figure) may also be provided in substrate 1, with the word line structures and bit line structures located at different heights of substrate 1, and both the word line structures and bit line structures connected to the active regions. The transistor structure of this embodiment is located in the active region of substrate 1.

[0063] In the embodiments disclosed herein, such as Figure 40a and Figure 40b As shown, the gate structure 20 is disposed on the substrate 1, and in a direction perpendicular to and away from the substrate 1, the gate structure 20 has a first gate portion 21, a second gate portion 22, and a third gate portion 23 arranged in sequence. Figure 40a and Figure 40b As shown, the gate structure 20 includes a gate and a gate dielectric layer, with the gate dielectric layer surrounding the outer surface of the gate. The gate includes a first gate 212, a second gate 222, and a third gate 232, and the gate dielectric layer includes a first gate dielectric layer 211, a second gate dielectric layer 221, and a third gate dielectric layer 231.

[0064] In some embodiments, the material of the gate dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and high-k dielectric.

[0065] In some embodiments, the gate may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten, aluminum, copper, etc.), metal compounds (e.g., titanium nitride, tantalum nitride), or silicides.

[0066] In this embodiment of the disclosure, such as Figure 40a and Figure 40b As shown, the first channel 601 is disposed on the substrate 1 and surrounds the outer surface of the first gate portion 21. Therefore, the first transistor in this embodiment of the present disclosure has a structure in which the channel surrounds the gate.

[0067] like Figure 39 , Figure 40a and Figure 40b As shown, the first source-drain layer 302 is disposed on the substrate 1 and connected to the opposite sides of the first channel 601.

[0068] The first source-drain layer 302 may include a first source portion and a first drain portion, wherein the first source portion is connected to one side of the first channel 601 and the first drain portion is connected to the opposite side of the first channel 601.

[0069] Thus, the first gate portion 21, the first channel 601, and the first source-drain layer 302 of the gate structure 20 constitute the first transistor. That is, the first source portion can be understood as the source of the first transistor, the first drain portion can be understood as the drain of the first transistor, and the first transistor is a transistor in which the channel surrounds the gate structure 20.

[0070] In the embodiments disclosed herein, such as Figure 40a and Figure 40b As shown, the isolation layer 7 covers the first channel 601 and the first source-drain layer 302, and surrounds the outer surface of the second gate portion 22.

[0071] The isolation layer 7 is made of an insulating material. In some embodiments, the material of the isolation layer 7 may be at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation layer 7, being made of an insulating material, is capable of isolating the first transistor and the second transistor.

[0072] In the embodiments disclosed herein, such as Figure 40a and Figure 40b As shown, the second channel 1501 is disposed on the isolation layer 7 and surrounds the outer surface of the third gate portion 23. Therefore, the second transistor in this embodiment of the present disclosure also has a channel surrounding the gate structure.

[0073] The material of the second channel 1501 can be the same as that of the first channel 601, for example, both can be monocrystalline silicon, which simplifies the process and saves costs during the preparation.

[0074] In embodiments of this disclosure, such as Figure 40a and Figure 40b As shown, the second source-drain layer 1202 is disposed on the isolation layer 7 and connected to the opposite sides of the second channel 1501.

[0075] The second source-drain layer 1202 may include a second source portion and a second drain portion, wherein the second source portion is connected to one side of the second channel 1501 and the second drain portion is connected to the opposite side of the second channel 1501.

[0076] Thus, the third gate portion 23, the second channel 1501, and the second source-drain layer 1202 of the gate structure 20 constitute the second transistor. That is, the second source portion can be understood as the source of the second transistor, the second drain portion can be understood as the drain of the second transistor, and the second transistor is a transistor in which the channel surrounds the gate structure 20.

[0077] In embodiments of this disclosure, one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor. For example, if the first transistor is an N-type transistor (NMOS), then the second transistor is a P-type transistor (PMOS); if the first transistor is a P-type transistor, then the second transistor is an N-type transistor.

[0078] In summary, in the embodiments of this disclosure, the first transistor and the second transistor are distributed in the vertical direction Y, share a gate structure 20, and are isolated by an isolation layer 7. This reduces the short-channel effect, halves the footprint of NMOS and PMOS, doubles the density of the transistor structure, improves the electrical performance of the transistor structure, and further breaks through the limits of Moore's Law.

[0079] This disclosure also provides a method for fabricating a transistor structure. Figures 1 to 40b The diagrams show the structural schematics of the transistor structure at different steps in the fabrication process. Figure 41 A flowchart illustrating the fabrication method of a transistor structure is shown.

[0080] like Figure 41 As shown, the method for fabricating the transistor structure according to the embodiments of this disclosure includes the following steps S411 to S415.

[0081] S411: Provides substrate 1.

[0082] S412: A first gate portion 21, a first channel 601 surrounding the first gate portion 21, and first source-drain layers 302 located on opposite sides of the first channel 601 are formed on the substrate 1 to form a first transistor.

[0083] S413: An isolation layer 7 with a first via 9 is formed on the first channel 601 and the first source-drain layer 302, the first via 9 corresponding to the first gate portion 21 in the vertical direction Y.

[0084] S414: A second gate portion 22 is formed in the first through hole 9.

[0085] S415: A third gate portion 23 is formed on the second gate portion 22, and a second channel 1501 surrounding the third gate portion 23 and a second source-drain layer 1202 located on opposite sides of the second channel 1501 are formed on the isolation layer 7 to form a second transistor; wherein, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor.

[0086] In the above method of the present disclosure embodiments, N-type transistors and P-type transistors distributed in the vertical direction Y can be formed, and the two transistors share a gate, which reduces the footprint of the transistor structure by half and doubles the density, further improving the electrical performance of the transistor structure.

[0087] The method for fabricating the transistor structure according to the embodiments of this disclosure will be described in detail below.

[0088] S411: Provides substrate 1.

[0089] The substrate 1 can be made of silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator stacked, silicon-germanium-on-insulator stacked, silicon-germanium-on-insulator, or germanium-on-insulator, etc. The substrate 1 can also be doped with certain dopant particles to change the electrical parameters according to design requirements. The substrate 1 is the same as the substrate 1 in the transistor structure embodiment, and will not be described again here.

[0090] S412: A first gate portion 21, a first channel 601 surrounding the first gate portion 21, and first source-drain layers 302 located on opposite sides of the first channel 601 are formed on the substrate 1 to form a first transistor.

[0091] In some embodiments, S412 may include the following contents A1 to A8.

[0092] A1: A first insulating layer 2 is formed on substrate 1, such as Figure 1 As shown.

[0093] In some embodiments, the material of the first insulating layer 2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0094] In some embodiments, a first insulating layer 2 of a certain thickness can be deposited on the substrate 1 using a deposition process. The deposition process can be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition, without particular limitation herein. When the first insulating layer 2 is silicon oxide, the first insulating layer 2 can also be formed by oxidizing the top portion of the silicon substrate 1 using a dry oxidation method or a wet oxidation method (e.g., in-situ steam generation, ISSG).

[0095] A2: A first trench 201 extending along the first horizontal direction X1 is formed in the first insulating layer 2.

[0096] A mask layer (not shown in the figure) can be formed on the first insulating layer 2, showing a first trench pattern extending along the first horizontal direction X1. This mask layer is then used to etch the first insulating layer 2, forming a first trench 201 in the first insulating layer 2, exposing the substrate 1. Figure 1 , Figure 2a and Figure 2b As shown.

[0097] In some embodiments, the first insulating layer 2 can be etched to form the first trench 201 using either a dry etching process or a wet etching process. Those skilled in the art can choose according to the actual situation, and no limitation is made here.

[0098] A3: A first polysilicon layer 3 is formed in the first trench 201.

[0099] like Figure 3 , Figure 4a and Figure 4b As shown, a first polysilicon layer 3 can be deposited in the first trench 201 using a deposition process, and the first polysilicon layer 3 fills the first trench 201. After the first polysilicon layer 3 is formed, a chemical mechanical polishing process can be used to remove the first polysilicon layer 3 above the top surface of the first insulating layer 2, so that the top surface of the first polysilicon layer 3 is flush with the top surface of the first insulating layer 2.

[0100] A4: Doping the first polysilicon layer 3 with either an N-type dopant ion or a P-type dopant ion to form a first doped polysilicon layer 301.

[0101] like Figure 4a and Figure 4b As shown, the first polysilicon layer 3 is used to form the source and drain of the first transistor, and therefore needs to be doped. If the first transistor is an N-type transistor, the first polysilicon layer 3 can be N-type doped, and the dopant can be phosphorus (P) or arsenic (As). If the first transistor is a P-type transistor, the first polysilicon layer 3 can be P-type doped, and the dopant can be boron (B) or gallium (Ga). Doping can be performed using ion implantation or thermal diffusion processes, and no special limitation is made here.

[0102] A5: Pattern the first doped polysilicon layer 301 and the first insulating layer 2 onto the substrate 1 to form an initial via 5. The diameter of the initial via 5 is larger than the size of the first doped polysilicon layer 301 in the second horizontal direction X2, which is perpendicular to the first horizontal direction X1.

[0103] like Figure 5 , Figure 6a and Figure 6b As shown, an initial mask layer 4 with an initial via 5 pattern is formed on the first insulating layer 2 and the first doped polysilicon layer 301, and the first insulating layer 2 and the first doped polysilicon layer 301 are patterned using the initial mask layer 4.

[0104] like Figure 7 , Figure 8a and Figure 8b As shown, the first doped polysilicon layer 301 and the first insulating layer 2 are patterned onto the substrate 1, exposing the surface of the substrate 1 to form an initial via 5. The diameter of the initial via 5 is larger than the dimension of the first doped polysilicon layer 301 in the second horizontal direction X2, which can also be understood as the diameter of the initial via 5 being larger than the width of the first doped polysilicon layer 301. The first horizontal direction X1 and the second horizontal direction X2 are perpendicular, and both the first horizontal direction X1 and the second horizontal direction X2 are perpendicular to the vertical direction Y.

[0105] Setting the diameter of the initial via 5 to be greater than the width of the first doped polysilicon layer 301 ensures that the first source-drain layer 302 formed in subsequent processes is located on opposite sides of the first channel 601, thus avoiding the interconnection between the source and drain in the first source-drain layer 302.

[0106] A6: A second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via 5.

[0107] like Figure 9 , Figure 10a and Figure 10b As shown, a second polysilicon layer 6 can be formed on the inner wall of the initial via 5, on the first insulating layer 2, and on the first doped polysilicon layer 301 using a deposition process. A first gate dielectric layer 211 is formed on the second polysilicon layer 6, i.e., the second polysilicon layer 6 surrounds the first gate dielectric layer 211. Then, the second polysilicon layer 6 and the first gate dielectric layer 211 located on the first insulating layer 2 and the first doped polysilicon layer 301 can be removed using a chemical mechanical polishing process, leaving only the second polysilicon layer 6 and the first gate dielectric layer 211 located on the inner wall of the initial via 5.

[0108] A7: Heat treatment of the first doped polysilicon layer 301 and the second polysilicon layer 6 forms the first source / drain layer 302 and the first channel 601, respectively.

[0109] like Figure 11 , Figure 12a and Figure 12b As shown, the first doped polysilicon layer 301 and the second polysilicon layer 6 are heat-treated so that both polysilicon layers are formed into monocrystalline silicon. That is, the first doped polysilicon layer 301 is formed into the first doped monocrystalline silicon layer, which is then formed into the first source / drain layer 302, and the second polysilicon layer 6 is formed into the second monocrystalline silicon layer, which is then formed into the first channel 601.

[0110] In some embodiments, the heat treatment temperature is 900℃ to 1200℃. Specifically, in addition to the two extreme values ​​mentioned above, the heat treatment temperature can also be 950℃, 1000℃, 1050℃, 1100℃, or 1150℃. Those skilled in the art can adjust it according to the actual situation, and no special limitation is made here.

[0111] A8: A first gate 212 is filled in the initial via 5 in which the first gate dielectric layer 211 is formed, and the first gate 212 and the first gate dielectric layer 211 form a first gate portion 21.

[0112] like Figure 13 , Figure 14a and Figure 14bAs shown, the first gate 212 can be filled into the initial via 5 where the first gate dielectric layer 211 is formed using a deposition process. For the first gate 212 that protrudes above the surface of the first insulating layer 2 and is deposited on the surface of the first insulating layer 2, the first gate 212 on the surface of the first insulating layer 2 can be removed using a chemical mechanical polishing process after the deposition process is completed, and the top surface of the first gate 212 in the initial via 5 can be processed to be flush with the surface of the first insulating layer 2. The first gate 212 and the first gate dielectric layer 211 form the first gate portion 21.

[0113] In some embodiments, the material of the first gate 212 may include at least one of polysilicon, tungsten, titanium nitride, tantalum nitride, and silicide, without limitation herein.

[0114] like Figure 14a and Figure 14b As shown, after the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layer 302 located on opposite sides of the first channel 601 are formed into a first transistor. The first transistor can be either an N-type transistor or a P-type transistor.

[0115] In some other embodiments, S412 may include the following contents B1 to B8.

[0116] B1: A first insulating layer 2 is formed on the substrate 1, such as Figure 1 As shown.

[0117] The first insulating layer 2 can be formed on the substrate 1 using a deposition process, a dry silicon oxide method, or a wet oxidation method. The material and specific formation process of the first insulating layer 2 can be the same as those of the first insulating layer 2 in A1 of the above embodiments, and will not be repeated here.

[0118] B2: A first trench 201 extending along the first horizontal direction X1 is formed in the first insulating layer 2.

[0119] like Figure 1 , Figure 2a and Figure 2b As shown, an etching process can be used to etch a first trench 201 extending along the first horizontal direction X1 in the first insulating layer 2. The process for forming the first trench 201 can be the same as A2 in the above embodiment, and will not be described again here.

[0120] B3: The first single-crystal silicon layer is epitaxially grown in the first trench 201.

[0121] In this embodiment, substrate 1 is a monocrystalline silicon substrate. After forming the first trench 201 in the first insulating layer 2, the first trench 201 is exposed on the surface of substrate 1. At this time, a monocrystalline silicon layer can be grown on the exposed surface of substrate 1 using epitaxial growth technology until the epitaxially grown monocrystalline silicon layer fills the first trench 201, thus forming a first monocrystalline silicon layer in the first trench 201. This first monocrystalline silicon layer is used to form the first source / drain layer 302 in subsequent processes. Compared with the above embodiment, there is no need to perform heat treatment on the first monocrystalline silicon layer, thereby saving process steps.

[0122] B4: Doping the first single-crystal silicon layer with either an N-type dopant ion or a P-type dopant ion to form the first doped single-crystal silicon layer.

[0123] Since the first single-crystal silicon layer is used to form the source and drain of the first transistor, it needs to be doped. If the first transistor is an N-type transistor, the first polycrystalline silicon layer 3 can be N-type doped, and the dopant can be phosphorus (P) or arsenic (As). If the first transistor is a P-type transistor, the first single-crystal silicon layer can be P-type doped, and the dopant can be boron (B) or gallium (Ga). Ion implantation or thermal diffusion processes can be used for doping; no special limitations are specified here.

[0124] B5: Pattern the first doped single-crystal silicon layer and the first insulating layer 2 onto the substrate 1 to form an initial via 5. The first doped single-crystal silicon layer is formed as a first source / drain layer 302. The diameter of the initial via 5 is larger than the size of the first doped single-crystal silicon layer in the second horizontal direction X2. The second horizontal direction X2 is perpendicular to the first horizontal direction X1.

[0125] An initial mask layer 4 with an initial via pattern 5 is formed on the first insulating layer 2 and the first doped single crystal silicon, and the first insulating layer 2 and the first doped single crystal silicon layer are patterned using the initial mask layer 4.

[0126] The first doped monocrystalline silicon layer and the first insulating layer 2 are patterned onto the substrate 1, exposing the surface of the substrate 1 to form an initial via 5. The diameter of the initial via 5 is larger than the size of the first doped monocrystalline silicon layer in the second horizontal direction X2, which can also be understood as the diameter of the initial via 5 being larger than the width of the first doped monocrystalline silicon layer.

[0127] Setting the diameter of the initial via 5 to be greater than the width of the first doped single crystal silicon ensures that the first source-drain layer 302 formed in subsequent processes is located on opposite sides of the first channel 601, thus avoiding the interconnection between the source and drain in the first source-drain layer 302.

[0128] B6: A second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via 5.

[0129] In some embodiments, a second polysilicon layer 6 and a first gate dielectric layer 211 can be sequentially formed on the inner wall of the initial via 5 using a deposition process, such that the second polysilicon layer 6 surrounds the first gate dielectric layer 211. The formation processes of the second polysilicon layer 6 and the first gate dielectric layer 211 are the same as A6 in the above embodiments, and will not be repeated here.

[0130] B7: Heat-treat the second polysilicon layer 6 to form the first channel 601.

[0131] In some embodiments, the heat treatment temperature is 900 to 1200°C. Specifically, in addition to the two extreme values ​​mentioned above, the heat treatment temperature can also be 950°C, 1000°C, 1050°C, 1100°C, or 1150°C. Those skilled in the art can adjust it according to the actual situation, and no special limitation is made here.

[0132] In some other embodiments, the second polycrystalline silicon layer 6 may not be formed. Instead, the first channel 601 may be formed directly by continuing epitaxial growth on the surface of the first monocrystalline silicon layer, thus eliminating the need for subsequent heat treatment processes.

[0133] B8: Fill the initial via 5 where the first gate dielectric layer 211 is formed with the first gate 212, and the first gate 212 and the first gate dielectric layer 211 form the first gate portion 21.

[0134] The material and process for forming the first gate 212 can be the same as those in A8 of the above embodiments, and will not be repeated here.

[0135] After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21 and the first source-drain layer 302 located on opposite sides of the first channel 601 are formed into a first transistor, which can be one of an N-type transistor and a P-type transistor.

[0136] In some other embodiments, S412 may include the following contents C1 to C9.

[0137] C1: A first trench is formed in the substrate 1, extending along the first horizontal direction X1.

[0138] Specifically, a mask layer with a first trench pattern can be formed on the substrate 1, and the substrate 1 can be etched using the mask layer to form a first trench extending along a first horizontal direction X1 in the substrate 1.

[0139] C2: A first polycrystalline silicon layer is formed in the first trench.

[0140] After the first trench is formed, the mask layer can be left unremoved. A first polysilicon layer can be deposited in the first trench using a deposition process to fill the first trench, and then the mask layer can be removed.

[0141] C3: Doping the first polysilicon layer with either an N-type dopant ion or a P-type dopant ion to form the first doped polysilicon layer.

[0142] The first polysilicon layer is used to form the source and drain electrodes of the first transistor, and therefore needs to be doped. If the first transistor is an N-type transistor, the first polysilicon layer can be N-type doped, and the dopant can be phosphorus (P) or arsenic (As). If the first transistor is a P-type transistor, the first polysilicon layer can be P-type doped, and the dopant can be boron (B) or gallium (Ga). Doping can be performed using ion implantation or thermal diffusion processes, and no special limitation is made here.

[0143] C4: Remove portions of substrate 1 located on both sides of the first doped polysilicon layer, so that the first doped polysilicon layer protrudes from the remaining substrate.

[0144] A mask layer is formed on the surface of substrate 1, covering a portion of the first doped polysilicon layer. The uncovered portion of substrate 1 can be removed using an etching process, i.e., the portions of substrate 1 located on both sides of the first doped polysilicon layer are removed. The remaining portion of substrate 1 is lower than the first doped polysilicon layer in the vertical direction Y. The surface of the remaining portion of substrate 1 can be flush with the bottom surface of the first doped polysilicon layer, i.e., the first doped polysilicon layer protrudes from the remaining substrate 1.

[0145] C5: A first insulating layer is formed on the remaining substrate 1 located on both sides of the first doped polysilicon layer, the top surface of the first insulating layer being flush with the top surface of the first doped polysilicon layer.

[0146] The first doped polysilicon layer is masked, for example, using the mask layer in C4, or another mask layer is re-formed to mask the first doped polysilicon layer. The first insulating layer can then be formed on the remaining substrate 1 using a deposition process. The mask layer is then removed by chemical mechanical polishing (CMP) to remove the portion of the first insulating layer above the first doped polysilicon layer, making the top surface of the first insulating layer flush with the top surface of the first doped polysilicon layer.

[0147] C6: Pattern the first doped polysilicon layer and the first insulating layer onto the remaining surface of the substrate 1 to form an initial via. The diameter of the initial via is larger than the size of the first doped polysilicon layer in the second horizontal direction X2, which is perpendicular to the first horizontal direction X1.

[0148] You can refer to this. Figure 7 , Figure 8a and Figure 8bThe first doped polysilicon layer 301 and the first insulating layer 2 are patterned onto the remaining substrate 1, exposing the surface of the substrate 1 to form an initial via 5. The diameter of the initial via 5 is larger than the size of the first doped polysilicon layer 301 in the second horizontal direction X2, which can also be understood as the diameter of the initial via 5 being larger than the width of the first doped polysilicon layer 301.

[0149] Setting the diameter of the initial via 5 to be greater than the width of the first doped polysilicon ensures that the first source-drain layer 302 formed in subsequent processes is located on opposite sides of the first channel 601, thus avoiding the interconnection between the source and drain in the first source-drain layer 302.

[0150] C7: A second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via 5.

[0151] C8: Heat treatment of the first doped polysilicon layer 301 and the second polysilicon layer 6 to form the first source / drain layer 302 and the first channel 601, respectively.

[0152] C9: A first gate 212 is filled in the initial via 5 in which the first gate dielectric layer 211 is formed, and the first gate 212 and the first gate dielectric layer 211 form a first gate portion 21.

[0153] The process for C7 to C9 in this embodiment can be the same as that for A6 to A8 in the above embodiments, and will not be described again here.

[0154] After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21 and the first source-drain layer 302 located on opposite sides of the first channel 601 are formed into a first transistor, which can be one of an N-type transistor and a P-type transistor.

[0155] In some other embodiments, S412 may include the following contents D1 to D8.

[0156] D1: A first masking layer is formed on the substrate 1. The first masking layer has a first trench pattern extending along a first horizontal direction X1, and the substrate 1 is exposed at the first trench pattern.

[0157] Specifically, a first masking layer and a photoresist layer can be formed sequentially on the substrate 1. A first trench pattern is formed on the photoresist layer using a photolithography process. Then, the first masking layer is patterned using an etching process to transfer the first trench pattern into the first masking layer and expose the substrate 1.

[0158] D2: Doping the exposed substrate 1 with either an N-type dopant ion or a P-type dopant ion to form a doped substrate.

[0159] After exposing substrate 1, a first masking layer is retained to shield other parts of substrate 1. The exposed portion of substrate 1 is doped with either N-type or P-type dopant ions. This doped portion of substrate 1 is used to form the first source / drain layer 302 in subsequent processes. Therefore, in this embodiment, the material of substrate 1 can be single-crystal silicon. After doping, the exposed substrate 1 forms a first doped single-crystal silicon layer.

[0160] Doping can be performed using ion implantation or thermal diffusion processes, and the implantation depth can be adjusted by changing the concentration of implanted ions and process parameters.

[0161] D3: Remove portions of substrate 1 located on both sides of the first doped single-crystal silicon layer, so that the first doped single-crystal silicon layer protrudes beyond the remaining substrate 1.

[0162] Specifically, the first masking layer is removed, and a second masking layer is formed on the first doped single-crystal silicon layer to mask the first doped single-crystal silicon layer. The exposed portion of the substrate 1 can be etched using an etching process, and the surface of the remaining substrate 1 can be flush with the bottom surface of the first doped single-crystal silicon layer, that is, the first doped single-crystal silicon layer protrudes from the remaining substrate 1.

[0163] D4: A first insulating layer 2 is formed on the remaining substrate 1 located on both sides of the first doped single-crystal silicon layer, and the top surface of the first insulating layer 2 is flush with the top surface of the first doped single-crystal silicon layer.

[0164] By retaining the second masking layer to shield the first doped monocrystalline silicon layer, a first insulating layer 2 can be formed on the remaining substrate 1 using a deposition process. Afterwards, the second masking layer is removed, and the portion of the first insulating layer 2 above the first doped monocrystalline silicon layer can be removed using a chemical mechanical polishing process, making the top surface of the first insulating layer 2 flush with the top surface of the first doped monocrystalline silicon layer.

[0165] D5: Pattern the first doped monocrystalline silicon layer and the first insulating layer 2 onto the remaining substrate 1 surface to form an initial via 5. The diameter of the initial via 5 is larger than the size of the first doped polycrystalline silicon layer 301 in the second horizontal direction X2.

[0166] The first doped monocrystalline silicon layer and the first insulating layer 2 are patterned onto the remaining substrate 1, exposing the surface of the remaining substrate 1 to form an initial via 5. The diameter of the initial via 5 is larger than the size of the first doped monocrystalline silicon layer in the second horizontal direction X2, which can also be understood as the diameter of the initial via 5 being larger than the width of the first doped monocrystalline silicon layer.

[0167] Setting the diameter of the initial via 5 to be greater than the width of the first doped single crystal silicon ensures that the first source-drain layer 302 formed in subsequent processes is located on opposite sides of the first channel 601, thus avoiding the interconnection between the source and drain in the first source-drain layer 302.

[0168] D6: A second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via 5.

[0169] D7: Heat-treat the second polysilicon layer 6 to form the first channel 601.

[0170] D8: A first gate 212 is filled in the initial via 5 in which the first gate dielectric layer 211 is formed, and the first gate 212 and the first gate dielectric layer 211 form a first gate portion 21.

[0171] The process steps in D6 to D8 of this embodiment can be the same as those in B6 to B8 of the above embodiment, and will not be repeated here. After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layers 302 located on opposite sides of the first channel 601 are formed into a first transistor. The first transistor can be one of an N-type transistor and a P-type transistor.

[0172] All of the above-described embodiments can form a first transistor. Those skilled in the art can choose according to the actual situation, and no special limitation is made here.

[0173] S413: An isolation layer 7 with a first via 9 is formed on the first channel 601 and the first source-drain layer 302, the first via 9 corresponding to the first gate portion 21 in the vertical direction Y.

[0174] Specifically, S413 includes the following contents E1 to E2.

[0175] E1: An isolation layer 7 is formed on the first gate portion 21, the first channel 601, the first source-drain layer 302 and the first insulating layer 2.

[0176] After the first transistor is formed, an isolation layer 7 is deposited on the first transistor to insulate it from the subsequently formed second transistor. Specifically, as shown... Figure 15 , Figure 16a and Figure 16b As shown, an isolation layer 7 can be formed on the first insulating layer 2 and the first transistor using a deposition process.

[0177] In some embodiments, the material of the insulating layer 7 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0178] E2: The patterned isolation layer 7 extends to the first gate portion 21 to form the first via 9.

[0179] like Figure 17 , Figure 18a and Figure 18bAs shown, a first mask layer 8 with a first via pattern is formed on the isolation layer 7, and the edge of the first via pattern is aligned with the outer edge of the first gate dielectric layer 211 in the vertical direction Y. Figure 19 , Figure 20a and Figure 20b As shown, the isolation layer 7 is patterned to form a first via 9, which corresponds to the first gate portion 21 in the vertical direction Y, exposing the first gate 212 and the first gate dielectric layer 211.

[0180] Of course, after patterning the isolation layer 7, the first via 9 can also expose the first channel 601, and then an insulating layer is formed above the first channel 601 in the first via 9. The material of the insulating layer can be the same as or different from the material of the isolation layer 7. Since a thinner insulating layer is formed separately, the insulating layer is more dense, which is beneficial for forming the second gate dielectric layer 221 in subsequent processes.

[0181] S414: A second gate portion 22 is formed in the first through hole 9.

[0182] Specifically, S414 includes the following contents F1 to F2.

[0183] F1: A second gate dielectric layer 221 is formed on the inner wall of the first through hole 9.

[0184] like Figure 21 , Figure 22a and Figure 22b As shown, a second gate dielectric layer 221 can be formed on the inner wall of the first through-hole 9 and the isolation layer 7 using a deposition process.

[0185] F2: A second gate 222 is filled in the first via 9 in which a second gate dielectric layer 221 is formed, and the second gate dielectric layer 221 and the second gate 222 form a second gate portion 22.

[0186] like Figure 23 , Figure 24a and Figure 24b As shown, a second gate 222 is filled into the first via 9, where a second gate dielectric layer 221 is formed, using a deposition process. The second gate dielectric layer 221 and the second gate 222 located on the surface of the isolation layer 7 can be removed using a chemical mechanical polishing process, making the top surfaces of the second gate dielectric layer 221 and the second gate 222 in the first via 9 flush with the top surface of the isolation layer 7. The second gate dielectric layer 221 and the second gate 222 form a second gate portion 22. The second gate portion 22 is connected to the first gate portion 21 and will subsequently be connected to the third gate portion 23 of the second transistor to form a gate structure 20.

[0187] In some embodiments, the second gate dielectric layer 221 may be made of the same material as the first gate dielectric layer 211, and the second gate 222 may be made of the same material as the first gate 212, so as to avoid changing materials in the fabrication process, simplify the process, and save costs.

[0188] S415: A third gate portion 23 is formed on the second gate portion 22, and a second channel 1501 surrounding the third gate portion 23 and a second source-drain layer 1202 located on opposite sides of the second channel 1501 are formed on the isolation layer 7 to form a second transistor; wherein, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor.

[0189] Specifically, S415 may include the following contents G1 to G8.

[0190] G1: A second insulating layer 10 is formed on the isolation layer 7 and the second gate portion 22.

[0191] In some embodiments, such as Figure 25 , Figure 26a and Figure 26b As shown, a second insulating layer 10 can be formed using a deposition process. The material of the second insulating layer 10 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the second insulating layer 10 can be the same as that of the first insulating layer 2, avoiding the need to change materials during the fabrication process, thereby simplifying the process and saving costs.

[0192] G2: A second trench 1001 extending along the first horizontal direction X1 is formed in the second insulating layer 10, exposing the second gate 222.

[0193] like Figure 25 , Figure 26a and Figure 26b As shown, a second mask layer 11 can be formed on the second insulating layer 10 with a second trench pattern extending along the first horizontal direction X1, such as... Figure 27 , Figure 28a and Figure 28b As shown, the second mask layer 11 is used to etch the second insulating layer 10 to form a second trench 1001 in the second insulating layer 10, exposing the second gate 222.

[0194] G3: A third polysilicon layer 12 is filled in the second trench 1001.

[0195] like Figure 29 , Figure 30a and Figure 30bAs shown, a third polysilicon layer 12 can be deposited in the second trench 1001 using a deposition process, and the third polysilicon layer 12 fills the first trench 201. After the third polysilicon layer 12 is formed, a chemical mechanical polishing process can be used to remove the third polysilicon layer 12 above the surface of the second insulating layer 10, so that the top surface of the third polysilicon layer 12 is flush with the top surface of the second insulating layer 10.

[0196] G4: Doping the third polysilicon layer 12 with another type of N-type dopant ion and P-type dopant ion to form the third doped polysilicon layer 1201.

[0197] like Figure 30a and Figure 30b As shown, the third polysilicon layer 12 is used to form the source and drain of the second transistor, and therefore needs to be doped. If the second transistor is an N-type transistor, the third polysilicon layer 12 can be N-type doped, and the dopant can be phosphorus (P) or arsenic (As). If the second transistor is a P-type transistor, the third polysilicon layer 12 can be P-type doped, and the dopant can be boron (B) or gallium (Ga). Ion implantation or thermal diffusion processes can be used for doping; no special limitations are specified here.

[0198] G5: Pattern the third doped polysilicon layer 1201 and the second insulating layer 10 to the second gate portion 22 and the isolation layer 7 to form a second via 14, the diameter of the second via 14 being larger than the size of the third doped polysilicon layer 1201 in the second horizontal direction X2.

[0199] like Figure 31 , Figure 32a and Figure 32b As shown, a third mask layer 13 with a second via pattern is formed on the second insulating layer 10 and the third doped polysilicon layer 1201, and the second insulating layer 10 and the third doped polysilicon layer 1201 are patterned using the third mask layer 13.

[0200] like Figure 33 , Figure 34a and Figure 34b As shown, the third doped polysilicon layer 1201 and the second insulating layer 10 are patterned to the second gate portion 22 and the isolation layer 7 to form a second via 14. The diameter of the second via 14 is larger than the size of the third doped polysilicon layer 1201 in the second horizontal direction X2, which can also be understood as the diameter of the second via 14 being larger than the width of the third doped polysilicon layer 1201.

[0201] Setting the diameter of the second via 14 to be greater than the width of the third doped polysilicon ensures that the second source-drain layer 1202 formed in subsequent processes is located on opposite sides of the second channel 1501, thus avoiding the interconnection between the source and drain in the second source-drain layer 1202.

[0202] G6: A fourth polysilicon layer 15 and a third gate dielectric layer 231 are sequentially formed on the inner wall of the second via 14.

[0203] like Figure 35 , Figure 36a and Figure 36b As shown, a fourth polysilicon layer 15 can be formed on the inner wall of the second via 14, the second insulating layer 10, and the third doped polysilicon layer 1201 using a deposition process. A third gate dielectric layer 231 is formed on the fourth polysilicon layer 15, i.e., the fourth polysilicon layer 15 surrounds the third gate dielectric layer 231. Then, the fourth polysilicon layer 15 and the third gate dielectric layer 231 located on the second insulating layer 10 and the third doped polysilicon layer 1201 can be removed using a chemical mechanical polishing process, leaving only the fourth polysilicon layer 15 and the third gate dielectric layer 231 located on the inner wall of the second via 14.

[0204] G7: A third gate 232 is filled in the second via 14 where a third gate dielectric layer 231 is formed, and the third gate 232 and the third gate dielectric layer 231 form a third gate portion 23.

[0205] like Figure 37 , Figure 38a and Figure 38b As shown, the third gate 232 can be filled into the second via 14, where the third gate dielectric layer 231 is formed, using a deposition process. For the third gate 232 that protrudes above the surface of the second insulating layer 10 and is deposited on the surface of the second insulating layer 10, the third gate 232 on the surface of the second insulating layer 10 can be removed using a chemical mechanical polishing process after the deposition process, and the top surface of the third gate 232 in the second via 14 can be processed to be flush with the surface of the second insulating layer 10. The third gate 232 and the third gate dielectric layer 231 form the third gate portion 23.

[0206] In some embodiments, the material of the third gate 232 may include at least one of polysilicon, tungsten, aluminum, copper, titanium nitride, tantalum nitride, and silicide, without limitation herein. The material of the third gate 232 may be the same as that of the first gate 212 and the second gate 222, and the material of the third gate dielectric layer 231 may be the same as that of the first gate dielectric layer 211 and the second gate dielectric layer 221, so as to avoid changing materials in the fabrication process, simplify the process, and save costs.

[0207] G8: Heat treatment of the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 to form the second source / drain layer 1202 and the second channel 1501, respectively.

[0208] like Figure 39 , Figure 40a and Figure 40bAs shown, the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 are heat-treated to form monocrystalline silicon, that is, the third doped polysilicon layer 1201 is formed into a third doped monocrystalline silicon layer, which is then formed into a second source / drain layer 1202, and the fourth polysilicon layer 15 is formed into a fourth monocrystalline silicon layer, which is then formed into a second channel 1501.

[0209] In some embodiments, the heat treatment temperature is 900 to 1200°C. Specifically, in addition to the two extreme values ​​mentioned above, the heat treatment temperature can also be 950°C, 1000°C, 1050°C, 1100°C, or 1150°C. Those skilled in the art can adjust it according to the actual situation, and no special limitation is made here.

[0210] Alternatively, G8 can be performed first, followed by G7. That is, the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 are first heat-treated to form the second source / drain layer 1202 and the second channel 1501, respectively. Then, the third gate 232 is filled into the second via 14 where the third gate dielectric layer 231 is formed, so that the third gate 232 and the third gate dielectric layer 231 form the third gate portion 23. Those skilled in the art can choose according to the actual situation; no special limitation is made here.

[0211] like Figure 40a and Figure 40b As shown, after the above process, the third gate portion 23, the second channel 1501 surrounding the third gate portion 23, and the second source-drain layers 1202 located on opposite sides of the second channel 1501 form a second transistor. This second transistor can be either an N-type transistor or a P-type transistor. Thus, this embodiment of the present disclosure provides a channel-around-gate structure that enables NMOS and PMOS to share the same gate and channel area. By adjusting the voltage at each terminal, NMOS and PMOS can operate separately, effectively halving the transistor footprint and doubling the area density, further breaking the limits of Moore's Law.

[0212] In summary, the transistor structure prepared by the method of this embodiment has the first transistor and the second transistor distributed in the vertical direction Y and sharing the same gate structure 20. This avoids placing the first transistor and the second transistor side by side in the horizontal direction, reduces the occupied area by half, doubles the density of the transistor structure, and improves the electrical performance of the transistor structure.

[0213] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A transistor structure, characterized in that, include: Substrate; A gate structure is disposed on the substrate, and in a direction perpendicular to and away from the substrate, the gate structure has a first gate portion, a second gate portion and a third gate portion arranged in sequence. A first channel is disposed on the substrate and surrounds the outer surface of the first gate portion; A first source / drain layer is disposed on the substrate and connected to the opposite sides of the first channel; An isolation layer covers the first channel and the first source / drain layer, and surrounds the outer surface of the second gate portion; The second channel is disposed on the isolation layer and surrounds the outer surface of the third gate portion; The second source-drain layer is disposed on the isolation layer and connected to the opposite sides of the second channel; Wherein, the first gate portion, the first channel, and the first source-drain layer of the gate structure constitute a first transistor, and the third gate portion, the second channel, and the second source-drain layer of the gate structure constitute a second transistor; One of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.

2. The transistor structure according to claim 1, characterized in that, The gate structure includes a gate and a gate dielectric layer, the gate dielectric layer being disposed around the outer surface of the gate.

3. The transistor structure according to claim 1, characterized in that, The first source-drain layer includes a first source portion and a first drain portion, wherein the first source portion is connected to one side of the first channel and the first drain portion is connected to the opposite side of the first channel; The second source-drain layer includes a second source portion and a second drain portion, wherein the second source portion is connected to one side of the second channel and the second drain portion is connected to the opposite side of the second channel.

4. A method for fabricating a transistor structure, characterized in that, include: Provide substrate; A first transistor is formed on the substrate by forming a first gate portion, a first channel surrounding the first gate portion, and first source-drain layers located on opposite sides of the first channel. An isolation layer with a first via is formed on the first channel and the first source / drain layer, wherein the first via corresponds to the first gate portion in the vertical direction; A second gate portion is formed in the first through-hole; A third gate portion is formed on the second gate portion, and a second channel surrounding the third gate portion and second source-drain layers located on opposite sides of the second channel are formed on the isolation layer to form a second transistor; wherein, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor.

5. The method according to claim 4, characterized in that, A first transistor is formed on the substrate by forming a first gate portion, a first channel surrounding the first gate portion, and first source / drain layers located on opposite sides of the first channel, comprising: A first insulating layer is formed on the substrate; A first trench extending in a first horizontal direction is formed in the first insulating layer; A first polycrystalline silicon layer is formed in the first trench; Doping the first polysilicon layer with one of N-type dopant ions and P-type dopant ions to form a first doped polysilicon layer; The first doped polysilicon layer and the first insulating layer are patterned onto the substrate to form an initial via. The diameter of the initial via is larger than the size of the first doped polysilicon layer in a second horizontal direction, which is perpendicular to the first horizontal direction. A second polysilicon layer and a first gate dielectric layer are sequentially formed on the inner wall of the initial via; The first doped polysilicon layer and the second polysilicon layer are heat-treated to form the first source / drain layer and the first channel, respectively. A first gate is filled in the initial via where the first gate dielectric layer is formed, and the first gate and the first gate dielectric layer form the first gate portion.

6. The method according to claim 4, characterized in that, A first transistor is formed on the substrate by forming a first gate portion, a first channel surrounding the first gate portion, and first source / drain layers located on opposite sides of the first channel, comprising: A first insulating layer is formed on the substrate; A first trench extending in a first horizontal direction is formed in the first insulating layer; A first single-crystal silicon layer is epitaxially grown in the first trench; Doping the first single-crystal silicon layer with one of N-type dopant ions and P-type dopant ions to form a first doped single-crystal silicon layer; The first doped single-crystal silicon layer and the first insulating layer are patterned onto the substrate to form an initial via. The first doped single-crystal silicon layer is formed as the first source-drain layer. The diameter of the initial via is larger than the size of the first doped single-crystal silicon layer in the second horizontal direction, which is perpendicular to the first horizontal direction. A second polysilicon layer and a first gate dielectric layer are sequentially formed on the inner wall of the initial via; The second polysilicon layer is heat-treated to form the first channel; A first gate is filled into the initial via where the first gate dielectric layer is formed, and the first gate and the first gate dielectric layer form the first gate portion.

7. The method according to claim 4, characterized in that, A first transistor is formed on the substrate by forming a first gate portion, a first channel surrounding the first gate portion, and first source / drain layers located on opposite sides of the first channel, comprising: A first trench extending along a first horizontal direction is formed in the substrate; A first polycrystalline silicon layer is formed in the first trench; Doping the first polysilicon layer with one of N-type dopant ions and P-type dopant ions to form a first doped polysilicon layer; Remove portions of the substrate located on both sides of the first doped polysilicon layer, so that the first doped polysilicon layer protrudes from the remaining substrate; A first insulating layer is formed on the remaining substrate located on both sides of the first doped polysilicon layer, the top surface of the first insulating layer being flush with the top surface of the first doped polysilicon layer. The first doped polysilicon layer and the first insulating layer are patterned onto the remaining surface of the substrate to form an initial via. The diameter of the initial via is larger than the size of the first doped polysilicon layer in a second horizontal direction, which is perpendicular to the first horizontal direction. A second polysilicon layer and a first gate dielectric layer are sequentially formed on the inner wall of the initial via; The first doped polysilicon layer and the second polysilicon layer are heat-treated to form the first source / drain layer and the first channel, respectively. A first gate is filled in the initial via where the first gate dielectric layer is formed, and the first gate and the first gate dielectric layer form the first gate portion.

8. The method according to any one of claims 5 to 7, characterized in that, An isolation layer with a first via is formed on the first channel and the first source / drain layer, comprising: An isolation layer is formed on the first gate portion, the first channel, the first source-drain layer and the first insulating layer; The isolation layer is patterned onto the first gate portion to form the first via.

9. The method according to claim 5, characterized in that, A second gate portion is formed in the first through-hole, including: A second gate dielectric layer is formed on the inner wall of the first through hole; A second gate is filled in the first via where the second gate dielectric layer is formed, and the second gate dielectric layer and the second gate form the second gate portion.

10. The method according to claim 9, characterized in that, A third gate portion is formed on the second gate portion, and a second channel surrounding the third gate portion and second source / drain layers located on opposite sides of the second channel are formed on the isolation layer to form a second transistor, comprising: A second insulating layer is formed on the isolation layer and on the second gate portion; A second trench extending along a first horizontal direction is formed in the second insulating layer, exposing the second gate; A third polysilicon layer is filled into the second trench; Doping the third polysilicon layer with another of the N-type dopant ions and the P-type dopant ions to form a third doped polysilicon layer; The third doped polysilicon layer and the second insulating layer are patterned to the second gate portion and the isolation layer to form a second via. The diameter of the second via is larger than the size of the third doped polysilicon layer in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction. A fourth polysilicon layer and a third gate dielectric layer are sequentially formed on the inner wall of the second via; A third gate is filled in the second via in which the third gate dielectric layer is formed, and the third gate and the third gate dielectric layer form the third gate portion; The third doped polysilicon layer and the fourth polysilicon layer are heat-treated to form the second source / drain layer and the second channel, respectively.

11. The method according to any one of claims 5 to 7 and 10, characterized in that, The heat treatment temperature is 900~1200℃.

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