An integrated CMOS device structure and fabrication method
By vertically integrating high electron mobility transistors with carbon nanotube devices in CMOS devices, the problem of insufficient electron and hole mobility in existing technologies is solved, realizing high-switching-speed N-channel and P-channel devices, saving chip area, and suitable for small-size, high-speed, radiation-resistant digital logic circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-06-27
- Publication Date
- 2026-07-31
AI Technical Summary
Existing CMOS devices cannot simultaneously achieve high electron and hole movement velocities, resulting in reduced saturation drain current levels and limited switching speeds.
By vertically integrating high electron mobility transistors and carbon nanotube devices, and connecting their gates and drains through an electrical isolation layer and a connecting metal, heterogeneous integration of NMOS and PMOS transistors is achieved.
High electron and hole movement speeds are achieved on a single substrate, improving switching speed and significantly saving chip area, making it suitable for small-size, high-speed, radiation-resistant digital logic circuits.
Smart Images
Figure CN116705798B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radio frequency application technology, specifically relating to an integrated CMOS device structure and fabrication method. Background Technology
[0002] III-V compound semiconductors, such as GaN, GaAs, and InP, are second- and third-generation semiconductors with advantages including high electron mobility, wide bandgap with a large continuously modulated range, good uniformity in large-size crystals, good lattice matching, low power consumption, and relatively simple fabrication processes. However, in the post-Moore's Law era, the semiconductor industry faces enormous technical and engineering challenges, while the demand for data computing and storage capabilities in the information society is increasing daily. Therefore, while struggling to develop silicon-based technology, the semiconductor field is also paying increasing attention to new materials and devices to extend Moore's Law. Among many new material structures, carbon nanotubes (CNTs) have also attracted widespread attention due to their unique quasi-one-dimensional structure and excellent electrical properties.
[0003] Existing single semiconductor materials struggle to simultaneously achieve high electron and hole movement velocities, thus limiting the development of semiconductor logic units and digital chips towards higher speeds. Traditional silicon-based III-V compound semiconductor devices, such as GaNHEMT, are primarily used to fabricate P-type substrate N-channel NMOS devices, which offer high device mobility and therefore superior frequency characteristics, enabling their application in high-frequency, high-power fields. Carbon-based materials, however, are more advantageous in realizing N-type substrate P-channel PMOS devices. Therefore, employing the fusion and heterogeneous integration technology of III-V semiconductors and carbon-based materials can simultaneously realize N-channel and P-channel devices with high switching speeds, making it an excellent choice for realizing high-speed, radiation-hardened digital circuits.
[0004] The existing methods for realizing carbon nanotube CMOS integrated circuits mainly include the following. In 2009, Peng Lianmao's research group achieved a doping-free method on the same Si substrate, using Pd contacts to realize P-type transistors and Sc contacts to realize N-type transistors, with symmetrical performance matching between P-type and N-type transistors, thus enabling lateral realization of CMOS integrated circuits on the substrate. Another method for realizing carbon nanotube CMOS circuits involves using metal contacts with different work functions, using Pt contacts to realize P-type transistors and Ti contacts to realize N-type transistors; and electrically doping the channel with SiO2. x To achieve p-type doping, use HfO x Achieve N-type doping.
[0005] Compared to carbon nanotubes, GaN materials have higher hole mobility. Therefore, although GaN can be used to manufacture PMOS transistors, its advantages cannot be fully realized due to the relatively low hole mobility of PMOS transistors. Thus, other materials, such as silicon or carbon nanotubes, are typically used to manufacture PMOS transistors. Furthermore, existing CMOS devices cannot simultaneously possess the high switching speeds of both N-channel and P-channel devices, and traditional integration methods result in larger chip areas and lower performance.
[0006] In summary, existing single semiconductor materials cannot simultaneously achieve high electron and hole movement velocities in the same device, thereby reducing the device's saturation drain current level and affecting the device's switching speed. Summary of the Invention
[0007] To address the aforementioned problems in the prior art, this invention provides an integrated CMOS device structure and fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0008] This invention provides an integrated CMOS device structure, comprising: a first device, a second device, an electrical isolation layer, a first interconnect metal, and a second interconnect metal, wherein...
[0009] The first device includes a III-V compound high electron mobility transistor, and the second device includes a carbon nanotube device;
[0010] The electrical isolation layer covers the surfaces of the source, drain, and gate of the first device;
[0011] The second device is flip-chip bonded to the electrical isolation layer;
[0012] The first connecting metal penetrates the electrical isolation layer to connect the gate of the first device and the gate of the second device;
[0013] The second connecting metal penetrates the electrical isolation layer to connect the drain of the first device and the drain of the second device;
[0014] The source of the first device is led out from the substrate side of the first device through a metal electrode; the source of the first device is used to connect to the ground terminal;
[0015] The source, drain, and gate of the second device are all led out from the substrate side of the second device through metal electrodes; the source of the second device is used to connect to the power supply terminal, the gate is used as the input terminal, and the drain is used as the output terminal.
[0016] In one embodiment of the present invention, the high electron mobility transistor includes a first substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first source, a first drain, a first gate, and a passivation layer, wherein,
[0017] The first substrate, the nucleation layer, and the buffer layer are stacked sequentially; the first source is located at one end of the surface of the buffer layer; the first drain is located at the other end of the surface of the buffer layer; the channel layer and the barrier layer are stacked on the buffer layer between the first source and the first drain; the passivation layer covers the surfaces of the barrier layer, the first source, and the first drain; the first gate is located between the first source and the first drain, and is located on the surface of the barrier layer and the surface of the passivation layer.
[0018] In one embodiment of the present invention, the carbon nanotube device includes a second substrate, a substrate base, a carbon nanotube array, a second source, a second drain, a dielectric layer, and a second gate, wherein,
[0019] The second substrate and the substrate are stacked sequentially, and the carbon nanotube array is distributed in an array on the substrate; the second source is located at one end of the surface of the carbon nanotube array; the second drain is located at the other end of the surface of the carbon nanotube array; the dielectric layer covers a portion of the surface of the second source, a portion of the surface of the second drain, and the surface of the carbon nanotube array between the second source and the second drain; the second gate is located on the surface of the dielectric layer between the second source and the second drain.
[0020] In one embodiment of the present invention, the material of the electrical isolation layer includes SiO2 or Al2O3, and the thickness is 2 to 5 μm.
[0021] Another embodiment of the present invention provides a method for fabricating an integrated CMOS device structure, comprising the steps of:
[0022] Fabricate a first device, wherein the first device comprises a III-V compound high electron mobility transistor;
[0023] An electrical isolation layer is fabricated on the first device such that the electrical isolation layer covers the surfaces of the source, drain, and gate of the first device;
[0024] The electrical isolation layer at the gate position of the first device is etched to form a first via, and the electrical isolation layer at the drain position of the first device is etched to form a second via;
[0025] Fabricate a second device, wherein the second device includes a carbon nanotube device;
[0026] A first connecting metal is prepared in the first through hole, and a second connecting metal is prepared in the second through hole;
[0027] The second device is inverted and bonded to the electrical isolation layer, such that the first connection metal connects the gate of the first device and the gate of the second device, and the second connection metal connects the drain of the first device and the drain of the second device.
[0028] A third via is etched from the substrate side of the first device to the source of the first device, a fourth via is etched from the substrate side of the second device to the source of the second device, a fifth via is etched to the drain of the second device, and a sixth via is etched to the gate of the second device.
[0029] A metal electrode is fabricated in the third via to bring out the source of the first device, and the source of the first device is used to connect to the ground terminal; metal electrodes are fabricated in the fourth, fifth and sixth vias to bring out the source, drain and gate of the second device, and the source of the second device is used to connect to the power supply terminal, the gate is used as the input terminal and the drain is used as the output terminal.
[0030] In one embodiment of the present invention, the fabrication of the first device includes the following steps:
[0031] A first substrate is provided, wherein the first substrate includes a first substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially;
[0032] A first source is fabricated at one end of the buffer layer and a first drain is fabricated at the other end, such that the channel layer and the barrier layer are located between the first source and the first drain.
[0033] Create electrical isolation for the active region;
[0034] A passivation layer is prepared on the surface of the barrier layer, the first source electrode, and the first drain electrode;
[0035] A first gate is fabricated between the first source and the first drain, such that the first gate is located on the surface of the barrier layer and the surface of the passivation layer.
[0036] In one embodiment of the present invention, an electrical isolation layer is fabricated on the first device such that the electrical isolation layer covers the surfaces of the source, drain, and gate of the first device, including:
[0037] Using plasma-enhanced chemical vapor deposition, a SiO2 dielectric with a thickness of 2–5 μm is deposited on the first device, so that the SiO2 dielectric covers the surfaces of the source, drain, and gate of the first device, forming the electrical isolation layer.
[0038] In one embodiment of the present invention, an electrical isolation layer is fabricated on the first device such that the electrical isolation layer covers the surfaces of the source, drain, and gate of the first device, including:
[0039] Using plasma atomic layer deposition (PAD), an Al2O3 dielectric with a thickness of 2–5 μm is deposited on the first device, so that the Al2O3 dielectric covers the surfaces of the source, drain, and gate of the first device, forming the electrical isolation layer.
[0040] In one embodiment of the present invention, the fabrication of the second device includes the following steps:
[0041] A second substrate is provided, wherein the second substrate includes a second substrate and a substrate substrate stacked sequentially;
[0042] Provides carbon nanotubes free of impurities and amorphous carbon;
[0043] Electrophoresis is used to form a carbon nanotube array on the substrate.
[0044] A second source electrode is fabricated at one end of the carbon nanotube array, and a second drain electrode is fabricated at the other end.
[0045] A dielectric layer is prepared on a portion of the surface of the second source electrode, a portion of the surface of the second drain electrode, and the surface of the carbon nanotube array between the second source electrode and the second drain electrode;
[0046] A second gate is formed on the surface of the dielectric layer between the second source and the second drain.
[0047] In one embodiment of the present invention, an electrophoresis method is used to form a carbon nanotube array on the substrate, including the following steps:
[0048] An array pattern is formed on the substrate.
[0049] Electrodes are fabricated on a substrate with an arrayed pattern;
[0050] The device was immersed in a function generator containing a carbon nanotube suspension, and a voltage was applied to prepare a carbon nanotube array.
[0051] The electrophoretic electrode is wet-etched so that the carbon nanotube array is attached to the substrate.
[0052] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0053] The integrated CMOS device structure of this invention integrates high electron mobility transistors and carbon nanotube devices in a vertical direction, with an electrical isolation layer between them. The gates of the high electron mobility transistors and carbon nanotube devices are connected by a connecting metal, and the drains are connected by a connecting metal. The high electron mobility transistors realize NMOS transistors, and the carbon nanotube devices realize PMOS transistors. This heterogeneous integration structure achieves high electron and hole mobility on a single substrate, resulting in N-channel and P-channel devices with high switching speeds. At the same time, the vertical integration significantly saves chip area. Therefore, this integrated CMOS device structure can realize small-size, high-speed, radiation-resistant digital logic circuits. Attached Figure Description
[0054] Figure 1 A schematic diagram of an integrated CMOS device structure provided in an embodiment of the present invention;
[0055] Figure 2 The circuit logic diagram of the CMOS device provided in the embodiments of the present invention;
[0056] Figure 3 This is a schematic diagram of the structure of a high electron mobility transistor provided in an embodiment of the present invention;
[0057] Figure 4 This is a schematic diagram of the structure of a carbon nanotube device provided in an embodiment of the present invention;
[0058] Figure 5 A schematic flowchart illustrating the fabrication method of the integrated CMOS device structure provided in an embodiment of the present invention;
[0059] Figure 6 This is a schematic diagram illustrating the process of fabricating an integrated CMOS device structure according to an embodiment of the present invention. Detailed Implementation
[0060] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0061] Example 1
[0062] Please see Figure 1 , Figure 1 This is a schematic diagram of an integrated CMOS device structure provided in an embodiment of the present invention.
[0063] The integrated CMOS device structure includes a first device 1, a second device 2, an electrical isolation layer 3, a first connection metal 4, and a second connection metal 5. The first device 1 includes a III-V compound high electron mobility transistor, and the second device 2 includes a carbon nanotube device. The electrical isolation layer 3 covers the surfaces of the source, drain, and gate of the first device 1. The second device 2 is flip-chip bonded to the electrical isolation layer 3. The first connection metal 4 penetrates the electrical isolation layer 3 to connect the gate of the first device 1 and the gate of the second device 2. The second connection metal 5 penetrates the electrical isolation layer 3 to connect the drain of the first device 1 and the drain of the second device 2. The source of the first device 1 is led out from the substrate side of the first device 1 through a metal electrode; the source of the first device 1 is used to connect to the ground terminal. The source, drain, and gate of the second device 2 are all led out from the substrate side of the second device 2 through metal electrodes. The source of the second device 2 is used to connect to the power supply terminal, the gate is used as the input terminal, and the drain is used as the output terminal.
[0064] Specifically, the first device 1 is an NMOS transistor with a source, drain, and gate, including but not limited to III-V compound high electron mobility transistors. The second device 2 is a PMOS transistor with a source, drain, and gate, including but not limited to carbon nanotube devices. An electrical isolation layer 3 is located between the source, drain, and gate of the first device 1 and the source, drain, and gate of the second device, thereby vertically bonding and integrating the first device 1 and the second device 2, and achieving electrical isolation between the first device 1 and the second device 2, forming a CMOS device with both N-channel and P-channel high switching speeds.
[0065] Please see Figure 2 , Figure 2 The circuit logic diagram of the CMOS device provided for the embodiments of the present invention. Figure 2 In a CMOS device, two MOS devices are used: an N-channel NMOS transistor on top and a P-channel PMOS transistor on the bottom. The gates of the two MOS transistors are connected together as the input terminal Ain; the drains of the two MOS transistors are connected together as the output terminal Yout; the source of the NMOS transistor is connected to the power supply terminal VDD; and the source of the PMOS transistor is connected to the ground terminal GND.
[0066] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a high electron mobility transistor provided in an embodiment of the present invention. Figure 3 In the high electron mobility transistor, a first substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, a first source 106, a first drain 107, a first gate 108, and a passivation layer 109 are included.
[0067] The first substrate 101, nucleation layer 102, and buffer layer 103 are stacked sequentially. A first source 106 is located at one end of the surface of the buffer layer 103; a first drain 107 is located at the other end of the surface of the buffer layer 103. A channel layer 104 and a barrier layer 105 are stacked on the buffer layer 103 between the first source 106 and the first drain 107. A passivation layer 109 covers the surfaces of the barrier layer 105, the first source 106, and the first drain 107. A first gate 108 is located between the first source 106 and the first drain 107, and is situated on the surfaces of the barrier layer 105 and the passivation layer 109.
[0068] Specifically, the first gate 108 is a T-shaped gate structure, including a gate lead and a gate cap. The gate lead extends through the passivation layer 109 to the surface of the barrier layer 105, and the gate cap is located on the surface of the passivation layer 109 and the surface of the gate cap.
[0069] Specifically, the material of the first substrate 101 includes one or more of Si, SiC, and sapphire substrate; the material of the nucleation layer 102 includes AlN; the material of the buffer layer 103 includes GaN; the material of the channel layer 104 includes one or more of GaN, GaAs, and InP; the material of the barrier layer 105 includes one or more of AlN, AlGaN, and InAlN; the materials of the first source 106 and the first drain 107 include stacked Ti, Al, N, and Au; the material of the first gate 108 includes stacked Ni and Au; and the material of the passivation layer 109 includes SiN.
[0070] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a carbon nanotube device provided in an embodiment of the present invention. Figure 4 In the process, the carbon nanotube device includes a second substrate 201, a substrate 202, a carbon nanotube array 203, a second source 204, a second drain 205, a dielectric layer 206, and a second gate 207.
[0071] In this design, a second substrate 201 and a substrate 202 are stacked sequentially, and a carbon nanotube array 203 is arrayed on the substrate 202. A second source electrode 204 is located at one end of the surface of the carbon nanotube array 203; a second drain electrode 205 is located at the other end of the surface of the carbon nanotube array 203. A dielectric layer 206 covers a portion of the surface of the second source electrode 204, a portion of the surface of the second drain electrode 205, and the surface of the carbon nanotube array 203 between the second source electrode 204 and the second drain electrode 205. A second gate electrode 207 is located on the surface of the dielectric layer 206 between the second source electrode 204 and the second drain electrode 205.
[0072] Specifically, the material of the second substrate 201 includes one or more of Si, SiC, and sapphire substrates; the material of the substrate 202 includes SiO2; the materials of the second source 204 and the second drain 205 both include stacked Ti, Al, Ni, and Au; and the material of the dielectric layer 206 includes H. f One or more of O2 and Al2O3; the material of the second gate 207 includes stacked Ni and Au.
[0073] In one specific embodiment, the material of the electrical isolation layer 3 includes SiO2 or Al2O3, and the thickness is 2 to 5 μm.
[0074] This embodiment of the integrated CMOS device structure vertically integrates high electron mobility transistors (HEMTs) and carbon nanotube devices, with an electrical isolation layer between them. The gates of the HEMTs and carbon nanotube devices are connected to each other using a metal connection, and their drains are connected to each other. The HEMTs realize NMOS transistors, and the carbon nanotube devices realize PMOS transistors. This heterogeneous integration structure fully leverages the advantages of both NMOS and PMOS transistors, achieving high electron and hole mobility on a single substrate. This results in N-channel and P-channel devices with high switching speeds. Furthermore, the vertical integration significantly saves chip area. Therefore, this flip-chip bonded integrated CMOS device structure can realize small-size, high-speed, radiation-resistant digital logic circuits.
[0075] Example 2
[0076] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic flowchart of the method for fabricating an integrated CMOS device structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the process of fabricating an integrated CMOS device structure according to an embodiment of the present invention.
[0077] The fabrication method of this integrated CMOS device structure includes the following steps:
[0078] S1. Prepare a first device 1, wherein the first device 1 includes a III-V compound high electron mobility transistor.
[0079] S2. An electrical isolation layer 3 is prepared on the first device 1, such that the electrical isolation layer 3 covers the surfaces of the source, drain and gate of the first device 1.
[0080] Specifically, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit SiO2 dielectric on the first device 1 with a thickness of 2–5 μm, so that the SiO2 dielectric covers the surfaces of the source, drain, and gate of the first device 1 to form an electrical isolation layer 3; alternatively, plasma atomic layer deposition (PAD) can be used to deposit Al2O3 dielectric on the first device 1 with a thickness of 2–5 μm, so that the Al2O3 dielectric covers the surfaces of the source, drain, and gate of the first device 1 to form an electrical isolation layer 3.
[0081] S3. Etch the electrical isolation layer 3 at the gate position of the first device 1 to form a first via, and etch the electrical isolation layer 3 at the drain position of the first device 1 to form a second via.
[0082] S4. Prepare a second device 2, wherein the second device 2 includes a carbon nanotube device.
[0083] S5. Prepare a first connecting metal 4 in the first through hole and prepare a second connecting metal 5 in the second through hole.
[0084] S6. The second device 2 is inverted and bonded to the electrical isolation layer 3, such that the first connecting metal 4 is connected to the gate of the first device 1 and the gate of the second device 2, and the second connecting metal 5 is connected to the drain of the first device 1 and the drain of the second device 2.
[0085] S7. Etch a third via from the substrate side of the first device 1 to the source of the first device 1, and prepare a metal electrode in the third via to lead out the source of the first device 1. The source of the first device 1 is used to connect to the ground terminal.
[0086] S8. Etch the fourth via to the source of the second device 2 from the substrate side, etch the fifth via to the drain of the second device 2, etch the sixth via to the gate of the second device 2, and prepare metal electrodes in the fourth, fifth and sixth vias to lead out the source, drain and gate of the second device 2. The source of the second device 2 is used to connect to the power supply terminal, the gate is used as the input terminal and the drain is used as the output terminal.
[0087] The above steps yield a CMOS device with both N-channel and P-channel characteristics, exhibiting high switching speeds.
[0088] In one specific embodiment, taking the fabrication of a high electron mobility transistor (HEMT) with an AlN barrier layer as an example, followed by the following steps: first, a high electron mobility transistor (HEMT) with an AlN barrier layer is fabricated; then, SiO2 is grown on the HEMT surface using plasma-enhanced chemical vapor deposition (PECVD) for electrical isolation; next, inductively coupled plasma etching (ICP) is used to etch the corresponding drain and gate of the HEMT, creating vias and fabricating interconnect metals; finally, the fabricated carbon nanotube device is flip-chip bonded to the HEMT, with the gate and drain of the carbon nanotube device corresponding to the gate and drain of the HEMT, respectively, to obtain a CMOS device with both N-channel and P-channel high switching speeds. The specific steps of this integrated CMOS device structure fabrication method include:
[0089] S1. Fabrication of the first device 1. This includes the following steps:
[0090] S11. A first substrate is provided, wherein the first substrate includes a first substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104 and a barrier layer 105 stacked sequentially.
[0091] Specifically, the first substrate is obtained through procurement, and from bottom to top, the first substrate includes a Si substrate 101, an AlN nucleation layer 102, a GaN buffer layer 103, a GaN channel layer 104, and an AlN barrier layer 105.
[0092] S12. A first source 106 is fabricated at one end of the buffer layer 103, and a first drain 107 is fabricated at the other end, such that the channel layer 104 and the barrier layer 105 are located between the first source 106 and the first drain 107. Specifically, this includes the following steps:
[0093] S121. Photolithographically etch the first source region 106 and the first drain region 107 on the AlN barrier layer 105.
[0094] First, the first substrate is baked on a hot plate at 200°C for 5 minutes. Then, a release sizing agent is applied and spun onto the AlN barrier layer 105, and the sample is baked on a hot plate at 200°C for 5 minutes. Next, a photoresist is applied and spun onto the release sizing agent, and the sample is baked on a hot plate at 900°C for 1 minute. The sample with the completed release sizing and spun onto the photolithography machine is then exposed to the coated surface. The exposed sample is then placed in a developer to remove the photoresist and release sizing agent. After rinsing with ultrapure water and blowing with nitrogen, the first source region 106 and the first drain region 107 are formed.
[0095] S122. Evaporate the source electrode 6 and drain electrode 7 on the AlN barrier layer 105 in the first source electrode region 106 and the first drain electrode region 107, and on the photoresist outside the first source electrode region 106 and the first drain electrode region 107.
[0096] First, the sample with the photolithographic pattern of the first source electrode 106 and the first drain electrode 107 is placed in a plasma resist stripper for 5 minutes for bottom film treatment; then, the sample is placed in an electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After the torsion process, ohmic metal is evaporated on the AlN barrier layer 105 in the first source 106 region and the first drain 107 region, and on the photoresist outside the first source 106 region and the first drain 107 region to form the first source 106 and the first drain 107. The ohmic metal is a metal stack structure composed of four metal layers Ti, Al, Ni and Au from bottom to top. After the ohmic metal is evaporated, the sample is subjected to a stripping process to remove the ohmic metal, photoresist and stripping adhesive outside the first source 106 and the first drain 107. The sample is then rinsed with ultrapure water and dried with nitrogen.
[0097] S123. The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing. The annealing process is as follows: under nitrogen, the annealing temperature is 830℃ and the annealing time is 30s, so that the ohmic metal on the AlN barrier layer 105 in the first source electrode 106 and the first drain electrode 107 extends to the surface of the buffer layer 103, thereby forming an ohmic contact between the metal and the heterojunction channel.
[0098] S13. Create electrical isolation for the active region.
[0099] Specifically, electrical isolation of the active region of a device can be fabricated using either ICP technology or ion implantation technology.
[0100] Taking the fabrication of electrical isolation in the active region of a device using ICP technology as an example, this step specifically includes:
[0101] S131, Photolithographically ...
[0102] First, the sample is baked on a 200°C hot plate for 5 minutes. Then, photoresist is applied and spun onto the sample, and the sample is baked on a 900°C hot plate for 1 minute. The sample is then placed in a lithography machine to expose the photoresist in the electrically isolated area. After exposure, the sample is placed in a developing solution to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen to form the electrically isolated area.
[0103] S132. Electrical isolation of the active region is fabricated on the AlN barrier layer 105.
[0104] First, the AlN barrier layer 105, GaN channel layer 104, and GaN buffer layer 103 of the electrically isolated region are sequentially etched using an ICP process to achieve mesa isolation of the active region; specifically, the etching depth can be 100 nm. Then, the sample is sequentially cleaned in acetone solution, stripping solution, acetone solution, and isopropanol solution to remove the photoresist outside the electrically isolated region. Finally, the sample is rinsed with ultrapure water and dried with nitrogen gas to achieve electrical isolation of the active region.
[0105] S14. A passivation layer 109 is prepared on the surface of the barrier layer 105, the first source 106, and the first drain 107. Specifically, this includes the following steps:
[0106] S141. Perform surface cleaning on the sample after completing the electrical isolation of the active region.
[0107] Specifically, the cleaning process includes: ultrasonically cleaning the sample in acetone solution for 3 minutes at an ultrasonic intensity of 2.5; heating the sample in a water bath at 60°C for 5 minutes; ultrasonically cleaning the sample in acetone solution for 3 minutes at an ultrasonic intensity of 2.5; ultrasonically cleaning the sample in isopropanol solution for 3 minutes at an ultrasonic intensity of 2.5; rinsing the sample with ultrapure water and drying it with nitrogen.
[0108] S142. On the first source 106, the first drain 107 and the AlN barrier layer 105 of the active region, a SiN passivation layer 109 with a thickness of 120 nm is grown using PECVD process. The growth process conditions are as follows: NH3 and SiH4 are used as reaction gases, the substrate temperature is 250℃, the reaction chamber pressure is 600 mTorr, and the RF power is 22W.
[0109] S15. A first gate 108 is formed between the first source 106 and the first drain 107, such that the first gate 108 is located on the surface of the barrier layer 105 and the surface of the passivation layer 109. Specifically, this includes the following steps:
[0110] S151. Photolithographically etch the GRSS region on the SiN passivation layer 109 as the gate pin region, and use ICP process to etch the SiN passivation layer 109 in the GRSS region.
[0111] First, the GRSS region is photolithographically etched on the SiN passivation layer 109. Specifically, this includes: baking the sample on a 200°C hot plate; applying and spinning the photoresist, then baking the sample on a 900°C hot plate for 1 minute; exposing the GRSS region photoresist in a photolithography machine; immersing the exposed sample in a developer to remove the GRSS region photoresist, followed by rinsing with ultrapure water and drying with nitrogen to form the GRSS region.
[0112] Then, the cleaned sample was etched using an ICP process to remove the SiN passivation layer 109 material in the GRSS region, forming a gate trench. The etching conditions for the SiN passivation layer 109 included: reaction gases of CF4 and O2, a reaction chamber pressure of 10 mTorr, RF power of 100 W for the upper electrode and 10 W for the lower electrode, and an etching depth of 125 nm. Afterward, the sample was sequentially cleaned in acetone solution, stripping solution, acetone solution, and isopropanol solution.
[0113] S152. The gate cap region of the grating electrode is formed on the passivation layer 109, and the first gate 108 is fabricated using an electron beam evaporation process.
[0114] First, using a double-layer photoresist lithography technique, the gate cap region of the grating electrode is formed on the passivation layer 109. Specifically, the steps include: baking the sample on a hot plate at 200°C for 5 minutes; coating the sample with a first layer of photoresist until it completely covers the upper surface of the SiN passivation layer 109; coating the sample with a second layer of photoresist until it completely covers the first layer; subjecting the coated sample to a second exposure; immersing the exposed sample in a developing solution to remove the photoresist from the T-shaped gate region, followed by rinsing with ultrapure water and drying with nitrogen to form the gate cap region.
[0115] Then, a metal is deposited to form the first gate 108 using electron beam evaporation. Specifically, the steps include: placing the sample with the photolithographic pattern on the gate electrode region into a plasma stripper for substrate treatment for 5 minutes; placing the cleaned sample into an electron beam evaporation stage, and waiting for the vacuum level in the reaction chamber of the electron beam evaporation stage to reach 2 × 10⁻⁶. -6 After Torr, gate metal is evaporated on the photoresist in and outside the gate electrode region. The gate metal is a metal stack structure composed of three layers of metal, Ni, Au and Ni, arranged sequentially from bottom to top, to obtain the first gate 108.
[0116] After the above steps, a high electron mobility transistor is obtained.
[0117] S2. An electrical isolation layer 3 is fabricated on the first device 1, such that the electrical isolation layer 3 covers the surfaces of the source, drain, and gate of the first device 1. Specifically, this includes the following steps:
[0118] S21. Perform surface cleaning on the high electron mobility transistor. The specific cleaning method is as follows: immerse the sample in acetone solution and ultrasonically clean for 3 minutes at an ultrasonic intensity of 2.5; immerse the sample in a stripping solution at 60°C and heat in a water bath for 5 minutes; immerse the sample sequentially in acetone solution and ultrasonically clean for 3 minutes at an ultrasonic intensity of 2.5; immerse the sample sequentially in isopropanol solution and ultrasonically clean for 3 minutes at an ultrasonic intensity of 2.5; rinse the sample with ultrapure water and dry it with nitrogen gas.
[0119] S22. On the first source 106, the first drain 107, the AlN barrier layer 105 of the active region and the SiN passivation layer 109, a SiO2 isolation layer with a thickness of 800nm is grown using PECVD process to form an electrical isolation layer 3. The process conditions for growing the SiO2 isolation layer are: using N2O and SiN4 as reaction gases, the substrate temperature is 300℃, the reaction chamber pressure is 900mTorr, and the RF power is 70W.
[0120] S3. Etch the electrical isolation layer 3 at the gate position of the first device 1 to form a first via, and etch the electrical isolation layer 3 at the drain position of the first device 1 to form a second via.
[0121] Specifically, a via opening region is formed on the SiO2 electrical isolation layer 3 by photolithography, and the electrical isolation layer 3 of the interconnect opening region is etched away using ICP process to form the first via and the second via. The specific steps include:
[0122] S31. Photolithographically etch the first and second connection metal aperture regions on the SiO2 electrical isolation layer 3.
[0123] The photolithography method includes: baking the sample on a hot plate at 200°C for 5 minutes; applying and spinning the photoresist at a spin speed of 3500 rpm, and baking the sample on a hot plate at 90°C for 1 minute; exposing the photoresist in the interconnect metal opening area in a photolithography machine; immersing the exposed sample in a developer to remove the photoresist in the interconnect opening area, and rinsing it with ultrapure water and drying it with nitrogen to form a first interconnect metal opening area at the gate position of the first device 1 and a second interconnect metal opening area at the drain position of the first device 1.
[0124] S32. Using ICP etching process, under the conditions of reaction gas CF4 and O2, reaction chamber pressure of 10mTorr, and RF power of upper electrode and lower electrode of 100W and 10W respectively, the SiO2 electrical isolation layer 3 connecting the first connecting metal opening area and the second connecting metal opening area is removed to form the first through hole and the second through hole.
[0125] S4. Fabricate the second device 2, wherein the second device 2 includes a carbon nanotube device. Specific steps include:
[0126] S41. A second substrate is provided, wherein the second substrate includes a second substrate 201 and a substrate substrate 202 stacked sequentially.
[0127] Specifically, the second substrate is obtained through procurement, and the second substrate includes, from bottom to top, a Si second substrate 201 and a SiO2 substrate 202.
[0128] S42 provides carbon nanotubes free of impurities and amorphous carbon.
[0129] Specifically, semiconductor carbon nanotubes with a purity higher than 99% are separated twice to obtain carbon nanotubes free of impurities and amorphous carbon.
[0130] The specific method is as follows: The purchased single-walled carbon nanotubes were mixed with poly(1-octylnonyl)-9H-carbazole PCz at a volume ratio of 1:1 for catalytic reaction; 25 ml of toluene solution was added to the above solution, and the mixture was soaked in an ice-water bath at 0°C and placed in a VCX500 cell disruptor for 30 min to ensure full contact; the mixture was pre-centrifuged at 20000 g for 30 min at 4°C, and 90% of the supernatant was collected; the mixture was then centrifuged again at 20000 g for 2 h at 4°C, and 90% of the supernatant was collected to obtain carbon nanotubes free of impurities and amorphous carbon.
[0131] S43. Using electrophoresis, carbon nanotube array 203 is formed on substrate 202. Specifically, this includes the following steps:
[0132] S431. An array pattern is formed on the substrate 202.
[0133] Specifically, an array pattern is formed on a SiO2 substrate 202 using photolithography.
[0134] S432. Electrodes are fabricated on a substrate 202 with an arrayed pattern.
[0135] Specifically, the sample is baked on a hot plate at 200°C for 5 minutes; the prepared sample is coated and spin-spinned with photoresist under a yellow light lamp, and then baked on a hot plate at 900°C for 1 minute; the coated and spin-spinned sample is placed in a photolithography machine to expose the coated surface, and then the exposed sample is placed in a developing solution to remove the photoresist; Cr / Au is deposited on a substrate 202 with an arrayed pattern using a magnetron sputtering process, with a thickness of approximately 400 nm, to prepare the electrode.
[0136] S433. The device is immersed in a function generator containing a carbon nanotube suspension and a voltage is applied to prepare a carbon nanotube array 203.
[0137] Specifically, the device is immersed in a function generator containing a carbon nanotube suspension, and the electrode is connected to the function generator. Electrophoresis is performed at 100 kHz and 10 V, so that the carbon nanotube suspension forms a carbon nanotube array 203 on the electrode surface.
[0138] S434, wet etching of the electrode, so that the carbon nanotube array 203 is attached to the substrate 202.
[0139] Specifically, wet etching is performed using BOE solution to remove the electrode metal below the carbon nanotube array 203. At this time, the carbon nanotube array 203 is attached to the substrate 202, thereby forming the carbon nanotube array 203 located on the substrate 202.
[0140] S44. A second source electrode 204 is fabricated at one end of the carbon nanotube array 203, and a second drain electrode 205 is fabricated at the other end. Specific steps include:
[0141] S441. Photolithographically print the second source 204 region and the second drain 205 region on the carbon nanotube array 203.
[0142] The specific photolithography method is as follows: the epitaxial substrate is baked on a hot plate at 200°C for 5 minutes; the release agent is applied and spun onto the SiO2 layer 11, and the sample is baked on a hot plate at 200°C for 5 minutes; the photoresist is applied and spun onto the release agent, and the sample is baked on a hot plate at 900°C for 1 minute; the sample after the coating and spun is placed in a photolithography machine to expose the coated surface, and the exposed sample is placed in a developer to remove the photoresist and release agent, and then rinsed with ultrapure water and bleed with nitrogen to form the second source 204 region and the second drain 205 region.
[0143] S442. The second source 204 and the second drain 205 are evaporated on the SiO2 substrate 202 in the second source 204 region and the second drain 205 region, and on the photoresist outside the second source 204 region and the second drain 205 region.
[0144] The specific method is as follows: The sample containing the second source electrode 204 region and the second drain electrode 205 region is placed in a plasma desizing machine for bottom film treatment for 5 minutes; the sample is then placed in an electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6 After the torsion process, ohmic metal is evaporated on the SiO2 substrate 202 in the second source 204 region and the second drain 205 region, and on the photoresist outside the second source 204 region and the second drain 205 region to form the second source 204 and the second drain 205. The ohmic metal is a metal stack structure composed of four metal layers Ti, Al, Ni and Au from bottom to top. After the source and drain metals are evaporated, the sample is subjected to a stripping process to remove the metal, photoresist and stripping adhesive outside the second source 204 and the second drain 205. The sample is then rinsed with ultrapure water and dried with nitrogen to form the second source 204 at one end of the carbon nanotube array 203 and the second drain 205 at the other end.
[0145] S45. A dielectric layer 206 is prepared on a portion of the surface of the second source electrode 204, a portion of the surface of the second drain electrode 205, and the surface of the carbon nanotube array 203 between the second source electrode 204 and the second drain electrode 205.
[0146] Specifically, using thermal atomic layer deposition (ALD) technology, a 10 nm thick H layer is grown in the middle of the second source 204 and the second drain 205, as well as in a portion above the second source 204 and the portion above the second drain 205. f The O2 high-k dielectric layer 206 was grown under the following conditions: the precursor sources were O3 and TEMAH, the substrate temperature was 300℃, and the reaction chamber pressure was 0.3 Torr.
[0147] S46. A second gate 207 is prepared on the surface of the dielectric layer 206 between the second source 204 and the second drain 205.
[0148] First, in H f The gate electrode region is photolithographically etched on the O2 dielectric layer 206. The specific method is as follows: the sample is baked on a hot plate at 200°C for 5 minutes; photoresist is spin-coated onto the sample, and the sample after coating is exposed; the exposed sample is placed in the developer to remove the photoresist in the gate region, and then rinsed with ultrapure water and dried with nitrogen to form the gate electrode region.
[0149] Then, a second gate electrode 207 is formed by depositing metal using electron beam evaporation. Specifically, the sample with the photolithographic pattern on the gate electrode region is placed in a plasma resist remover for 5 minutes for substrate treatment; the cleaned sample is then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6 After Torr, gate metal is evaporated on the photoresist in and outside the gate electrode region. The gate metal is a metal stack structure composed of three layers of metal, Ni, Au and Ni, arranged sequentially from bottom to top, thereby forming the second gate 207.
[0150] The second device was prepared through the above steps.
[0151] S5. Prepare a first connecting metal 4 in the first through hole and prepare a second connecting metal 5 in the second through hole.
[0152] S6. The second device 2 is inverted and bonded to the electrical isolation layer 3, such that the first connecting metal 4 is connected to the gate of the first device 1 and the gate of the second device 2, and the second connecting metal 5 is connected to the drain of the first device 1 and the drain of the second device 2.
[0153] S7. Etch the third via from the substrate side of the first device 1 to the source of the first device 1, etch the fourth via from the substrate side of the second device 2 to the source of the second device 2, etch the fifth via to the drain of the second device 2, and etch the sixth via to the gate of the second device 2.
[0154] Specifically, using the ICP process, a third via is etched from the substrate side of the first device 1 to the source of the first device 1, a fourth via is etched from the substrate side of the second device 2 to the source of the second device 2, a fifth via is etched to the drain of the second device 2, and a sixth via is etched to the gate of the second device 2.
[0155] S8. A metal electrode is prepared in the third through hole to bring out the source of the first device 1. The source of the first device 1 is used to connect to the ground terminal. Metal electrodes are prepared in the fourth, fifth and sixth through holes to bring out the source, drain and gate of the second device 2. The source of the second device 2 is used to connect to the power supply terminal, the gate is used as the input terminal and the drain is used as the output terminal.
[0156] Specifically, Ni / Au metal electrodes are fabricated in the fourth, fifth, and sixth through holes to bring out the source, drain, and gate of the second device 2; Cu or Au metal electrodes are fabricated in the third through hole to bring out the source of the first device 1.
[0157] Finally, the device was rinsed with ultrapure water and dried with nitrogen to complete the fabrication of the integrated CMOS device structure.
[0158] This embodiment employs a process of first fabricating a high electron mobility transistor (HEMT), then depositing an electrical isolation layer, followed by inductively coupled plasma etching (ICP-C) to etch the corresponding drain and gate of the HEMT, creating vias, and fabricating a connection metal. Finally, the fabricated carbon nanotubes are flip-chip bonded to the HEMT, with the carbon nanotube gate and drain corresponding to the HEMT gate and drain, respectively, resulting in a CMOS device with both N-channel and P-channel characteristics and high switching speeds. In summary, this embodiment utilizes the fusion of III-V semiconductors and carbon-based materials, along with heterogeneous integration technology, to simultaneously achieve N-channel and P-channel devices with high switching speeds. Furthermore, vertical integration saves chip area, enabling the realization of small-size, high-speed, radiation-hardened digital logic circuits.
[0159] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. An integrated CMOS device structure, characterized in that, include: The device comprises a first component (1), a second component (2), an electrical isolation layer (3), a first connecting metal (4), and a second connecting metal (5), wherein... The first device (1) includes a III-V compound high electron mobility transistor, and the second device (2) includes a carbon nanotube device; The electrical isolation layer (3) covers the surfaces of the source, drain and gate of the first device (1); The second device (2) is flip-chip bonded to the electrical isolation layer (3); The first connecting metal (4) penetrates the electrical isolation layer (3) to connect the gate of the first device (1) and the gate of the second device (2); The second connecting metal (5) penetrates the electrical isolation layer (3) to connect the drain of the first device (1) and the drain of the second device (2); The source of the first device (1) is led out from the substrate side of the first device (1) through a metal electrode; the source of the first device (1) is used to connect to the ground terminal; The source, drain and gate of the second device (2) are all led out from the substrate side of the second device (2) through metal electrodes; the source of the second device (2) is used to connect to the power supply terminal, the gate is used as the input terminal and the drain is used as the output terminal.
2. The integrated CMOS device structure according to claim 1, characterized in that, The high electron mobility transistor includes a first substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104), a barrier layer (105), a first source (106), a first drain (107), a first gate (108), and a passivation layer (109), wherein, The first substrate (101), the nucleation layer (102), and the buffer layer (103) are stacked sequentially; the first source electrode (106) is located at one end of the surface of the buffer layer (103); the first drain electrode (107) is located at the other end of the surface of the buffer layer (103); the channel layer (104) and the barrier layer (105) are stacked on the buffer layer (103) between the first source electrode (106) and the first drain electrode (107); the passivation layer (109) covers the surfaces of the barrier layer (105), the first source electrode (106), and the first drain electrode (107); the first gate electrode (108) is located between the first source electrode (106) and the first drain electrode (107), and is located on the surface of the barrier layer (105) and the surface of the passivation layer (109).
3. The integrated CMOS device structure according to claim 1, characterized in that, The carbon nanotube device includes a second substrate (201), a substrate (202), a carbon nanotube array (203), a second source (204), a second drain (205), a dielectric layer (206), and a second gate (207), wherein, The second substrate (201) and the substrate (202) are stacked sequentially, and the carbon nanotube array (203) is arrayed on the substrate (202); the second source electrode (204) is located at one end of the surface of the carbon nanotube array (203); the second drain electrode (205) is located at the other end of the surface of the carbon nanotube array (203); the dielectric layer (206) covers a portion of the surface of the second source electrode (204), a portion of the surface of the second drain electrode (205), and the surface of the carbon nanotube array (203) between the second source electrode (204) and the second drain electrode (205); the second gate electrode (207) is located on the surface of the dielectric layer (206) between the second source electrode (204) and the second drain electrode (205).
4. The integrated CMOS device structure according to claim 1, characterized in that, The electrical isolation layer (3) is made of SiO2 or Al2O3 and has a thickness of 2 to 5 μm.
5. A method for fabricating an integrated CMOS device structure, characterized in that, Including the following steps: Fabricate a first device (1), wherein the first device (1) comprises a III-V compound high electron mobility transistor; An electrical isolation layer (3) is prepared on the first device (1) such that the electrical isolation layer (3) covers the surface of the source, drain and gate of the first device (1); The electrical isolation layer (3) at the gate position of the first device (1) is etched to form a first via, and the electrical isolation layer (3) at the drain position of the first device (1) is etched to form a second via; Fabricate a second device (2), wherein the second device (2) includes a carbon nanotube device; A first connecting metal (4) is prepared in the first through hole, and a second connecting metal (5) is prepared in the second through hole; The second device (2) is inverted and bonded to the electrical isolation layer (3), such that the first connecting metal (4) connects the gate of the first device (1) and the gate of the second device (2), and the second connecting metal (5) connects the drain of the first device (1) and the drain of the second device (2); The third via is etched from the substrate side of the first device (1) to the source of the first device (1), the fourth via is etched from the substrate side of the second device (2) to the source of the second device (2), the fifth via is etched to the drain of the second device (2), and the sixth via is etched to the gate of the second device (2). Metal electrodes are prepared in the third through hole to bring out the source of the first device (1), and the source of the first device (1) is used to connect to the ground terminal; metal electrodes are prepared in the fourth through hole, the fifth through hole and the sixth through hole to bring out the source, drain and gate of the second device (2), and the source of the second device (2) is used to connect to the power supply terminal, the gate is used as the input terminal and the drain is used as the output terminal.
6. The method for fabricating an integrated CMOS device structure according to claim 5, characterized in that, The fabrication of the first device (1) includes the following steps: A first substrate is provided, wherein the first substrate includes a first substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104) and a barrier layer (105) stacked sequentially. A first source (106) is formed at one end of the buffer layer (103), and a first drain (107) is formed at the other end, such that the channel layer (104) and the barrier layer (105) are located between the first source (106) and the first drain (107); Create electrical isolation for the active region; A passivation layer (109) is prepared on the surface of the barrier layer (105), the first source (106) and the first drain (107); A first gate (108) is prepared between the first source (106) and the first drain (107) such that the first gate (108) is located on the surface of the barrier layer (105) and the surface of the passivation layer (109).
7. The method for fabricating an integrated CMOS device structure according to claim 5, characterized in that, An electrical isolation layer (3) is fabricated on the first device (1) such that the electrical isolation layer (3) covers the surfaces of the source, drain, and gate of the first device (1), including: Using plasma-enhanced chemical vapor deposition, a SiO2 dielectric with a thickness of 2-5 μm is deposited on the first device (1), so that the SiO2 dielectric covers the surface of the source, drain and gate of the first device (1) to form the electrical isolation layer (3).
8. The method for fabricating an integrated CMOS device structure according to claim 5, characterized in that, An electrical isolation layer (3) is fabricated on the first device (1) such that the electrical isolation layer (3) covers the surfaces of the source, drain, and gate of the first device (1), including: Using plasma atomic layer deposition, an Al2O3 dielectric with a thickness of 2 to 5 μm is deposited on the first device (1), so that the Al2O3 dielectric covers the surface of the source, drain and gate of the first device (1) to form the electrical isolation layer (3).
9. The method for fabricating an integrated CMOS device structure according to claim 6, characterized in that, The fabrication of the second device (2) includes the following steps: A second substrate is provided, wherein the second substrate includes a second substrate (201) and a substrate substrate (202) stacked sequentially; Provides carbon nanotubes free of impurities and amorphous carbon; Electrophoresis is used to form a carbon nanotube array (203) on the substrate (202); A second source electrode (204) is fabricated at one end of the carbon nanotube array (203), and a second drain electrode (205) is fabricated at the other end; A dielectric layer (206) is prepared on a portion of the surface of the second source electrode (204), a portion of the surface of the second drain electrode (205), and the surface of the carbon nanotube array (203) between the second source electrode (204) and the second drain electrode (205); A second gate (207) is formed on the surface of the dielectric layer (206) between the second source (204) and the second drain (205).
10. The method for fabricating an integrated CMOS device structure according to claim 9, characterized in that, The carbon nanotubes are used to form a carbon nanotube array (203) on the substrate (202) by electrophoresis, including the following steps: An array pattern is formed on the substrate (202); Electrodes are fabricated on a substrate (202) with an arrayed pattern; The device was immersed in a function generator containing a carbon nanotube suspension and a voltage was applied to prepare a carbon nanotube array (203). The electrode is wet-etched so that the carbon nanotube array (203) is attached to the substrate (202).