Organic light emitting display device and method of manufacturing the same

Abstract

The present disclosure relates to an organic light emitting display device and a manufacturing method thereof. The organic light emitting display device includes both a polycrystalline semiconductor element and an oxide semiconductor element, and in order to solve damage of an oxide semiconductor pattern during a heat treatment process in a process of forming the oxide semiconductor element, until a process of forming the polycrystalline semiconductor element is completed, a portion of a connection electrode connecting the polycrystalline semiconductor pattern to a source and a drain is formed in advance, and then by forming another portion of the connection electrode for completing connection between the source and the drain to the polycrystalline semiconductor pattern in the process of forming the oxide semiconductor element, the connection electrode can have a connection node located between two edges thereof, whereby the performance of the oxide semiconductor element can be improved.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically to organic light-emitting display devices including hybrid thin-film transistors formed using different types of semiconductor materials during the formation of a plurality of thin-film transistors included in a pixel circuit section of a unit pixel. Specifically, this disclosure relates to an organic light-emitting display device capable of presenting a wide range of grayscale images and achieving fast on-off operation by adjusting the S-factor of at least one particular thin-film transistor among the plurality of thin-film transistors, and to a method of manufacturing an organic light-emitting display device for preventing or at least reducing the degradation of at least one thin-film transistor including an oxide semiconductor pattern. Background Technology

[0002] In recent years, with the development of multimedia, flat panel displays have become increasingly important. To meet the demands for various display devices, flat panel displays such as liquid crystal displays (LCDs), plasma displays, and organic light-emitting diode (OLED) displays have been developed and commercialized. OLED displays, compared to other flat panel displays, offer advantages such as faster response times, higher luminous efficiency, and wider viewing angles, and are therefore becoming increasingly popular.

[0003] In this type of organic light-emitting display device, multiple pixels can be arranged in a matrix pattern, and each pixel can include a light-emitting element portion represented by an organic light-emitting layer and a pixel circuit portion represented by at least one thin-film transistor. The pixel circuit portion can include multiple TFTs, such as driving thin-film transistors (TFTs) for providing drive current to operate the light-emitting element portion and switching TFTs for providing gating signals to the driving TFTs.

[0004] Furthermore, the gating driver used to provide gating signals to the pixels can be located in the non-display area of ​​the organic light-emitting display device.

[0005] As described above, since multiple thin-film transistors disposed in the pixel circuit section and gating driver of a pixel (e.g., a sub-pixel) can perform different functions, their electrical characteristics may need to be different from each other. To enable the multiple thin-film transistors disposed in a pixel to have different electrical characteristics, for example, the multiple thin-film transistors may be configured with different structures or comprise different semiconductor materials. In this example, such semiconductor material layers may need to be formed in different layers and may be exposed to different etching conditions during the etching process, thereby potentially degrading the quality and reliability of the oxide semiconductor material during the heat treatment process. This disclosure provides an organic light-emitting display device to solve these problems and enable the stable acquisition or maintenance of thin-film transistor performance.

[0006] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned or associated with it. The background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0007] Considering that the effects of hydrogen particles on polycrystalline semiconductor patterns and oxide semiconductor patterns located in different layers in each pixel are different, one or more exemplary embodiments of this disclosure may provide an organic light-emitting display device that can improve the performance of both polycrystalline semiconductor patterns and oxide semiconductor patterns, reduce or prevent leakage current, and display various grayscale images at low grayscale.

[0008] According to various aspects of this disclosure, an organic light-emitting display device is provided, comprising: a substrate including a display area and a non-display area located outside the display area; a first thin-film transistor disposed above the substrate and including a first semiconductor pattern, a first gate overlapping the first semiconductor pattern, and a first source and a first drain connected to the first semiconductor pattern through a plurality of inserted insulating layers; and a second thin-film transistor disposed above the substrate and including a second semiconductor pattern disposed in a different layer from the first semiconductor pattern, a second gate overlapping the second semiconductor pattern, a second source and a second drain connected to the second semiconductor pattern, and a second light-shielding pattern located in the first semiconductor pattern. Below a second semiconductor pattern, overlapping with the second semiconductor pattern and connected to one of the second source and the second drain; a third thin-film transistor, the third thin-film transistor being disposed above a substrate, and including a third semiconductor pattern disposed in the same layer as the second semiconductor pattern, a third gate overlapping with the third semiconductor pattern, a third source and a third drain connected to the third semiconductor pattern, and a third light-shielding pattern located below and overlapping the third semiconductor pattern, wherein the vertical distance between the second light-shielding pattern and the second semiconductor pattern may be shorter than the vertical distance between the third light-shielding pattern and the third semiconductor pattern, and the first source and the first drain may respectively pass through multiple insulating layers and be connected through a first connection electrode including at least one connection node.

[0009] The first semiconductor pattern may include a polycrystalline semiconductor pattern, and the second and third semiconductor patterns may include oxide semiconductor patterns.

[0010] The first thin-film transistor can be disposed in either the display area or the non-display area, and the second and third thin-film transistors can be disposed in the display area.

[0011] The second thin-film transistor can be a driving thin-film transistor disposed in the sub-pixel, and the third thin-film transistor can be a switching thin-film transistor disposed in the sub-pixel.

[0012] The plurality of insulating layers may include: a first gate insulating layer disposed between a first semiconductor pattern and a first gate; at least one intermediate insulating layer disposed between the first gate and an upper buffer layer; an upper buffer layer located between the intermediate insulating layer and a second semiconductor pattern; a second gate insulating layer located between a second semiconductor pattern and a second gate; and an interlayer insulating layer located between the second gate and a second source and a second drain.

[0013] The second light-shielding pattern can be located inside the upper buffer layer, and the third light-shielding pattern can be located below the upper buffer layer.

[0014] The upper buffer layer may include multiple sub-buffer layers, and the second light-shielding pattern may be disposed between the sub-buffer layers.

[0015] The first connection electrode may include a connection node located between the upper buffer layer and the second gate insulating layer.

[0016] The first connection electrode may be made of the same material as the first source and the second drain.

[0017] Different conductors can make ohmic contact with the upper and lower parts of the first connecting electrode respectively, based on the connection node.

[0018] The second source and the second drain can be connected to the second semiconductor pattern. For example, the second source and the second drain can be connected to the second semiconductor pattern via a second connection electrode formed as a single body.

[0019] The organic light-emitting display device may further include at least one lower buffer layer located on a substrate; and a first light-shielding pattern, which may be further disposed between the substrate and a first semiconductor pattern.

[0020] At least one intermediate insulating layer may include a silicon nitride layer.

[0021] According to various aspects of this disclosure, a method for manufacturing an organic light-emitting display device is provided, the method comprising the steps of: preparing a substrate including a display area and a non-display area; forming a first semiconductor pattern on at least one lower buffer layer located on the substrate; forming a first gate insulating layer on the first semiconductor pattern; forming a first gate on the first gate insulating layer; forming at least one intermediate insulating layer on the first gate; forming an upper buffer layer including a second light-shielding pattern on the at least one intermediate insulating layer; forming a first portion of a first contact hole, the first portion of the first contact hole passing through the upper buffer layer, at least one intermediate insulating layer and the first gate insulating layer, and exposing a portion of the first semiconductor pattern; forming... A first portion of a first connecting electrode is formed, the first portion of the first connecting electrode being connected to a first semiconductor pattern through a first portion of a first contact hole; a second semiconductor pattern is formed on an upper buffer layer; a second gate is formed on a second gate insulating layer located on the second semiconductor pattern, the second gate overlapping the second semiconductor pattern; an interlayer insulating layer is formed on the second gate; a second portion of a first contact hole is formed, the second portion of the first contact hole passing through the interlayer insulating layer and the second gate insulating layer and exposing the first portion of the first connecting electrode; and a second portion of a first connecting electrode is formed, the second portion of the first connecting electrode being connected to the first portion of the first connecting electrode through the second portion of the first contact hole.

[0022] In the process of forming a first semiconductor pattern on at least one lower buffer layer located on a substrate, a first light-shielding pattern that overlaps with the first semiconductor pattern located above the substrate can be formed.

[0023] The lower buffer layer may include a first lower buffer layer disposed between the substrate and the first light-shielding pattern and a second lower buffer layer disposed between the first light-shielding pattern and the first semiconductor pattern.

[0024] In the process of forming a second semiconductor pattern on the upper buffer layer, a third semiconductor pattern comprising the same material as the second semiconductor pattern may also be formed on the upper buffer layer.

[0025] In the process of forming the first gate on the first gate insulating layer, a third light-shielding pattern overlapping with the third semiconductor pattern and the first electrode of the storage capacitor may also be formed.

[0026] The method may further include the step of forming a second electrode of the storage capacitor between the first gate and the upper buffer layer, which overlaps with the first electrode of the storage capacitor.

[0027] In the process of forming an upper buffer layer including a second light-shielding pattern on the intermediate insulating layer, a second electrode of the storage capacitor that overlaps with the first electrode of the storage capacitor may also be formed.

[0028] In the process of forming a first portion of a first contact hole that passes through an upper buffer layer, at least one intermediate insulating layer, and a first gate insulating layer and exposes a portion of a first semiconductor pattern, the upper buffer layer deposited in the non-display area and the inorganic insulating layer disposed between the upper buffer layer and the substrate may be removed together.

[0029] In the process of forming the second part of the first connecting electrode that is connected to the first part of the first connecting electrode through the second part of the first contact hole, the first source and the first drain connected to the second part of the first connecting electrode, as well as the second source and the second drain connected to the second semiconductor pattern, can be formed together.

[0030] In the process of forming the second portion of the first contact hole that passes through the interlayer insulating layer and the second gate insulating layer and exposes the first portion of the first connection electrode, the interlayer insulating layer and the second gate insulating layer located in the non-display area of ​​the substrate can be removed together.

[0031] According to one or more exemplary embodiments of the present disclosure, an organic light-emitting display device can be provided that reduces or prevents leakage current and thereby achieves low power consumption by implementing a pixel circuit section including both polycrystalline semiconductor elements and oxide semiconductor elements. According to one or more exemplary embodiments of the present disclosure, an organic light-emitting display device can be provided that can display various grayscale images at low grayscale by including oxide semiconductor devices with large S-factors in the driving thin-film transistors of the pixels. According to one or more exemplary embodiments of the present disclosure, an organic light-emitting display device can be provided that prevents or reduces damage to the oxide semiconductor pattern during a heat treatment process and thereby improves the reliability of the corresponding oxide semiconductor element, because a polycrystalline semiconductor pattern and a portion of the connecting electrodes connecting the polycrystalline semiconductor pattern to the source and drain are pre-formed before the oxide semiconductor pattern is formed. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate various aspects of this disclosure and, together with the detailed embodiments, serve to explain the principles of this disclosure. In the drawings:

[0033] Figure 1A Example organic light-emitting display devices according to various aspects of this disclosure are illustrated;

[0034] Figure 1B This is an example cross-sectional view of the display device taken along line “G-G’” in Figure 1;

[0035] Figure 2Example sub-pixels of organic light-emitting display devices according to various aspects of this disclosure are illustrated;

[0036] Figure 3 Example circuit diagram of a sub-pixel of an organic light-emitting display device according to various aspects of this disclosure;

[0037] Figure 4A An example cross-sectional view of an organic light-emitting display device according to various aspects of the present disclosure, showing a thin-film transistor in a gating driver disposed in a non-display area, and a driving thin-film transistor and a switching thin-film transistor disposed in the display area;

[0038] Figure 4B The storage capacitor in the organic light-emitting display device according to various aspects of this disclosure is configured to... Figure 4A Different example cross-sectional views of the storage capacitor in the implementation scheme;

[0039] Figure 4C As an organic light-emitting display device according to various aspects of this disclosure Figure 4A An example cross-sectional view of the curved area, a portion of the non-display area, in the embodiment; and

[0040] Figures 5A to 5E The manufacturing process is illustrated in sequence. Figure 4A Example cross-sectional views of the processes of an organic light-emitting display device according to various aspects of the present disclosure in an embodiment. Detailed Implementation

[0041] Description of embodiments of the present disclosure will now be given in detail, examples of which are illustrated in the accompanying drawings. The advantages and features of the present disclosure, as well as its implementation methods, will be elucidated through the following illustrative embodiments described with reference to the accompanying drawings. In the following description, unless otherwise stated, the structures, implementations, methods, and operations described herein are not limited to the specific examples set forth herein and may be varied as is known in the art. The present disclosure may be implemented in different forms and should not be construed as limited to the illustrative embodiments set forth herein. Rather, these illustrative embodiments are provided to make the present disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, the scope of protection of the present disclosure is defined by the body of the claims and their equivalents.

[0042] The shapes, dimensions, ratios, angles, quantities, etc., illustrated in the accompanying drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise stated, the same reference numerals denote the same elements throughout. The names of the elements used in the following description have been chosen solely for convenience of writing the specification and may therefore differ from those used in actual products. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions might unnecessarily obscure aspects of this disclosure. Where terms such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” etc., are used, one or more other elements may be added unless, for example, a term such as “only,” is used. Unless the context clearly indicates otherwise, elements described in the singular are intended to include multiple elements, and elements described in the plural are intended to include a single element. Unless the context clearly indicates otherwise, the singular form used herein is intended to include the plural form.

[0043] When interpreting a component, it will be interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided. Furthermore, the term "can" fully encompasses all the meanings of the term "able to".

[0044] When describing positional relationships, such as using terms like "above," "over," "below," "over," "beside," or "adjacent" to describe the positional relationship between two parts, one or more other components may be located between the two components unless more restrictive terms such as "immediately," "directly," or "immediately" are used. For example, if one element or layer is positioned "above" another element or layer, a third element or layer may be inserted between the first and second elements or layers. Furthermore, terms like "left," "right," "top," "bottom," "downward," "upward," "above," and "below" refer to any frame of reference.

[0045] When describing temporal relationships, if the temporal order is described as such as "after," "following," "next," or "before," discontinuous situations may be included unless more restrictive terms such as "exactly," "immediately," or "directly" are used. The term "at least one" can be understood to include any or all combinations of one or more related listed items. For example, "at least one of the first, second, and third elements" means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first, second, and third elements).

[0046] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0047] The expressions "first element," "second element," and " / or" "third element" can be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A, only B, or only C; any or some combination of A, B, and C; or all of A, B, and C.

[0048] Unless otherwise stated, when describing a component or layer as "connected," "joined," or "attached" to another component or layer, the component or layer may be directly connected, joined, or attached to another component or layer, or indirectly connected, joined, or attached to another component or layer, with one or more intermediate components or layers "set" or "inserted" between the components or layers. Similarly, when describing a component or layer as "in contact," "overlapping," etc., with another component or layer, unless otherwise stated, the component or layer may be directly in contact with, overlap with, etc., another component or layer, or indirectly in contact with, overlap with, etc., with one or more intermediate components or layers "set" or "inserted" between the components or layers.

[0049] In the following, examples and embodiments of various aspects according to this disclosure will be described in detail with reference to the accompanying drawings. Additionally, for ease of description, the scale of each element illustrated in the drawings may differ from the actual scale. Therefore, the elements shown are not limited to the specific scale illustrated in the drawings.

[0050] Figure 1A This is a schematic block diagram of an example organic light-emitting display device 100 according to various aspects of the present disclosure, and Figure 1B An example cross-sectional view of the organic light-emitting display device 100 taken along line “G-G’” in Figure 1. Figure 2 for Figure 1A The diagram below illustrates a sample subpixel.

[0051] like Figure 1AAs shown, the organic light-emitting display device 100 may include an image processor 110, a degradation compensator 150, a memory 160, a timing controller 120, a data driver 140, a power supply 180, and a display panel PAN equipped with a gating driver 130. The display panel PAN may include a display area AA and a non-display area NA. In some embodiments, the non-display area NA of the display panel PAN may include a curved area BA. The display panel PAN can be folded or bent in the curved area BA, thereby reducing the bezel of the display panel PAN.

[0052] The image processor 110 can output drive signals or control signals for driving or controlling various components or devices, as well as image data received from an external image data provider. For example, such drive signals output from the image processor 110 may include data enable signals, vertical synchronization signals, horizontal synchronization signals, clock signals, etc.

[0053] The degradation compensator 150 can calculate the degradation compensation gain value of the sub-pixel SP of the display panel based on the sensed voltage Vsen received from the data driver 140, and calculate the dimming weight value based on the degradation compensation gain value. Thereafter, the degradation compensator 150 can use the degradation compensation gain value and the dimming weight value to modulate the input image data Idata of each sub-pixel SP in the current frame, and provide the image data Mdata generated from the modulation to the timing controller 120.

[0054] In addition to the modulated image data from the degradation compensator 150, the timing controller 120 can receive drive signals, etc. The timing controller 120 can generate and provide a gating timing control signal GDC for controlling the operating timing of the gating driver 130 and a data timing control signal DDC for controlling the operating timing of the data driver 140 based on one or more drive signals provided by the image processor 110.

[0055] The timing controller 120 can control the timing of the operation of the gating driver 130 and the data driver 140 to enable at least one sensed voltage Vsen from at least one sub-pixel SP to be acquired and provided to the degradation compensator 150.

[0056] The gating driver 130 can output one or more scan signals to the display panel PAN in response to the gating timing control signal GDC provided by the timing controller 120. The gating driver 130 can output one or more scan signals through multiple gating lines GL1 to GLm. In embodiments, the gating driver 130 can be implemented as an integrated circuit (IC); however, the embodiments of this disclosure are not limited thereto. In particular, the gating driver 130 can be implemented as a gate-in-panel (GIP) structure, in which one or more thin-film transistors are directly stacked on a substrate inside the organic light-emitting display device 100. The gating driver 130 implemented as a GIP structure can include multiple circuit elements such as shift registers, level shifters, etc.

[0057] The data driver 140 can output one or more data voltages to the display panel PAN in response to the data timing control signal DDC provided by the timing controller 120. The data driver 140 can sample and latch the digital data signal DATA received from the timing controller 120, and convert the digital data signal DATA into an analog data voltage based on the gamma voltage.

[0058] The data driver 140 can output one or more data voltages through multiple data lines DL1 to DLn.

[0059] The data driver 140 can provide the degradation compensator 150 with the sensed voltage Vsen received from the display panel PAN via the sensed voltage readout line.

[0060] In some embodiments, the data driver 140 may be mounted on the upper surface of the display panel PAN in the form of an integrated circuit (IC), or may be directly disposed in the display panel PAN; however, the embodiments disclosed herein are not limited thereto.

[0061] Power supply 180 can output a high-level drive voltage EVDD and a low-level drive voltage EVSS to provide power to the display panel PAN. The high-level drive voltage EVDD and the low-level drive voltage EVSS can be provided to the display panel PAN via one or more power lines. In one embodiment, power supply 180 can provide voltage to data driver 140 or strobe driver 130 to enable data driver 140 or strobe driver 130 to be driven.

[0062] The display panel PAN can display images based on data voltages and scan signals provided by data drivers 140 and strobe drivers 130, which can be set in the non-display area NA, and power, for example, voltages provided by power supply 180.

[0063] The display area AA of the display panel PAN may include a plurality of subpixels SP for displaying images. The plurality of subpixels SP may include one or more red subpixels, one or more green subpixels, and one or more blue subpixels, or one or more white subpixels, one or more red subpixels, one or more green subpixels, and one or more blue subpixels. In embodiments, all subpixels among the white, red, green, and blue subpixels may have the same area or size, or may have different areas or sizes.

[0064] The memory 160 can store not only a lookup table for degradation compensation gain, but also the degradation compensation time of the organic light-emitting elements (e.g., organic light-emitting diodes) of the sub-pixel SP. For example, the degradation compensation time of the organic light-emitting elements can be one or more times when the organic light-emitting display panel is driven, or the number of times the organic light-emitting display panel is driven.

[0065] In an implementation, the non-display area NA may include a curved area BA, in which the display panel PAN can be bent or folded. The curved area BA may be an area where signal pads (not shown), gating drivers 130, data drivers 140, etc., are located and do not perform the function of displaying images, and can be folded or bent towards the rear surface of the display area NA. Figure 1A As shown, the curved area BA can be located between the display area AA and the data driver 140. In an embodiment, the curved area BA can be located at at least one of the top edge, bottom edge, left edge, and right edge of the non-display area NA. Therefore, the area occupied by the display area AA in the entire area of ​​the display panel can be maximized, and the non-display area NA can be hidden behind the display area AA.

[0066] The signal link LK located in the bending area BA can connect the signal lines located in the display area AA to the signal pads. The signal link LK can extend in a direction that intersects the bending direction of the bending area BA (i.e., its area becomes larger), thereby minimizing bending stress.

[0067] like Figure 1B and Figure 4CAs shown, at least one opening (OA1 and / or OA2) can be provided in the bending region BA, allowing the bending region BA to be easily folded or bent. At least one opening (OA1 and / or OA2) can be formed by removing at least a portion of the inorganic insulating layers 111 that might be disposed in the bending region BA and cause cracking. Specifically, when the substrate 101 is bent, continuous bending stress can be applied to at least one inorganic insulating layer 111 disposed in the bending region BA. Since the inorganic insulating layer 111 has lower elasticity than organic insulating materials, cracks are easily generated in the inorganic insulating layer 111.

[0068] Cracks that have formed in the inorganic insulating layer 111 may extend along the inorganic insulating layer 111 into the display area AA, and these cracks may lead to line defects and / or drive failure of related components or devices. Therefore, in an embodiment, at least one planarization layer PLN comprising an organic insulating material having greater elasticity than the inorganic insulating layer 111 may be disposed in the bending area BA. The planarization layer PLN can alleviate bending stress generated when the substrate 101 is bent or folded, thereby preventing or at least reducing crack formation. Since at least one opening (OA1 and / or OA2) in the bending area BA can be formed using the same masking process as at least one of the plurality of contact holes disposed in the display area AA, the structure of at least one opening (OA1 and / or OA2) and the formation process can be simplified. According to embodiments of this disclosure, a novel structure of a display device is provided that can solve the problem of damage to the semiconductor pattern during the formation of at least one opening (OA1 and / or OA2) in the bending area BA and at least one contact hole in the display area. (Refer to...) Figures 4A to 4C Describe the structure in detail.

[0069] In some implementations, such as Figure 2 As shown, a sub-pixel SP can be connected to a gating line GL1, a data line DL1, a sense voltage readout line SRL1, and a power line PL1. The number of transistors and capacitors included in the sub-pixel SP, as well as the driving method of the sub-pixel SP, can vary depending on considerations for the sub-pixel SP circuit design.

[0070] Figure 3 An example circuit diagram of a sub-pixel SP of an organic light-emitting display device 100 according to various aspects of this disclosure.

[0071] like Figure 3As shown, the organic light-emitting display device 100 according to various aspects of the present disclosure may include a gate line GL and a data line DL, a power line PL, and a sensing line SL that define sub-pixels SP by being arranged in a manner that intersects each other, and includes a driving thin-film transistor DT, an organic light-emitting element D such as an organic light-emitting diode, a storage capacitor Cst, a first switching thin-film transistor ST1, and a second switching thin-film transistor ST2 contained in the sub-pixels SP.

[0072] The organic light-emitting element D may include an anode connected to the second node N2, a cathode connected to a low-level voltage supply line or a low-level voltage supply terminal for providing a low-level driving voltage EVSS, and an organic light-emitting layer located between the anode and the cathode.

[0073] The driving thin-film transistor DT can control the current Id flowing through the organic light-emitting element D according to the gate-source voltage Vgs. The driving thin-film transistor DT may include a gate connected to the first node N1, a drain connected to the power supply line PL to which a high-level driving voltage EVDD is applied, and a source connected to the second node N2.

[0074] The storage capacitor Cst can be connected between the first node N1 and the second node N2.

[0075] When the display panel PAN is driven, the first switching thin-film transistor ST1 can apply a data voltage Vdata applied to the data line DL to the first node N1 in response to the gating signal SCAN, and enable the driving thin-film transistor DT to conduct. In this example, the first switching thin-film transistor ST1 may include a gate connected to the gating line GL to which the scan signal SCAN is applied, a drain connected to the data line DL to which the data voltage Vdata is applied, and a source connected to the first node N1.

[0076] The second switching thin-film transistor ST2 can switch the current between the second node N2 and the sensing voltage readout line SRL in response to the sensing signal SEN, so that the source voltage at the second node N2 can be stored in the sensing capacitor Cx of the voltage readout line SRL. When the display panel PAN is driven, the second switching thin-film transistor ST2 can switch the current flowing between the second node N2 and the sensing voltage readout line SRL in response to the sensing signal SEN to reset the source voltage of the driving thin-film transistor DT to the initialization voltage Vpre. In this example, the gate of the second switching thin-film transistor ST2 can be connected to the same sensing line SL or another sensing line SL, and its drain and source can be connected to the second node N2 and the sensing voltage readout line SRL, respectively.

[0077] Despite Figure 3As shown, an organic light-emitting display device 100 having a structure including three thin-film transistors (T) and a storage capacitor (C) (which may be referred to as a 3T1C structure) has been discussed as an example; however, the organic light-emitting display device 100 of this disclosure is not limited to this specific structure. For example, the organic light-emitting display device 100 according to embodiments of this disclosure may have one or more of various structures such as 4T1C, 5T1C, 6T1C, 7T1C, 8T1C, etc.

[0078] Figure 4A This is a cross-sectional view of an organic light-emitting display device 100 according to an embodiment of the present disclosure, and illustrates a first thin-film transistor GT, which includes a polycrystalline semiconductor pattern and is disposed in a non-display area NA (e.g., GIP area), representing a thin-film transistor; a driving thin-film transistor DT, which includes a first oxide semiconductor pattern and is disposed inside a sub-pixel in the display area AA and configured to drive an organic electroluminescent element such as an organic light-emitting diode; a switching thin-film transistor ST, which includes a second oxide semiconductor pattern; and a storage capacitor Cst.

[0079] Figure 4B An example is given showing only the storage capacitor and... Figure 4A The storage capacitor Cst in the embodiments are formed or arranged differently, and the configuration and / or formation of the remaining elements are different from their configuration in the embodiments. Figure 4A The implementation methods are essentially the same.

[0080] like Figure 4A As shown, the driving thin-film transistor DT and the switching thin-film transistor ST can be disposed in the sub-pixel above the substrate 401. Although Figure 4A An example is shown of driving a thin-film transistor DT and having only one first switching thin-film transistor ST; however, this is merely for the sake of description. In actual implementation, multiple switching thin-film transistors can be set in a sub-pixel.

[0081] In one embodiment, one or more first thin-film transistors GT, including a gating driver, may be disposed in the non-display area NA of substrate 401.

[0082] The first thin-film transistor GT may include a polycrystalline semiconductor pattern 414 disposed on at least one lower buffer layer (402 and / or 411) disposed on a substrate 401, a first gate insulating layer 442 for insulating the polycrystalline semiconductor pattern 414, a first gate 416 disposed on the first gate insulating layer 442 and overlapping the polycrystalline semiconductor pattern 414, a plurality of insulating layers disposed on the first gate 416, and a first source 417S and a first drain 417D disposed on the plurality of insulating layers.

[0083] The first thin-film transistor GT may also include a first light-shielding pattern BSM-1 located below the polycrystalline semiconductor pattern 414 to protect the polycrystalline semiconductor pattern 414 from light from the outside. In some embodiments, the first light-shielding pattern BSM-1 may not be necessary. Therefore, the first light-shielding pattern BSM-1 may be selectively formed according to design considerations.

[0084] The first light-shielding pattern BSM-1 may be a metal pattern formed on the first lower buffer layer 402. The material of the first light-shielding pattern BSM-1 according to embodiments of the present disclosure is not limited to such thin-film metal.

[0085] The first light-shielding pattern BSM-1 can be formed below the polycrystalline semiconductor pattern 414 and has a larger size than the polycrystalline semiconductor pattern 414 so as to completely block external light from entering the polycrystalline semiconductor pattern 414. For example, the first light-shielding pattern BSM-1 can completely overlap with the polycrystalline semiconductor pattern 414.

[0086] The substrate 401 may have a multilayer structure in which organic and inorganic layers are stacked alternately. For example, the substrate 401 may be formed such that an organic layer, such as polyimide, and an inorganic layer, such as silicon oxide (SiO2), are stacked alternately.

[0087] A first lower buffer layer 402 may be disposed on a substrate 401. The first lower buffer layer 402 may block moisture and other substances that may penetrate from the outside, and may be formed such that at least one silicon oxide (SiO2) film or the like is stacked to form a multilayer.

[0088] The first light-shielding pattern BSM-1 can be set on the first lower buffer layer 402.

[0089] The second lower buffer layer 411 may also be disposed on the first light-shielding pattern BSM-1. The second lower buffer layer 411 may include the same material as the first lower buffer layer 402.

[0090] A polycrystalline semiconductor pattern 414 can be disposed on the second lower buffer layer 411. The polycrystalline semiconductor pattern 414 can be formed using a polycrystalline semiconductor material and includes a first channel region 414a through which charge moves, and a first source region 414b and a first drain region 414c adjacent to the first channel region 414a, the first channel region 414a being interposed between the first source region 414b and the first drain region 414c. The first source region 414b and the first drain region 414c can be conductive regions generated by doping the intrinsic polycrystalline semiconductor pattern with impurity ions such as phosphorus or boron.

[0091] The polycrystalline semiconductor pattern 414 can be insulated by the first gate insulating layer 442.

[0092] The first gate insulating layer 442 can be formed by depositing an inorganic insulating layer, such as silicon oxide (SiO2), on the entire surface of a substrate 401 on which a polycrystalline semiconductor pattern 414 is formed. The first gate insulating layer 442 can protect the polycrystalline semiconductor pattern 414 from external influences and insulate the polycrystalline semiconductor pattern 414 relative to the outside.

[0093] A first gate 416 overlapping with the first channel region 414a of the polycrystalline semiconductor pattern 414 can be disposed on the first gate insulating layer 442.

[0094] The first gate 416 may include a metallic material. For example, the first gate 416 may be formed of a single layer or multiple layers, which may include one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or include one or more alloys containing two or more of them; however, embodiments of this disclosure are not limited thereto.

[0095] Multiple insulating layers may be disposed between the first gate 416 and the first source 417S and the first drain 417D.

[0096] Reference Figure 4A The plurality of insulating layers may include a first interlayer insulating layer 443 contacting the upper surface of the first gate 416, and a second interlayer insulating layer 444, an upper buffer layer 445, a second gate insulating layer 446, and a third interlayer insulating layer 447 sequentially stacked on the first interlayer insulating layer 443. The first interlayer insulating layer 443 and the second interlayer insulating layer 444 may be referred to as intermediate insulating layers to distinguish them from the third interlayer insulating layer 447.

[0097] The first source 417S and the first drain 417D can be disposed on the third interlayer insulating layer 447. The first source 417S and the first drain 417D can be directly connected to the first source region 414b and the first drain region 414c through the first contact hole CH1 and the second contact hole CH2 passing through the first gate insulating layer 442, the first interlayer insulating layer 443, the second interlayer insulating layer 444, the upper buffer layer 445, the second gate insulating layer 446 and the third interlayer insulating layer 447, respectively.

[0098] For example, the first source 417S and the first drain 417D can be connected to the first source region 414b and the first drain region 414c respectively through the first connection electrode CE1 disposed in the first contact hole CH1 and the second contact hole CH2.

[0099] The first contact hole CH1 may include a first portion CH1-1 passing through the first gate insulating layer 442, the first interlayer insulating layer 443, the second interlayer insulating layer 444 and the upper buffer layer 445, and a second portion CH1-2 passing through the second gate insulating layer 446 and the third interlayer insulating layer 447.

[0100] For example, the first connecting electrode CE1 disposed in the first contact hole CH1 may include a first portion disposed in the first part CH1-1 of the first contact hole and a second portion disposed in the second part CH1-2 of the first contact hole.

[0101] The first part of the first connecting electrode CE1 and the second part of the first connecting electrode CE1 may have at least one connecting node that is connected to each other inside the first contact hole CH1.

[0102] Reference Figure 4A The first part of the first connecting electrode CE1 and the second part of the first connecting electrode CE1 may have a connection node located at the boundary between the upper buffer layer 445 and the second gate insulating layer 446.

[0103] Since the first part of the first connecting electrode CE1 and the second part of the first connecting electrode CE1 are formed through different processes, a connection node can be formed at the location where the first part and the second part are connected.

[0104] The first portion and the second portion of the first connecting electrode CE1 may include the same conductive material as the first source 417S and the first drain 417D.

[0105] For example, the second portion of the first connecting electrode CE1, as well as the first source 417S and the first drain 417D, can be formed substantially simultaneously or together in a single photolithography process.

[0106] In this embodiment, the first portion and the second portion of the first connecting electrode CE1 may comprise different conductive materials. For example, the first portion and the second portion of the first connecting electrode CE1 may be in ohmic contact with each other to reduce resistance.

[0107] The first connecting electrode CE1 can be formed from a single layer or multiple layers. The first connecting electrode CE1 can be formed from multiple layers of titanium, aluminum and titanium stacked together.

[0108] For example, the first interlayer insulating layer 443 may include at least one inorganic layer and may include a silicon nitride layer (SiNx) containing hydrogen particles.

[0109] During the heat treatment process following the provision of the first interlayer insulating layer 443 to cover the first gate 416, hydrogen particles may diffuse into the first source region 414b and the first drain region 414c, making them conductive. Therefore, this provides the advantage of reducing associated processes, as a separate impurity doping process is not required to make the first source region 414b and the first drain region 414c, which are intrinsic semiconductor materials, conductive.

[0110] In an implementation, the pixel circuit section 430 of a sub-pixel may include a driving thin-film transistor DT and at least one switching thin-film transistor ST. In an example where a sub-pixel includes one or more switching thin-film transistors ST, all of the one or more switching thin-film transistors may include an oxide semiconductor pattern, or some of the switching thin-film transistors may include an oxide semiconductor pattern and the others may include a polycrystalline semiconductor pattern (this may be referred to as a hybrid type).

[0111] For example, Figure 4A An example is shown of a driving thin-film transistor DT including an oxide semiconductor pattern and a switching thin-film transistor including an oxide semiconductor pattern.

[0112] The driving thin-film transistor DT may include a first oxide semiconductor pattern 424, a second gate 426 overlapping the first oxide semiconductor pattern 424, a second source 427S, and a second drain 427D.

[0113] Oxide semiconductors can include oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). More specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

[0114] In conventional technologies, polycrystalline semiconductor patterns, which are advantageous for high-speed operation, have been used as active layers for driving thin-film transistors (TFTs). However, TFTs that include polycrystalline semiconductor patterns suffer from leakage current flowing in the off-state and the power consumption caused by this leakage current. In particular, this power consumption in the off-state becomes more problematic when the display device operates at low speeds (such as when playing still images such as text documents or photos). According to embodiments of this disclosure, the display device 100 may include TFTs that include oxide semiconductor patterns as active layers to help prevent or reduce leakage current.

[0115] In examples where thin-film transistors employ oxide semiconductor patterns as the active layer, the material properties of oxide semiconductors result in large current fluctuations per unit voltage fluctuation, often leading to display artifacts at low grayscale levels where precise current control is required. To address this issue, according to embodiments of this disclosure, the display device 100 may include a driving thin-film transistor containing an oxide semiconductor pattern, in which the current fluctuation in the active layer is relatively less affected by fluctuations in the voltage applied to the gate.

[0116] The driving thin-film transistor DT may include a first oxide semiconductor pattern 424 located on an upper buffer layer 445, a second gate insulating layer 446 covering the first oxide semiconductor pattern 424, a second gate 426 disposed on the second gate insulating layer 446 and overlapping the first oxide semiconductor pattern 424, a third interlayer insulating layer 447 covering the second gate 426, and a second source 427S and a second drain 427D disposed on the third interlayer insulating layer 447.

[0117] The first oxide semiconductor pattern 424 used as the active layer may include a second channel region 424a through which charge moves, and a second source region 424b and a second drain region 424c adjacent to the second channel region 424a, wherein the second channel region 424a is interposed between the second source region 424b and the second drain region 424c.

[0118] The second channel region 424a may include an intrinsic oxide semiconductor without any doped impurities. In an embodiment, the second source region 424b and the second drain region 424c may be conductive regions generated by doping group IIIA or group VA impurity ions into the intrinsic oxide semiconductor.

[0119] The second light-shielding pattern BSM-2 can be formed below the first oxide semiconductor pattern 424. The second light-shielding pattern BSM-2 can be a metal pattern capable of shielding external light in order to prevent or at least reduce the failure of the first oxide semiconductor pattern 424 due to external light reaching the first oxide semiconductor pattern 424.

[0120] The second light-shielding pattern BSM-2 can be a metal layer comprising titanium (Ti) material, which has excellent ability to capture hydrogen particles. For example, the second light-shielding pattern BSM-2 can be formed from a single layer of titanium or a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy comprising molybdenum (Mo) and titanium (Ti). However, embodiments of this disclosure are not limited thereto. For example, the second light-shielding pattern BSM-2 can also be formed from another metal layer comprising titanium (Ti).

[0121] Titanium (Ti) can trap hydrogen particles that diffuse into the upper buffer layer 445 to prevent hydrogen particles from reaching the first oxide semiconductor pattern 424.

[0122] In one embodiment, the second light-shielding pattern BSM-2 can be vertically disposed below the first oxide semiconductor pattern 424, such that the second light-shielding pattern BSM-2 can overlap with the first oxide semiconductor pattern 424. In another embodiment, the second light-shielding pattern BSM-2 can have a larger size or area than the first oxide semiconductor pattern 424, such that the second light-shielding pattern BSM-2 can completely overlap with the first oxide semiconductor pattern 424.

[0123] The second source 427S driving the thin-film transistor DT can be electrically connected to the second light-shielding pattern BSM-2. In the example where the second light-shielding pattern BSM-2 is electrically connected to the second source 427S, the following additional advantages can be obtained.

[0124] Because the second source region 424b and the second drain region 424c are doped with impurities, the parasitic capacitance C act Parasitic capacitance C can be formed inside the first oxide semiconductor pattern 424. gi It can be formed between the second gate 426 and the first oxide semiconductor pattern 424, and the parasitic capacitance C buf It can be formed between the second light-shielding pattern BSM-2, which is electrically connected to the second source 427S, and the first oxide semiconductor pattern 424.

[0125] Since the first oxide semiconductor pattern 424 and the second light-shielding pattern BSM-2 are electrically connected through the second source 427S, the parasitic capacitance C act and parasitic capacitance C buf They can be connected in parallel, and the parasitic capacitance C act and parasitic capacitance C gi They can be connected in series. When V gat When the gate voltage is applied to the second gate 426, the effective voltage V actually applied to the first oxide semiconductor pattern 424 can be obtained by Equation 1 below. eff .

[0126] ΔV=Cgi / (Cgi+Cact+Cbuf)×ΔVgat

[0127] Therefore, due to the effective voltage V applied to the second channel region 424a eff With parasitic capacitance C buf It is inversely proportional, so the parasitic capacitance C can be adjusted. buf This adjusts the effective voltage applied to the first oxide semiconductor pattern 424. For example, when the second light-shielding pattern BSM-2 is positioned close to the first oxide semiconductor pattern 424 to increase the parasitic capacitance C... buf At this time, the actual current value flowing through the first oxide semiconductor pattern 424 can be reduced.

[0128] The reduction in the effective current value flowing through the first oxide semiconductor pattern 424 can mean that the s-factor of driving the thin-film transistor DT can be increased, and the voltage V actually applied to the second gate 426 can be expanded. gat The control range of the driving thin-film transistor DT is controlled.

[0129] Therefore, when the second source 424S driving the thin-film transistor DT is electrically connected to the second light-shielding pattern BSM-2 and the second light-shielding pattern BSM-2 is positioned close to the first oxide semiconductor pattern 424, even at low grayscale, organic light-emitting elements such as organic light-emitting diodes can be precisely controlled, and thus, display artifacts such as color difference and screen blotch that frequently occur at low grayscale can be resolved.

[0130] Here, the s-factor is sometimes called the "subthreshold slope" and represents the voltage required for the current to increase tenfold. In a graph (IV curve) showing the characteristics of the drain current relative to the gate voltage, the s-factor is equal to the reciprocal of the slope of the graph in the range below the threshold voltage.

[0131] A small s-factor may mean a large slope in the characteristic curve (IV) of the drain current relative to the gate voltage. In this case, the corresponding thin-film transistor can be turned on by even a very small voltage, thus improving the switching characteristics of the thin-film transistor. However, because the threshold voltage is reached in a short time, the corresponding grayscale may not be sufficient to accurately display the image.

[0132] A large s-factor may mean a small slope in the characteristic curve (IV) of the drain current relative to the gate voltage. In this case, although the turn-on / turn-off response speed of the corresponding thin-film transistor may be reduced, the grayscale is sufficient to accurately display the image because the threshold voltage is reached within a relatively long time.

[0133] For example, as the second light-shielding pattern BMS-2 is inserted into the interior of the upper buffer layer 445, the second light-shielding pattern BMS-2 can be disposed close to the first oxide semiconductor pattern 424. In this embodiment, Figures 4A to 4C An example is illustrated using multiple sub-buffer layers. For instance, the upper buffer layer 445 may have a structure in which a first sub-buffer layer 445a and a second sub-buffer layer 445b are stacked. In an embodiment, the upper buffer layer 445 may have a structure in which a first sub-buffer layer 445a, a second sub-buffer layer 445b, and a third sub-buffer layer (not shown) are stacked in sequence.

[0134] The second light-shielding pattern BSM-2 can be disposed on the first sub-buffer layer 445a disposed on the second interlayer insulating layer 444. The second sub-buffer layer 445b can be disposed on the second light-shielding pattern BSM-2.

[0135] although Figure 4A The embodiments described illustrate a structure in which multiple sub-buffer layers are stacked such that the second light-shielding pattern BSM-2 can be inserted into the interior of the upper buffer layer 445; however, the embodiments of this disclosure are not limited thereto. As suggested in Formula 1 above, since the effective voltage applied to the second channel region 424a can be adjusted by adjusting the distance between the second light-shielding pattern BSM-2 and the first oxide semiconductor pattern 424, a technique for adjusting the distance between the second light-shielding pattern BSM-2 and the first oxide semiconductor pattern 424 can be provided.

[0136] The first sub-buffer layer 445a and the second sub-buffer layer 445b may include silicon oxide (SiO2).

[0137] The first sub-buffer layer 445a and the second sub-buffer layer 445b may comprise silicon oxide (SiO2) free of hydrogen particles, thus protecting the oxide semiconductor pattern from hydrogen particles that may penetrate during the heat treatment process, and improving the reliability of the oxide semiconductor pattern.

[0138] The second light-shielding pattern BSM-2 can be a metal layer comprising titanium (Ti) material, which has excellent ability to capture hydrogen particles. For example, the second light-shielding pattern BSM-2 can be formed from a single layer of titanium, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy comprising molybdenum (Mo) and titanium (Ti). However, the embodiments of this disclosure are not limited thereto. For example, the second light-shielding pattern BSM-2 can also be formed from another metal layer comprising titanium (Ti).

[0139] Titanium (Ti) is able to trap hydrogen particles that diffuse into the upper buffer layer 445 to prevent hydrogen particles from reaching the first oxide semiconductor pattern 424.

[0140] In an embodiment, considering its function, the second light-shielding pattern BSM-2 can be vertically disposed below the first oxide semiconductor pattern 424 so that the second light-shielding pattern BSM-2 can overlap with the first oxide semiconductor pattern 424. In an embodiment, the second light-shielding pattern BSM-2 can have a larger size or area than the first oxide semiconductor pattern 424 so that the second light-shielding pattern BSM-2 can completely overlap with the first oxide semiconductor pattern 424.

[0141] The second gate 426 driving the thin-film transistor DT can be disposed above the first oxide semiconductor pattern 424. The second gate 426 can overlap with the second channel region 424a. The second gate insulating layer 446 can be interposed between the second gate 426 and the first oxide semiconductor pattern 424.

[0142] The second source 427S and the second drain 427D can be disposed above the second gate 426.

[0143] The third interlayer insulating layer 447 can be inserted between the second source 427S, the second drain 427D, and the second gate 426.

[0144] The second source 427S can be connected to the second source region 424b through the fifth contact hole CH5 passing through the second gate insulating layer 446 and the third interlayer insulating layer 447, and the second drain 427D can be connected to the second drain region 424c through the sixth contact hole CH6 passing through the second gate insulating layer 446 and the third interlayer insulating layer 447.

[0145] In one embodiment, the second source 427S can be electrically connected to the second light-shielding pattern BSM-2 through a fourth contact hole CH4 passing through a portion of the upper buffer layer 445, the second gate insulating layer 446, and the third interlayer insulating layer 447.

[0146] Each of the fifth contact hole CH5 and the sixth contact hole CH6 can be formed as a single body, and the second connecting electrode CE2 can be disposed inside each of the fifth contact hole CH5 and the sixth contact hole CH6.

[0147] The second source 427S and the second drain 427D can be connected to the second source region 424b and the second drain region 224c respectively through the corresponding second connecting electrode CE2.

[0148] The second connecting electrode CE2, the second source 427S, and the second drain 427D may comprise the same conductive material. For example, the second connecting electrode CE2, the second source 427S, and the second drain 427D may comprise the same material as the first source 417S and the first drain 417D, and may be formed substantially simultaneously with the first source 417S and the first drain 417D.

[0149] In an embodiment, the second light-shielding pattern BSM-2 can be connected to the second source electrode 427S via the third connecting electrode CE3 disposed inside the fourth contact hole CH4.

[0150] The fourth contact hole CH4 may include a first portion CH4-1 formed in the second sub-buffer layer 445b, and a second portion CH4-2 formed through the second gate insulating layer 446 and the third interlayer insulating layer 447.

[0151] The third connecting electrode CE3 may include a first portion formed in the first portion CH4-1 of the fourth contact hole and a second portion formed in the second portion CH4-2 of the fourth contact hole, and has a connecting node located at the boundary between the first portion and the second portion.

[0152] The first portion and the second portion of the third connecting electrode CE3 may comprise the same conductive material. In another embodiment, the first portion and the second portion of the third connecting electrode CE3 may comprise different conductive materials, and in this embodiment, the first portion and the second portion may comprise different types of conductor materials, which allow for ohmic contact between them to achieve low contact resistance.

[0153] The second source 427S, the second drain 427D, and the second portion of the third connecting electrode may comprise the same material and are substantially formed simultaneously.

[0154] Reference Figure 4A Subpixels may also include storage capacitors Cst.

[0155] The storage capacitor Cst can store the data voltage applied through the data line for a certain period of time and provide data voltage to organic light-emitting elements such as organic light-emitting diodes.

[0156] The storage capacitor Cst may include two corresponding electrodes and a dielectric disposed between the two electrodes. The storage capacitor Cst may include a first electrode 450A and a second electrode 450B corresponding to the first electrode 450A. The first electrode 450A contains the same material as the first gate 416 and is disposed in the same layer as the first gate 416.

[0157] The first interlayer insulating layer 443 can be inserted between the first electrode 450A and the second electrode 450B of the storage capacitor. The second electrode 450B of the storage capacitor can be electrically connected to the second source electrode 427S.

[0158] The second electrode 450B of the storage capacitor can be connected to the second source electrode 427S via the fourth connection electrode CE4 formed in the third contact hole CH3.

[0159] Similar to the first contact hole CH1 and the fourth contact hole CH4, the third contact hole CH3 may include two parts. Similar to the first connecting electrode CE1 and the third connecting electrode CE3, the fourth connecting electrode CE4 may have a connecting node located between its two edges (e.g., in its middle portion).

[0160] For example, the third contact hole CH3 may include a first portion CH3-1 passing through the upper buffer layer 445 and the second interlayer insulating layer 444, and a second portion CH3-2 passing through the second gate insulating layer 446 and the third interlayer insulating layer 447. In an embodiment, the fourth connection electrode CE4 may include a first portion formed in the first portion CH3-1 of the third contact hole and a second portion formed in the second portion CH3-2 of the third contact hole, and has a connection node located at the boundary between the first portion and the second portion.

[0161] Figure 4B An example is shown where the storage capacitor Cst is configured differently. Figure 4A The storage capacitor Cst in the embodiment.

[0162] Figure 4A The second electrode 450B of the storage capacitor and the second light-shielding pattern BSM-2 are disposed in different layers. In this embodiment where the second electrode 450B and the second light-shielding pattern BSM-2 of the storage capacitor are formed in different layers, an additional masking process is required. Figure 4B In this embodiment, the second electrode 450B of the storage capacitor and the second light-shielding pattern BSM-2 can be formed together during a single masking process. (Including...) Figure 4B The remaining elements in the implementation scheme can be substantially the same as those in the following embodiments. Figure 4A Since the components are the same, related discussions will be omitted for the sake of convenience.

[0163] Reference Figure 4A Subpixels may include switching thin-film transistors (STs) containing oxide semiconductor patterns. Although in Figure 4A The illustration shows a switching thin-film transistor (ST), but one or more ST switching transistors can be provided in a sub-pixel. For example, one or more ST switching transistors can be provided in the pixel circuit of a sub-pixel according to various configurations such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 8T1C, etc.

[0164] The switching thin-film transistor ST may include a second oxide semiconductor pattern 432, a third gate 433, a third source 434S, and a third drain 434D.

[0165] The second oxide semiconductor pattern 432 may include a third channel region 432a, and a third source region 432b and a third drain region 432c adjacent to the third channel region 432a, wherein the third channel region 432a is interposed between the third source region 432b and the third drain region 432c.

[0166] The third gate 433 can be positioned on the second gate insulating layer 446 located on the second oxide semiconductor pattern 432.

[0167] The third source 434S and the third drain 434D can be located on the third interlayer insulating layer 447 located on the third gate 433.

[0168] The third source 434S and the third drain 434D can be connected to the third source region 432b and the third drain region 432c respectively through the seventh contact hole CH7 and the eighth contact hole CH8 passing through the second gate insulating layer 446 and the third interlayer insulating layer 447.

[0169] In an implementation, the third light-shielding pattern BSM-3 may be disposed below the second oxide semiconductor pattern 432.

[0170] The third light-shielding pattern BSM-3 can be disposed below the second oxide semiconductor pattern 432 while overlapping with it, so as to protect the second oxide semiconductor pattern 432 from external light.

[0171] The third light-shielding pattern BSM-3 can be disposed on the first gate insulating layer 442 or the first interlayer insulating layer 443.

[0172] The third light-shielding pattern BSM-3 may comprise the same material as the first gate 416 and be disposed in the same layer as the first gate 416. In an embodiment, the third light-shielding pattern BSM-3 may comprise the same material as the first electrode 450A or the second electrode 450B of the storage capacitor Cst and be disposed in the same layer as the first electrode 450A or the second electrode 450B of the storage capacitor Cst.

[0173] Despite Figure 4AAlthough not shown, the third light-shielding pattern BSM-3 can be electrically connected to the third source 434S. The third light-shielding pattern BSM-3 can protect the second oxide semiconductor pattern 432 from external light, and in some embodiments, a voltage can be applied to the third light-shielding pattern BSM-3 to stabilize the third channel region 432a, thereby improving the reliability of the switching thin-film transistor ST.

[0174] In some embodiments, the display device 100 may include a curved bezel structure. (See also...) Figure 4C When the first portion CH1-1 of the first contact hole in the non-display area is formed, the upper buffer layer 445 formed in the bezel bending area BA of the non-display area NA, and one or more inorganic insulating layers disposed between the upper buffer layer 445 and the substrate 401, can also be etched and removed. (Refer to...) Figure 4C All inorganic insulating layers located within a height d2 from the substrate 401 can be removed to form the second opening OA2. In this process, a portion of the upper surface of the substrate 401 located in the non-display area NA may also be etched.

[0175] The inorganic insulating layer may include a first lower buffer layer 402, a second lower buffer layer 411, a first gate insulating layer 442, a first interlayer insulating layer 443, a second interlayer insulating layer 444, and an upper buffer layer 445.

[0176] The first portion CH1-1 of the first contact hole can penetrate the first interlayer insulating layer 443 containing hydrogen particles formed on the first gate 416, and in this situation, hydrogen particles may be generated. Such hydrogen particles can help to conduct the source and drain regions of the polycrystalline semiconductor pattern during thermal processing, but when these hydrogen particles enter the oxide semiconductor pattern, the reliability of the thin-film transistor may be reduced. In some embodiments, the first portion CH1-1 of the first contact hole can be pre-formed before the oxide semiconductor pattern is formed on the upper buffer layer 445, thereby protecting the oxide semiconductor pattern from hydrogen particles that may be generated from the first interlayer insulating layer 443.

[0177] In an implementation, the bezel bending region BA may include a first opening OA1. The first opening OA1 can be substantially formed simultaneously with the formation of the fifth contact hole CH5 to the eighth contact hole CH8 in the display region AA. For example, the first opening OA1 can be formed by etching the second gate insulating layer 446 and the third interlayer insulating layer 447 disposed in the non-display region NA.

[0178] Since the bend area BA is the area where the substrate 401 and the thin film or layer stacked thereon are folded or bent, it may be desirable to remove all inorganic insulating layers that are prone to cracking.

[0179] In this embodiment, all inorganic insulating layers disposed on the substrate 401 in the bend region BA can be removed, and instead, a first planarization layer PLN1 and a second planarization layer PLN2, which can be organic layers, can be disposed. This protects the wires or other components disposed in the bend region BA.

[0180] Reference Figure 4A After setting the pixel circuit section 430, which includes multiple thin-film transistors, in the display area AA, a light-emitting element section 460 and an encapsulation layer 470 can also be set above the substrate 401.

[0181] A first planarization layer PLN1 can be disposed above a substrate 401 on which a driving thin-film transistor DT and a switching thin-film transistor ST are disposed. The first planarization layer PLN1 can include an organic material such as photo-acrylic, or can be formed from multiple layers including inorganic and organic layers. A connection electrode 455 can be disposed on the first planarization layer PLN1. The connection electrode 455 can electrically connect the anode 456 of the light-emitting element portion 460 to the driving thin-film transistor DT through a ninth contact hole CH9 formed in the first planarization layer PLN1.

[0182] In one embodiment, the conductive layer used to form the connecting electrode 455 may form a portion of the connecting line 452 in the bending region BA.

[0183] The second planarization layer PLN2 can be disposed on the connecting electrode 455. As in the first planarization layer PLN1, the second planarization layer PLN2 can include an organic material such as photoacrylic acid, or can be formed of multiple layers including inorganic and organic layers.

[0184] The anode 456 can be disposed on the second planarization layer PLN2. The anode 456 can be electrically connected to the connecting electrode 455 through the tenth contact hole CH10 formed in the second planarization layer PLN2.

[0185] The anode 456 may be formed of a single layer or multiple layers, which may include one or more metals such as Ca, Ba, Mg, Al, Ag, etc., or one or more alloys containing two or more of them, and may be connected to the second drain 479D of the driving thin film transistor DT, so that an image signal can be applied to the anode 456.

[0186] In addition to the anode 456, the anode connection electrode 457, which is used to electrically connect the common voltage line VSS to the cathode 463, can also be provided in the non-display area NA.

[0187] A dike layer 461 can be provided on the second planarization layer PLN2. The dike layer 461 can be a separator for separating each sub-pixel, and can protect the sub-pixel by preventing or at least reducing the mixing of light of a specific color output from a neighboring sub-pixel into the light emitted from that sub-pixel.

[0188] An organic light-emitting layer 462 can be disposed on the surface of the anode 456 and at least a portion of the inclined surface of the embankment layer 461. The organic light-emitting layer 462 can be disposed in each sub-pixel and can be an R organic light-emitting layer emitting red light, a G organic light-emitting layer emitting green light, or a B organic light-emitting layer emitting blue light. In an embodiment, the organic light-emitting layer 462 can be a W organic light-emitting layer emitting white light.

[0189] The organic light-emitting layer 462 may include not only the light-emitting layer, but also an electron injection layer and a hole injection layer for injecting electrons and holes into the light-emitting layer, respectively, and an electron transport layer and a hole transport layer for transporting the injected electrons and holes into the organic layer, respectively.

[0190] The cathode 463 may be disposed on the organic light-emitting layer 462. The cathode 463 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a thin metal through which visible light is transmitted, but the embodiments disclosed herein are not limited thereto.

[0191] Encapsulation layer 470 may be disposed on cathode 463. Encapsulation layer 470 may be formed as a single layer including an inorganic layer, as a double layer of an inorganic layer and an organic layer, or as a triple layer of an inorganic layer, an organic layer, and an inorganic layer. The inorganic layer may include inorganic materials such as SiNx, SiX, etc., but embodiments of this disclosure are not limited thereto. In some embodiments, the organic layer may include organic materials such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, etc., or mixtures thereof, but embodiments of this disclosure are not limited thereto.

[0192] Figure 4A An example is an encapsulation layer 470 formed of three layers, such as an inorganic layer 471, an organic layer 472, and an inorganic layer 473.

[0193] A cover glass (not shown) may be disposed on the encapsulation layer 470 and attached, for example, using an adhesive layer (not shown). While any material can be used as the adhesive layer as long as it has good adhesion, heat resistance, and water resistance, in some embodiments, thermosetting resins such as epoxy compounds, acrylate compounds, or acrylic rubbers may be used. In embodiments, a light-curing resin may be used as the adhesive layer, and the adhesive layer may be cured by irradiation with light, for example, ultraviolet light.

[0194] The adhesive layer can be used as an encapsulant to prevent or at least reduce moisture penetration into the organic light-emitting display device and to bond the substrate 401 to the cover glass (not shown).

[0195] For example, protective films such as polystyrene (PS) film, polyethylene (PE) film, polyethylene naphthalate (PEN) film, polyimide (PI) film, or glass can be used as cover glass (not shown) for use as an encapsulation cap for encapsulating the organic light-emitting display device 100.

[0196] As described, the connecting electrodes (i.e., the first connecting electrode CE1, the third connecting electrode CE3, and the fourth connecting electrode CE4) may include connecting nodes located between the two edges of each connecting electrode, depending on the design considerations for the manufacturing process, and thus, this can provide the effect of preventing or at least reducing the reduction in the reliability of the oxide semiconductor patterns 424 and 432 due to hydrogen particles generated during the heat treatment process.

[0197] In conventional techniques, to reduce masking processes, the first source 417S to the third source 434S and the first drain 417D to the third drain 434D are formed simultaneously using a single masking process. Furthermore, each source and the corresponding source region of each corresponding semiconductor pattern can be connected to each other via contact holes formed by a single masking process, and hydrogen particles may be generated during the contact hole formation process.

[0198] In other words, during the process of forming the contact hole, hydrogen particles, including those in the first interlayer insulating layer 443 and the second interlayer insulating layer 444, may penetrate into the oxide semiconductor pattern formed on the upper buffer layer 445, thereby potentially reducing the reliability of the oxide semiconductor pattern. According to an embodiment of this disclosure, before the oxide semiconductor pattern is formed on the upper buffer layer 445, a first portion CH1-1 of the first contact hole, exposing the first source region 414b and the first drain region 414c of the polycrystalline semiconductor pattern, is first formed, followed by the formation of the oxide semiconductor pattern, and subsequently, a second portion CH1-2 of the first contact hole is formed. Therefore, it is possible to prevent or at least reduce the reduction in the reliability of the oxide semiconductor pattern due to hydrogen particles generated during the heat treatment process.

[0199] In the following text, reference will be made to Figures 5A to 5E A method for manufacturing a display device according to several aspects of this disclosure is briefly described.

[0200] Reference Figure 5A A first lower buffer layer 402, comprising silicon oxide, can be formed on the flexible substrate 401. The first lower buffer layer 402 can be formed from multiple layers. The first lower buffer layer 402 can be deposited on the entire upper surface of the substrate 401, including the display area AA and the non-display area NA. The first lower buffer layer 402 can be formed by chemical vapor deposition (CVD).

[0201] The first lower buffer layer 402 can be used to protect the thin-film transistor array layer from oxygen particles, moisture, etc. that penetrate from under the flexible substrate 401.

[0202] The first light-shielding pattern BSM-1 can be formed on the first lower buffer layer 402. The first light-shielding pattern BSM-1 can prevent or at least reduce the influence of external light on the semiconductor pattern formed on the substrate 401, thereby preventing or at least reducing the failure of the thin film transistor.

[0203] Reference Figure 5A The first light-shielding pattern BSM-1 can be formed below the first thin-film transistor GT disposed in the non-display area NA. In an embodiment in which a thin-film transistor including a polycrystalline semiconductor pattern is formed in the display area AA, the first light-shielding pattern BSM-1 can also be formed in this structure.

[0204] The first light-shielding pattern BSM-1 can be a conductive and opaque metallic pattern. However, embodiments of this disclosure are not limited thereto. For example, a semiconductor pattern or the like can be used for the first light-shielding pattern BSM-1.

[0205] The first light-shielding pattern BSM-1 can be formed by depositing a thin metal film on the first lower buffer layer 402 and then patterning it by performing a photolithography process.

[0206] The second lower buffer layer 411 can be deposited on the first light-shielding pattern BSM-1. The second lower buffer layer 411 can be formed in the same process as the first lower buffer layer 402 and uses the same material as the first lower buffer layer 402.

[0207] Then, a polycrystalline semiconductor pattern 414 can be formed on the second lower buffer layer 411. The polycrystalline semiconductor pattern 414 can be completed by depositing an amorphous semiconductor pattern on the second lower buffer layer 411 and then crystallizing it using a crystallization method and thereby patterning it.

[0208] A first gate insulating layer 442 may be deposited on a polycrystalline semiconductor pattern 414. The first gate insulating layer 442 may be an inorganic layer comprising silicon oxide. The first gate insulating layer 442 may be used to electrically insulate between a first gate 416 formed on the first gate insulating layer 442 and the polycrystalline semiconductor pattern 414.

[0209] The first gate 416 can be formed on the first gate insulating layer 442. When the first gate 416 is formed on the first gate insulating layer 442, the first electrode 450A of the storage capacitor and the third light-shielding pattern BSM-3 can be formed together. In addition, the same metal material as the first gate 416 can be used to form various interconnect lines and pads disposed in the non-display area NA.

[0210] The first gate 416 may include a metallic material. For example, the first gate 416 may be formed of a single layer or multiple layers, which may include one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or include one or more alloys containing two or more of them; however, embodiments of this disclosure are not limited thereto.

[0211] The first gate 416 can be formed by depositing a metal material on the first gate insulating layer 442 and then patterning it by performing a photolithography process.

[0212] The first gate 416 can be formed such that the first gate 416 partially overlaps with the polycrystalline semiconductor pattern 414. The overlapping region can become the channel region of the polycrystalline semiconductor pattern 414.

[0213] A first interlayer insulating layer 443 may be formed on the first gate 416. The first interlayer insulating layer 443 may be formed as a single layer or multiple layers, such that an inorganic layer including silicon nitride is deposited to form a single layer or multiple layers. The first interlayer insulating layer 443 may include a silicon nitride layer containing hydrogen particles. After the first interlayer insulating layer 443 is formed, hydrogen particles may diffuse and penetrate into the polycrystalline semiconductor pattern 414 during a heat treatment process performed on the first interlayer insulating layer 443, thereby making the polycrystalline semiconductor pattern 414 conductive, resulting in the formation of a first source region 414b and a first drain region 414c.

[0214] Next, a second electrode 450B of the storage capacitor, which overlaps with the first electrode 450A of the storage capacitor, can be formed on the first interlayer insulating layer 443.

[0215] The second electrode 450B of the storage capacitor can be formed using the same material as the first electrode 450A of the storage capacitor.

[0216] Next, a second interlayer insulating layer 444, comprising silicon oxide, can be deposited on the second electrode 450B of the storage capacitor. Each or all of the first interlayer insulating layer 443 and the second interlayer insulating layer 444 can be formed by a single layer or multiple layers.

[0217] Next, an upper buffer layer 445 can be formed on the second interlayer insulating layer 444.

[0218] According to embodiments of this disclosure, since the upper buffer layer 445 includes a second light-shielding pattern BSM-2, the upper buffer layer 445 may include a first sub-upper buffer layer 445a and a second sub-upper buffer layer 445b. The upper buffer layer 445 may include silicon oxide.

[0219] After depositing the first sub-buffer layer 445a on the second interlayer insulating layer 444, a second light-shielding pattern BSM-2 can be formed on the first sub-buffer layer 445a.

[0220] although Figure 5A An embodiment of the upper buffer layer 445 having a stacked structure of two inorganic layers is illustrated, but the embodiments of this disclosure are not limited thereto. For example, the upper buffer layer 445 may have a stacked structure of multiple inorganic layers. The distance between the second light-shielding pattern BSM-2 and the oxide semiconductor pattern 424 can be adjusted by forming the second light-shielding pattern BSM-2 in one of the multiple inorganic layers.

[0221] Next, a second sub-buffer layer 445b can be deposited on the second light-shielding pattern BSM-2 to complete the top buffer layer 445. The top buffer layer 445 can be used to distinguish between the polycrystalline semiconductor thin-film transistor formed thereunder and the oxide semiconductor thin-film transistor formed thereon.

[0222] According to an embodiment of the present disclosure, after the upper buffer layer 445 is formed, the process of forming contact holes through the deposited insulating layer can be performed first, instead of continuously forming oxide semiconductor patterns 424 on the upper buffer layer 445.

[0223] In the contact hole process, the first portion CH1-1 of the first contact hole exposing the first source region 414b, the first portion CH2-1 of the second contact hole exposing the first drain region 414c, the first portion CH3-1 of the third contact hole exposing the second electrode 450B of the storage capacitor, and the first portion CH4-1 of the fourth contact hole exposing the second light-shielding pattern BSM-2 can be formed substantially simultaneously.

[0224] Additionally, refer to Figure 5B At least a portion of each of the inorganic layers deposited on the non-display area NA of substrate 401 can be removed together. That is, referring to Figure 5BThe inorganic layer disposed within the range from the upper surface of the upper buffer layer 445 to the surface of the substrate 401 (i.e., the depth d2) can be removed. Since the inorganic layer in the non-display area NA is removed, the array substrate can be bent or folded.

[0225] When the first portion CH1-1 of the first contact hole is formed by passing through the first interlayer insulating layer 443 containing hydrogen particles, hydrogen particles may be generated in this situation. However, according to embodiments of the present disclosure, this process is performed before the oxide semiconductor pattern 424 is formed on the upper buffer layer 445, which can prevent or at least reduce damage to the oxide semiconductor pattern 424 from the oxide particles.

[0226] Next, refer to Figure 5C The first portion CE1-1 of the first connecting electrode can be formed in the first portion CH1-1 of the first contact hole. The first portion CE1-1 of the first connecting electrode can be connected to the first source region 414b and the first drain region 414c.

[0227] When the first portion CE1-1 of the first connecting electrode is formed, the first portion CE3-1 of the third connecting electrode and the first portion CE4-1 of the fourth connecting electrode can be formed together.

[0228] Next, refer to Figure 5D The first oxide semiconductor pattern 424 and the second oxide semiconductor pattern 432 can be formed on the upper buffer layer 445. Next, the second gate insulating layer 446, the second gate 426 and the third interlayer insulating layer 447 can be sequentially formed on the first oxide semiconductor pattern 424 and the second oxide semiconductor pattern 432.

[0229] Next, a second portion CH1-2 can be formed through the third interlayer insulating layer 447 and the second gate insulating layer 446 to form the first contact hole.

[0230] When the second portion CH1-2 of the first contact hole is formed, the second portion CH3-2 of the third contact hole, the second portion CH4-2 of the fourth contact hole, the fifth contact hole CH5 exposing the second source region 424b, the sixth contact hole CH6 exposing the second drain region 424c, the seventh contact hole CH7 exposing the third source region 432b, and the eighth contact hole CH8 exposing the third drain region 432c can substantially be formed simultaneously. For example, when the second portion CH1-2 of the first contact hole is formed, as follows: Figure 5D As shown, the second gate insulating layer 446 and the third interlayer insulating layer 447 within the depth of d1 can be removed.

[0231] In addition, the second gate insulating layer 446 and the third interlayer insulating layer 447 disposed in the non-display area NA of the substrate 401 can be removed together.

[0232] Next, refer to Figure 5E When the second part CE1-2 of the first connecting electrode is formed, the second connecting electrode CE2, the second part CE3-2 of the third connecting electrode and the second part CE4-2 of the fourth connecting electrode can be formed together.

[0233] The second portion CE1-2 of the first connecting electrode can be formed together with the first source electrode 417S. Therefore, the first source electrode 417S and the second portion CE1-2 of the first connecting electrode can be formed together in a single masking process. Since the second source electrode 427S and the second drain electrode 427D can be formed together with the first source electrode 417S and the first drain electrode 417D, the second connecting electrode CE2 can be formed together with the second source electrode 427S and the second drain electrode 427D.

[0234] Next, a first planarization layer PLN1 can be formed covering the source and drain (417S and 417D, 427S and 427D, and 434S and 434D), and then a second planarization layer PLN2 can be formed on the first planarization layer PLN1, causing the pixel circuit section 430 to be insulated.

[0235] The display device can be completed by forming the light-emitting element portion 460 and the encapsulation layer 470 on the second planarization layer PLN2.

[0236] The discussion and accompanying drawings given above are merely exemplary in nature and are not intended to limit the scope of this disclosure or its application. It will be apparent to those skilled in the art that various modifications and variations, such as combinations, separations, substitutions, and alterations of configurations, are possible in the described examples and embodiments without departing from the scope of the embodiments and examples of this disclosure. Although exemplary embodiments have been described for illustrative purposes, those skilled in the art will understand that various modifications and applications are possible without departing from the essential characteristics of this disclosure. For example, specific components of exemplary embodiments may be modified in various ways. The scope of this disclosure is to be interpreted as defined by the claims, and all technical ideas within the scope of the claims are to be construed as being included within the scope of this invention.

[0237] Cross-references to related applications

[0238] This application claims priority to Korean Patent Application No. 10-2022-0026589, filed with the Korean Intellectual Property Office on March 2, 2022, the entire contents of which are incorporated herein by reference.

Claims

1. An organic light-emitting display device, the organic light-emitting display device comprising: A substrate having a display area and a non-display area located outside the display area; A first thin-film transistor is disposed above the substrate and includes a first semiconductor pattern, a first gate overlapping the first semiconductor pattern, and a first source and a first drain connected to the first semiconductor pattern through a plurality of inserted insulating layers. The second thin-film transistor is disposed above the substrate and includes a second semiconductor pattern disposed in a different layer from the first semiconductor pattern, a second gate overlapping the second semiconductor pattern, a second source and a second drain connected to the second semiconductor pattern, and a second light-shielding pattern located below the second semiconductor pattern, overlapping the second semiconductor pattern and connected to one of the second source and the second drain. A third thin-film transistor is disposed above the substrate and includes a third semiconductor pattern disposed in the same layer as the second semiconductor pattern, a third gate overlapping the third semiconductor pattern, a third source and a third drain connected to the third semiconductor pattern, and a third light-shielding pattern located below and overlapping the third semiconductor pattern. Wherein, the vertical distance between the second light-shielding pattern and the second semiconductor pattern is shorter than the vertical distance between the third light-shielding pattern and the third semiconductor pattern, and The first source and the first drain each pass through multiple insulating layers and are connected by a first connection electrode including at least one connection node.

2. The organic light-emitting display device according to claim 1, wherein, The first semiconductor pattern includes a polycrystalline semiconductor pattern, and the second and third semiconductor patterns include oxide semiconductor patterns.

3. The organic light-emitting display device according to claim 2, wherein, The first thin-film transistor is disposed in either the display area or the non-display area, and the second and third thin-film transistors are disposed in the display area.

4. The organic light-emitting display device according to claim 3, wherein, The second thin-film transistor is a driving thin-film transistor disposed in the sub-pixel, and the third thin-film transistor is a switching thin-film transistor disposed in the sub-pixel.

5. The organic light-emitting display device according to claim 1, wherein, The plurality of insulating layers include: A first gate insulating layer is disposed between the first semiconductor pattern and the first gate; At least one intermediate insulating layer is disposed between the first gate and the upper buffer layer; The upper buffer layer is located between the at least one intermediate insulating layer and the second semiconductor pattern; A second gate insulating layer, the second gate insulating layer being located between the second semiconductor pattern and the second gate; and An interlayer insulating layer is located between the second gate and the second source and the second drain.

6. The organic light-emitting display device according to claim 5, wherein, The second light-shielding pattern is located inside the upper buffer layer, and the third light-shielding pattern is located below the upper buffer layer.

7. The organic light-emitting display device according to claim 6, wherein, The upper buffer layer includes multiple sub-buffer layers, and the second light-shielding pattern is disposed between the sub-buffer layers.

8. The organic light-emitting display device according to claim 6, wherein, The first connection electrode includes a connection node located between the upper buffer layer and the second gate insulating layer.

9. The organic light-emitting display device according to claim 8, wherein, The first connection electrode is made of the same material as the first source electrode and the second drain electrode.

10. The organic light-emitting display device according to claim 8, wherein, Different conductors make ohmic contact with the upper and lower parts of the first connecting electrode, respectively, based on the connection node.

11. The organic light-emitting display device according to claim 1, wherein, The second source and the second drain are connected to the second semiconductor pattern via a second connection electrode formed as a single body.

12. The organic light-emitting display device according to claim 1, further comprising: At least one lower buffer layer, the at least one lower buffer layer being located on the substrate; as well as A first light-shielding pattern is disposed between the substrate and the first semiconductor pattern.

13. The organic light-emitting display device according to claim 5, wherein, The at least one intermediate insulating layer includes a silicon nitride layer.

14. A method for manufacturing an organic light-emitting display device, the method comprising the following steps: A substrate is prepared, on which a display area and a non-display area are disposed; A first semiconductor pattern is formed on at least one lower buffer layer located on the substrate; A first gate insulating layer is formed on the first semiconductor pattern; A first gate is formed on the first gate insulating layer; At least one intermediate insulating layer is formed on the first gate; An upper buffer layer comprising a second light-shielding pattern is formed on the at least one intermediate insulating layer; A first portion of the first contact hole is formed, the first portion of the first contact hole passing through the upper buffer layer, the at least one intermediate insulating layer and the first gate insulating layer, and exposing a portion of the first semiconductor pattern; A first portion of a first connecting electrode is formed, and the first portion of the first connecting electrode is connected to the first semiconductor pattern through the first portion of the first contact hole; A second semiconductor pattern is formed on the upper buffer layer; A second gate is formed on a second gate insulating layer located on the second semiconductor pattern, and the second gate overlaps with the second semiconductor pattern; An interlayer insulating layer is formed on the second gate; A second portion of the first contact hole is formed, the second portion of the first contact hole passing through the interlayer insulating layer and the second gate insulating layer, and exposing the first portion of the first connection electrode; as well as A second portion of the first connecting electrode is formed, and the second portion of the first connecting electrode is connected to the first portion of the first connecting electrode through the second portion of the first contact hole.

15. The method according to claim 14, wherein, The step of forming the first semiconductor pattern on the at least one lower buffer layer located on the substrate includes: forming a first light-shielding pattern overlapping the first semiconductor pattern above the substrate.

16. The method according to claim 15, wherein, The lower buffer layer includes a first lower buffer layer disposed between the substrate and the first light-shielding pattern, and a second lower buffer layer disposed between the first light-shielding pattern and the first semiconductor pattern.

17. The method of claim 14, wherein, In the process of forming the second semiconductor pattern on the upper buffer layer, a third semiconductor pattern comprising the same material as the second semiconductor pattern is also formed on the upper buffer layer.

18. The method according to claim 17, wherein, In the process of forming the first gate on the first gate insulating layer, a third light-shielding pattern overlapping with the third semiconductor pattern and a first electrode of the storage capacitor are also formed.

19. The method of claim 18, further comprising the step of: A second electrode of the storage capacitor is formed between the first gate and the upper buffer layer, overlapping with the first electrode of the storage capacitor.

20. The method according to claim 18, wherein, In the process of forming the upper buffer layer including the second light-shielding pattern on the intermediate insulating layer, a second electrode of the storage capacitor overlapping with the first electrode of the storage capacitor is also formed.

21. The method according to claim 14, wherein, In the process of forming the first portion of the first contact hole that passes through the upper buffer layer, the at least one intermediate insulating layer and the first gate insulating layer and exposes the portion of the first semiconductor pattern, the upper buffer layer deposited in the non-display area and the inorganic insulating layer deposited between the upper buffer layer and the substrate are removed together.

22. The method according to claim 14, wherein, In the process of forming the second portion of the first connecting electrode that is connected to the first portion of the first connecting electrode through the second portion of the first contact hole, a first source and a first drain that are connected to the second portion of the first connecting electrode, and a second source and a second drain that are connected to the second semiconductor pattern are formed together.

23. The method according to claim 14, wherein, In the process of forming the second portion of the first contact hole that passes through the interlayer insulating layer and the second gate insulating layer and exposes the first portion of the first connection electrode, the interlayer insulating layer and the second gate insulating layer deposited in the non-display area of ​​the substrate are removed together.

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