Charge-coupled device and image sensor

Abstract

This application provides a charge-coupled device (CCD) and an image sensor, relating to the field of semiconductor technology, to solve the technical problem of poor anti-corona effect. The CCCD includes a substrate, a memory cell group, and an anti-corona structure. The memory cell group includes two rows of memory cells, with the anti-corona structure between the two rows. Each row of memory cells includes an N-type buried layer disposed within the substrate. The anti-corona structure includes an N-type doped region disposed within the substrate and between adjacent N-type buried layers, and a first doped layer connecting the N-type buried layer and the N-type doped region. The first doped layer has an N-type conductivity, and its doping concentration is lower than that of the N-type buried layer and the N-type doped region. The first doped layer acts as an electron barrier between the N-type buried layer and the N-type doped region, storing electrons in the N-type buried layer and serving as an overflow channel for electrons after the N-type buried layer is full, allowing excess electrons to overflow into the N-type doped region, thus achieving a better anti-corona effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a charge-coupled device and an image sensor. Background Technology

[0002] Time Delay Integration (TDI) image sensors have been widely used in fields such as space exploration, industrial inspection, and medical imaging. The imaging mechanism of TDI image sensors involves exposing each pixel as it passes through the object being photographed, accumulating the exposures, and thus solving the problem of weak imaging signals caused by insufficient exposure time for high-speed moving objects. This increases the effective exposure time and improves the image signal-to-noise ratio.

[0003] Time-delay integral image sensors include charge-coupled devices (CCDs), which can achieve lossless charge transfer and accumulation without introducing additional noise. CCDs typically consist of multiple rows of memory cells. To prevent electrons from overflowing into adjacent memory cells, an anti-corona structure is placed between adjacent rows. However, existing anti-corona structures have poor anti-corona performance. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a charge-coupled device and an image sensor to improve the anti-halo effect of the anti-halo structure.

[0005] In a first aspect, embodiments of this application provide a charge-coupled device, including a substrate, a plurality of memory cell groups arranged at intervals along a first direction, and an anti-corona structure, wherein each memory cell group includes two columns of memory cells arranged at intervals along the first direction, and the anti-corona structure is disposed between the two columns of memory cells;

[0006] Each column of the memory cells includes an N-type buried layer disposed in the substrate and extending along a second direction, the second direction intersecting the first direction. The anti-corona structure includes an N-type doped region disposed in the substrate and located between adjacent N-type buried layers, a first doped layer connecting the N-type buried layer and the N-type doped region, a first dielectric layer disposed on the substrate and opposite to the first doped layer, and an anti-corona gate disposed on the first dielectric layer.

[0007] The first doped layer has an N-type conductivity, and the doping concentration of the first doped layer is lower than the doping concentration of the N-type buried layer and lower than the doping concentration of the N-type doped region.

[0008] In some possible embodiments, there are multiple anti-corona structures between two columns of storage cells in each group of storage cells, and the multiple anti-corona structures are spaced apart along the second direction;

[0009] The charge-coupled device further includes an isolation layer disposed within the substrate. The isolation layer is located between the N-type doped regions of two adjacent anti-corona structures and between the first doped layers of two adjacent anti-corona structures. The conductivity type of the isolation layer is P-type, and the potential of the isolation layer is the lowest.

[0010] In some possible embodiments, each column of the memory cells further includes a second dielectric layer disposed on the substrate and opposite to the N-type buried layer, and a plurality of control gates disposed on the second dielectric layer and spaced apart along the second direction;

[0011] The N-type buried layer between two adjacent control gates along the second direction is opposite to and adjacent to the isolation layer.

[0012] In some possible embodiments, the first doped layer is made of monocrystalline silicon, and along the first direction, the length of the first doped layer is greater than 0.5 micrometers, the depth is less than 0.5 micrometers, and the doping concentration is less than 2 × 10⁻⁶. 16 / cm 3 And higher than 1×10 14 / cm 3 ;

[0013] And / or, along the second direction, the distance between two adjacent anti-corona gates is greater than 0.2 micrometers;

[0014] And / or, along the first direction, the distance between the control gate and the anti-corona gate is greater than 0.1 micrometers and less than 0.4 micrometers.

[0015] In some possible embodiments, the isolation layer is made of monocrystalline silicon, and along the second direction, the isolation layer has a width greater than 0.3 micrometers, a depth greater than 0.6 micrometers, and a doping concentration greater than 5 × 10⁻⁶. 16 / cm 3 Furthermore, the doping concentration on the top surface of the isolation layer is greater than 1×10⁻⁶. 18 / cm 3 .

[0016] In some possible embodiments, the anti-corona structure further includes a second doped layer disposed below the first doped layer, the second doped layer having an opposite conductivity type to the first doped layer, and the doping concentration of the second doped layer being greater than that of the first doped layer.

[0017] In some possible embodiments, the second doped layer of the plurality of anti-corona structures arranged along the second direction is a single structure.

[0018] In some possible embodiments, the charge-coupled device further includes a buffer layer disposed within the substrate, the buffer layer covering both ends of the N-type doped region along the first direction and the bottom end of the N-type doped region;

[0019] The buffer layer has an N-type conductivity, and the doping concentration of the buffer layer is less than the doping concentration of the N-type doped region.

[0020] In some possible embodiments, the buffer layer is made of monocrystalline silicon, and along the second direction, the width of the buffer layer is greater than 0.15 micrometers, and the doping concentration is less than 3 × 10⁻⁶. 17 / cm 3 And higher than 1×10 14 / cm 3 .

[0021] The charge-coupled device provided in this application has at least the following advantages:

[0022] In the charge-coupled device (CCD) embodiments of this application, an anti-corona structure is provided between the two columns of memory cells in each memory cell group. The anti-corona structure includes an N-type doped region and a first doped layer. The first doped layer connects the N-type doped region and the N-type buried layer of the memory cell. The conductivity type of the first doped layer is N-type, and the doping concentration of the first doped layer is lower than that of the N-type buried layer and lower than that of the N-type doped region. The first doped layer can act as an electron potential barrier from the corresponding N-type buried layer to the N-type doped region, allowing the potential well of the N-type buried layer to store electrons. At the same time, it serves as an overflow channel for electrons when the number of electrons in the potential well of the N-type buried layer exceeds the full-well capacity, allowing excess electrons to overflow to the N-type doped region through the first doped layer, thus preventing excess electrons from overflowing into adjacent potential wells. This avoids bright spots / halos in the charge-coupled device, achieving a better anti-corona effect. In addition, the first doped layer has an N-type conductivity. On the one hand, electrons have a higher mobility in the N-type first doped layer, which allows electrons to overflow into the N-type doped region more quickly, resulting in higher electron overflow efficiency. On the other hand, the first doped layer and the N-type buried layer have the same conductivity, so the first doped layer will not reduce the doping concentration of the N-type buried layer, thus ensuring the performance of the memory cell.

[0023] Secondly, embodiments of this application also provide an image sensor, which includes the charge-coupled device as described above, and thus has at least the advantage of better anti-halo effect, as described above, and will not be repeated here.

[0024] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the charge-coupled device and image sensor provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a cross-sectional view of a charge-coupled device in related technologies;

[0027] Figure 2 This is a top view of a charge-coupled device in related technologies;

[0028] Figure 3 This is a cross-sectional view of the charge-coupled device in an embodiment of this application;

[0029] Figure 4 This is a top view of the charge-coupled device in the embodiments of this application.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10 - Substrate; 20 - Memory cell group;

[0032] 21-N-type buried layer; 22-Second dielectric layer;

[0033] 23 - Control gate; 30 - Isolation region;

[0034] 41 - N-type doped region; 42 - First doped layer;

[0035] 43 - Second doped layer; 44 - Isolation layer;

[0036] 45 - Buffer layer; 46 - First dielectric layer;

[0037] 47-Anti-corona gate; 50-P-well. Detailed Implementation

[0038] The related technologies have the problem of poor anti-nausea effect. The inventor's research revealed the following: (See below) Figure 1 and Figure 2 To facilitate the display of the relative position of the N-type buried layer 21,Figure 2 The second dielectric layer is not shown. The anti-corona structure is a corona-resistant transistor, typically an NMOS transistor. The anti-corona transistor is located between two columns of memory cells, and the current direction of the anti-corona transistor is parallel to the charge transfer direction in each column of memory cells.

[0039] The anti-corona transistor has a P-well 50. The N-type buried layer 21 in the memory cell on one side of the P-well 50 serves as the source of the anti-corona transistor, and the N-type doped region 41 on the other side of the P-well 50 serves as the drain. When the gate voltage of the anti-corona transistor rises to the operating voltage, the electron barrier at or near the surface of the P-well 50 decreases, and electrons overflow from the N-type buried layer 21 of the memory cell to the drain of the anti-corona transistor. However, because the anti-corona transistor uses a P-well 50, the electron mobility in the inversion layer is relatively low.

[0040] Furthermore, when using a P-well 50, if the doping concentration of the P-well 50 is low, there will be a significant short-channel effect. The height of the electron barrier on or near the surface of the P-well 50 varies considerably with process fluctuations, leading to full-well losses. If the doping concentration of the P-well 50 is high, the diffusion of the P-well 50 will reduce the doping concentration of the N-type buried layer 21 in the memory cell, resulting in full-well losses and edge effects. If the doping concentration of the P-well 50 is high in the region adjacent to the source and low in the region adjacent to the drain, the above problems can be avoided. However, an electron barrier may form below the anti-corona gate 47 of the anti-corona transistor, reducing the rate of electron overflow.

[0041] This application provides a charge-coupled device (CCD) including an anti-corona structure. A first doped layer is connected between the source (N-type buried layer of the memory cell) and the drain (N-type doped region) of the anti-corona structure. The first doped layer has an N-type conductivity and its doping concentration is lower than that of the N-type buried layer and the N-type doped region. The first doped layer acts as an electron barrier between the N-type buried layer and the N-type doped region, allowing the potential well in the N-type buried layer to store electrons. Simultaneously, it serves as an overflow channel for electrons when the number of electrons in the potential well of the N-type buried layer exceeds the full-well capacity, allowing excess electrons to overflow into the N-type doped region via the first doped layer. This prevents excess electrons from overflowing into adjacent potential wells, thereby avoiding bright spots / halos in the CCCD and achieving a better anti-corona effect.

[0042] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] See Figure 3 and Figure 4 In particular, for ease of displaying the N-type buried layer 21, Figure 4 The second dielectric layer is not shown. For example... Figure 3 and Figure 4 As shown, this application provides a charge-coupled device (CCD) comprising a substrate 10, a plurality of memory cell groups 20, and an anti-corona structure. The substrate 10 can be a semiconductor substrate; exemplaryly, the substrate 10 can be a silicon substrate, germanium substrate, silicon carbide substrate, silicon germanide substrate, germanium-on-insulator (GOI) substrate, or silicon-on-insulator (SOI) substrate, etc. The substrate 10 can be an undoped substrate or a doped substrate; for example, the substrate 10 can be a P-type substrate.

[0044] Multiple storage cell groups 20 are arranged at intervals along a first direction, which can be a horizontal direction, such as... Figure 4 The X direction is shown. Each memory cell group 20 includes two columns of memory cells, which are spaced apart along the first direction. Charge in each column of memory cells is transferred along a second direction, meaning the charge transfer process in each column is relatively independent. The second direction intersects the first direction, for example, perpendicular to it; the second direction can be vertical, such as... Figure 4 Y direction shown.

[0045] Each column of memory cells includes an N-type buried layer 21 disposed within a substrate 10, extending along a second direction. The conductivity type of the N-type buried layer 21 differs from that of the substrate 10, which is P-type, so that a potential well is formed in a portion of the N-type buried layer 21 near the substrate 10 to collect charge. This arrangement allows charge to leave the surface of the substrate 10, preventing charge trapping and reducing dark current.

[0046] Each column of memory cells also includes a second dielectric layer 22 disposed on the substrate 10, and a control gate 23 disposed on the second dielectric layer 22. The second dielectric layer 22 is opposite to the N-type buried layer 21, and its material can be silicon oxide. In some examples, the second dielectric layer 22 is a strip structure extending along a second direction to facilitate the fabrication of the second dielectric layer 22.

[0047] Multiple control gates 23 are arranged at intervals along a second direction on the second dielectric layer 22. Each control gate 23 corresponds to one memory cell. That is, each column of memory cells has multiple memory cells arranged at intervals along the second direction, and each memory cell includes a control gate 23, as well as the second dielectric layer 22 and the N-type buried layer 21 covered by the control gate 23. The multiple memory cells are arranged at intervals along a first direction and at intervals along the second direction to form a memory cell array.

[0048] An isolation region 30 is provided between two adjacent groups of memory cells 20 along the first direction to prevent the diffusion of charge (e.g., electrons) between adjacent groups of memory cells 20. Specifically, an isolation layer 44 is provided between the 2nth column of memory cells and the 2n+1th column of memory cells, where n is a positive integer greater than or equal to 1. That is, an isolation layer 44 is provided between the second column of memory cells and the third column of memory cells, an isolation layer 44 is provided between the fourth column of memory cells and the fifth column of memory cells, and so on.

[0049] The conductivity type of the isolation region 30 is opposite to that of the N-type buried layer 21, and the depth of the isolation region 30 is greater than that of the N-type buried layer 21. The N-type buried layer 21 has an N-type conductivity, while the isolation region 30 has a P-type conductivity. The P-type isolation region 30 provides an electronic barrier between the two adjacent N-type buried layers 21 to prevent electrons in the memory cell group 20 from diffusing into the adjacent memory cell group 20.

[0050] In this design, isolation region 30 is connected to zero potential. Even after collecting electrons, isolation region 30 remains at a high potential, making it difficult for electrons to cross the high-potential isolation layer 44, thus achieving isolation between the two rows of memory cells adjacent to isolation region 30. The conductivity type of isolation region 30 can be the same as that of substrate 10, and the doping concentration of isolation region 30 is higher than that of substrate 10.

[0051] Continue reading Figure 3 and Figure 4 The anti-corona structure is disposed between two columns of memory cells in each memory cell group 20 to prevent charge diffusion between the two columns of memory cells in the same group. It is understood that an anti-corona structure or isolation region 30 is disposed between any two adjacent columns of memory cells, and the anti-corona structure and isolation region 30 are disposed alternately along the first direction.

[0052] The anti-corona structure includes an N-type doped region 41, a first doped layer 42, a first dielectric layer 46, and an anti-corona gate 47. The N-type doped region 41 is disposed within the substrate 10 and located between adjacent N-type buried layers 21. The N-type doped region 41 is a heavily doped region and can be formed by ion implantation. The N-type doped region 41 has an N-type conductivity and acts as the drain of the anti-corona structure, collecting electrons overflowing from the adjacent N-type buried layers 21.

[0053] The first doped layer 42 is connected between the N-type buried layer 21 and the N-type doped region 41. The conductivity type of the first doped layer 42 is N-type. The doping concentration of the first doped layer 42 is lower than that of the N-type buried layer 21 and lower than that of the N-type doped region 41. That is, the conductivity type of the first doped layer 42, the N-type doped region 41, and the N-type buried layer 21 are all N-type, and the doping concentration of the first doped layer 42 is the lowest among the three.

[0054] With this configuration, when the gate voltage of the anti-corona gate 47 of the anti-corona structure reaches the operating voltage, the first doped layer 42 acts as a potential barrier for electrons between the corresponding (i.e., adjacent) N-type buried layer 21 and N-type doped region 41, allowing the potential well of the N-type buried layer 21 to store electrons. At the same time, it acts as an overflow channel for electrons in the potential well of the N-type buried layer 21 when the number of electrons exceeds the full well capacity, allowing the excess electrons to overflow into the N-type doped region 41 through the first doped layer 42, preventing the excess electrons from overflowing into the adjacent potential well, thereby avoiding bright spots-halos in the charge-coupled device and achieving a better anti-corona effect.

[0055] Furthermore, the first doped layer 42 has an N-type conductivity. On the one hand, electrons have a higher mobility in the N-type first doped layer 42 compared to the inversion layer, which allows electrons to overflow into the N-type doped region 41 more quickly, resulting in higher electron overflow efficiency. On the other hand, the first doped layer 42 and the N-type buried layer 21 have the same conductivity, so the first doped layer 42 will not reduce the doping concentration of the N-type buried layer 21, thus ensuring the performance of the memory cell.

[0056] In some examples, the first doped layer 42 can be made of monocrystalline silicon, which has a low dark current, and the doping concentration of the first doped layer 42 is less than 2 × 10⁻⁶. 16 / cm 3 And higher than 1×10 14 / cm 3 Along the first direction, the length of the first doped layer 42 is greater than 0.5 micrometers to reduce or avoid short-channel effects, and the depth of the first doped layer 42 is less than 0.5 micrometers to facilitate the formation of the first doped layer 42 by ion implantation.

[0057] Since the height of the barrier is relatively stable with respect to the process, by controlling the doping process conditions, the first doped layer 42 can form a process-stable barrier region at the end near the memory cell and a drift enhancement region at the end near the N-type doped region 41, thereby separating the barrier region and the drift enhancement region to improve the performance of the first doped layer 42.

[0058] Continue reading Figure 3 and Figure 4 A first dielectric layer 46 is disposed on the substrate 10 and adjacent to a first doped layer 42. The first dielectric layer 46 may be made of silicon oxide. Along the second direction, the two ends of the first dielectric layer 46 may be flush with the two ends of the first doped layer 42. The first dielectric layer 46 may be formed simultaneously with the second dielectric layer 22, for example, through a thermal oxidation process. The thickness of the first dielectric layer 46 is less than the thickness of the second dielectric layer 22, so that the second dielectric layer 22 can withstand higher voltages.

[0059] An anti-corona gate 47 is disposed on the first dielectric layer 46, and a gate voltage is applied thereon. The anti-corona gate 47 can be made of polysilicon, and can be formed by photolithography simultaneously with other polysilicon gates. Along the first direction, the distance between the anti-corona gate 47 and the control gate 23 is greater than 0.1 micrometers and less than 0.4 micrometers.

[0060] The first doped layer 42, the N-type buried layer 21 and N-type doped region 41 on both sides, the first dielectric layer 46 on top, and the anti-corona gate 47 constitute an anti-corona transistor, which is an NMOS (N-Metal Oxide Semiconductor) transistor. The N-type doped region 41 is the drain region of the anti-corona transistor, and the N-type buried layer 21 is the source region. That is, the anti-corona transistor and the memory cell share the N-type buried layer 21 to improve the space utilization of the charge-coupled device. The control gate 23 of each anti-corona transistor is electrically independent, so that each anti-corona transistor can be controlled individually, thereby ensuring the anti-corona effect of each memory cell.

[0061] Because an N-type doped region 41 is provided between the two N-type buried layers 21, and a first doped layer 42 is provided between the N-type doped region 41 and each N-type buried layer 21, the two ends of the first doped layer 42 along the first direction are respectively connected to the N-type buried layer 21 and the N-type doped region 41, that is, the two sides of each N-type doped region 41 ( Figure 3 The left and right sides (shown) are respectively connected to the first doped layer 42. The anti-corona structure located between the two columns of memory cells includes two anti-corona transistors, and these two anti-corona transistors share an N-type doped region 41. That is, the anti-corona transistors corresponding to the two opposite memory cells perpendicular to the charge transfer direction share a drain region.

[0062] In some examples, the anti-corona structure further includes a second doped layer 43 disposed below the first doped layer 42. The second doped layer 43 has the opposite conductivity type to the first doped layer 42, and the doping concentration of the second doped layer 43 is greater than that of the first doped layer 42. The first doped layer 42 has an N-type conductivity, and the second doped layer 43 has a P-type conductivity. The doping concentration of the second doped layer 43 is greater than 5 × 10⁻⁶. 16 / cm 3 .

[0063] A second doped layer 43 is provided, and the doping concentration of the second doped layer 43 is relatively higher than that of the first doped layer 42, so that the first doped layer 42 can be regarded as a thin layer electrically. The potential of the first doped layer 42 is controlled by the gate voltage of the anti-corona gate 47 and the second doped layer 43. The short-channel performance of the first doped layer 42 is relatively good, and the height of the electron barrier under the anti-corona gate 47 is not easily affected by process fluctuations and is relatively stable.

[0064] Understandably, the highest potential in the first doped layer 42 is slightly lower than the full-well potential of the N-type buried layer 21 when the gate voltage of the corresponding anti-corona gate 47 rises to the operating voltage. The highest potential in the first doped layer 42 is affected by the gate voltage of the anti-corona gate 47, the depth and doping concentration of the first doped layer 42, and the doping concentration of the second doped layer 43.

[0065] The fabrication of the first doped layer 42 and the second doped layer 43 is relatively flexible. In some examples, the first doped layer 42 and the second doped layer 43 can be formed before the well annealing in the CMOS standard process, that is, before the first dielectric layer 46 and the second dielectric layer 22. For example, boron (5 × 10⁻⁶) is implanted into the substrate 10 using a separate mask. 12 / cm 2 Up to 1×10 14 / cm 2 A second doped layer 43 is formed, and then phosphorus or arsenic (5 × 10⁻⁶) is implanted. 11 / cm 2 Up to 2×10 12 / cm 2 The first doped layer 42 is formed.

[0066] In other examples, the first doped layer 42 can be formed simultaneously with the N-type buried layer 21, and then a second doped layer 43 can be implanted below the first doped layer 42 using a separate mask. The second doped layer 43 and the first doped layer 42 partially overlap. Since the conductivity type of the second doped layer 43 is different from that of the first doped layer, the formation of the second doped layer 43 will compensate for some of the donor impurities in the first doped layer 42, thereby making the number of donor impurities per unit area in the first doped layer 42 lower than that in the N-type buried layer 21, and the doping concentration of the first doped layer 42 lower than that of the N-type buried layer 21. This configuration ensures the relationship between the doping concentrations of the first doped layer 42 and the N-type buried layer 21 while forming the second doped layer 43, simplifying the fabrication steps of the charge-coupled device.

[0067] In the example where each column of storage cells includes multiple storage cells arranged along the second direction, in order to ensure the anti-corona effect, there are multiple anti-corona structures between two columns of storage cells in the same storage cell group 20. The multiple anti-corona structures are arranged at intervals along the second direction, and an isolation layer 44 is provided between two adjacent anti-corona structures along the second direction.

[0068] An isolation layer 44 is disposed within the substrate 10 and located between the N-type doped regions 41 of two adjacent anti-corona structures, and between the first doped layers 42 of two adjacent anti-corona structures. The isolation layer 44 has a P-type conductivity and the lowest potential. Specifically, the lowest potential of the isolation layer 44 means that when the lowest potential is zero, the isolation layer 44 is connected to zero; and when the lowest potential is negative, the isolation layer 44 is connected to the maximum negative voltage.

[0069] By setting up an isolation layer 44 and connecting it to the lowest potential, multiple anti-corona structures in the same column are separated. This prevents the anti-corona gate 47 of the anti-corona structure in the same column of memory cells from being continuous along the second direction. It also prevents the doped layer of the anti-corona structure in the same column of memory cells from being continuous along the second direction. This prevents excess electrons in one of the memory cells in a column from overflowing into the N-type doped region 41 of the anti-corona structure and then diffusing along the second direction in the N-type doped region 41. Furthermore, it prevents electrons from drifting into the memory cell when there are no stored electrons in the same column of memory cells and the control gate 23 is under high voltage.

[0070] It is understandable that when the anti-corona structure is a single unit, excess electrons after the memory cell is full will overflow into the N-type doped region 41 of the anti-corona structure. These electrons, especially those in the barrier flat region, will diffuse within the N-type doped region 41 and then into the N-type doped region 41 of a nearby memory cell that is in a collecting state and has very few stored electrons. They will then drift into that memory cell, causing electron overflow between memory cells. By providing an isolation layer 44 connected to the lowest potential, the isolation layer 44 is positioned at the highest electron barrier, thus suppressing the above process, i.e., preventing excess electrons from diffusing into the N-type doped region 41 and drifting to nearby memory cells in a collecting state.

[0071] Specifically, the isolation layer 44 is located between the N-type doped regions 41 of two adjacent anti-corona structures along the second direction, and between the first doped layer 42, to provide isolation between the anti-corona structures in the same column perpendicular to the charge transfer direction. The isolation layer 44 is made of monocrystalline silicon. Along the second direction, the width of the isolation layer 44 is greater than 0.3 micrometers to ensure isolation effectiveness. The depth of the isolation layer 44 is greater than 0.6 micrometers, so that the depth of the isolation layer 44 is greater than the depth of the first doped layer 42. The doping concentration of the isolation layer 44 is greater than 5 × 10⁻⁶. 16 / cm 3 Furthermore, the doping concentration on the top surface of the isolation layer 44 is greater than 1×10⁻⁶. 18 / cm 3 The isolation layer 44 can be formed by boron implantation after the sidewalls are formed in a standard CMOS process and before the source / drain regions are implanted.

[0072] In an example where each column of memory cells includes multiple control gates 23, the N-type buried layer 21 between two adjacent control gates 23 along the second direction is opposite and adjacent to the isolation layer 44. For example, the isolation layer 44 is center-aligned with the gap between the corresponding control gate 23, and along the second direction, the width of the isolation layer 44 is greater than the gap between the corresponding control gates 23. With this configuration, each memory cell has an independent and electrically isolated electron overflow channel, thereby enabling each memory cell to correspond to an anti-corona structure and improving the anti-corona effect.

[0073] By adjusting the barrier height, each anti-corona gate 47 and the corresponding control gate 23 of the memory cell can use the same timing. When the memory cell is in the off state, the control gate 23 is negatively biased, and the interface state of the second dielectric layer 22 is filled with holes. At this time, the corresponding anti-corona gate 47 is also negatively biased, and the interface state of the first dielectric layer 46 below the anti-corona gate 47 is also filled with holes, so as to reduce the dark current of the anti-corona structure.

[0074] In some examples, along the second direction, both ends of the anti-corona gate 47 may protrude from the corresponding first doped layer 42. For example, along the second direction, the distance between two adjacent anti-corona gates 47 is greater than 0.2 micrometers. The second doped layer 43 of the plurality of anti-corona structures arranged along the second direction is an integral structure to facilitate the formation of the second doped layer 43. That is, the second doped layer 43 in the same column of anti-corona structures is an integral part extending along the second direction, and the second doped layer 43 has a plurality of first doped layers 42 arranged at intervals along the second direction.

[0075] To prevent tunneling between the N-type doped region 41 of the anti-corona structure and the surface of the isolation layer 44, a buffer layer 45 is provided at least between the N-type doped region 41 and the isolation layer 44. The buffer layer 45 is disposed within the substrate 10 and covers both ends of the N-type doped region 41 along the first direction and the bottom end of the N-type doped region 41. The buffer layer 45 has an N-type conductivity and a lower doping concentration than the N-type doped region 41. The buffer layer 45 is made of monocrystalline silicon, and along the second direction, its width is greater than 0.15 micrometers, and its doping concentration is less than 3 × 10⁻⁶ micrometers. 17 / cm 3 And higher than 1×10 14 / cm 3 The buffer layer 45 can be formed by phosphorus implantation after the sidewalls are formed in a standard CMOS process and before the source / drain regions are implanted.

[0076] In some possible implementations, the fabrication of charge-coupled devices can be embedded in CMOS processes to improve fabrication versatility. Specifically, this can include the following processes: well implantation in standard CMOS processes, implantation of the N-type buried layer 21 of the memory cell, implantation of the isolation region 30 of the memory cell, well implantation of the peripheral transistor of the memory cell, implantation of the second doped layer 43, implantation of the first doped layer 42, well annealing, formation of the gate (including the control gate 23 and the anti-corona gate 47) in standard CMOS processes, formation of the sidewall in standard CMOS processes, implantation of the isolation layer 44, implantation of the buffer layer 45, implantation and annealing of the source and drain regions in standard CMOS processes, and metallization in standard CMOS processes.

[0077] In summary, in the charge-coupled device of this application embodiment, an anti-corona structure is provided between the two columns of memory cells in each memory cell group 20. The anti-corona structure includes an N-type doped region 41 and a first doped layer 42. The first doped layer 42 connects the N-type doped region 41 and the N-type buried layer 21 of the memory cell. The conductivity type of the first doped layer 42 is N-type, and the doping concentration of the first doped layer 42 is lower than that of the N-type buried layer 21 and lower than that of the N-type doped region 41. The first doped layer 42 can act as a potential barrier for electrons from the corresponding N-type buried layer 21 to the N-type doped region 41, allowing electrons to be stored in the potential well of the N-type buried layer 21. At the same time, it serves as an overflow channel for electrons when the number of electrons in the potential well of the N-type buried layer 21 exceeds the full capacity, allowing excess electrons to overflow to the N-type doped region 41 through the first doped layer 42, preventing excess electrons from overflowing into the adjacent potential well, thereby avoiding bright spots-halos in the charge-coupled device and exhibiting a good anti-corona effect. Furthermore, the first doped layer 42 has an N-type conductivity. On the one hand, the electron mobility in the first doped layer 42 is higher than that in the inversion layer, which allows electrons to overflow into the N-type doped region 41 more quickly, resulting in higher electron overflow efficiency. On the other hand, the first doped layer 42 and the N-type buried layer 21 have the same conductivity, so the first doped layer 42 will not reduce the doping concentration of the N-type buried layer 21, thus ensuring the performance of the memory cell.

[0078] This application also provides an image sensor, such as a time-delay integral image sensor. The image sensor includes the charge-coupled device described in the above embodiments, and therefore has at least the advantage of better anti-halo performance, as detailed above, and will not be repeated here.

[0079] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0080] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A charge-coupled device, characterized in that, The device includes a substrate, a plurality of memory cell groups arranged at intervals along a first direction, and an anti-corona structure. Each memory cell group includes two columns of memory cells arranged at intervals along the first direction, and the anti-corona structure is disposed between the two columns of memory cells. Each column of the memory cells includes an N-type buried layer disposed in the substrate and extending along a second direction, the second direction intersecting the first direction. The anti-corona structure includes an N-type doped region disposed in the substrate and located between adjacent N-type buried layers, a first doped layer connecting the N-type buried layer and the N-type doped region, a first dielectric layer disposed on the substrate and opposite to the first doped layer, and an anti-corona gate disposed on the first dielectric layer. The first doped layer has an N-type conductivity, and the doping concentration of the first doped layer is lower than the doping concentration of the N-type buried layer and lower than the doping concentration of the N-type doped region.

2. The charge-coupled device according to claim 1, characterized in that, Each group of storage cells has multiple anti-corona structures between two columns of storage cells, and the multiple anti-corona structures are arranged at intervals along the second direction. The charge-coupled device further includes an isolation layer disposed within the substrate. The isolation layer is located between the N-type doped regions of two adjacent anti-corona structures and between the first doped layers of two adjacent anti-corona structures. The isolation layer is of P-type conductivity and has the lowest potential.

3. The charge-coupled device according to claim 2, characterized in that, Each column of the memory cells further includes a second dielectric layer disposed on the substrate and opposite to the N-type buried layer, and a plurality of control gates disposed on the second dielectric layer and spaced apart along the second direction; The N-type buried layer between two adjacent control gates along the second direction is opposite to and adjacent to the isolation layer.

4. The charge-coupled device according to claim 3, characterized in that, The first doped layer is made of monocrystalline silicon. Along the first direction, the length of the first doped layer is greater than 0.5 micrometers, the depth is less than 0.5 micrometers, and the doping concentration is less than 2 × 10⁻⁶. 16 / cm 3 And higher than 1×10 14 / cm 3 ; And / or, along the second direction, the distance between two adjacent anti-corona gates is greater than 0.2 micrometers; And / or, along the first direction, the distance between the control gate and the anti-corona gate is greater than 0.1 micrometers and less than 0.4 micrometers.

5. The charge-coupled device according to claim 2, characterized in that, The isolation layer is made of monocrystalline silicon, and along the second direction, the width of the isolation layer is greater than 0.3 micrometers, the depth is greater than 0.6 micrometers, and the doping concentration is greater than 5 × 10⁻⁶. 16 / cm 3 Furthermore, the doping concentration on the top surface of the isolation layer is greater than 1×10⁻⁶. 18 / cm 3 .

6. The charge-coupled device according to any one of claims 2-5, characterized in that, The anti-corona structure further includes a second doped layer disposed below the first doped layer. The second doped layer has the opposite conductivity type to the first doped layer, and the doping concentration of the second doped layer is greater than that of the first doped layer.

7. The charge-coupled device according to claim 6, characterized in that, The second doped layer of the plurality of anti-corona structures arranged along the second direction is an integral structure.

8. The charge-coupled device according to any one of claims 1-5, characterized in that, The charge-coupled device further includes a buffer layer disposed in the substrate, the buffer layer covering both ends of the N-type doped region along the first direction and the bottom end of the N-type doped region; The buffer layer has an N-type conductivity, and the doping concentration of the buffer layer is less than the doping concentration of the N-type doped region.

9. The charge-coupled device according to claim 8, characterized in that, The buffer layer is made of monocrystalline silicon, and along the second direction, the width of the buffer layer is greater than 0.15 micrometers, and the doping concentration is less than 3 × 10⁻⁶. 17 / cm 3 And higher than 1×10 14 / cm 3 .

10. An image sensor, characterized in that, Includes the charge-coupled device according to any one of claims 1-9.

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