An impact-resistant super-junction device and a method of fabricating the same

Abstract

The application discloses an anti-impact super junction device and a preparation method thereof, relates to the field of super junction device anti-impact ability layout technology, and comprises a substrate, a first epitaxial layer, a second epitaxial layer, a voltage resistance layer, a gate oxide layer, a gate, an interlayer dielectric, a metal via, a circuit linking layer and a passivation layer. At least one voltage resistance layer comprises a second polarity columnar region and a first polarity columnar region. The second polarity columnar region comprises a plurality of second polarity columns, the first polarity columnar region comprises a plurality of first polarity columns, and the second polarity columns perpendicular to each other are alternately arranged. The preparation method comprises the following steps: A, preparation of the epitaxial layer; B, preparation of the voltage resistance layer; C, preparation of a front VDMOS structure; and D, preparation of the circuit linking layer and the passivation layer. The voltage resistance layer can be repeatedly prepared according to patterns on a mask, and finally, the super junction device with very good anti-impact ability is obtained.

Description

Technical Field

[0001] This invention relates to the field of layout technology for improving the shock resistance of superjunction devices, and particularly to an shock-resistant superjunction device and its preparation method. Background Technology

[0002] Superjunction devices are semiconductor devices that utilize a repeating structure of vertical P-type and N-type pillars to achieve a transverse electric field component, thereby improving the longitudinal withstand voltage. Compared with traditional VDMOS devices, they can use higher concentrations of N-type and P-type doping, which can greatly reduce the voltage on the conductive channel. Therefore, they have advantages such as strong overcurrent capability, high power density, fast switching speed, and low output loss.

[0003] However, superjunction devices on the market currently require high-depth P-type and N-type pillars to achieve withstand voltage. In actual production processes, a certain degree of process tolerance is usually required. Therefore, some design methods are needed to ensure that superjunction devices have good impact resistance within the parameter calibration range. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the first objective of this invention is to provide an impact-resistant superjunction device. This objective is achieved through the following technical solution: an impact-resistant superjunction device comprising, from bottom to top, a substrate, a first epitaxial layer, a second epitaxial layer, at least one withstand voltage layer, a gate oxide layer, a gate, an interlayer dielectric, a metal via, a circuit connection layer, and a passivation layer;

[0005] The withstand voltage layer includes a second polar columnar region and a first polar columnar region; a plurality of body regions and source electrodes are disposed between the withstand voltage layer and the gate oxide layer; the metal vias are uniformly distributed in the interlayer dielectric, and the lower end of the metal vias is connected to the body regions and source electrodes, and the upper end is connected to the circuit connection layer.

[0006] Furthermore, the number of layers in the pressure-resistant layer is greater than one. The resistivity of the second epitaxial layer is less than the resistivity of the first epitaxial layer with the second polarity.

[0007] Furthermore, the second polar columnar region includes a plurality of second polar columns, and the first polar columnar region includes a plurality of first polar columns; the mutually perpendicular second polar columns are arranged alternately.

[0008] With the upper right corner as the origin, the vertical direction is x, and the horizontal direction is y; several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction, and several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction.

[0009] The interval between several second polarity columns extending along the y direction and arranged along the x direction is the second polarity first type interval; the interval between several second polarity columns extending along the x direction and arranged along the y direction is the second polarity second type interval; the second polarity first type interval includes dx(n+i); the second polarity second type interval includes dy(n+i);

[0010] The interval between a second polar column extending in the x direction and its adjacent second polar column extending in the y direction, and the interval between a second polar column extending in the x direction and its adjacent second polar column extending in the x direction, are the second polar third type intervals; the second polar third type intervals include x(n+i)a and x(n+i)b.

[0011] The interval between a second polar column extending in the y direction and its adjacent second polar column extending in the x direction, and the interval between a second polar column extending in the y direction and its adjacent second polar column extending in the y direction, are the second polarity fourth type intervals; the second polarity fourth type intervals include y(n+i)a and y(n+i)b.

[0012] When the first type of second polarity spacing is equal to the second type of second polarity spacing, and the third type of second polarity spacing is equal to the fourth type of second polarity spacing, the superjunction device is in a two-dimensional charge balance state. When the first type of second polarity spacing is not equal to the second type of second polarity spacing, and the third type of second polarity spacing is not equal to the fourth type of second polarity spacing, the superjunction device may be in a state of excess first polarity charge or excess second polarity charge. n and i are non-negative integers.

[0013] The second objective of this invention is to provide a method for fabricating an impact-resistant superjunction device. This objective is achieved through the following technical solution: a method for fabricating an impact-resistant superjunction device, comprising the following steps:

[0014] A. Preparation of the epitaxial layer;

[0015] B. Preparation of the pressure-resistant layer;

[0016] C. Fabrication of the front-side VDMOS structure;

[0017] D. Fabrication of circuit link layer and passivation layer.

[0018] Furthermore, the pressure-resistant layer includes a second polar columnar region and a first polar columnar region; the second polar columnar region includes a plurality of second polar columns, and the first polar columnar region includes a plurality of first polar columns;

[0019] With the upper right corner as the origin, the vertical direction is x, and the horizontal direction is y; several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction, and several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction.

[0020] Furthermore, step A specifically includes the following steps:

[0021] S1. A first epitaxial layer is grown on a silicon substrate by chemical vapor deposition as a buffer layer for the shock-resistant superjunction device.

[0022] S2. A high-concentration second epitaxial layer is obtained by performing a high-concentration second epitaxial growth on the first epitaxial layer or by using ion implantation.

[0023] Furthermore, when the pressure-resistant layer is a single layer, step B specifically includes the following steps:

[0024] S3. Continue to grow the epitaxial layer using chemical vapor deposition;

[0025] S4. After growing the hard film, spin-coating of photoresist is performed. The pattern on the photomask is defined on the photoresist by exposure through a photolithography machine. After etching, the pattern on the photoresist is defined on the hard film.

[0026] S5. Perform deep trench etching, and then remove the hard film;

[0027] S6. A reverse conductive layer is grown by chemical vapor deposition to fill the deep trench, thereby obtaining the withstand voltage layer of the device described in this invention. High-temperature thermal annealing is then performed to repair lattice damage and activate the injected impurities.

[0028] Furthermore, when the pressure-resistant layer is greater than one layer, step B specifically includes the following steps:

[0029] S7. Continue to grow the epitaxial layer by chemical vapor deposition, perform ion implantation, and spin-coate photoresist. Expose the photomask by a photolithography machine to define the pattern on the photoresist. After ion implantation, the reverse doped region is obtained.

[0030] S8. Repeat step S7 to obtain the voltage-resistant layer of the impact-resistant superjunction device;

[0031] S9. Perform high-temperature thermal annealing to repair lattice damage and activate injected impurities.

[0032] Furthermore, step C specifically includes the following steps:

[0033] S10, gate oxide layer growth, polysilicon growth and etching;

[0034] S11, body region injection, and source injection;

[0035] S12, Ohmic contact area injection.

[0036] Furthermore, step D specifically includes the following steps:

[0037] S13, Interlayer dielectric layer deposition;

[0038] S14. Define the area of ​​the metal via by etching after exposure, and deposit the metal via by sputtering.

[0039] A metal layer is obtained by deposition, followed by spin coating with photoresist, exposure, and then etching using a dry or wet / dry method to obtain a circuit connection layer.

[0040] S15. Deposit a passivation layer and open the pad area using photolithography and etching processes.

[0041] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0042] (1) The present invention has local electric field extrema between the P-type pillar and the N-type epitaxial layer, which reduces the current value of the epitaxial layer participating in voltage division after the device experiences local avalanche, thereby changing the avalanche point of the device and improving the avalanche current withstand capability of the device.

[0043] (2) The present invention has a high concentration of N-type carriers below the P-type pillar, which reduces the injection efficiency of P-type carriers, thereby reducing the reverse overshoot current and reverse recovery time of the superjunction device operating in reverse recovery mode.

[0044] (3) The superjunction device achieves overall voltage withstand capability through repeating periodic units within the cell and a ring of terminal structures on the outer side. Since the repeating periodic units of the superjunction device are located within the silicon, the potential difference and the extreme values ​​of the electric field generated by this potential difference are also within the silicon. Therefore, the shock resistance of the cell structure is only affected by the shape and concentration distribution of the P-type and N-type pillars. The potential difference borne by the outer terminal structure of the superjunction device exists not only within the silicon but also on the chip surface. Therefore, its shock resistance is not only related to the P-type and N-type pillars but also to the potential difference and electric field distribution on the terminal surface. This invention, through flexible adjustment of the layout, adjusts the peak electric field to improve the avalanche current withstand capability and provides a discharge channel for the superjunction device to withstand avalanche at different locations, thus significantly enhancing the shock resistance of the superjunction device. Attached Figure Description

[0045] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0046] Figure 1 This is a schematic diagram of steps S1 and S2 of the preparation method of the impact-resistant superjunction device as described in Examples 1-5 in Example 6 or the preparation method of the impact-resistant superjunction device as described in Example 7 in Example 8.

[0047] Figure 2 This is a schematic diagram of step S3 of the preparation method of the impact-resistant superjunction device as described in Examples 1-5 in Example 6 or the preparation method of the impact-resistant superjunction device as described in Example 7 in Example 8.

[0048] Figure 3 This is a schematic diagram of the voltage withstand layer layout for the superjunction device in Example 1 or Example 7;

[0049] Figure 4 This is a schematic diagram of the voltage-resistant layer layout of the superjunction device in Example 2 or Example 7;

[0050] Figure 5 This is a schematic diagram of the voltage-resistant layer layout of the superjunction device in Example 3 or Example 7;

[0051] Figure 6 This is a schematic diagram of the voltage withstand layer layout of the superjunction device in Example 4 or Example 7;

[0052] Figure 7 This is a schematic diagram of the voltage-resistant layer layout of the superjunction device in Example 5 or Example 7;

[0053] Figure 8 This is a schematic diagram of step S5 in the fabrication method of the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0054] Figure 9 This is a schematic diagram of step S6 in the fabrication method of the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0055] Figure 10 This is a schematic diagram of step S10 in the fabrication method of the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0056] Figure 11 This is a schematic diagram of step S11 of the fabrication method for the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0057] Figure 12 This is a schematic diagram of step S13 of the fabrication method for the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0058] Figure 13 This is a schematic diagram of step S14 of the fabrication method for the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0059] Figure 14This is a schematic diagram of step S15 of the fabrication method for the impact-resistant superjunction device as described in Examples 1-5 in Example 6;

[0060] Figure 15 This is a schematic diagram of step S7 in the fabrication method of the impact-resistant superjunction device as described in Example 7 in Example 8;

[0061] Figure 16 This is a schematic diagram of step S8 in the fabrication method of the impact-resistant superjunction device as described in Example 7 in Example 8;

[0062] Figure 17 This is a schematic diagram of step S10 in the fabrication method of the impact-resistant superjunction device as described in Example 7 in Example 8;

[0063] Figure 18 This is a schematic diagram of step S11 in the fabrication method of the impact-resistant superjunction device as described in Example 7 in Example 8;

[0064] Figure 19 This is a schematic diagram of step S13 of the fabrication method for the impact-resistant superjunction device as described in Example 7 in Example 8;

[0065] Figure 20 This is a schematic diagram of step S14 of the fabrication method for the impact-resistant superjunction device as described in Example 7 in Example 8;

[0066] Figure 21 This is a schematic diagram of step S15 of the fabrication method for the impact-resistant superjunction device as described in Example 7 in Example 8;

[0067] Reference numerals: 1. Silicon substrate; 2. First epitaxial layer; 3. Second epitaxial layer; 4. First polar columnar region; 5. Second polar columnar region; 6. Gate oxide layer; 7. Gate; 8. Body region; 9. Source; 10. Interlayer dielectric; 11. Metal via; 12. Circuit connection layer; 13. Passivation layer. Detailed Implementation

[0068] The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any way. For those skilled in the art, several changes and modifications can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values; these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of various ranges, the endpoint values ​​of various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges. These numerical ranges should be considered as specifically disclosed herein. The present invention will be described in detail below with reference to specific embodiments:

[0069] Example 1

[0070] An impact-resistant superjunction device, such as Figure 14 As shown, the structure includes, from bottom to top, a substrate, a first epitaxial layer, a second epitaxial layer, a withstand voltage layer, a gate oxide layer, a gate, an interlayer dielectric, a metal via, a circuit connection layer, and a passivation layer; the withstand voltage layer includes a second polar columnar region and a first polar columnar region; several body regions and a source electrode are disposed between the withstand voltage layer and the gate oxide layer; the metal vias are uniformly distributed in the interlayer dielectric, and the lower end of the metal via is connected to the body region and the source electrode, and the upper end is connected to the circuit connection layer.

[0071] The resistivity of the second epitaxial layer is less than the resistivity of the first epitaxial layer of the second polarity. The second polar columnar region includes a plurality of second polar columns, and the first polar columnar region includes a plurality of first polar columns; with the upper right corner as the origin, the vertical direction as the x-direction, and the horizontal direction as the y-direction; in the y-direction, a plurality of second polar columns extending along the y-direction are alternately arranged with second polar columns extending along the x-direction, and in the x-direction, a plurality of second polar columns extending along the y-direction are alternately arranged with second polar columns extending along the x-direction.

[0072] The interval between several second polarity columns extending along the y direction and arranged along the x direction is the second polarity first type interval; the interval between several second polarity columns extending along the x direction and arranged along the y direction is the second polarity second type interval; the second polarity first type interval includes dx(n+i); the second polarity second type interval includes dy(n+i).

[0073] The interval between a second polar column extending in the x direction and its adjacent second polar column extending in the y direction, and the interval between a second polar column extending in the x direction and its adjacent second polar column extending in the x direction, are the second polar third type intervals; the second polar third type intervals include x(n+i)a and x(n+i)b.

[0074] The interval between a second polar column extending in the y direction and its adjacent second polar column extending in the x direction, and the interval between a second polar column extending in the y direction and its adjacent second polar column extending in the y direction, are the fourth type of second polarity intervals; the fourth type of second polarity intervals include y(n+i)a and y(n+i)b. n and i are non-negative integers.

[0075] Specifically, in this embodiment, such as Figure 3As shown, the first type of intervals of the second polarity specifically includes 1dx0, 1dx2, 1dx3…1dxn, 1dx(n+1), 1dx(n+2)…1dx(n+i). The second type of intervals of the second polarity specifically includes 1dy0, 1dy1, 1dy2, 1dy3…1dyn. The third type of intervals of the second polarity specifically includes 1x1a, 1x1b, 1x2a, 1x2b, 1x3a, 1x3b…1xna, 1xnb, 1x(n+1)a, 1x(n+1)b, ​​1x(n+2)a, 1x(n+2b)…1x(n+i)a, 1x(n+i)b. The second polarity fourth type of interval specifically includes 1y1a, 1y1b, 1y2a, 1y2b, 1y3a, 1y3b…1yna, 1ynb, 1y(n+1)a, 1y(n+1)b, ​​1y(n+2)a, 1y(n+2)b…1y(n+i)a, 1y(n+i)b, where n is greater than or equal to i and i is greater than or equal to 1.

[0076] When the first type of second polarity spacing is equal to the second type of second polarity spacing, and the third type of second polarity spacing is equal to the fourth type of second polarity spacing, the superjunction device is in a two-dimensional charge balance state. When the first type of second polarity spacing is not equal to the second type of second polarity spacing, and the third type of second polarity spacing is not equal to the fourth type of second polarity spacing, the superjunction device may be in a working state with excess first polarity charge or excess second polarity charge.

[0077] Example 2

[0078] An impact-resistant superjunction device, such as Figure 4 As shown, the difference from Example 1 is that the first type of interval of the second polarity specifically includes 2dx1, 2dx2, 2dx3…2dxn, 2dx(n+1), 2dx(n+2)…2dx(n+i). The second type of interval of the second polarity specifically includes 2dy0, 2dy1, 2dy2…2dy(n+i). The third type of interval of the second polarity specifically includes 2x1a, 2x1b, 2x2a, 2x2b, 2x3a, 2x3b…2xna, 2xnb…2x(n+i)a, 2x(n+i)b. The fourth type of interval of the second polarity specifically includes 2y1a, 2y1b, 2y2a, 2y2b…2yna, 2ynb, 2y(n+1)a, 2y(n+1)b…2y(n+i)a, 2y(n+i)b, where n is greater than or equal to i and i is greater than or equal to 1.

[0079] Example 3

[0080] An impact-resistant superjunction device, such as Figure 5As shown, the difference from Embodiment 1 is that the first type of interval of the second polarity specifically includes 3dx1, 3dx2, 3dx3…3dxn, 3dx(n+1), 3dx(n+2)…3dx(n+i). The second type of interval of the second polarity specifically includes 3dy1, 3dy2, 3dy3…3dy(n+1), 3dy(n+2)…3dy(n+i). The third type of interval of the second polarity specifically includes 3x0a, 3x1a, 3x1b, 3x2a, 3x2b, 3x3a, 3x3b…3xna, 3xnb, 3x(n+1)a, 3x(n+1)b, ​​3x(n+2)a, 3x(n+2)b…3x(n+i)a, 3x(n+i)b. The second polarity fourth type of interval specifically includes 3y1a, 3y1b, 3y2a, 3y2b…3yna, 3ynb, 3y(n+1)a, 3y(n+1)b, ​​3y(n+2)a, 3y(n+2)b…3y(n+i)a, 3y(n+i)b, where n is greater than or equal to i and i is greater than or equal to 1.

[0081] Example 4

[0082] An impact-resistant superjunction device, such as Figure 6 As shown, the difference from Embodiment 1 is that the first type of interval of the second polarity specifically includes 4dx1, 4dx2, 4dx3…4dxn, 4dx(n+1), 4dx(n+2)…4dx(n+i). The second type of interval of the second polarity specifically includes 4dy1, 4dy2, 4dy3…4dy(n+1), 4dy(n+2)…4dy(n+i). The third type of interval of the second polarity specifically includes 4x1a, 4x1b, 4x2a, 4x2b, 4x3a, 4x3b…4xna, 4xnb, 4x(n+1)a, 4x(n+1)b, ​​4x(n+2)a, 4x(n+2)b…4x(n+i)a, 4x(n+i)b. The second polarity fourth type of interval specifically includes 4y1a, 4y1b, 4y2a, 4y2b…4yna, 4ynb, 4y(n+1)a, 4y(n+1)b, ​​4y(n+2)a, 4y(n+2)b…4y(n+i)a, 4y(n+i)b, where n is greater than or equal to i and i is greater than or equal to 1.

[0083] Example 5

[0084] An impact-resistant superjunction device, such as Figure 7As shown, the difference from Embodiment 1 is that the first type of interval of the second polarity specifically includes 5dx1, 5dx2, 5dx3…5dxn, 5dx(n+1), 5dx(n+2)…5dx(n+i). The second type of interval of the second polarity specifically includes 5dy1, 5dy2, 5dy3…5dy(n+1), 5dy(n+2)…5dy(n+i). The third type of interval of the second polarity specifically includes 5x1a, 5x1b, 5x2a, 5x2b, 5x3a, 5x3b…5xna, 5xnb, 5x(n+1)a, 5x(n+1)b, ​​5x(n+2)a, 5x(n+2)b…5x(n+i)a, 5x(n+i)b. The second polarity fourth type of interval specifically includes 5y1a, 5y1b, 5y2a, 5y2b…5yna, 5ynb, 5y(n+1)a, 5y(n+1)b, ​​5y(n+2)a, 5y(n+2)b…5y(n+i)a, 5y(n+i)b, where n is greater than or equal to i and i is greater than or equal to 1.

[0085] Example 6

[0086] A method for fabricating an impact-resistant superjunction device as described in Examples 1-5 includes the following steps:

[0087] A. Preparation of the epitaxial layer;

[0088] B. Preparation of the pressure-resistant layer;

[0089] C. Fabrication of the front-side VDMOS structure;

[0090] D. Fabrication of circuit link layer and passivation layer.

[0091] In a specific embodiment, step A, the fabrication of the epitaxial layer, specifically includes the following steps:

[0092] Step S1, as follows Figure 1 As shown, a second polar first epitaxial layer 2 is grown on a silicon substrate 1 by chemical vapor deposition.

[0093] Step S2, as follows Figure 1 As shown, a high-concentration second epitaxial layer 3 can be fabricated by performing a second epitaxial layer 2 on the first epitaxial layer 2, or by performing a low-concentration epitaxial layer followed by ion implantation. The resistivity of the second epitaxial layer 3 is less than that of the first epitaxial layer 2.

[0094] In a specific embodiment, step B, the preparation of the pressure-resistant layer, specifically includes the following steps:

[0095] Step S3, as follows Figure 2 As shown, epitaxial layer 5 is further grown using chemical vapor deposition, serving as the second polar columnar region.

[0096] Step S4: After growing the hard film, spin-coating of photoresist is performed. Exposure is achieved using a photolithography machine, defining the pattern on the photomask onto the photoresist. After etching, the pattern on the photoresist is defined onto the hard film. The pattern on the photomask can be... Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 The layout shown is as follows.

[0097] Step S5, as follows Figure 8 As shown, after deep trench etching, the hard film is removed to obtain the second polar columnar region 5.

[0098] Step S6, as follows Figure 9 As shown, a reverse conductive layer is grown by chemical vapor deposition, the deep trench is filled, and high-temperature annealing is performed to obtain the first polar columnar region 4, thereby obtaining the voltage-resistant layer of the device described in this invention.

[0099] In a specific embodiment, step C, the fabrication of the front-side VDMOS structure, specifically includes the following steps:

[0100] Step S10, as follows Figure 10 As shown, a high-temperature oxidation process is used to grow the gate oxide layer, followed by polysilicon growth and etching after patterning is defined by photoresist exposure, thereby obtaining the gate oxide layer 6 and gate 7 of the front-side VDMOS.

[0101] Step S11, as follows Figure 11 As shown, after body region implantation and source electrode implantation, high-temperature thermal annealing is performed to obtain body region 8 and source electrode 9.

[0102] Step S12: After defining the pattern by photoresist exposure, inject the ohmic contact area.

[0103] In a specific embodiment, step D, the fabrication of the circuit link layer and the passivation layer, specifically includes the following steps:

[0104] Step S13, as follows Figure 12 As shown, interlayer medium 10 is obtained through chemical vapor deposition.

[0105] Step S14, as follows Figure 13 As shown, the area of ​​the metal via 11 is defined by spin-coating photoresist followed by exposure and etching, and the metal via is deposited by sputtering. The metal layer is then formed through the deposition process, followed by spin-coating photoresist, exposure, and a dry or wet / dry hybrid method to form the circuit connection layer 12.

[0106] Step S15, as follows Figure 14As shown, one or more passivation layers 13 are deposited, and the pad areas are opened using photolithography and etching processes. The final result is as shown in Examples 1-5. Figure 14 The shock-resistant superjunction device shown.

[0107] Example 7

[0108] An impact-resistant superjunction device, such as Figure 21 As shown, the difference from Example 1 is that the number of pressure-resistant layers is greater than one.

[0109] Example 8

[0110] A method for fabricating an impact-resistant superjunction device as shown in Example 7 includes the following steps:

[0111] A. Preparation of the epitaxial layer;

[0112] B. Preparation of the pressure-resistant layer;

[0113] C. Fabrication of the front-side VDMOS structure;

[0114] D. Fabrication of circuit link layer and passivation layer.

[0115] In a specific embodiment, step A, the fabrication of the epitaxial layer, specifically includes the following steps:

[0116] Step S1, as follows Figure 1 As shown, a second polar first epitaxial layer 2 is grown on a silicon substrate 1 by chemical vapor deposition.

[0117] Step S2, as follows Figure 1 As shown, a high-concentration second epitaxial layer 3 can be fabricated by performing a second epitaxial layer 2 on the first epitaxial layer 2, or by performing a low-concentration epitaxial layer followed by ion implantation. The resistivity of the second epitaxial layer 3 is less than that of the first epitaxial layer 2.

[0118] In a specific embodiment, step B, the preparation of the pressure-resistant layer, specifically includes the following steps:

[0119] Step S7, as follows Figure 15 As shown, the epitaxial layer is further grown by chemical vapor deposition to obtain the second polar region 5b0; then photoresist spin coating is performed, and the pattern on the photomask is defined on the photoresist by exposure through a photolithography machine. After ion implantation, the first polar region 4b0 is obtained.

[0120] The mask pattern required to form the first polarity region can be adopted using... Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 The layout shown is as follows.

[0121] Step S8, as follows Figure 16 As shown, the process described in step S7 above is repeated 0-N times to realize the first polarity regions 4b1, 4b2, 4bn and the second polarity regions 5b1, 5b2, 5bn, which serve as the withstand voltage layer of the device of the present invention, wherein n is greater than or equal to 1.

[0122] Step S9: Perform high-temperature thermal annealing to repair lattice damage and activate injected impurities. Due to the effects of the high-temperature process, the first polar diffusion region 4bx is formed.

[0123] In a specific embodiment, step C, the fabrication of the front-side VDMOS structure, specifically includes the following steps:

[0124] Step S10, as follows Figure 17 As shown, a high-temperature oxidation process is used to grow the gate oxide layer, followed by polysilicon growth and etching after patterning is defined by photoresist exposure, thereby obtaining the gate oxide layer 6 and gate 7 of the front-side VDMOS.

[0125] Step S11, as follows Figure 18 As shown, after body region implantation and source electrode implantation, high-temperature thermal annealing is performed to obtain body region 8 and source electrode 9.

[0126] Step S12: After defining the pattern by photoresist exposure, inject the ohmic contact area.

[0127] In a specific embodiment, step D, the fabrication of the circuit link layer and the passivation layer, specifically includes the following steps:

[0128] Step S13, as follows Figure 19 As shown, interlayer medium 10 is obtained through chemical vapor deposition.

[0129] Step S14, as follows Figure 20 As shown, the area of ​​the metal via 11 is defined by spin-coating photoresist followed by exposure and etching, and the metal via is deposited by sputtering. The metal layer is then formed through the deposition process, followed by spin-coating photoresist, exposure, and a dry or wet / dry hybrid method to form the circuit connection layer 12.

[0130] Step S15, as follows Figure 21 As shown, one or more passivation layers 13 are deposited, and the pad areas are opened using photolithography and etching processes. The final result is as shown in Example 7. Figure 21 The shock-resistant superjunction device shown.

[0131] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. An impact-resistant superjunction device, characterized in that, It includes, from bottom to top, a substrate, a first epitaxial layer, a second epitaxial layer, at least one withstand voltage layer, a gate oxide layer, a gate, an interlayer dielectric, a metal via, a circuit connection layer, and a passivation layer; The withstand voltage layer includes a second polar columnar region and a first polar columnar region; a plurality of body regions and source electrodes are disposed between the withstand voltage layer and the gate oxide layer; the metal vias are uniformly distributed in the interlayer dielectric, and the lower end of the metal vias is connected to the body regions and source electrodes, and the upper end is connected to the circuit connection layer. The second polar columnar region includes a plurality of second polar columns, and the first polar columnar region includes a plurality of first polar columns; With the upper right corner as the origin, the vertical direction is x, and the horizontal direction is y; several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction, and several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction. The interval between several second polarity columns extending along the y direction and arranged along the x direction is the second polarity first type interval; the interval between several second polarity columns extending along the x direction and arranged along the y direction is the second polarity second type interval; The interval between a second polar column extending in the x direction and its adjacent second polar column extending in the y direction, and the interval between a second polar column extending in the x direction and its adjacent second polar column extending in the x direction, are the second polar third type intervals. The interval between a second polar column extending in the y direction and its adjacent second polar column extending in the x direction, and the interval between a second polar column extending in the y direction and its adjacent second polar column extending in the y direction, are the fourth type of second polarity intervals. When the first type of second polarity spacing is equal to the second type of second polarity spacing, and the third type of second polarity spacing is equal to the fourth type of second polarity spacing, the superjunction device is in a two-dimensional charge balance state. When the first type of second polarity spacing is not equal to the second type of second polarity spacing, and the third type of second polarity spacing is not equal to the fourth type of second polarity spacing, the superjunction device is in a working state with excess first polarity charge or excess second polarity charge.

2. The impact-resistant superjunction device according to claim 1, characterized in that, The number of pressure-resistant layers is greater than one.

3. A method for fabricating an impact-resistant superjunction device, characterized in that, Includes the following steps: A. Preparation of the epitaxial layer; B. Preparation of the pressure-resistant layer; C. Fabrication of the front-side VDMOS structure; D. Fabrication of circuit link layer and passivation layer; The pressure-resistant layer includes a second polar columnar region and a first polar columnar region; the second polar columnar region includes a plurality of second polar columns, and the first polar columnar region includes a plurality of first polar columns; With the upper right corner as the origin, the vertical direction is x, and the horizontal direction is y; several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction, and several second polar columns extending along the y direction are alternately arranged with second polar columns extending along the x direction. The interval between several second polarity columns extending along the y direction and arranged along the x direction is the second polarity first type interval; the interval between several second polarity columns extending along the x direction and arranged along the y direction is the second polarity second type interval; The interval between a second polar column extending in the x direction and its adjacent second polar column extending in the y direction, and the interval between a second polar column extending in the x direction and its adjacent second polar column extending in the x direction, are the second polar third type intervals. The interval between a second polar column extending in the y direction and its adjacent second polar column extending in the x direction, and the interval between a second polar column extending in the y direction and its adjacent second polar column extending in the y direction, are the fourth type of second polarity intervals. When the first type of second polarity spacing is equal to the second type of second polarity spacing, and the third type of second polarity spacing is equal to the fourth type of second polarity spacing, the superjunction device is in a two-dimensional charge balance state. When the first type of second polarity spacing is not equal to the second type of second polarity spacing, and the third type of second polarity spacing is not equal to the fourth type of second polarity spacing, the superjunction device is in a working state with excess first polarity charge or excess second polarity charge.

4. The method for fabricating the impact-resistant superjunction device according to claim 3, characterized in that, Step A specifically includes the following steps: S1. A first epitaxial layer is grown on a silicon substrate by chemical vapor deposition as a buffer layer for the shock-resistant superjunction device. S2. A high-concentration second epitaxial layer is obtained by performing a high-concentration second epitaxial growth on the first epitaxial layer or by using ion implantation.

5. The method for fabricating the impact-resistant superjunction device according to claim 3, characterized in that, When the pressure-resistant layer is a single layer, step B specifically includes the following steps: S3. Continue to grow the epitaxial layer using chemical vapor deposition; S4. After growing the hard film, spin-coating of photoresist is performed. The pattern on the photomask is defined on the photoresist by exposure through a photolithography machine. After etching, the pattern on the photoresist is defined on the hard film. S5. Perform deep trench etching, and then remove the hard film; S6. A reverse conductive layer is grown by chemical vapor deposition to fill the deep trench, thereby obtaining the withstand voltage layer of the device described in this invention. High-temperature thermal annealing is then performed to repair lattice damage and activate the injected impurities.

6. The method for fabricating the impact-resistant superjunction device according to claim 5, characterized in that, When the pressure-resistant layer is greater than one layer, step B specifically includes the following steps: S7. Continue to grow the epitaxial layer by chemical vapor deposition, perform ion implantation, and spin-coate photoresist. Expose the photomask by a photolithography machine to define the pattern on the photoresist. After ion implantation, the reverse doped region is obtained. S8. Repeat step S7 to obtain the voltage-resistant layer of the impact-resistant superjunction device; S9. Perform high-temperature thermal annealing to repair lattice damage and activate injected impurities.

7. The method for fabricating the impact-resistant superjunction device according to claim 3, characterized in that, Step C specifically includes the following steps: S10, gate oxide layer growth, polysilicon growth and etching; S11, body region injection, and source injection; S12, Ohmic contact area injection.

8. The method for preparing the impact-resistant superjunction device according to claim 3, characterized in that, Step D specifically includes the following steps: S13, Interlayer dielectric layer deposition; S14. Define the area of ​​the metal via by etching after exposure, and deposit the metal via by sputtering. A metal layer is obtained by deposition, followed by spin coating with photoresist, exposure, and then etching using a dry or wet / dry method to obtain a circuit connection layer. S15. Deposit a passivation layer and open the pad area using photolithography and etching processes.

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