Longitudinal bcd devices and methods of fabrication

Abstract

The application provides a longitudinal BCD device and a preparation method, and the longitudinal BCD device comprises an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, a P-type buried layer, a BCD structure and a Trench VDMOS structure; the first N-type epitaxial layer is epitaxially grown on the surface of the N-type substrate, and the second N-type epitaxial layer is epitaxially grown on the surface of the first N-type epitaxial layer; the BCD structure is arranged on the second N-type epitaxial layer and the P-type buried layer, and the Trench VDMOS structure is formed on the second N-type epitaxial layer; the BCD structure is provided with a VBB lead-out end and a GND lead-out end, the Trench VDMOS structure is provided with a source lead-out end, and the N-type substrate is provided with a drain lead-out end at the lower end face; by integrating the Trench VDMOS structure and the BCD structure, the compatibility of the BCD process and the VDMOS is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of monolithic integrated circuit technology, and in particular to a vertical BCD device and its fabrication method. Background Technology

[0002] The mainstream power semiconductor integration technology is the Bipolar-CMOS-DMOS process (BCD process for short). The BCD process is a process that integrates Bipolar devices, CMOS devices, and DMOS devices on the same silicon substrate. Among them, Bipolar devices have the characteristics of high and low noise, high precision, and high current density per unit area, while CMOS devices have the characteristics of high integration, simple logic control, and low power consumption. When integrated with high-power DMOS devices on a chip, it has the advantages of improving system performance, reducing cost, and reducing power consumption.

[0003] The existing mature BCD process is a planar structure. LDMOS is widely used because it is more compatible with CMOS process. However, due to its lateral structure, it is limited by the on-resistance and cannot provide large current. It can only meet the needs of low-power applications. To meet the high-power requirements, VDMOS devices need to be integrated in the BCD process. However, since VDMOS is a vertical structure, its compatibility with planar structure process is poor. Summary of the Invention

[0004] This invention provides a vertical BCD device and its fabrication method to overcome the shortcomings of poor compatibility between BCD technology and VDMOS in the prior art.

[0005] This invention provides a vertical BCD device, comprising: an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, a BCD structure, and a Trench VDMOS structure;

[0006] The first N-type epitaxial layer is epitaxially grown on the surface of the N-type substrate, and the second N-type epitaxial layer is epitaxially grown on the surface of the first N-type epitaxial layer;

[0007] The BCD structure is disposed on the second N-type epitaxial layer. The Trench VDMOS structure is formed on the second N-type epitaxial layer by etching, oxidation, deposition, photolithography and ion implantation processes. A shallow trench isolation region is provided between the Trench VDMOS structure and the BCD structure.

[0008] The BCD structure is provided with a VBB lead and a GND lead, the Trench VDMOS structure is provided with a Trench VDMOS source lead, and the drain lead of the Trench VDMOS structure is provided on the side of the N-type substrate away from the first N-type epitaxial layer.

[0009] According to a vertical BCD device provided by the present invention, the Trench VDMOS structure includes: a Trench VDMOS trench region, a Trench VDMOS gate, and a Trench VDMOS PB region;

[0010] The Trench VDMOS trench region is formed on the second N-type epitaxial layer by the etching process;

[0011] The Trench VDMOS gate is formed inside the Trench VDMOS trench region through the oxidation process and the deposition process;

[0012] The Trench VDMOS PB region is formed within the second N-type epitaxial layer and is located on both sides of the Trench VDMOS gate.

[0013] According to the present invention, a vertical BCD device is provided, wherein the BCD structure includes: a P-type buried layer, a DPW region, an LDMOS device, a CMOS device, and a Bipolar device;

[0014] The P-type buried layer is disposed inside the first N-type epitaxial layer, the DPW region is formed inside the second N-type epitaxial layer, the DPW region and the P-type buried layer form an isolation island structure, and the DPW region and the P-type buried layer are connected.

[0015] The LDMOS device, the CMOS device, and the Bipolar device are sequentially fabricated inside the isolation island structure.

[0016] According to a longitudinal BCD device provided by the present invention, the BCD structure further includes: a DNW region;

[0017] The DNW region is formed within the second N-type epitaxial layer, and the DNW region is disposed between the DPW regions;

[0018] Shallow trench isolation regions are provided between the Trench VDMOS structure and the BCD structure, and between the LDMOS device, the CMOS device, and the Bipolar device.

[0019] According to a longitudinal BCD device provided by the present invention, the implanted ions in the DPW region are P-type ions, the implanted ions in the DNW region are N-type ions, and the implanted ions in the P-type buried layer are boron ions.

[0020] A longitudinal BCD device provided by the present invention further includes: a P+ contact area and an N+ contact area;

[0021] Both the P+ contact region and the N+ contact region are disposed on the surface of the Trench VDMOS PB region;

[0022] The P+ contact area is also disposed on the surface of the DPW area, and the N+ contact area is also disposed on the surface of the DNW area;

[0023] A shallow trench isolation area is further provided between the P+ contact area on the surface of the DPW area and the N+ contact area on the surface of the DNW area.

[0024] According to a longitudinal BCD device provided by the present invention, the thickness of the first N-type epitaxial layer is 7.0-8.0 μm, and the resistivity is 3.0-5.0 ohm*cm;

[0025] The thickness of the second N-type epitaxial layer is 6.4–6.8 μm, and the resistivity is 1.1–1.3 ohm*cm.

[0026] The present invention also provides a method for fabricating a longitudinal BCD device as described in any of the preceding claims, comprising:

[0027] Select crystal orientation as <100> N-type substrate;

[0028] A first N-type epitaxial layer is grown on the N-type substrate. Using a P-type buried layer photomask, a P-type buried layer ion implantation region is formed in the first N-type epitaxial layer by photolithography. Boron ions are then implanted in the P-type buried layer ion implantation region by ion implantation, and furnace tube push-bonding is performed at a temperature of 1000-1100°C to form a P-type buried layer.

[0029] A second N-type epitaxial layer continues to grow on the P-type buried layer;

[0030] Using a DPW photomask, a DPW region is formed in the second N-type epitaxial layer by photolithography, and then ion implantation is performed on the DPW region by ion implantation.

[0031] Using the DNW photomask, a DNW region is formed in the second N-type epitaxial layer by photolithography, and then ion implantation is performed on the DNW region by ion implantation.

[0032] A silicon dioxide layer is formed on the surface of the second N-type epitaxial layer using a deposition process. Then, using a Trench VDMOS Trench mask, the silicon dioxide layer is etched in the etching area formed on the surface of the second N-type epitaxial layer by a photolithography process, retaining a silicon dioxide of a preset size as a hard mask for trench etching.

[0033] Based on the hard mask, the second N-type epitaxial layer is etched using an etching process to form a TrenchVDMOS trench region;

[0034] An oxidation process is used to form the gate oxide layer of the Trench VDMOS in the trench region, and a polysilicon layer is deposited on the gate oxide layer using a deposition process. Then, the polysilicon layer is etched back to form the gate of the Trench VDMOS.

[0035] Using the PB photomask of Trench VDMOS, the PB implantation region is formed on the surface of the second N-type epitaxial layer by photolithography, and the Trench VDMOS PB region is formed by ion implantation.

[0036] Shallow trench isolation for CMOS devices, LDMOS devices, and Bipolar devices is formed in the non-Trench VDMOS region using an STI photomask and photolithography and etching processes.

[0037] An LDMOS device, a CMOS device, and a Bipolar device are sequentially fabricated in the isolation island structure formed by the DPW region and the P-type buried layer.

[0038] Using P+ and N+ photomasks respectively, P+ contact regions and N+ contact regions are formed through photolithography and ion implantation processes, respectively forming the drain and source of the P-type MOS device, the drain and source of the N-type MOS device, the lead-out terminal of the DPW region, and the lead-out terminal of the DNW region;

[0039] Forming an intermediate dielectric layer, contact holes, and a metal layer;

[0040] The N-type substrate is gold-plated to form the drain terminal of the Trench VDMOS.

[0041] According to a method for fabricating a vertical BCD device provided by the present invention, the ion implantation energy of the P-type buried layer is 50 keV to 80 keV, and the implantation dose is 5.5E13cm. -2 ~8.5E13cm -2 ;

[0042] The ion implantation energy of the Trench VDMOS PB region is 50 keV to 80 keV, and the implantation dose is 1.5E15cm. -2 ~3E15cm -2 ;

[0043] The DPW performs ion implantation in three stages. The first ion implantation energy is 1500 keV to 1700 keV, and the implantation dose is 2.0E12cm. -2 ~3.0E12cm -2 The second ion implantation energy was 400 keV–800 keV, and the implantation dose was 1.5E12cm.-2 ~2.5E12cm -2 The third ion implantation energy was 120 keV–180 keV, and the implantation dose was 1.0E12cm. -2 ~2.0E12cm -2 ;

[0044] The DNW underwent ion implantation in three stages. The first ion implantation energy was 2800 keV to 3200 keV, and the implantation dose was 4.5E12cm. -2 ~5.5E12cm -2 The second ion implantation energy was 1100 keV–1400 keV, and the implantation dose was 4.0E12cm. -2 ~5.0E12cm -2 The third ion implantation energy was 120 keV–180 keV, and the implantation dose was 3.5E12cm. -2 ~4.5E12cm -2 .

[0045] According to a method for fabricating a vertical BCD device provided by the present invention, the etching depth of the Trench VDMOS trench formed on the second N-type epitaxial layer is 1.2 μm to 2.0 μm.

[0046] This invention provides a vertical BCD device and its fabrication method. The vertical BCD device includes: an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, a BCD structure, and a Trench VDMOS structure. The first N-type epitaxial layer is epitaxially grown on the surface of the N-type substrate, and the second N-type epitaxial layer is epitaxially grown on the surface of the first N-type epitaxial layer. The BCD structure is disposed on the second N-type epitaxial layer, and the Trench VDMOS structure is formed on the second N-type epitaxial layer through etching, oxidation, deposition, photolithography, and ion implantation processes. The BCD structure has a VBB terminal and a GND terminal, and the Trench VDMOS structure has a Trench VDMOS source terminal. The drain terminal of the Trench VDMOS structure is disposed on the side of the N-type substrate away from the first N-type epitaxial layer. By integrating the Trench VDMOS structure and the BCD structure into one unit, the high current and high power requirements are met, and the compatibility between the BCD process and VDMOS is effectively improved. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of the vertical BCD device provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic flowchart of the fabrication method of the vertical BCD device provided in the embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure after forming an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, and a P-type buried layer, according to an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of the structure after the DPW region is formed, provided in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the structure after the formation of the DNW region provided in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the structure after the formation of the silicon dioxide layer provided in the embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the structure after the formation of the Trench VDMOS trench region provided in an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram of the structure after forming the Trench VDMOS gate according to an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of the structure after forming the Trench VDMOS PB region according to an embodiment of the present invention;

[0057] Figure 10 This is a schematic diagram of the structure after shallow trench isolation is formed, as provided in an embodiment of the present invention;

[0058] Figure 11 This is a schematic diagram of the structure after fabricating LDMOS devices, CMOS devices, and Bipolar devices according to embodiments of the present invention;

[0059] Figure 12 This is a schematic diagram of the structure after the formation of the P+ contact region and the N+ contact region provided in the embodiment of the present invention;

[0060] Figure label:

[0061] 1. N-type substrate; 2. First N-type epitaxial layer; 3. Second N-type epitaxial layer; 4. P-type buried layer; 5. DPW region; 6. DNW region; 7. Trench VDMOS trench region; 8. Trench VDMOS gate; 9. Trench VDMOS PB region; 10. Shallow trench isolation region; 11. P+ contact region; 12. N+ contact region; 13. Trench VDMOS source terminal; 14. VBB terminal; 15. GND terminal; 16. Trench VDMOS drain terminal; 17. Silicon dioxide layer. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0063] The following is combined with Figures 1-12 This invention describes a vertical BCD device and its fabrication method.

[0064] Figure 1 This is a schematic diagram of the structure of the vertical BCD device provided in an embodiment of the present invention.

[0065] like Figure 1 As shown in the figure, an embodiment of the present invention provides a vertical BCD device, comprising: an N-type substrate 1, a first N-type epitaxial layer 2, a second N-type epitaxial layer 3, a BCD structure, and a Trench VDMOS structure; the first N-type epitaxial layer 2 is epitaxially grown on the surface of the N-type substrate 1, and the second N-type epitaxial layer 3 is epitaxially grown on the surface of the first N-type epitaxial layer 2; the BCD structure is disposed on the second N-type epitaxial layer 3, and the Trench VDMOS structure is formed on the second N-type epitaxial layer 3 by etching, oxidation, deposition, photolithography, and ion implantation processes; the BCD structure is provided with a VBB lead 14 and a GND lead 15, the Trench VDMOS structure is provided with a Trench VDMOS source lead 13, and the drain lead 16 of the Trench VDMOS structure is disposed on the side of the N-type substrate 1 away from the first N-type epitaxial layer 2.

[0066] In a specific implementation, the N-type substrate 1 side is defined as the bottom side, and the second N-type epitaxial layer 3 side is defined as the top side, such as... Figure 1 As shown, Figure 1 The left side is the bottom side. Figure 1 The right side is the top side. The N-type substrate 1, the first N-type epitaxial layer 2, and the second N-type epitaxial layer 3 are arranged sequentially in the longitudinal direction. The first N-type epitaxial layer 2 is obtained by epitaxial growth on the upper surface of the N-type substrate 1, and a P-type buried layer 4 is disposed inside the first N-type epitaxial layer 2, such as... Figure 1 Three P-type buried layers 4 are provided, and then a second N-type epitaxial layer 3 is epitaxially grown on the upper surface of the first N-type epitaxial layer 2. Both the BCD structure and the TrenchVDMOS structure are disposed within the second N-type epitaxial layer 3.

[0067] By integrating the BCD structure and the Trench VDMOS structure within the second N-type epitaxial layer 3, the compatibility issue between the BCD process and VDMOS can be effectively resolved. Furthermore, since the DMOS uses a Trench VDMOS, and the drain is led out from the back of the BCD device and the side of the N-type substrate 1 furthest from the second N-type epitaxial layer 3, under the same voltage withstand capability, the vertically stacked structure of the N-type substrate 1, the first N-type epitaxial layer 2, and the second N-type epitaxial layer 3 results in a smaller chip area, higher chip utilization, and reduced complexity of high-voltage interconnects compared to the BCD process integrating planar VDMOS.

[0068] Furthermore, the P-type buried layer 4 serves as the base region of the parasitic NPN transistor. By adjusting the concentration of the P-type buried layer 4, the conduction of the parasitic NPN transistor can be suppressed, preventing latch-up effects and effectively protecting the device from overheating and burning out.

[0069] Furthermore, such as Figure 1 As shown, based on the above embodiments, the Trench VDMOS structure in this embodiment includes: a Trench VDMOS trench region 7, a Trench VDMOS gate 8, and a Trench VDMOS PB region 9; the Trench VDMOS trench region 7 is formed on the second N-type epitaxial layer 3 by an etching process; the Trench VDMOS gate 8 is formed inside the Trench VDMOS trench region 7 by an oxidation process and a deposition process; the Trench VDMOS PB region 9 is formed in the second N-type epitaxial layer 3 and is located on both sides of the Trench VDMOS gate 8.

[0070] Specifically, an etching process is used to etch the upper surface of the second N-type epitaxial layer 3 to form a Trench VDMOS trench region 7. The Trench VDMOS trench region 7 contains a Trench VDMOS gate 8, while the Trench VDMOS trench region 7 is surrounded by a Trench VDMOS PB region 9. Therefore, the Trench VDMOS trench region 7 separates the Trench VDMOS gate 8 from the Trench VDMOS PB region 9. The Trench VDMOS trench region 7, the Trench VDMOS gate 8, and the Trench VDMOS PB region 9 are all integrated with the BCD structure on the second N-type epitaxial layer 3, better achieving compatibility between the BCD process and VDMOS.

[0071] Furthermore, such as Figure 1 As shown, based on the above embodiments, the BCD structure in this embodiment includes: a P-type buried layer, a DPW region 5, a DNW region 6, an LDMOS device, a CMOS device, and a Bipolar device; the P-type buried layer is disposed inside the first N-type epitaxial layer, the DPW region 5 is formed inside the second N-type epitaxial layer 3, the DPW region 5 and the P-type buried layer 4 form an isolation island structure, and the DPW region 5 is connected to the P-type buried layer 4; the LDMOS device, the CMOS device, and the Bipolar device are sequentially fabricated inside the isolation island structure; the DNW region 6 is formed inside the second N-type epitaxial layer 3, the DNW region 6 is disposed between the DPW regions 5, and shallow trench isolation regions 10 are disposed between the Trench VDMOS structure and the BCD structure, and between the LDMOS device, the CMOS device, and the Bipolar device.

[0072] Specifically, a DPW region 5 is formed on the upper surface of the second N-type epitaxial layer 3 through high-energy injection and high-temperature push-bonding, and a deep DNW region 6 is formed through a high-temperature push-well process. The DPW region 5 is connected to the P-type buried layer 4 in the longitudinal direction. Figure 1 As shown, in the non-TrenchVDMOS region, DPW region 5 and DNW region 6 are spaced apart, thus forming isolation islands between DPW regions 5 with P-type buried layers 4. LDMOS devices, CMOS devices, and Bipolar devices are respectively disposed within these isolation islands. Figure 1As shown, three P-type buried layers 4 are configured, forming isolation island structures with the corresponding DPW region 5 and DNW region 6, respectively. An LDMOS device is placed inside the first isolation island structure to form an LDMOS region, a CMOS device is placed inside the second isolation island structure to form a CMOS region, and a Bipolar device is placed inside the third isolation island structure to form a Bipolar region. This allows for the integration of the Trench VDMOS trench region 7, Trench VDMOS gate 8, Trench VDMOS PB region 9, DPW region 5, DNW region 6, LDMOS device, CMOS device, and Bipolar device within the second N-type epitaxial layer 3, improving the compatibility of the BCD process with VDMOS.

[0073] Among them, the ions implanted in DPW region 5 are P-type ions such as boron ions, the ions implanted in DNW region 6 are N-type ions such as phosphorus ions, and the ions implanted in P-type buried layer 4 are boron ions.

[0074] Furthermore, such as Figure 1 As shown, based on the above embodiment, this embodiment further includes: a P+ contact region 11 and an N+ contact region 12; both the P+ contact region 11 and the N+ contact region 12 are disposed on the surface of the Trench VDMOS PB region 9; the P+ contact region 11 is also disposed on the surface of the DPW region 5, and the N+ contact region 12 is also disposed on the surface of the DNW region 6; a shallow trench isolation region 10 is also disposed between the P+ contact region 11 disposed on the surface of the DPW region 5 and the N+ contact region 12 disposed on the surface of the DNW region 6.

[0075] Specifically, P+ contact region 11 and N+ contact region 12 are used to form the drain and source of the P-type MOS device, the drain and source of the N-type MOS device, the lead-out terminal of the DPW, and the lead-out terminal of the DNW, respectively. P+ contact region 11 and N+ contact region 12 are formed on the surface of the Trench VDMOS PB region 9 on the second N-type epitaxial layer 3. P+ contact region 11 and N+ contact region 12 are formed on both sides of the PB region of the Trench VDMOS trench region 7, and then the Trench VDMOS source is led out. P+ contact region 11 is formed on the upper surface of each DPW region 5, and N+ contact region 12 is formed on the upper surface of each DNW, and both are effectively isolated by the shallow trench isolation region 10. VBB is led out from the P+ contact region 11 on the surface of each DPW region 5, and GND is led out from the N+ contact region 12 on the surface of each DNW region 6.

[0076] Furthermore, based on the above embodiments, the thickness of the first N-type epitaxial layer 2 in this embodiment is 7.0-8.0 μm, and the resistivity is 3.0-5.0 ohm*cm; the thickness of the second N-type epitaxial layer 3 is 6.4-6.8 μm, and the resistivity is 1.1-1.3 ohm*cm.

[0077] In this invention, the LDMOS device, CMOS device, and Bipolar device in the vertical BCD device are all fabricated within an isolation island formed by the DPW region 5 and the P-type buried layer 4. The lead-out structure formed by the P-type buried layer 4 and the DPW region 5 is biased to ground potential on the chip surface, forming a reverse-biased diode between the DPW region 5 and the P-type buried layer 4 and the first N-type epitaxial layer 2. This ensures electrical insulation between the other devices and the substrate in the vertical direction, resulting in strong anti-interference capability of the vertical BCD device. Simultaneously, the Trench VDMOS trench region 7, Trench VDMOS gate 8, and Trench VDMOS PB region 9 are integrated, effectively improving the compatibility of the vertical BCD device with VDMOS.

[0078] In traditional BCD technology, the substrate is a P-type substrate, and the device leads are all front-side out. Only LDMOS or VDMOS with front-side leads can be integrated, but both are limited by on-resistance. Since LDMOS has a lateral structure, the on-resistance limitation prevents it from providing large currents, limiting its application to low-power applications and failing to meet the demands of high-power motor drives. However, in the BCD device with integrated VDMOS of this invention, the drain of the N-type substrate (Trench VDMOS) is connected to a high voltage during use. To avoid the influence of this voltage on the BCD device, each BCD device is placed within an isolation island composed of the DPW region and the P-type buried layer. When the N-type substrate is connected to a high voltage, the DPW and P-type buried layer form a reverse-biased diode with the N-type substrate, providing isolation. Therefore, the BCD device is not affected by the high voltage on the N-type substrate during operation.

[0079] Figure 2 This is a schematic flowchart of the fabrication method of the vertical BCD device provided in the embodiment of the present invention.

[0080] like Figure 2 As shown in the figure, the method for fabricating a vertical BCD device provided in this embodiment of the invention mainly includes the following steps:

[0081] 101. Select crystal orientation as <100> N-type substrate.

[0082] 102. A first N-type epitaxial layer is grown on an N-type substrate. Using a P-type buried layer photomask, a P-type buried layer ion implantation region is formed in the first N-type epitaxial layer by photolithography. Boron ions are then implanted in the P-type buried layer ion implantation region by ion implantation, and furnace tube push-bonding is performed at a temperature of 1000-1100℃ to form a P-type buried layer.

[0083] Among them, the ion implantation energy of the P-type buried layer 4 is 50 keV to 80 keV, and the implantation dose is 5.5E13cm. -2 ~8.5E13cm -2 .

[0084] 103. Continue to grow a second N-type epitaxial layer on the P-type buried layer.

[0085] like Figure 3 The diagram shown is a schematic representation of the structure formed after steps 101, 102, and 103, relating to the N-type substrate 1, the first N-type epitaxial layer 2, the second N-type epitaxial layer 3, and the P-type buried layer 4. Figure 3 The structural relationship between the N-type substrate 1, the first N-type epitaxial layer 2, the second N-type epitaxial layer 3, and the P-type buried layer 4 can be clearly understood.

[0086] 104. Using the DPW photomask, the DPW region is formed in the second N-type epitaxial layer by photolithography, and then the DPW region is implanted with ions by ion implantation.

[0087] like Figure 4 The diagram shown is a schematic representation of the structure after the formation of DPW region 5. Figure 4 An isolation island structure can be obtained between DPW region 5 and P-type buried layer 4, and DPW region 5 and P-type buried layer 4 are connected. The high-temperature push-bonding temperature for forming DPW region 5 can be 1100-1150℃, and the time is 120-180 minutes.

[0088] In this process, ion implantation of DPW region 5 was selectively performed in three stages. The first ion implantation energy was 1500 keV–1700 keV, and the implantation dose was 2.0E12cm. -2 ~3.0E12cm -2 The second ion implantation energy was 400 keV–800 keV, and the implantation dose was 1.5E12cm. -2 ~2.5E12cm -2 The third ion implantation energy was 120 keV–180 keV, and the implantation dose was 1.0E12cm. -2 ~2.0E12cm -2 .

[0089] 105. Using the DNW photomask, the DNW region is formed in the second N-type epitaxial layer by photolithography, and then the DNW region is implanted with ions by ion implantation.

[0090] like Figure 5 The diagram shown is a structural schematic after the formation of DNW region 6. Figure 5 The relationship between DPW zone 5, P-type buried layer 4 and DNW zone 6 can be seen, and the DPW zone and DNW zone are set at intervals.

[0091] The DNW region 5 underwent selective ion implantation in three stages. The first stage involved implantation at an energy of 2800 keV–3200 keV and an implantation dose of 4.5E12cm. -2 ~5.5E12cm -2 The second ion implantation energy was 1100 keV–1400 keV, and the implantation dose was 4.0E12cm. -2 ~5.0E12cm -2 The third ion implantation energy was 120 keV–180 keV, and the implantation dose was 3.5E12cm. -2 ~4.5E12cm -2 .

[0092] It should be noted that there is no logical order between steps 105 and 104.

[0093] 106. A silicon dioxide layer is formed on the surface of the second N-type epitaxial layer using a deposition process. Then, using a Trench VDMOS Trench mask, the silicon dioxide layer is etched in the etching area formed on the surface of the second N-type epitaxial layer by photolithography. A silicon dioxide of a preset size is retained as a hard mask for trench etching.

[0094] like Figure 6 The diagram shown is a schematic of the structure after the formation of silicon dioxide layer 17.

[0095] 107. Based on a hard mask, the second N-type epitaxial layer is etched using an etching process to form a Trench VDMOS trench region.

[0096] like Figure 7 The diagram shown is a schematic of the structure after the Trench VDMOS trench region 7 is formed. The etching depth of the second N-type epitaxial layer 3 is 1.2 μm to 2.0 μm using an etching process.

[0097] 108. An oxidation process is used to form the gate oxide layer of the Trench VDMOS in the trench region, and a polysilicon layer is deposited on the gate oxide layer using a deposition process. Then, the polysilicon layer is etched back to form the gate of the Trench VDMOS.

[0098] like Figure 8 The diagram shown is a schematic of the structure after the Trench VDMOS gate 8 is formed.

[0099] 109. Using the PB photomask of Trench VDMOS, the implantation region of PB is formed on the surface of the second N-type epitaxial layer by photolithography, and the Trench VDMOS PB region is formed by ion implantation.

[0100] like Figure 9 The diagram shown is a schematic of the structure after the formation of the Trench VDMOS PB region 9. The high-temperature push-through temperature for forming the Trench VDMOS PB region 9 is 1050-1100℃, and the time is 30-60 minutes. Furthermore, the ion implantation energy of the Trench VDMOS PB region 9 is 50keV-80keV, and the implantation dose is 1.5E15cm⁻¹. -2 ~3E15cm -2 .

[0101] 110. Shallow trench isolation of CMOS devices, LDMOS devices and Bipolar devices is formed in the non-Trench VDMOS region using STI photomask, photolithography and etching processes.

[0102] like Figure 10 The diagram shown is a structural schematic after the shallow trench isolation 10 is formed.

[0103] 111. LDMOS devices, CMOS devices and Bipolar devices are fabricated sequentially in the isolation island structure formed by the DPW region and the P-type buried layer.

[0104] like Figure 11 The diagram shown is a schematic of the structure after fabricating LDMOS, CMOS, and Bipolar devices.

[0105] 112. Using P+ and N+ photomasks respectively, P+ contact regions and N+ contact regions are formed through photolithography and ion implantation processes, respectively forming the drain and source of the P-type MOS device, the drain and source of the N-type MOS device, the lead-out terminal of the DPW region, and the lead-out terminal of the DNW region.

[0106] like Figure 12 The diagram shown is a schematic of the structure after the formation of the P+ contact region 11 and the N+ contact region 12.

[0107] 113. Formation of intermediate dielectric layer, contact hole and metal layer.

[0108] The formation of the intermediate dielectric layer, contact holes, and metal layer completes all the process steps for the front side of the wafer.

[0109] 114. Gold plating is performed on the N-type substrate to form the drain terminal of the Trench VDMOS. Specifically, the lower surface of the N-type substrate is thinned using a Trench VDMOS backside thinning process, and then gold plating is performed to form the drain terminal 16 of the Trench VDMOS on the lower surface of the N-type substrate, as shown below. Figure 1 As shown, a vertical BCD device integrating VDMOS is obtained. The thickness of the lower end face of the N-type substrate after thinning is 100-200 μm, and the gold plating material is Ti / Ni / Ag.

[0110] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a vertical BCD device, characterized in that, include: Select crystal orientation as <100> N-type substrate; A first N-type epitaxial layer is grown on the N-type substrate. Using a P-type buried layer photomask, a P-type buried layer ion implantation region is formed in the first N-type epitaxial layer by photolithography. Boron ions are then implanted in the P-type buried layer ion implantation region by ion implantation, and furnace tube push-bonding is performed at a temperature of 1000~1100℃ to form a P-type buried layer. A second N-type epitaxial layer continues to grow on the P-type buried layer; Using a DPW photomask, a DPW region is formed in the second N-type epitaxial layer by photolithography, and then ion implantation is performed on the DPW region by ion implantation. Using the DNW photomask, a DNW region is formed in the second N-type epitaxial layer by photolithography, and then ion implantation is performed on the DNW region by ion implantation. A silicon dioxide layer is formed on the surface of the second N-type epitaxial layer using a deposition process. Then, using a Trench VDMOS Trench mask, the silicon dioxide layer is etched in the etching area formed on the surface of the second N-type epitaxial layer by a photolithography process, retaining a silicon dioxide of a preset size as a hard mask for trench etching. Based on the hard mask, the second N-type epitaxial layer is etched using an etching process to form a Trench VDMOS trench region; An oxidation process is used to form the gate oxide layer of the Trench VDMOS in the trench region, and a polysilicon layer is deposited on the gate oxide layer using a deposition process. Then, the polysilicon layer is etched back to form the gate of the Trench VDMOS. Using the PB photomask of Trench VDMOS, the PB implantation region is formed on the surface of the second N-type epitaxial layer by photolithography, and the Trench VDMOS PB region is formed by ion implantation. Shallow trench isolation for CMOS devices, LDMOS devices, and Bipolar devices is formed in the non-Trench VDMOS region using an STI photomask and photolithography and etching processes. An LDMOS device, a CMOS device, and a Bipolar device are sequentially fabricated in the isolation island structure formed by the DPW region and the P-type buried layer. Using P+ and N+ photomasks respectively, P+ contact regions and N+ contact regions are formed through photolithography and ion implantation processes, respectively forming the drain and source of the P-type MOS device, the drain and source of the N-type MOS device, the lead-out terminal of the DPW region, and the lead-out terminal of the DNW region; Forming an intermediate dielectric layer, contact holes, and a metal layer; The N-type substrate is gold-plated to form the drain terminal of the Trench VDMOS.

2. The method for fabricating a longitudinal BCD device according to claim 1, characterized in that, The ion implantation energy of the P-type buried layer is 50 keV~80 keV, and the implantation dose is 5.5E13cm. -2 ~8.5E13cm -2 ; The ion implantation energy of the Trench VDMOS PB region is 50 keV~80 keV, and the implantation dose is 1.5E15cm. -2 ~3E15cm -2 ; The DPW performs ion implantation in three stages. The first ion implantation energy is 1500 keV~1700 keV, and the implantation dose is 2.0E12cm. -2 ~3.0E12cm -2 The second ion implantation energy was 400 keV~800 keV, and the implantation dose was 1.5E12cm. -2 ~2.5E12cm -2 The third ion implantation energy was 120 keV~180 keV, and the implantation dose was 1.0E12cm. -2 ~2.0E12cm -2 ; The DNW underwent ion implantation in three stages. The first ion implantation energy was 2800 keV~3200 keV, and the implantation dose was 4.5E12cm. -2 ~5.5E12cm -2 The second ion implantation energy was 1100 keV~1400 keV, and the implantation dose was 4.0E12cm. -2 ~5.0E12cm -2 The third ion implantation energy was 120 keV~180 keV, and the implantation dose was 3.5E12cm. -2 ~4.5E12cm -2 .

3. The method for fabricating a longitudinal BCD device according to claim 1, characterized in that, The etching depth of the Trench VDMOS trench formed on the second N-type epitaxial layer is 1.2μm~2.0μm.

4. A vertical BCD device, characterized in that, The vertical BCD device is fabricated using the fabrication method of any one of claims 1-3, wherein the vertical BCD device comprises: an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, a BCD structure, and a Trench VDMOS structure; The first N-type epitaxial layer is epitaxially grown on the surface of the N-type substrate, and the second N-type epitaxial layer is epitaxially grown on the surface of the first N-type epitaxial layer; The BCD structure is disposed on the second N-type epitaxial layer, and the Trench VDMOS structure is formed on the second N-type epitaxial layer by etching, oxidation, deposition, photolithography and ion implantation processes. The BCD structure is provided with a VBB lead and a GND lead, the Trench VDMOS structure is provided with a Trench VDMOS source lead, and the drain lead of the Trench VDMOS structure is provided on the side of the N-type substrate away from the first N-type epitaxial layer.

5. The longitudinal BCD device according to claim 4, characterized in that, The Trench VDMOS structure includes: a Trench VDMOS trench region, a Trench VDMOS gate, and a Trench VDMOS PB region; The Trench VDMOS trench region is formed on the second N-type epitaxial layer by the etching process; The Trench VDMOS gate is formed inside the Trench VDMOS trench region through the oxidation process and the deposition process; The Trench VDMOS PB region is formed within the second N-type epitaxial layer and is located on both sides of the Trench VDMOS gate.

6. The longitudinal BCD device according to claim 5, characterized in that, The BCD structure includes: a P-type buried layer, a DPW region, an LDMOS device, a CMOS device, and a Bipolar device; The P-type buried layer is disposed inside the first N-type epitaxial layer, the DPW region is formed inside the second N-type epitaxial layer, the DPW region and the P-type buried layer form an isolation island structure, and the DPW region and the P-type buried layer are connected. The LDMOS device, the CMOS device, and the Bipolar device are sequentially fabricated inside the isolation island structure.

7. The longitudinal BCD device according to claim 6, characterized in that, The BCD structure also includes: a DNW region; The DNW region is formed within the second N-type epitaxial layer, and the DNW region is disposed between the DPW regions; Shallow trench isolation regions are provided between the Trench VDMOS structure and the BCD structure, and between the LDMOS device, the CMOS device, and the Bipolar device.

8. The longitudinal BCD device according to claim 7, characterized in that, The implanted ions in the DPW region are P-type ions, the implanted ions in the DNW region are N-type ions, and the implanted ions in the P-type buried layer are boron ions.

9. The longitudinal BCD device according to claim 7, characterized in that, Also includes: P+ contact area and N+ contact area; Both the P+ contact region and the N+ contact region are disposed on the surface of the Trench VDMOS PB region; The P+ contact area is also disposed on the surface of the DPW area, and the N+ contact area is also disposed on the surface of the DNW area; A shallow trench isolation area is further provided between the P+ contact area on the surface of the DPW area and the N+ contact area on the surface of the DNW area.

10. The longitudinal BCD device according to any one of claims 4-9, characterized in that, The thickness of the first N-type epitaxial layer is 7.0~8.0 μm, and the resistivity is 3.0~5.0 ohm·cm; The thickness of the second N-type epitaxial layer is 6.4~6.8 μm, and the resistivity is 1.1~1.3 ohm·cm.

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