A chip-level contact system

Abstract

The application relates to a chip-level contact system. The chip-level contact system comprises at least two chips which are sequentially cascaded, and in the two chips which are adjacently cascaded: at least a lower-level chip comprises an upper-level communication pin, at least an upper-level chip comprises a lower-level communication pin; the upper-level communication pin of the lower-level chip is coupled with the lower-level communication pin of the upper-level chip, one of the upper-level chip and the lower-level chip can convert data information into a current signal and send the current signal to the other of the upper-level chip and the lower-level chip through the coupled upper-level communication pin and lower-level communication pin, and the other of the upper-level chip and the lower-level chip can obtain the data information according to the current signal. The chip-level contact system of the application uses a small number of pins when communicating between the two chips which are adjacently cascaded, simplifies the circuit structure, is beneficial to cost reduction, and can transmit information between the adjacent chips.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a chip cascade system. Background Technology

[0002] Chip cascading can support more series-connected battery cell systems for battery protection. In traditional cascaded chips, to transmit signals, the two output pins of the upper-level chip are coupled to the two input pins of the lower-level chip via two wires. That is, to achieve communication, the upper-level chip and the lower-level chip need to be coupled via two wires, requiring four pins. This results in a large number of pins, a complex circuit structure, and high cost. Furthermore, since the two output pins of the upper-level chip can only output information, it can only realize the transmission of information from the upper-level chip to the lower-level chip, and cannot realize the transmission of information from the lower-level chip to the upper-level chip. Summary of the Invention

[0003] The purpose of this invention is to overcome the above-mentioned technical problems and provide a chip cascade system that uses fewer pins when communicating between two adjacent cascaded chips, simplifies the circuit structure, helps reduce costs, and allows adjacent chips to transmit information to each other.

[0004] To achieve the above objectives, the present invention provides a chip cascading system, comprising at least two chips cascaded sequentially. In the two adjacent cascaded chips, at least the lower-level chip includes an upper-level communication pin, and at least the upper-level chip includes a lower-level communication pin. The upper-level communication pin of the lower-level chip is coupled to the lower-level communication pin of the upper-level chip. One of the upper-level chip and the lower-level chip can convert data information into a current signal and transmit it to the other of the upper-level chip and the lower-level chip through the coupled upper-level communication pin and the lower-level communication pin. The other of the upper-level chip and the lower-level chip can obtain the data information based on the current signal.

[0005] Optionally, when the upper-level chip transmits the data information to the lower-level chip, the data information includes first data information, and the current signal includes a first current signal characterizing the first data information; or, when the lower-level chip transmits the data information to the upper-level chip, the data information includes second data information, and the current signal includes a second current signal characterizing the second data information; each chip includes a communication module, wherein: the communication module includes a lower-level communication unit, the lower-level communication unit in the upper-level chip being able to send the first current signal to the lower-level chip and / or receive the second current signal sent by the lower-level chip and obtain the second data information based on the second current signal; and / or, the communication module includes an upper-level communication unit, the upper-level communication unit in the lower-level chip being able to send the second current signal to the upper-level chip and / or receive the first current signal sent by the upper-level chip and obtain the first data information based on the first current signal.

[0006] Optionally, each chip includes a voltage pin, wherein: the lower-level communication unit of the communication module includes a first switch and a lower-level current source, one end of the first switch is coupled to the lower-level communication pin of the chip, one end of the lower-level current source is coupled to the other end of the first switch, and the other end of the lower-level current source is coupled to the voltage pin of the chip; the first switch is used to receive a first high-low level signal characterizing the first data information, and to conduct and close according to the first high-low level signal, so that the lower-level current source provides the first current signal to the lower-level communication pin of the chip; and / or, the upper-level communication unit of the communication module includes a first detection circuit and a first resistor, one end of the first resistor is coupled to the upper-level communication pin of the chip, and the other end is coupled to the voltage pin of the chip; the first resistor can receive the first current signal sent by the upper-level chip through the upper-level communication pin of the chip; the first detection circuit can convert the voltage fluctuation caused by the first current signal on the first resistor into a first high-low level signal, and the first high-low level signal can characterize the first data information.

[0007] Optionally, the first detection circuit of the communication module includes a first comparator, the first input terminal of the first comparator is coupled to one end of the first resistor, the second input terminal of the first comparator is coupled to the other end of the first resistor, and the first comparator can compare the voltage difference between its first input terminal and its second input terminal with a first deviation voltage to obtain the first high and low level signal.

[0008] Optionally, the first comparator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a bias resistor, a first current source, a second current source, and a first inverter; the substrates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are coupled to their respective sources and to a power supply voltage terminal; the gates of the first PMOS transistor and the second PMOS transistor are coupled to the drains of the first PMOS transistor and the first NMOS transistor; the drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor and to the gate of the third PMOS transistor; the first The gate of the NMOS transistor is the first input terminal of the first comparator, and the gate of the second NMOS transistor is the second input terminal of the first comparator. The substrates of the first and second NMOS transistors are coupled together and grounded at one end of each of the first and second current sources. One end of the bias resistor is coupled to the source of the first NMOS transistor, and the other end is coupled to the source of the second NMOS transistor. The other end of the first current source is coupled to the other end of the bias resistor. The drain of the third PMOS transistor and the other end of the second current source are coupled to the input terminal of the first inverter. The output terminal of the first inverter is the output terminal of the first comparator.

[0009] Optionally, each chip includes a ground pin, wherein: the upper-level communication unit of the communication module includes a second switch and an upper-level current source, one end of the second switch is coupled to the upper-level communication pin of the chip, one end of the upper-level current source is coupled to the other end of the second switch, and the other end of the upper-level current source is coupled to the lower-level communication pin of the chip; the second switch can receive a second high-low level signal characterizing the second data information and turn on and off according to the second high-low level signal, so that the upper-level current source provides the second current signal to the upper-level communication pin of the chip; and / or, the lower-level communication unit of the communication module includes a second detection circuit and a second resistor, one end of the second resistor is coupled to the lower-level communication pin of the chip, and the other end is coupled to the ground pin of the chip; the second resistor can receive the second current signal sent by the next-level chip through the lower-level communication pin of the chip; the second detection circuit can convert the voltage fluctuation caused by the second current signal on the second resistor into a second high-low level signal, which characterizes the second data information.

[0010] Optionally, the second detection circuit of the communication module includes a second comparator, the first input terminal of the second comparator being coupled to one end of the second resistor, the second input terminal of the second comparator being coupled to the other end of the second resistor, and the second comparator being able to compare the voltage difference between its first input terminal and its second input terminal with a second deviation voltage to obtain the second high and low level signal.

[0011] Optionally, the second comparator includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a bias resistor, a first current source, a second current source, and a first inverter; the substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled to their respective sources and grounded; the gates of the first NMOS transistor and the second NMOS transistor are coupled and coupled to the drains of the second NMOS transistor and the first PMOS transistor; the drain of the first NMOS transistor is coupled to the drain of the second PMOS transistor and coupled to the gate of the third NMOS transistor; the first PMOS transistor... The gate of the S-channel transistor is the first input terminal of the second comparator, and the gate of the second PMOS transistor is the second input terminal of the second comparator. The substrate of the first PMOS transistor is coupled to the substrate of the second PMOS transistor and is coupled to one end of the first current source and one end of the second current source, respectively, to the power supply voltage terminal. One end of the bias resistor is coupled to the source of the first PMOS transistor, and the other end is coupled to the source of the second PMOS transistor. The other end of the first current source is coupled to one end of the bias resistor. The other end of the second current source is coupled to the drain of the third NMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is the output terminal of the second comparator.

[0012] Optionally, the chip cascade system includes multiple resistors and at least two battery packs connected in series. Each battery pack includes one or more cells connected in series. The battery packs are coupled to the chips in a one-to-one correspondence. The first end of each battery pack is coupled to the ground end of the corresponding chip. The end of each cell in the battery pack that is away from the first end of the battery pack is coupled to a voltage pin of the corresponding chip through one of the multiple resistors. In two adjacent cascaded chips, the voltage pin of the lower-level chip is coupled to the ground pin of the upper-level chip through a third resistor. The first resistor of the lower-level chip, the third resistor, and the second resistor of the upper-level chip form a parallel circuit. The third resistor is one of the multiple resistors.

[0013] Optionally, each chip further includes a detection module and a control module. The detection module is used to detect the charging or discharging parameter information of the cells in the correspondingly coupled battery pack. The communication module of the local chip is used to receive a current signal sent by one of the upstream chip and the downstream chip to obtain data information of the upstream chip and the downstream chip. The control module of the local chip is used to form a high or low level signal representing the data information of the local chip based on the charging or discharging parameter information of the local chip and the data information obtained by the communication module of the local chip. The communication module of the local chip is also used to send a current signal representing the data information of the local chip to the other of the upstream chip and the downstream chip based on the high or low level signal.

[0014] Optionally, the detection module includes: a voltage detection module having a voltage pin, a ground pin, and a first state output terminal and a second state output terminal coupled to the control module; the voltage detection module detects the corresponding coupled battery cell through the voltage pin, wherein: when the battery cell is detected to have a charging overvoltage, the output signal of the first state output terminal is set to a high level and sent to the control module; when the battery cell is detected to have a discharging overvoltage, the output signal of the second state output terminal is set to a high level and sent to the control module; and / or, a temperature detection module for detecting the temperature of the battery cell corresponding to this chip and sending the detection result to the control module.

[0015] Optionally, the chip cascade system further includes a first voltage terminal, a second voltage terminal, a first switching device, and a second switching device. The first terminal of the at least two battery packs connected in series is coupled to the first voltage terminal. The first switching device and the second switching device are sequentially coupled between the second terminal of the at least two battery packs connected in series and the second voltage terminal. The control module of the first-stage chip in the at least two cascaded chips further includes a first output pin and a second output pin. The control terminal of the first switching device is coupled to the first output pin, and the control terminal of the second switching device is coupled to the second output pin. The control module of the first-stage chip is further configured to generate a first control signal based on the data information of the chip and output it through the first output pin to control the first switching device to turn off to prevent discharge or to control the first switching device to turn on to resume discharge. And / or, the control module of the first-stage chip is further configured to generate a second control signal based on the data information of the chip and output it through the second output pin to control the second switching device to turn off to prevent charging or to control the second switching device to turn on to resume charging.

[0016] Optionally, the detection module of the first-stage chip further includes a current detection module, and the chip cascade system further includes a fourth resistor. The current detection module has an input pin, one end of the fourth resistor is coupled to the input pin, and the other end is coupled to the second voltage terminal. The current detection module further includes at least one of the following: a first output terminal, which determines that a discharge overcurrent occurs when the current detection module detects that the voltage of the input pin is greater than a first set voltage, sets the output signal of the first output terminal to a high level, and sends it to the control module; a second output terminal, which determines that a charging overcurrent occurs when the current detection module detects that the voltage of the input pin is less than a second set voltage, sets the output signal of the second output terminal to a high level, and sends it to the control module; a third output terminal, which determines that the second voltage terminal is coupled to a load when the current detection module detects that the voltage of the input pin is greater than a third set voltage, sets the output signal of the third output terminal to a high level, and sends it to the control module; and a fourth output terminal, which determines that the second voltage terminal is coupled to a charger when the current detection module detects that the voltage of the input pin is less than a fourth set voltage, sets the output signal of the fourth output terminal to a high level, and sends it to the control module.

[0017] In the above scheme, one of the upper-level chip and the lower-level chip can convert data information into a current signal and send it to the other of the upper-level chip and the lower-level chip through coupled upper-level communication pins and lower-level communication pins. The other of the upper-level chip and the lower-level chip can obtain data information based on the current signal. In this way, the number of pins can be reduced when cascading chips, the circuit structure can be simplified, and the cost can be reduced. Moreover, adjacent chips can transmit signals to each other, that is, the upper-level chip can transmit signals to the lower-level chip, and the lower-level chip can also transmit signals to the upper-level chip.

[0018] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of an exemplary structure of a chip cascade system provided in this application embodiment;

[0021] Figure 2 for Figure 1 The diagram shows an exemplary structure of a communication module between two adjacent chips in a chip cascade system.

[0022] Figure 3 for Figure 2 A schematic diagram of an exemplary structure of the first comparator of the communication module in the chip cascade system shown;

[0023] Figure 4 For this Figure 2 A schematic diagram of an exemplary structure of the second comparator of the communication module in the chip cascade system shown;

[0024] Figure 5 for Figure 1 A schematic diagram of an exemplary structure of the first-stage chip in the chip cascade system shown;

[0025] Figure 6 for Figure 1 The diagram shows an exemplary structure of a chip located above the first-level chip in a chip cascading system. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that the term "coupled" as used in this text includes both direct connections between two or more circuit objects without any intervening circuit objects, and indirect connections between two or more circuit objects achieved through one or more intervening circuit objects. For example, two circuit objects directly connected to each other are said to be "coupled" to each other. Similarly, two circuit objects connected by one or more intervening circuit objects are also said to be "coupled" to each other. In other words, "coupled" can be a direct electrical connection or an indirect electrical connection, where there are other components in between, such as resistors or capacitors.

[0028] In existing chip cascade systems, in order to achieve communication, each chip has a large number of pins, resulting in a complex circuit structure and high cost. Furthermore, since the two output pins of the upper-level chip can only output information, it can only realize the transmission of information from the upper-level chip to the lower-level chip, but not the transmission of information from the lower-level chip to the upper-level chip.

[0029] In view of this, the present application provides a chip cascading system that uses fewer pins when communicating between two adjacent cascaded chips, which simplifies the circuit structure, helps to reduce costs, and allows adjacent chips to transmit information to each other, that is, the upper-level chip can transmit information to the lower-level chip, and the lower-level chip can also transmit information to the upper-level chip.

[0030] Figure 1 This is an exemplary structural diagram of a chip cascade system provided in an embodiment of this application. Figure 1 As shown, the chip cascade system includes at least two chips cascaded sequentially. Among the two adjacent cascaded chips: at least the lower-level chip includes an upper-level communication pin SCH, and at least the upper-level chip includes a lower-level communication pin SCL. The upper-level communication pin SCH of the lower-level chip is coupled to the lower-level communication pin SCL of the upper-level chip. One of the upper-level chip and the lower-level chip can convert data information into a current signal and send it to the other of the upper-level chip and the lower-level chip through the coupled upper-level communication pin SCH and lower-level communication pin SCL. The other of the upper-level chip and the lower-level chip can obtain data information based on the current signal.

[0031] In other words, the upper-level chip can convert data information into a current signal and send it to the lower-level chip through the coupled upper-level communication pin SCH and lower-level communication pin SCL. The lower-level chip can obtain the data information based on the current signal. Alternatively, the lower-level chip can convert data information into a current signal and send it to the upper-level chip through the coupled upper-level communication pin SCH and lower-level communication pin SCL. The upper-level chip can obtain the data information based on the current signal. In this way, the upper-level chip and the lower-level chip can communicate with each other.

[0032] In the above scheme, one of the upper-level chip and the lower-level chip can convert data information into a current signal and send it to the other of the upper-level chip and the lower-level chip through the coupled upper-level communication pin SCH and lower-level communication pin SCL. The other of the upper-level chip and the lower-level chip can obtain data information based on the current signal. In this way, when two adjacent cascaded chips communicate, each chip only needs to set one pin, which can reduce the number of pins, simplify the circuit structure, and help reduce costs. Moreover, two adjacent cascaded chips can transmit information to each other, that is, the upper-level chip can transmit information to the lower-level chip, and the lower-level chip can also transmit information to the upper-level chip.

[0033] Specifically, in Figure 1 In the chip cascading system, four chips are illustrated, namely IC1, IC2, IC3, and IC4. Among them, IC4 is the top-level chip, and IC1 is the bottom-level chip, i.e., the first-level chip. IC1 can be a different chip from IC2 to IC4, and the other chips IC2 to IC4, except for the first-level chip IC1, can be completely identical chips.

[0034] In one example, such as Figure 1 As shown, chip IC1 can be in an 8-pin package, including three voltage pins V1-V3, a ground pin VSS, an upper-level communication pin SCH, and the input pin VM, first output pin DO, and second output pin CO, which will be described below. IC1 can be, for example, sop8, ssop8, tssop8, or DFN8. Chips IC2 to IC4 can all be in a 6-pin package, each chip including three voltage pins V1-V3, a ground pin VSS, a lower-level communication pin SCL, and an upper-level communication pin SCH. IC2 to IC4 can be, for example, sot23-6 or DFN6.

[0035] The upper-level communication pin SCH of two adjacent cascaded chips is coupled to the lower-level communication pin SCL. For example, the upper-level communication pin SCH of IC1 is coupled to the lower-level communication pin SCL of IC2; the upper-level communication pin SCH of IC2 is coupled to the lower-level communication pin SCL of IC3; and the upper-level communication pin SCH of IC3 is coupled to the lower-level communication pin SCL of IC4.

[0036] The upper-level chip can transmit signals to the upper-level chip's communication pin SCH via its lower-level communication pin SCL, and the lower-level chip can transmit signals to its upper-level chip's communication pin SCH via its lower-level communication pin SCL, thus realizing the four chips IC1, IC2, IC3, and IC4 connected in series. Since IC4 is the uppermost chip, it does not need to transmit information with its upper-level chip; therefore, IC4's SCH pin can be left floating, i.e., not coupled to other nodes. Furthermore, since IC1 is the lowermost chip, it does not need to transmit information with its lower-level chip; therefore, IC1 can include the upper-level communication pin SCH and the input pin VM, but may not include the lower-level communication pin SCL. The voltage of the input pin VM can reflect whether overcurrent discharge, overcurrent charging, whether a load is plugged in, or whether a charger is plugged in, etc., which will be described in detail below.

[0037] Continue to refer to Figure 1 A chip cascade system may include multiple resistors R1-R12 and at least two battery packs connected in series. Each battery pack includes one or more cells connected in series, such as BAT1-BAT3. The battery packs are coupled to the chips in a one-to-one correspondence. Figure 1 The illustrated chip cascade system shows four chips, and therefore the system can include four battery packs, each containing a total of 12 cells BAT1 to BAT12. The first battery pack includes cells BAT1 to BAT3, the second battery pack includes cells BAT4 to BAT6, the third battery pack includes cells BAT7 to BAT9, and the fourth battery pack includes cells BAT10 to BAT12.

[0038] Each battery pack, such as BAT1 to BAT3, has its first terminal coupled to the ground terminal VSS of the corresponding chip. The end of each cell in the battery pack, such as BAT1, furthest from the first terminal of the battery pack, is coupled to a voltage pin, such as V1, of the corresponding chip via one of several resistors R1-R12, such as R1. The voltage pin V3 of the lower-level chip is coupled to the ground pin VSS of the upper-level chip via a third resistor Rn. The third resistor Rn is... Figure 1 One of R3, R6, R9, and R12. For example, the voltage pin V3 of chip IC1 (lower-level chip) is coupled to the ground pin VSS of chip IC2 (upper-level chip) through resistor R3.

[0039] In other words, the voltage pins V1, V2, and V3 of chips IC1, IC2, IC3, and IC4 are each connected to a resistor, with battery cells coupled between adjacent resistors. The ground pin VSS is also coupled to a battery cell between itself and its adjacent resistor. For example, in chip IC1, the ground pin VSS is coupled to one end of battery cell BAT1, which is the first end of battery pack BAT1 to BAT3; the voltage pin V1 of chip IC1 is coupled between battery cells BAT1 and BAT2; the voltage pin V2 of chip IC1 is coupled between battery cells BAT2 and BAT3; and the voltage pin V3 of chip IC1 is coupled to one end of battery cell BAT3, which is the second end of battery pack BAT1 to BAT3.

[0040] like Figure 1 As shown, the cascaded chip system also includes a first voltage terminal VDD, a second voltage terminal VN, a first switching device FET1, and a second switching device FET2. The first terminal (positive terminal) of at least two series-connected battery packs (e.g., cells BAT1-BAT12) is coupled to the first voltage terminal VDD. The first switching device FET1 and the second switching device FET2 are sequentially coupled between the second terminal (negative terminal) of the at least two series-connected battery packs (i.e., cells BAT1-BAT12) and the second voltage terminal VN. Additionally, each chip may include a control module (described below). The control module CTRL of the first-stage chip IC1 in the at least two cascaded chips also includes a first output pin DO and a second output pin CO. The control terminal of the first switching device FET1 is coupled to the first output pin DO, and the control terminal of the second switching device FET2 is coupled to the second output pin CO. In this configuration, the first switching device FET1 can be an NMOS transistor, and the second switching device FET2 can be an NMOS transistor. The drain of the first switching device FET1 and the drain of the second switching device FET2 are coupled together. The substrate of the first switching device FET1 is coupled to the source and to the ground pin VSS of the first-level chip IC1, and its gate is coupled to the first output pin DO. The substrate of the second switching device FET2 is coupled to the source and to the second voltage terminal VN, and its gate is coupled to the second output pin CO.

[0041] The control module CTRL of the first-level chip is also used to generate a first control signal based on the data information of this chip, and output it through the first output pin DO to control the first switching device FET1 to turn off to prevent discharge or control the first switching device FET1 to turn on to restore discharge. In one example, when the control signal received by the first output pin DO is low, the first switching device FET1 is turned off to prevent discharge; when the control signal received by the first output pin DO is high, the first switching device FET1 is turned on to restore discharge.

[0042] The control module CTRL of the first-level chip is also used to generate a second control signal based on the data information of this chip, and output it through the second output pin CO to control the second switching device FET2 to turn off to disable charging or control the second switching device FET2 to turn on to resume charging. In one example, when the control signal received by the second output pin CO is low, the second switching device FET2 is turned off to disable charging; when the control signal received by the second output pin CO is high, the second switching device FET2 is turned on to resume charging.

[0043] Furthermore, when an upper-level chip transmits data information to a lower-level chip, the data information may include first data information, which is data information obtained by the upper-level chip. The first data information may include information detected by the detection module of the upper-level chip (described below), or information received by the upper-level chip from its next-level chip. In this case, the current signal may include a first current signal representing the first data information, which can be sent from the upper-level chip to the lower-level chip. When a lower-level chip transmits data information to an upper-level chip, the data information may include second data information, which is data information obtained by the lower-level chip. The second data information may include information detected by the detection module of the lower-level chip (described below), or information received by the lower-level chip from its next-level chip. In this case, the current signal may include a second current signal representing the second data information, which can be sent from the lower-level chip to the upper-level chip.

[0044] The signals transmitted from the upper-level chip to the upper-level chip's upper-level communication pin SCH via the lower-level communication pin SCL include, but are not limited to, at least one of the following: Overvoltage of the battery cell at this level or above necessitates prohibiting charging; Overvoltage of the battery cell at this level or above necessitates prohibiting discharging; Overvoltage of the battery cell exiting charging at this level or above necessitates re-allowing charging; Overvoltage of the battery cell exiting discharge at this level or above necessitates re-allowing discharging; Overheating of the battery cell at this level or above necessitates prohibiting charging; Overheating of the battery cell exiting discharge at this level or above necessitates allowing charging; Overheating of the battery cell at this level or above necessitates prohibiting discharging; Overheating of the battery cell exiting discharge at this level or above necessitates allowing discharging; Overheating of the battery cell at this level or above necessitates prohibiting charging; Overheating of the battery cell exiting discharge at this level or above necessitates allowing ... prohibiting discharging; Overheating of the battery cell exiting discharge at this level or above necessitates allowing dis

[0045] The signals transmitted by the lower-level chip to the lower-level communication pin SCL of the upper-level chip through the upper-level communication pin SCH include, but are not limited to, at least one of the following: the current level or the lower level detects a coupled load or a coupled charger, etc.

[0046] Figure 2 for Figure 1 This is a schematic diagram illustrating an exemplary structure of a communication module between adjacent chips in a chip cascade system. Figure 2 As shown, adjacent chip levels include an upper-level chip and a lower-level chip, each chip including a communication module Comm. The circuit within the rectangle formed by the dotted lines above represents an exemplary implementation of the Comm communication module of the upper-level chip; the circuit within the rectangle formed by the dotted lines below represents an exemplary implementation of the Comm communication module of the lower-level chip. Figure 2 In this context, the communication module Comm of the upper-level chip has the same circuit structure as the communication module Comm of the lower-level chip.

[0047] Each chip's communication module Comm may include a lower-level communication unit TL and / or a higher-level communication unit TH. That is, the chip's communication module may have, but is not limited to, the following three schemes: Scheme 1, the chip's communication module may only include the lower-level communication unit TL; Scheme 2, the chip's communication module may only include the higher-level communication unit TH; Scheme 3, the chip's communication module may include both the lower-level communication unit TL and the higher-level communication unit TH.

[0048] Specifically, the lower-level communication unit TL in the upper-level chip can send a first current signal to the lower-level chip and / or receive a second current signal sent by the lower-level chip, and obtain second data information based on the second current signal. The upper-level communication unit TH in the lower-level chip can send a second current signal to the upper-level chip and / or receive a first current signal sent by the upper-level chip, and obtain first data information based on the first current signal.

[0049] In one example, a chip cascade system may consist of only two chips: an upper-level chip and a lower-level chip. The communication module of the upper-level chip may consist only of the lower-level communication unit TL, and the communication module of the lower-level chip may consist only of the upper-level communication unit TH. The upper-level and lower-level chips can transmit information to each other through the lower-level communication unit TL and the upper-level communication unit TH. Furthermore, since the first-level chip does not need to communicate with its next-level chip, its communication module may consist only of the upper-level communication unit TH, without the lower-level communication unit TL. Similarly, since the top-level chip does not need to communicate with its previous-level chip, its communication module may consist only of the lower-level communication unit TL, without the upper-level communication unit TH.

[0050] In some designs, to standardize the design modules, each chip can have the same structure. Therefore, each chip can simultaneously include a lower-level communication unit (TL) and a higher-level communication unit (TH). This article mainly focuses on an example where a chip simultaneously includes both a lower-level communication unit (TL) and a higher-level communication unit (TH).

[0051] Continue to refer to Figure 2 Each chip may include a voltage pin V3. The lower-level communication unit TL of the communication module includes a first switch SL1 and a lower-level current source IL1. One end of the first switch SL1 is coupled to the lower-level communication pin SCL of this chip. For example, one end of the first switch SL1 may be coupled to the first node VA of this chip, and the first node VA of this chip is coupled to the lower-level communication pin SCL of this chip. One end of the lower-level current source IL1 is coupled to the other end of the first switch SL1, and the other end of the lower-level current source IL1 is coupled to the voltage pin V3 of this chip. The first switch SL1 is used to receive a first high / low level signal representing first data information, and to turn on and off according to the first high / low level signal, so that the lower-level current source IL1 provides a first current signal to the first node VA.

[0052] The upper-level communication unit TH of the communication module includes a first detection circuit (the first comparator Comp1, which will be described below) and a first resistor RV1. One end of the first resistor RV1 is coupled to the upper-level communication pin SCH of this chip. In one example, one end of the first resistor RV1 can be coupled to the second node VB of this chip, and the second node VB of this chip is coupled to the upper-level communication pin SCH of this chip. The other end of the first resistor RV1 is coupled to the voltage pin V3 of this chip. The first resistor RV1 can receive the first current signal sent by the upper-level chip through the upper-level communication pin SCH of this chip. The first detection circuit can convert the voltage fluctuation caused by the first current signal on the first resistor RV1 into a first high / low level signal, which can represent the first data information.

[0053] Specifically, the first high / low level signal can control the on / off state of the first switch SL1, causing voltage fluctuations across the first resistor RV1. When the first switch SL1 is on, current flows through the first resistor RV1, resulting in a high level; when the first switch SL1 is off, no current flows through the first resistor RV1, resulting in a low level. Furthermore, the first detection circuit of the communication module may include a first comparator Comp1. The first input terminal of the first comparator Comp1 is coupled to one end of the first resistor RV1, and the second input terminal of the first comparator Comp1 is coupled to the other end of the first resistor RV1. The first comparator Comp1 can compare the voltage difference between its first and second input terminals with a first deviation voltage to obtain the first high / low level signal. The first deviation voltage is a built-in deviation voltage of the comparator and can be preset.

[0054] Additionally, each chip may include a ground pin VSS. The upper-level communication unit TH of the communication module includes a second switch SH1 and an upper-level current source IH1. One end of the second switch SH1 is coupled to the upper-level communication pin SCH of this chip. For example, one end of the second switch SH1 may be coupled to the second node VB of this chip, and the second node VB of this chip is coupled to the upper-level communication pin SCH of this chip. One end of the upper-level current source IH1 is coupled to the other end of the second switch SH1, and the other end of the upper-level current source IH1 is coupled to the lower-level communication pin SCL / first node VA of this chip. The second switch SH1 can receive a second high-low level signal representing the second data information and turn on and off according to the second high-low level signal, so that the upper-level current source IH1 provides a second current signal to the second node VB.

[0055] The lower-level communication unit TL of the communication module may include a second detection circuit (the second comparator Comp2, which will be described below) and a second resistor RG1. One end of the second resistor RG1 is coupled to the lower-level communication pin SCL / first node VA of this chip, and the other end is coupled to the ground pin VSS of this chip. The second resistor RG1 can receive the second current signal sent by the next-level chip through the lower-level communication pin SCL of this chip. The second detection circuit can convert the voltage fluctuation caused by the second current signal on the second resistor RG1 into a second high-low level signal. The second high-low level signal can characterize the second data information.

[0056] Specifically, the second high / low level signal can control the on / off state of the second switch SH1, causing voltage fluctuations across the second resistor RG1. When the second switch SH1 is on, current flows through the second resistor RG1, resulting in a high level; when the second switch SH1 is off, no current flows through the second resistor RG1, resulting in a low level. Furthermore, the second detection circuit of the communication module may include a second comparator Comp2. The first input terminal of the second comparator Comp2 is coupled to one end of the second resistor RG1, and the second input terminal of the second comparator Comp2 is coupled to the other end of the second resistor RG1. The second comparator Comp2 can compare the voltage difference between its first and second input terminals with a second deviation voltage to obtain the second high / low level signal. The second deviation voltage is a built-in deviation voltage of the comparator and can be preset.

[0057] In other words, the communication module between the upper-level chip and the lower-level chip can have, but is not limited to, the following three situations:

[0058] The first scenario involves the upper-level chip sending information to the lower-level chip. The lower-level communication unit TL of the upper-level chip's communication module may only include the first switch SL1 and the lower-level current source IL1, without the need for the second detection circuit (such as the second comparator Comp2) and the second resistor RG1. Similarly, the upper-level communication unit TH of the lower-level chip's communication module may only include the first detection circuit (such as the first comparator Comp1) and the first resistor RV1, without the need for the second switch SH1 and the upper-level current source IH1.

[0059] The second scenario involves a lower-level chip needing to send information to an upper-level chip. The upper-level communication unit TH of the lower-level chip's communication module may only include the second switch SH1 and the upper-level current source IH1, without needing the first detection circuit (such as the first comparator Comp1) and the first resistor RV1. Similarly, the lower-level communication unit TL of the upper-level chip's communication module may only include the second detection circuit (such as the second comparator Comp2) and the second resistor RG1, without needing the first switch SL1 and the lower-level current source IL1.

[0060] The third scenario involves the need for the upper-level chip and the lower-level chip to be able to send information to each other at different times. For example... Figure 2 As shown, the lower-level communication unit TL of the communication module of the upper-level chip may include a first switch SL1, a lower-level current source IL1, a second detection circuit (such as a second comparator Comp2), and a second resistor RG1. The upper-level communication unit TH of the communication module of the lower-level chip may simultaneously include a first detection circuit (such as a first comparator Comp1), a first resistor RV1, a second switch SH1, and an upper-level current source IH1.

[0061] It is understood that in other embodiments of this application, the first resistor RV1 and the second resistor RG1 may not form a parallel circuit. In the third case described above, the first resistor RV1 and the third resistor Rn of the lower-level chip and the second resistor RG1 of the upper-level chip may form a parallel circuit.

[0062] Specifically, with Figure 2 Taking the communication module Comm of the upper-level chip as an example, this communication module Comm includes resistors RV1 and RG1, switches SH1 and SL1, current source IH1, and current source IL1. The resistor RG1 of the upper-level chip, along with the series resistor Rn (located outside the chip), and the resistor RV1 of the lower-level chip, can be connected in parallel between node VA (or node VB) and node Cell. The third resistor Rn is... Figure 1 One of the resistors R3, R6, R9, and R12 shown. For example, if... Figure 2 If the two adjacent chips in the process are IC1 and IC2, then Rn is R3.

[0063] When an upper-level chip needs to transmit information to a lower-level chip, the lower-level chip's control module CTRL receives the relevant information from the upper-level chip and controls the LD to output a pulse signal of a certain period, i.e., the first high and low level signal. When the pulse signal is high, switch SL1 is turned on, and current IL1 is split into two paths: one flows through resistor RG1 of the upper-level chip, and the other flows through resistor Rn and resistor RV1 of the lower-level chip. For example, RG1 and RV1 are designed to be 200K ohms, and currents IL1 and IH1 are 2 microamps. Rn is usually relatively small compared to RG1 and RV1, for example, 100 ohms to 1K ohms, so Rn can be basically ignored in calculations. RG1 and RV1 are connected in parallel, and the equivalent resistance becomes 100K ohms. IL1 flows through this 100K ohm, generating a voltage of 0.2V, that is, the voltage at node VA is 0.2V higher than the voltage at node Cell. Since VA (located in the upper-level chip) and VB (located in the lower-level chip) are shorted together by a metal wire, the voltage of VB is equal to the voltage of VA.

[0064] A typical comparator compares the voltages at its positive and negative input terminals and outputs the comparison result. Figure 2The difference between Comp1 in this chip and a regular comparator is that Comp1 compares the voltage difference between the positive and negative input terminals with the comparator's built-in bias voltage (which can be preset). Specifically, the positive input terminal of Comp1 in the lower-level chip is connected to node VB, and the negative input terminal is connected to voltage pin V3. Since the resistance Rn is small and negligible, V3 is approximately equal to VSS, so the negative input terminal can be considered to be connected to VSS. The lower-level chip can compare the voltage difference VB-VSS (i.e., VB voltage minus VSS voltage, where VSS is the voltage of node Cell) with the comparator's built-in bias voltage (for example, it can be designed to be 0.1V) through Comp1.

[0065] If the voltage difference VB-VSS is greater than 0.1V, the DOH pin of the communication module Comm outputs a high level to the control module CTRL. When LD is a periodic pulse signal, the control switch SL1 is periodically turned on to generate a periodic pulse current, which causes the generated voltage difference VB-VSS to also have periodic fluctuations with an amplitude of 0 to 0.2V. Therefore, the output of comparator Comp1 in the lower-level chip is a periodic pulse signal (and the frequency and phase are consistent with the LD signal in the upper-level chip). The control module CTRL of the lower-level chip can obtain the first high and low level signals based on the comparison result output by comparator Comp1. This realizes the function of transmitting signals from the upper-level chip to the lower-level chip.

[0066] When a lower-level chip needs to transmit information to a higher-level chip, such as Figure 2 As shown, the HD signal generated by the control module CTRL in the lower-level chip is a periodic pulse signal, i.e., the second high and low level signal. When HD is high, the control switch SH1 is turned on, and the current IH1 flows through resistors RG1, RV1, and Rn. The resistance value of resistor Rn is relatively small, so it can be ignored in the calculation. For example, RG1 and RV1 are both 200K ohms, and the current IH1 is 2 microamps. This forms a voltage difference VSS-VA (i.e., the VSS node voltage minus the node VA voltage. The VSS voltage is also equal to the node Cell voltage, and the node VA voltage is also equal to the VB node voltage). The comparator Comp2 also has a built-in deviation voltage. When the voltage difference VSS-VA is greater than the built-in deviation voltage of the comparator Comp2, the output DOL of the comparator Comp2 becomes high; when the voltage difference VSS-VA is less than the built-in deviation voltage of the comparator Comp2, the output DOL of the comparator Comp2 becomes low.

[0067] When HD is a periodic pulse signal, the control switch SH1 is periodically turned on to generate a periodic pulse current, which causes the generated voltage difference VSS-VA to also have periodic fluctuations with an amplitude of 0 to 0.2V. Therefore, the output of comparator Comp2 in the upper-level chip is a periodic pulse signal (and the frequency and phase are consistent with the HD signal in the lower-level chip). The control module CTRL of the upper-level chip can obtain the second high and low level signals based on the comparison result output by comparator Comp2. In this way, the function of transmitting signals from the lower-level chip to the upper-level chip is realized.

[0068] Figure 3 for Figure 2 This is a schematic diagram of an exemplary structure of the first comparator of the communication module in the chip cascade system shown. Figure 3 As shown, optionally, the first comparator includes a first PMOS transistor (MPC1), a second PMOS transistor (MPC2), a third PMOS transistor (MPC3), a first NMOS transistor (MNC1), a second NMOS transistor (MNC2), a bias resistor Ros, a first current source I1, a second current source I2, and a first inverter INV1; the substrates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are coupled to their respective sources and to the power supply voltage terminal VCC; the gates of the first PMOS transistor and the second PMOS transistor are coupled to the drains of the first PMOS transistor and the first NMOS transistor; the drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor and to the gate of the third PMOS transistor; the first N... The gate of the MOS transistor is the first input terminal of the first comparator Comp1, such as the positive input terminal V+. The gate of the second NMOS transistor is the second input terminal of the first comparator Comp1, such as the negative input terminal V-. The substrates of the first NMOS transistor and the second NMOS transistor are coupled together and grounded at one end of the first current source I1 and the second current source I2 respectively. One end of the bias resistor Ros is coupled to the source of the first NMOS transistor and the other end is coupled to the source of the second NMOS transistor. The other end of the first current source is coupled to the other end of the bias resistor Ros. The drain of the third PMOS transistor and the other end of the second current source are coupled to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 is the output terminal OUT of the first comparator Comp1.

[0069] exist Figure 3In this configuration, due to the relatively high input signal, an NMOS transistor is required as the differential input pair, consisting of MNC1 and MNC2. Additionally, a bias resistor Ros assists in generating a bias voltage, equal to Ros·I1 / 2, where Ros is the resistance of the bias resistor Ros and I1 is the current of the current source I1. In one example, the bias voltage can be designed to be 0.1V. If we ignore the bias resistor Ros, assuming its resistance is zero, the first comparator Comp1 compares the voltages at its positive input V+ and negative input V-. If the voltage at the positive input V+ is higher than the voltage at the negative input V-, then MNC1 will receive more current than MNC2 (dividing the current of I1, since the sum of the drain currents of MNC1 and MNC2 equals the current of I1). Therefore, the current of MPC1 is greater than the current of MNC2 (because the drain current of MPC1 is equal to the drain current of MNC1). MPC2 replicates the current of MPC1, so the drain current of MPC2 is greater than the drain current of MNC2. Consequently, the gate voltage of MPC3 becomes higher (making the drain current of MPC3 lower than the current of I2), causing the input of inverter INV1 to become lower, and thus the output OUT of inverter INV1 becomes higher. This indicates that V+ is the positive input. This is the basic principle of a comparator. Adding the bias resistor Ros causes an asymmetry between the V+ and V- inputs. This is equivalent to generating an input bias voltage. At the flip point of the output OUT of the first comparator Comp1, the current of MNC1 equals the current of MNC2. Therefore, the drain current of both MNC1 and MNC2 is equal to I1 / 2. This current flows through the bias resistor Ros, generating a voltage drop of Ros·(I1 / 2) across Ros. For MNC1 and MNC2, their source voltages are not equal, and the difference is Ros·(I1 / 2). If the currents of MNC1 and MNC2 are to be equal, then the V+ voltage needs to be higher than the V- voltage by Ros·(I1 / 2). Equivalently, the output OUT of the first comparator Comp1 flips when the difference between the V+ and V- voltages is greater than or equal to Ros·(I1 / 2).

[0070] Figure 4 For this Figure 2 This is a schematic diagram of an exemplary structure of the second comparator in the communication module of the chip cascade system shown. Figure 4As shown, optionally, the second comparator includes a first PMOS transistor (MPC1), a second PMOS transistor (MPC2), a first NMOS transistor (MNC1), a second NMOS transistor (MNC2), a third NMOS transistor (MNC3), a bias resistor Ros, a first current source I1, a second current source I1, and a first inverter INV1; the substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled to their respective sources and grounded; the gates of the first NMOS transistor and the second NMOS transistor are coupled to the drains of the second NMOS transistor and the first PMOS transistor; the drain of the first NMOS transistor is coupled to the drain of the second PMOS transistor and to the gate of the third NMOS transistor. The gate of the first PMOS transistor is the first input terminal of the second comparator Comp2, such as the positive input terminal V+. The gate of the second PMOS transistor is the second input terminal of the second comparator Comp2, such as the negative input terminal V-. The substrates of the first and second PMOS transistors are coupled together and are coupled to one end of each of the first and second current sources to the power supply voltage terminal. One end of the bias resistor is coupled to the source of the first PMOS transistor and the other end is coupled to the source of the second PMOS transistor. The other end of the first current source is coupled to one end of the bias resistor. The other end of the second current source is coupled to the drain of the third NMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is the output terminal OUT of the second comparator Comp2.

[0071] exist Figure 4In this configuration, due to the relatively low input signal, a PMOS transistor is required as the differential input pair, consisting of MPC1 and MPC2. Additionally, a bias resistor Ros assists in generating a bias voltage, the value of which is equal to Ros·I1 / 2, where Ros is the resistance of the bias resistor Ros and I1 is the current of the current source I1. In one example, the bias voltage can be designed to be 0.1V. If we ignore the bias resistor Ros, assuming its resistance is zero, the second comparator Comp2 compares the voltages at the positive input terminal V+ and the negative input terminal V-. If the V+ voltage is higher than the V- voltage, MPC1 will draw less current than MPC2 (dividing the current of I1, since the sum of the drain currents of MPC1 and MPC2 equals the current of I1). Therefore, the current of MNC2 is less than the current of MPC2 (because the drain current of MPC1 is equal to the drain current of MNC2). MNC1 replicates the current of MNC2, so the drain current of MPC2 is greater than the drain current of MNC1. Consequently, the gate voltage of MNC3 becomes higher (making the drain current of MNC3 greater than the current of I2), causing the input of inverter INV1 to become lower, and thus the output OUT of inverter INV1 becomes higher. This indicates that V+ is the positive input terminal. This is the basic principle of a comparator. Adding the bias resistor Ros causes an asymmetry between the V+ and V- inputs, effectively creating an input bias voltage. At the toggle point of the output OUT of the second comparator Comp2, the current of MPC1 equals the current of MPC2. Therefore, the drain current of both MPC1 and MPC2 is equal to I1 / 2. This current flows through the bias resistor Ros, creating a voltage drop of Ros·(I1 / 2) across Ros. For MPC1 and MPC2, their source voltages are not equal, with a difference of Ros·(I1 / 2). If the currents of MPC1 and MPC2 are to be equal, the V+ voltage must be Ros·(I1 / 2) higher than the V- voltage. Equivalently, the output OUT of the second comparator Comp2 toggles when the difference between the V+ and V- voltages is greater than or equal to Ros·(I1 / 2).

[0072] Figure 5 for Figure 1 The diagram shows an exemplary structure of the first-stage chip in a chip cascade system. Figure 6 for Figure 1 The diagram illustrates an exemplary structure of a chip located above the first-stage chip in a chip cascading system. Figure 6 The chip shown can be Figure 1 This illustrates an exemplary implementation of one of chips IC2 to IC4 in the chip cascade system shown. For example... Figure 5 and Figure 6As shown, each chip, in addition to the communication module Comm, may also include a detection module (such as the voltage detection module VDet and temperature detection module TDet, which will be introduced below) and a control module CTRL. The detection module is used to detect the charging or discharging parameter information of the cells in the corresponding coupled battery pack; the communication module Comm of this level chip is used to receive the current signal sent by one of the upper-level chip and the lower-level chip to obtain the data information of one of the upper-level chip and the lower-level chip; the control module CTRL of this level chip is used to form a high or low level signal representing the data information of this level chip based on the charging or discharging parameter information of this level chip and the data information obtained by the communication module Comm of this level chip; the communication module Comm of this level chip is also used to send a current signal representing the data information of this level chip to the other of the upper-level chip and the lower-level chip based on the high or low level signal.

[0073] like Figure 5 As shown, chip IC1 may include a voltage detection module VDet, a current detection module IDet, a temperature detection module TDet, a communication module Comm, and a control module CTRL, and has a total of 8 pins, namely VSS, V1, V2, V3, VM, DO, CO, and SCH.

[0074] The voltage detection module VDet has voltage pins V1, V2, and V3, a ground pin VSS, and a first state output terminal VOC and a second state output terminal VOD coupled to the control module CTRL. The voltage detection module VDet can detect the voltage of three battery cells BAT1, BAT2, and BAT3, which are respectively coupled to voltage pins V1, V2, and V3. Specifically, the voltage detection module VDet detects the voltage of the corresponding coupled battery cells through the voltage pins. If one of them experiences charging overvoltage, the output signal of the first state output terminal VOC is set to a high level and sent to the control module CTRL; if one of them experiences discharging overvoltage, the output signal of the second state output terminal VOD is set to a high level and sent to the control module CTRL. The temperature detection module TDet detects the temperature of at least one of the three battery cells BAT1, BAT2, and BAT3 and sends the resulting digital signal TD to the control module CTRL.

[0075] The current sensing module IDet also includes at least one of a first output terminal EDI, a second output terminal ECI, a third output terminal Load, and a fourth output terminal CHG. The current sensing module IDet determines whether a discharge overcurrent or charging overcurrent has occurred, and whether a load or charger is plugged into the second voltage terminal VN, by detecting the voltage at pin VM. When the current sensing module IDet detects a discharge overcurrent, for example, if the voltage at input pin VM is greater than a first set voltage such as +200mV, it determines that a discharge overcurrent has occurred, sets the output signal of the first output terminal EDI to a high level, and sends the high-level signal to the control module CTRL. When the current sensing module IDet detects a charging overcurrent, for example, if the voltage at input pin VM is less than a second set voltage such as -200mV, it determines that a charging overcurrent has occurred, sets the output signal of the second output terminal ECI to a high level, and sends the high-level signal to the control module CTRL. When the current sensing module IDet detects an inserted load, for example, if the voltage at input pin VM is greater than a third set voltage such as +50mV, it determines that the second voltage terminal VN is coupled to a load. It then sets the output signal at the third output terminal Load to a high level and sends this high-level signal to the control module CTRL. Conversely, when the current sensing module IDet detects an inserted charger, for example, if the voltage at input pin VM is less than a fourth set voltage such as -50mV, it determines that the second voltage terminal VN is coupled to a charger. It then sets the output signal at the fourth output terminal CHG to a high level and sends this high-level signal to the control module CTRL. The control module CTRL can output high and low level signals (for overcurrent discharge, overcurrent charging, and charger or load connection) to the communication module Comm via the output terminal HD. This information can then be transmitted to the next higher-level chip via the upper-level communication pin SCH.

[0076] Continue to refer to Figure 5 The communication module Comm generates DOH and DOL signals by communicating with chips at other levels. When a higher-level chip transmits a signal to this chip, DOH is generated and output to the control module CTRL; when a lower-level chip transmits a signal to this chip, DOL is generated and output to the control module CTRL. Since IC1 is the lowest-level chip, the SCL of the communication module Comm does not need to be coupled and is in a floating state (without any signal connected). Therefore, it will not generate a useful DOL signal. This part of the circuit can be removed or simplified. Of course, in many designs, it can be retained for the purpose of design module standardization, but these signals remain unchanged, for example, they are kept at a low level.

[0077] The control module CTRL can generate periodic pulse signals LD (such as the first high / low level signal) and periodic pulse signals HD (such as the second high / low level signal) based on the detection results of the detection module, and output them to the communication module Comm.

[0078] In addition, the control module CTRL can generate status control signals CO and DO based on the DOH, DOL, VOC, VOD, EDI, ECI, Load, CHG, and TD signals. Each signal is an output signal from a corresponding output terminal; for example, the VOC signal is the signal output from the first state output terminal, and the VOD signal is the signal output from the second state output terminal. When the VOC signal goes high (indicating that the chip has detected charging overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected charging overvoltage in the upper-level cell, the CO signal is set low to prevent charging. When the VOD signal goes high (indicating that the chip has detected discharging overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected discharging overvoltage in the upper-level cell, the DO signal is set low to prevent discharging. When the EDI signal goes high (indicating that the chip has detected discharging overcurrent), the DO signal is set low to prevent discharging. When the ECI signal goes high (indicating that the chip has detected charging overcurrent), the DO signal is set low to prevent discharging. When the VOC signal goes low (indicating that this chip has detected an overvoltage discharge in the corresponding cell) or the DOH signal contains information indicating that an upstream chip has detected an overvoltage discharge in the upstream cell, the CO signal is set high to resume charging. When the VOD signal goes low (indicating that this chip has detected an overvoltage discharge in the corresponding cell) or the DOH signal contains information indicating that an upstream chip has detected an overvoltage discharge in the upstream cell, the DO signal is set high to resume discharging. When the EDI signal goes low (indicating that this chip has detected an overcurrent discharge), the DO signal is set high to resume discharging. When the ECI signal goes low (indicating that this chip has detected an overcurrent discharge), the DO signal is set high to resume discharging.

[0079] like Figure 1 and Figure 5 As shown, the chip cascade system also includes a fourth resistor Rm. The current sensing module IDet has an input pin VM. One end of the fourth resistor Rm is coupled to the input pin VM, and the other end is coupled to the second voltage terminal VN. The fourth resistor Rm prevents the chip from burning out if the charger is connected in reverse.

[0080] Since the battery packs corresponding to each level of chips are connected in series, the current in the cells coupled to each chip is equal. Therefore, only the first-level chip IC1 needs to include a current detection module IDet to detect the current in the circuit. The other higher-level chips, such as IC2 to IC4, do not need to include a current detection module IDet. Therefore, as... Figure 6 As shown, in one of the higher-level chips (IC2-IC4) besides the first-level chip IC1, the chip may include a voltage detection module VDet, a temperature detection module TDet, a communication module Comm, and a control module CTRL, with a total of 6 pins: VSS, V1, V2, V3, SCH, and SCL. The functions of the voltage detection module VDet, the temperature detection module TDet, the communication module Comm, and the control module CTRL are similar to those of the corresponding modules in chip IC1. For example, in... Figure 6 In this circuit, the temperature detection module TDet detects the temperature of the battery cell coupled to the corresponding chip and sends the detection result, such as a digital signal TD, to the control module CTRL. The communication module Comm can communicate with its upstream chip via its upstream communication pin SCH, allowing it to receive and send information to the upstream chip. The communication module Comm can also communicate with its downstream chip via its downstream communication pin SCL, allowing it to receive and send information to the downstream chip.

[0081] in addition, Figure 6 The control module CTRL in the chip shown may not include the first output pin DO and the second output pin CO. The control module CTRL can generate HD and LD signals based on the DOH, DOL, VOC, VOD, and TD signals, and send them to the communication module Comm. The communication module Comm can communicate with the previous level chip through its upper-level communication pin SCH or with the next level chip through its lower-level communication pin SCL.

[0082] When the VOC signal goes high (indicating that this chip has detected overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected overvoltage in the upper-level cell, the overvoltage information is sent to the communication module Comm via the control signal LD, and then transmitted to the next-level chip via the lower-level communication pin SCL. When the VOD signal goes high (indicating that this chip has detected overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected overvoltage in all the upper-level cells, the overvoltage information is sent to the communication module Comm via the control signal LD, and then transmitted to the next-level chip via the lower-level communication pin SCL.

[0083] When the VOC signal goes low (indicating that this chip has detected a discharge overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected a discharge overvoltage in all cells of the upper-level chip, the discharge overvoltage information is sent to the communication module Comm via the control signal LD, and then transmitted to the next-level chip via the lower-level communication pin SCL. When the VOD signal goes low (indicating that this chip has detected a discharge overvoltage in the corresponding cell) or the DOH signal contains information indicating that the upper-level chip has detected a discharge overvoltage in all cells of the upper-level chip, the discharge overvoltage information is sent to the communication module Comm via the signal LD, and then transmitted to the next-level chip via the lower-level communication pin SCL.

[0084] Information from the previous level chip can be sent to the control module CTRL via the chip's DOH pin; information from the next level chip can be sent to the control module CTRL via the chip's DOL pin. The control module CTRL sends information such as whether a charger or load can be connected to it to the communication module Comm via its HD pin, and then transmits it to the next level chip via the higher-level communication pin SCH.

[0085] In summary, in this application, one of the upper-level chip and the lower-level chip can convert data information into a current signal and send it to the other of the upper-level chip and the lower-level chip through coupled upper-level communication pins and lower-level communication pins. The other of the upper-level chip and the lower-level chip can obtain data information based on the current signal. This reduces the number of pins when cascading chips, simplifies the circuit structure, and helps to reduce costs. Furthermore, adjacent chips can transmit signals to each other, that is, the upper-level chip can transmit signals to the lower-level chip, and the lower-level chip can also transmit signals to the upper-level chip.

[0086] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0087] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip cascade system, characterized in that, Including at least two chips cascaded in sequence, and two adjacent cascaded chips: At least one lower-level chip includes an upper-level communication pin, and at least one upper-level chip includes a lower-level communication pin; the upper-level communication pin of the lower-level chip is coupled to the lower-level communication pin of the upper-level chip; one of the upper-level chip and the lower-level chip can convert data information into a current signal and transmit it to the other of the upper-level chip and the lower-level chip through the coupled upper-level communication pin and the lower-level communication pin; the other of the upper-level chip and the lower-level chip can obtain the data information based on the current signal; each chip includes a voltage pin and a ground pin; in two adjacent cascaded chips, the lower-level chip includes a first resistor, one end of which is coupled to the upper-level communication pin of the lower-level chip, and the other end of which is coupled to the voltage pin of the lower-level chip; The upper-level chip includes a second resistor, one end of which is coupled to the lower-level communication pin of the upper-level chip, and the other end is coupled to the ground pin of the upper-level chip. The chip cascade system also includes multiple resistors and at least two battery packs connected in series. Each battery pack includes one or more cells connected in series. The battery packs are coupled to the chips in a one-to-one correspondence. The first end of the battery pack is coupled to the ground end of the corresponding chip. The end of each cell in the battery pack that is away from the first end of the battery pack is coupled to a voltage pin of the corresponding chip through one of the multiple resistors. In two adjacent cascaded chips, the voltage pin of the lower-level chip is coupled to the ground pin of the upper-level chip through a third resistor. The first resistor of the lower-level chip, the third resistor, and the second resistor of the upper-level chip form a parallel circuit. The third resistor is one of the multiple resistors. At least when the upper-level chip transmits data information to the lower-level chip, the current signal is split into two paths via the parallel circuit. One path flows through the second resistor of the upper-level chip, and the other path flows through the third resistor and the first resistor of the lower-level chip in sequence. A voltage fluctuation caused by a current signal is generated on the first resistor of the lower-level chip, enabling the lower-level chip to obtain data information based on the voltage fluctuation.

2. The chip cascade system according to claim 1, characterized in that, When the upper-level chip transmits the data information to the lower-level chip, the data information includes first data information, and the current signal includes a first current signal characterizing the first data information; Alternatively, when the lower-level chip transmits the data information to the upper-level chip, the data information includes second data information, and the current signal includes a second current signal characterizing the second data information; each chip includes a communication module, wherein: The communication module includes a lower-level communication unit. The lower-level communication unit in the upper-level chip can send the first current signal to the lower-level chip and / or receive the second current signal sent by the lower-level chip and obtain the second data information based on the second current signal. And / or, The communication module includes an upper-level communication unit. The upper-level communication unit in the lower-level chip can send the second current signal to the upper-level chip and / or receive the first current signal sent by the upper-level chip and obtain the first data information based on the first current signal.

3. The chip cascade system according to claim 2, characterized in that, Each chip includes voltage pins, where: The lower-level communication unit of the communication module includes a first switch and a lower-level current source. One end of the first switch is coupled to a lower-level communication pin of the chip, and one end of the lower-level current source is coupled to the other end of the first switch. The other end of the lower-level current source is coupled to a voltage pin of the chip. The first switch is used to receive a first high-low level signal representing the first data information, and to turn on and off according to the first high-low level signal, so that the lower-level current source provides the first current signal to the lower-level communication pin of the chip; and / or, The first resistor can receive the first current signal sent by the previous level chip through the upper level communication pin of the chip. The first detection circuit can convert the voltage fluctuation caused by the first current signal on the first resistor into a first high-low level signal. The first high-low level signal can characterize the first data information.

4. The chip cascade system according to claim 3, characterized in that, The first detection circuit of the communication module includes a first comparator. The first input terminal of the first comparator is coupled to one end of the first resistor, and the second input terminal of the first comparator is coupled to the other end of the first resistor. The first comparator can compare the voltage difference between its first input terminal and its second input terminal with a first deviation voltage to obtain the first high and low level signals.

5. The chip cascade system according to claim 4, characterized in that, The first comparator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a bias resistor, a first current source, a second current source, and a first inverter; The substrates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are coupled to their respective sources and to the power supply voltage terminal. The gates of the first PMOS transistor and the second PMOS transistor are coupled to the drains of the first PMOS transistor and the first NMOS transistor. The drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor and to the gate of the third PMOS transistor. The gate of the first NMOS transistor is the first input terminal of the first comparator, the gate of the second NMOS transistor is the second input terminal of the first comparator, the substrate of the first NMOS transistor is coupled to the substrate of the second NMOS transistor and grounded at one end of the first current source and the second current source respectively, one end of the bias resistor is coupled to the source of the first NMOS transistor and the other end is coupled to the source of the second NMOS transistor, and the other end of the first current source is coupled to the other end of the bias resistor; The drain of the third PMOS transistor and the other end of the second current source are coupled to the input terminal of the first inverter, and the output terminal of the first inverter is the output terminal of the first comparator.

6. The chip cascade system according to claim 2, characterized in that, Each chip includes a ground pin, in which: The upper-level communication unit of the communication module includes a second switch and an upper-level current source. One end of the second switch is coupled to the upper-level communication pin of the current-level chip, and one end of the upper-level current source is coupled to the other end of the second switch. The other end of the upper-level current source is coupled to the lower-level communication pin of the current-level chip. The second switch can receive a second high-low level signal representing the second data information and turn on and off according to the second high-low level signal, so that the upper-level current source provides the second current signal to the upper-level communication pin of the current-level chip; and / or, The second resistor can receive the second current signal sent by the next-level chip through the lower-level communication pin of the chip. The second detection circuit can convert the voltage fluctuation caused by the second current signal on the second resistor into a second high-low level signal. The second high-low level signal can characterize the second data information.

7. The chip cascade system according to claim 6, characterized in that, The second detection circuit of the communication module includes a second comparator. The first input terminal of the second comparator is coupled to one end of the second resistor, and the second input terminal of the second comparator is coupled to the other end of the second resistor. The second comparator can compare the voltage difference between its first input terminal and its second input terminal with a second deviation voltage to obtain the second high and low level signal.

8. The chip cascade system according to claim 7, characterized in that, The second comparator includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a bias resistor, a first current source, a second current source, and a first inverter; The substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled to their respective sources and grounded. The gates of the first NMOS transistor and the second NMOS transistor are coupled to each other and to the drains of the second NMOS transistor and the first PMOS transistor. The drain of the first NMOS transistor is coupled to the drain of the second PMOS transistor and to the gate of the third NMOS transistor. The gate of the first PMOS transistor is the first input terminal of the second comparator, and the gate of the second PMOS transistor is the second input terminal of the second comparator. The substrate of the first PMOS transistor is coupled to the substrate of the second PMOS transistor and coupled to one end of the first current source and one end of the second current source, respectively, to the power supply voltage terminal. One end of the bias resistor is coupled to the source of the first PMOS transistor, and the other end is coupled to the source of the second PMOS transistor. The other end of the first current source is coupled to one end of the bias resistor. The other end of the second current source is coupled to the drain of the third NMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is the output terminal of the second comparator.

9. The chip cascade system according to claim 1, characterized in that, Each chip further includes a detection module and a control module. The detection module is used to detect the charging or discharging parameter information of the cells in the correspondingly coupled battery pack. The communication module of this chip is used to receive a current signal sent by one of the previous-level chip and the next-level chip to obtain the data information of the previous-level chip and the next-level chip. The control module of this chip is used to form a high or low level signal representing the data information of this chip based on the charging or discharging parameter information of this chip and the data information obtained by the communication module of this chip. The communication module of this chip is also used to send a current signal representing the data information of this chip to the other of the previous-level chip and the next-level chip based on the high or low level signal.

10. The chip cascade system according to claim 9, characterized in that, The detection module includes: A voltage detection module has a voltage pin, a ground pin, and a first state output terminal and a second state output terminal coupled to the control module. The voltage detection module detects the corresponding coupled battery cell through the voltage pin, wherein: when a charging overvoltage is detected in the battery cell, the output signal of the first state output terminal is set to a high level and sent to the control module; when a discharging overvoltage is detected in the battery cell, the output signal of the second state output terminal is set to a high level and sent to the control module; and / or, The temperature detection module is used to detect the temperature of the battery cell coupled to the chip at this level and send the detection result to the control module.

11. The chip cascade system according to claim 9 or the present invention, characterized in that, The chip cascade system further includes a first voltage terminal, a second voltage terminal, a first switching device, and a second switching device. The first terminals of the at least two series-connected battery packs are coupled to the first voltage terminal. The first switching device and the second switching device are sequentially coupled between the second terminals of the at least two series-connected battery packs and the second voltage terminal. The control module of the first-stage chip in the at least two cascaded chips further includes a first output pin and a second output pin. The control terminal of the first switching device is coupled to the first output pin, and the control terminal of the second switching device is coupled to the second output pin, wherein: The control module of the first-level chip is further configured to generate a first control signal based on the data information of the chip, and output it through the first output pin to control the first switching device to turn off to prevent discharge or control the first switching device to turn on to restore discharge; and / or, The control module of the first-level chip is also used to generate a second control signal based on the data information of the chip and output it through the second output pin to control the second switching device to turn off to prevent charging or control the second switching device to turn on to resume charging.

12. The chip cascade system according to claim 11, characterized in that, The detection module of the first-stage chip further includes a current detection module, and the chip cascade system further includes a fourth resistor. The current detection module has an input pin, one end of the fourth resistor is coupled to the input pin, and the other end is coupled to the second voltage terminal. The current detection module further includes at least one of the following: When the current detection module detects that the voltage of the input pin is greater than the first set voltage, it determines that there is an overcurrent discharge, sets the output signal of the first output terminal to a high level, and sends it to the control module. When the current detection module detects that the voltage of the input pin is less than the second set voltage, it determines that there is an overcurrent in the charging circuit, sets the output signal of the second output terminal to a high level, and sends it to the control module. When the current detection module detects that the voltage of the input pin is greater than the third set voltage, it determines that the second voltage terminal is coupled to the load, sets the output signal of the third output terminal to a high level, and sends it to the control module. The fourth output terminal, when the current detection module detects that the voltage of the input pin is less than the fourth set voltage, determines that the second voltage terminal is coupled to the charger, sets the output signal of the fourth output terminal to a high level, and sends it to the control module.

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