Power-down detection and power-down retention function circuit and electronic device

Abstract

The application discloses a power-off detection and power-off holding function circuit and electronic equipment, and relates to the technical field of power-off detection and power-off holding function circuits. The power-off detection and power-off holding function circuit comprises a power supply output end for connecting a processor, an energy storage circuit connected with the power supply output end, a power-off holding control circuit connected in series between the energy storage circuit and the power supply output end, a controlled end of the power-off holding control circuit connected with the processor, and the power-off holding control circuit used for controlling the connection between the energy storage circuit and the power supply output end to be turned on or turned off. Based on the control of the processor, the electrical connection between the energy storage circuit and the power supply output end is disconnected, so that the energy storage circuit stops supplying power to the processor. The application can solve the problem of wasting energy in the existing power-off storage scheme.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to a circuit and electronic equipment with power-off detection and power-off retention functions. Background Technology

[0002] When the main power supply to an industrial system control product suddenly fails, a backup power supply needs to be activated to provide continuous power for a certain period of time. This is to store relevant data from the power outage and to prevent malfunctions in memory devices such as FLASH memory caused by improper read / write operations during a power outage. Therefore, a system circuit with power outage detection and power supply maintenance functions is required. In existing technologies, some solutions do not perform any control after a power outage, until the backup energy storage equipment is depleted, resulting in energy waste. Summary of the Invention

[0003] The main objective of this invention is to propose a power-loss detection and power-loss retention circuit, which aims to solve the problem of energy waste in existing power-loss storage solutions.

[0004] To achieve the above objectives, the present invention proposes a power-down detection and power-down retention circuit, comprising:

[0005] A power output terminal is used to connect to the processor;

[0006] An energy storage circuit is connected to the power supply output terminal;

[0007] A power-down retention control circuit is connected in series between the energy storage circuit and the power output terminal. The controlled terminal of the power-down retention control circuit is connected to the processor. The power-down retention control circuit is used to control the connection between the energy storage circuit and the power output terminal to be turned on / off.

[0008] Furthermore, based on the control of the processor, the electrical connection between the energy storage circuit and the power output terminal is disconnected, so that the energy storage circuit stops supplying power to the processor.

[0009] Optionally, the power-down detection and power-down retention circuit further includes:

[0010] A power input terminal, which is connected to the power output terminal, is used to connect to an input power source;

[0011] A power conversion circuit has a first output terminal and a second output terminal, an input terminal of the power conversion circuit is connected to a power input terminal, a first output terminal of the power conversion circuit is connected to the input of the power output terminal, and a second output terminal of the power conversion circuit is connected to the input terminal of the energy storage circuit.

[0012] The power conversion circuit is used to convert the input power into a supply voltage and output it from the first output terminal to the power output terminal to power the processor.

[0013] And, it is used to convert the input power supply into a charging voltage and output it from the second output terminal to the energy storage circuit to charge the energy storage circuit.

[0014] Optionally, the power-down detection and power-down retention circuit further includes:

[0015] A power input terminal, which is connected to the power output terminal, is used to connect to an input power source;

[0016] A power detection circuit is provided, wherein the detection terminal of the power detection circuit is connected to the power input terminal, and the output terminal of the power detection circuit is connected to the controlled terminal of the power-down retention control circuit. The power detection circuit is used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit controls the energy storage circuit to be electrically connected to the power output terminal, so that the energy storage circuit supplies power to the processor.

[0017] Optionally, the locking detection terminal of the power detection circuit is connected to the output terminal of the power detection circuit, and the power detection circuit is further used to lock when the power-down retention signal is detected, so as to continuously output the power-down retention signal.

[0018] Optionally, the lock detection terminal of the power detection circuit is also connected to the processor. The power detection circuit is further configured to unlock when it receives a shutdown signal output by the processor, and stop outputting a power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit disconnects the electrical connection between the energy storage circuit and the power output terminal, so that the energy storage circuit stops supplying power to the processor.

[0019] Optionally, the power detection circuit includes:

[0020] A power-down detection circuit is provided, wherein the detection terminal of the power-down detection circuit is connected to the power input terminal, and the output terminal of the power-down detection circuit is connected to the controlled terminal of the power-down retention control circuit. The power-down detection circuit is used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit controls the energy storage circuit to be electrically connected to the power output terminal, so that the energy storage circuit supplies power to the processor.

[0021] A power-down self-locking circuit is provided, wherein the control terminal of the power-down self-locking circuit is connected to the controlled terminal of the power-down detection circuit, and the locking detection terminal of the power-down self-locking circuit is connected to the output terminal of the power-down detection circuit. The power-down self-locking circuit is used to control the power-down detection circuit to continuously output the power-down holding signal when the power-down holding signal is detected.

[0022] Optionally, the output terminal of the power detection circuit is also connected to the processor. The power detection circuit is also used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the processor so that the processor can store data.

[0023] Optionally, the power-down detection and power-down retention circuit further includes:

[0024] A power management circuit is provided, wherein the input terminal of the power management circuit is connected to the power output terminal, and the output terminal of the power management circuit is connected to the power supply terminal of the processor. The power management circuit is used to convert the power output terminal into a power supply and output it to the processor to power the processor.

[0025] Optionally, the control terminal of the processor is connected to the controlled terminal of the power management circuit, and the processor is further configured to output a shutdown signal to the power management circuit after data storage is completed, so as to control the power management circuit to stop supplying power to the processor.

[0026] Optionally, the output terminal of the power management circuit is also connected to the controlled terminal of the power-down retention control circuit;

[0027] The power-down retention control circuit is also used to disconnect the electrical connection between the energy storage circuit and the power output terminal when the output voltage of the power management circuit is greater than the second preset voltage.

[0028] Optionally, the power-down retention control circuit includes an eighth resistor, a ninth resistor, a second switch, a third switch, and a fourth switch. The input terminal of the third switch is connected to the output terminal of the energy storage circuit, the output terminal of the third switch is connected to the output terminal of the fourth switch, the input terminal of the fourth switch is connected to the power output terminal, the controlled terminals of the third and fourth switches are connected to the input terminal of the second switch, the output terminal of the second switch is grounded, the controlled terminal of the second switch is connected to the power supply terminal of the processor through the eighth resistor, the first terminal of the ninth resistor is connected to the output terminal of the third switch, and the second terminal of the ninth resistor is connected to the input terminal of the second switch.

[0029] The present invention also proposes an electronic device, including a processor and a power-down detection and power-down retention circuit as described above;

[0030] The processor is connected to the power output terminal of the power-down detection and power-down retention function circuit.

[0031] In this invention, by incorporating an energy storage circuit and a power-down retention control circuit, the power-down retention control circuit can be activated when the system loses power. This allows the energy storage circuit to provide power to the processor for power-down data storage, enabling the processor to successfully complete the data storage task. Simultaneously, after completing the power-down data storage, the processor can control the power-down retention control circuit to disconnect the power supply to the energy storage circuit, thereby preventing the waste of stored energy. This also extends the lifespan of the energy storage devices in the energy storage circuit and improves the stability and practicality of the power-down detection and retention circuitry. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0033] Figure 1 This is a functional module diagram of an embodiment of the power-down detection and power-down retention function circuit of the present invention;

[0034] Figure 2 This is a functional module schematic diagram of another embodiment of the power-down detection and power-down retention function circuit of the present invention;

[0035] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the power-down detection and power-down retention function circuit of the present invention.

[0036] Explanation of icon numbers:

[0037]

[0038]

[0039] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0041] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0042] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0043] Currently, industrial system control products require a backup power supply to maintain power for a certain period when the main power input suddenly fails. This backup power is used to store relevant data during the power outage and to prevent malfunctions in memory devices such as FLASH memory caused by improper read / write operations during a power outage. Therefore, a system circuit with power outage detection and power supply maintenance functions is needed. In existing technologies, some solutions do not perform any control after a power outage, continuing until the backup energy storage equipment is depleted, resulting in energy waste.

[0044] To address the above problems, this invention proposes a circuit for power-down detection and power-down retention, referring to... Figures 1 to 3 In one embodiment, the power-down detection and power-down retention function circuit includes:

[0045] A power output terminal is used to connect to the processor;

[0046] Energy storage circuit 10 is connected to the power supply output terminal;

[0047] A power-down retention control circuit 20 is connected in series between the energy storage circuit 10 and the power output terminal. The controlled terminal of the power-down retention control circuit 20 is connected to the processor. The power-down retention control circuit 20 is used to control the connection between the energy storage circuit 10 and the power output terminal to be turned on / off.

[0048] Furthermore, based on the control of the processor, the electrical connection between the energy storage circuit 10 and the power output terminal is disconnected, so that the energy storage circuit 10 stops supplying power to the processor.

[0049] In this embodiment, the power output terminal is used to connect to the processor so that it can provide normal power to the downstream processor when the power supply circuit fails, enabling the downstream load processor to store data in a timely manner and prevent data loss due to power failure. The power output terminal can also be connected to the power supply circuit to provide normal power to the connected downstream load. The energy storage circuit 10 can be implemented using energy storage devices such as energy storage capacitors or rechargeable batteries. The energy storage circuit 10 can also be electrically connected to the power supply circuit that normally supplies power to the downstream processor so that it stores a portion of the electrical energy output by the power supply circuit when it is providing normal power to the connected processor, and uses it as temporary power. The electrical energy in the energy storage circuit 10 can also come from other circuits. The power-down retention control circuit 20 can be implemented using switching transistors, etc., to control the connection or disconnection of the path between the energy storage circuit 10 and the power output terminal. The power-down retention control circuit 20 is used to control the energy storage circuit 10 to be electrically connected to the power output terminal when the downstream load processor fails, so that the energy storage circuit 10 provides temporary power to the downstream load processor.

[0050] It is important to note that the controlled terminal of the power-down retention control circuit 20 is connected to the processor. When the processor outputs a shutdown signal, the power-down retention control circuit 20 controls the energy storage circuit 10 to disconnect from the power output terminal, causing the energy storage circuit 10 to stop supplying power to the processor. Therefore, the processor can be configured to store data during power failure and output a shutdown signal after data storage is complete, causing the energy storage circuit 10 to stop supplying power. The actual power-down process can be described as follows: When the power supply circuit fails, the power-down retention control circuit 20 is turned on, controlling the energy storage circuit 10 to electrically connect to the power output terminal to supply power to the processor. At the same time, the processor begins storing relevant data when the power supply circuit fails, and after the processor completes the power-down data storage, it outputs a shutdown signal to the power-down retention control circuit 20, controlling the power-down retention control circuit 20 to shut down, thereby causing the energy storage circuit 10 to stop supplying power. This configuration allows the processor to disconnect the power supply to the energy storage circuit 10 after completing the power-down data storage, thus preventing the waste of stored energy. It also extends the lifespan of the energy storage devices in the energy storage circuit 10 and improves the stability and usability of the power-down detection and retention circuitry. Furthermore, direct control of the temporary power supply path by the processor eliminates the cost of additional monitoring circuitry, reduces circuit complexity, and enhances the stability of the power-down detection and retention circuitry.

[0051] In this invention, by setting up an energy storage circuit 10 and a power-down retention control circuit 20, the power-down retention control circuit 20 can be turned on when the system loses power, enabling the energy storage circuit 10 to provide power for the processor to perform power-down data storage, thus allowing the processor to successfully complete the power-down data storage task. Simultaneously, after completing the power-down data storage task, the processor can also control the power-down retention control circuit 20 to disconnect the power supply path to the energy storage circuit 10, thereby avoiding waste of the electrical energy stored in the energy storage circuit 10. This also improves the lifespan of the energy storage devices in the energy storage circuit 10 and enhances the stability and practicality of the power-down detection and power-down retention function circuit.

[0052] Reference Figures 1 to 3 In one embodiment, the power-down detection and power-down retention function circuit further includes:

[0053] A power input terminal, which is connected to the power output terminal, is used to connect to an input power source;

[0054] A power conversion circuit 30 has a first output terminal and a second output terminal. The input terminal of the power conversion circuit 30 is connected to a power input terminal. The first output terminal of the power conversion circuit 30 is connected to the power output terminal. The second output terminal of the power conversion circuit 30 is connected to the input terminal of the energy storage circuit 10.

[0055] The power conversion circuit 30 is used to convert the input power into a supply voltage and output it from the first output terminal to the power output terminal to power the processor.

[0056] And, it is used to convert the input power supply into a charging voltage and output it from the second output terminal to the energy storage circuit 10 to charge the energy storage circuit 10.

[0057] Understandably, in applications where the load circuit processor consumes a lot of power and requires a long power-down hold-up time (e.g., a load power consumption of 30W requiring a power-down hold-up time of more than 10 seconds), the energy storage circuit 10 needs to use a large-capacity supercapacitor or rechargeable battery, resulting in a long energy storage charging time. However, the integrated PMIC or multi-channel independent output power chip U4 in the subsequent load circuit has strict requirements on the rising edge of power-on. When the normal power supply circuit and the energy storage circuit share the same power supply in the system, i.e., when the first output terminal and the second output terminal in this embodiment are the same output terminal, the power output terminal will have an excessively large rising edge due to the charging of the energy storage circuit 10. This will cause abnormal output of the integrated PMIC or multi-channel independent output power chip U4 in the load circuit. At the same time, the charging time of the supercapacitor or rechargeable battery in the energy storage circuit 10 from 0V to full charge is very long, resulting in slow power supply to the subsequent load. This will also lead to a longer time from power-on to processor startup in the product system, affecting the user experience.

[0058] Therefore, in this embodiment, the power conversion circuit 30 can be equipped with two power outputs, outputting through a first output terminal and a second output terminal respectively. The first output terminal outputs directly to the power output terminal for normal power supply, while the second output terminal outputs to the energy storage circuit 10 for charging the energy storage circuit 10. This configuration, by providing power through two separate power sources, ensures that the voltage rise time meets the requirements of the subsequent load by directly outputting voltage from the first output terminal. Furthermore, while the energy storage circuit 10 is being charged at the second output terminal, the subsequent load can be powered by the first output terminal, avoiding the drawback of long power-on time and improving the user experience.

[0059] In this embodiment, the power conversion circuit 30 can be implemented using two DC-DC voltage conversion circuits, AC-DC voltage conversion circuits, or other circuits. The two power supplies can be selected according to actual usage requirements. For example, when applied to industrial communication, the input power at the power input terminal is typically 24V; when applied to communication equipment, the input power at the power input terminal is typically 48V. Processors such as ARM, MCU, or FPGA, which need to perform data saving operations during power failure, generally require a power supply of less than 5V. Furthermore, the input voltage of power management ICs for processors or FPGAs that require multiple power supplies is mostly less than 12V. Therefore, power conversion is necessary. Since the actual power parameters required by the internal circuits of industrial products vary, the two power conversion circuits within the power conversion circuit 30 can be selected according to actual usage requirements to convert the input power into the power supply required by the processor. Meanwhile, the power conversion corresponding to the energy storage circuit 10 can also be selected according to the type of energy storage device in the energy storage circuit 10. For example, when the energy storage device in the energy storage circuit 10 is a rechargeable battery, the power conversion corresponding to the energy storage circuit 10 can be implemented by a dedicated battery charging management power IC to improve the service life of the rechargeable battery.

[0060] Reference Figures 1 to 3 In one embodiment, the power-down detection and power-down retention function circuit further includes:

[0061] A power input terminal, which is connected to the power output terminal, is used to connect to an input power source;

[0062] A power detection circuit 40 is provided, with its detection terminal connected to the power input terminal and its output terminal connected to the controlled terminal of the power-down retention control circuit 20. The power detection circuit 40 is used to detect the output voltage of the power input terminal and, when the output voltage of the power input terminal is less than a first preset voltage, outputs a power-down retention signal to the power-down retention control circuit 20, so that the power-down retention control circuit 20 controls the energy storage circuit 10 to be electrically connected to the power output terminal, so that the energy storage circuit 10 supplies power to the processor.

[0063] Optionally, the output terminal of the power detection circuit 40 is also connected to the processor. The power detection circuit 40 is also used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the processor so that the processor can store data.

[0064] In this embodiment, the power input terminal can be connected to the power output terminal so that the input power supply provides normal power to the downstream load processor. When the power input terminal loses power, the energy storage circuit 10 provides temporary power to the downstream load processor. The first preset voltage can be the minimum voltage at which the system can operate normally. For example, when the voltage at the power input terminal is greater than 5V, the downstream load processor can operate normally, while when the voltage at the power input terminal is less than 5V, the downstream load processor cannot operate normally. Therefore, 5V can be set as the first preset voltage. Thus, when the output voltage at the power input terminal is greater than the first preset voltage, it indicates that the power input terminal is powered on, and when the output voltage at the power input terminal is less than the first preset voltage, it indicates that the power input terminal is powered off.

[0065] The power detection circuit 40 can be implemented using voltage divider resistors, a comparator, and a switching transistor. When the output voltage at the power input terminal is less than a first preset voltage (i.e., when the power input terminal is powered off), it outputs a power-down retention signal to the power-down retention control circuit 20 and the processor. This causes the power-down retention control circuit 20 to control the energy storage circuit 10 to electrically connect to the power output terminal, allowing the energy storage circuit 10 to temporarily power the downstream load processor. This enables the downstream load processor to complete data storage in a timely manner, preventing data loss and improving the stability and security of the electronic equipment. The power detection circuit 40 can also use a comparator to output the power-down retention signal. The first preset voltage is used as a reference voltage in the comparator, allowing the power detection circuit 40 to output a power-down retention signal when the output voltage at the power input terminal is less than the first preset voltage, thereby controlling the power-down retention control circuit 20.

[0066] Reference Figures 1 to 3 In one embodiment, the locking detection terminal of the power detection circuit 40 is connected to the output terminal of the power detection circuit 40, and the power detection circuit 40 is further used to lock when the power-down retention signal is detected, so as to continuously output the power-down retention signal.

[0067] In this embodiment, the power detection circuit 40 also has a self-locking function. That is, when the power detection circuit 40 detects that the output voltage at the power input terminal is less than a first preset voltage, it outputs a power-down retention signal. After confirming that the power detection circuit 40 has output the power-down retention signal, it enters a locked state, so that the power detection circuit 40 continuously outputs the power-down retention signal, thereby controlling the power-down retention control circuit 20 to remain in the conducting state. This setting can prevent the power input power from being immediately restored after a power outage, which would cause the output of the power detection circuit 40 to change, causing the energy storage circuit 10 to stop supplying power to the load processor. In other words, it avoids abnormal power interruption during the power-down data saving process in the load circuit, which could lead to abnormal data saving function or device damage.

[0068] Reference Figures 1 to 3 In one embodiment, the lock detection terminal of the power detection circuit 40 is also connected to the processor. The power detection circuit 40 is also used to unlock when it receives the shutdown signal output by the processor and stop outputting the power-down retention signal to the power-down retention control circuit 20, so that the power-down retention control circuit 20 disconnects the electrical connection between the energy storage circuit 10 and the power output terminal, so that the energy storage circuit 10 stops supplying power to the processor.

[0069] In this embodiment, the locking detection terminal of the power detection circuit 40 is also connected to the processor. After completing the power-down data storage, the processor can output a shutdown signal, controlling the power-down retention control circuit 20 to disconnect the power supply path of the energy storage circuit 10, and simultaneously controlling the power detection circuit 40 to unlock, thus restoring the power detection circuit 40 to its initial state. This configuration allows the processor to unlock the power detection circuit 40 after completing the power-down data storage, enabling the power detection circuit 40 to restart detecting the power input state. This ensures that when the system loses power, the power supply path of the energy storage circuit 10 is promptly restored, improving the stability and safety of the power-down detection and power-down retention circuitry.

[0070] Reference Figures 1 to 3 In one embodiment, the power detection circuit 40 includes:

[0071] A power-down detection circuit is provided, wherein the detection terminal of the power-down detection circuit is connected to the power input terminal, and the output terminal of the power-down detection circuit is connected to the controlled terminal of the power-down retention control circuit 20. The power-down detection circuit is used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the power-down retention control circuit 20, so that the power-down retention control circuit 20 controls the energy storage circuit 10 to be electrically connected to the power output terminal, so that the energy storage circuit 10 supplies power to the processor.

[0072] A power-down self-locking circuit is provided, wherein the control terminal of the power-down self-locking circuit is connected to the controlled terminal of the power-down detection circuit, and the locking detection terminal of the power-down self-locking circuit is connected to the output terminal of the power-down detection circuit. The power-down self-locking circuit is used to control the power-down detection circuit to continuously output the power-down holding signal when the power-down holding signal is detected.

[0073] In this embodiment, the power detection circuit 40 can be divided into two parts: a power-down detection circuit and a power-down state self-locking circuit, as shown in the figure. Figure 3 , Figure 3This is a schematic diagram of a circuit structure for an embodiment of a power-down detection and power-down retention circuit. The power-down detection circuit consists of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third diode D3, and a comparator U1. The power-down latch-up circuit consists of a first switching transistor Q1, a third capacitor C3, and a seventh resistor group R7. Specifically, the comparator U1 is powered by VDD4. The first resistor R1 and the second resistor R2 serve as reference sources for setting the first preset voltage of the input power supply. The voltage division value of the first resistor R1 and the second resistor R2 is Vref1 = VDD4 * R1 / (R1 + R2). The sixth resistor R6 is used to set the hysteresis threshold of the comparator U1 to eliminate jitter and interference. The value of the sixth resistor R6 should be much larger than the values ​​of the third resistor R3 and the fifth resistor R5. The value of the input power supply VIN after being divided by the fourth resistor R4 and the fifth resistor R5 is approximately Vref2 = VIN * R5 / (R4 + R5). According to the working principle of comparator U1, when Vref2 is less than Vref1, that is, when the input power is off, comparator U1 outputs a high level; when Vref2 is greater than Vref1, that is, when the input power is on, comparator U1 outputs a low level. In addition, the function of the first capacitor C1 is to form a low-pass filter circuit with the fourth resistor R4 to filter out transient stray interference signals from the outside input, so as to prevent the power failure detection circuit from being falsely triggered. During the system power-down process, when the input power supply VIN is less than the first preset voltage, the VIN_CHECK signal becomes high. The first switch Q1, after being set with a certain hysteresis filter delay by the seventh resistor R7 and the second capacitor C2, operates in the conducting state. Subsequently, the fifth resistor R5 is approximately short-circuited after being turned on by the first switch Q1, and the detected value Vref2 becomes approximately equal to 0V, ensuring that Vref2 remains less than Vref1 after power-down. The comparator U1 maintains a high output level, and the signal VIN_CHECK also remains high. Therefore, the power-down holding control circuit 20 remains in the conducting state, and the energy storage circuit 10 continuously supplies power to the load circuit. Thus, the main function of this circuit is to self-lock the state after power-down.

[0074] Reference Figures 1 to 3 In one embodiment, the power-down detection and power-down retention function circuit further includes:

[0075] A power management circuit 50 is provided, wherein the input terminal of the power management circuit 50 is connected to the power output terminal, and the output terminal of the power management circuit 50 is connected to the power supply terminal of the processor. The power management circuit 50 is used to convert the power output terminal into a power supply and output it to the processor to power the processor.

[0076] In this embodiment, a power management circuit 50 is also provided to manage the power output to the processor. The power management circuit 50 can be implemented by using an integrated PMIC or a multi-channel independent output power chip to power the processor, so as to meet the multi-channel power supply requirements of the processor. At the same time, setting up a power management circuit 50 to power the processor is beneficial to improving the processor's processing power and service life, and improving the stability and safety of the power failure detection and power failure retention function circuit.

[0077] Optionally, the control terminal of the processor is connected to the controlled terminal of the power management circuit 50. The processor is also configured to output a shutdown signal to the power management circuit 50 after data storage is completed, so as to control the power management circuit 50 to stop supplying power to the processor.

[0078] In one embodiment, in addition to the integrated PMIC or multiple independent output power chip that supplies power to the processor, the power management circuit 50 may also include a switching circuit. This switching circuit is positioned between the integrated PMIC or multiple independent output power chip and the power output terminal to control the connection and disconnection between the power output terminal and the integrated PMIC or multiple independent output power chip. This configuration allows the processor to control the power management circuit 50 to stop supplying power after data storage is complete, thereby enabling the processor's self-reboot function.

[0079] Optionally, the output terminal of the power management circuit 50 is also connected to the controlled terminal of the power-down retention control circuit 20;

[0080] The power-down retention control circuit 20 is also used to disconnect the electrical connection between the energy storage circuit 10 and the power output terminal when the output voltage of the power management circuit 50 is greater than the second preset voltage.

[0081] In one embodiment, the output terminal of the power management circuit 50 is also connected to the controlled terminal of the power-down retention control circuit 20, that is, the controlled terminal of the power-down retention control circuit 20 is connected to the power supply terminal of the processor. The second preset voltage can be a voltage value at which the processor can operate normally. With this configuration, during the power-on process at the power input terminal, since the power management circuit 50 sets a certain delay time for the power supply terminal of the processor to establish the working voltage, it is ensured that the power-down retention control circuit 20 and the power detection circuit 40 are in the cut-off state throughout the entire power-on process.

[0082] Reference Figure 3In one embodiment, the power-down retention control circuit 20 includes an eighth resistor R8, a ninth resistor R9, a second switch Q2, a third switch Q3, and a fourth switch Q4. The input terminal of the third switch Q3 is connected to the output terminal of the energy storage circuit 10, the output terminal of the third switch Q3 is connected to the output terminal of the fourth switch Q4, the input terminal of the fourth switch Q4 is connected to the power output terminal, the controlled terminals of the third switch Q3 and the fourth switch Q4 are connected to the input terminal of the second switch Q2, the output terminal of the second switch Q2 is grounded, the controlled terminal of the second switch Q2 is connected to the power supply terminal of the processor through the eighth resistor R8, the first terminal of the ninth resistor R9 is connected to the output terminal of the third switch Q3, and the second terminal of the ninth resistor R9 is connected to the input terminal of the second switch Q2.

[0083] It is understandable that in existing power-down solutions, the power-down retention control circuit 20 typically uses a MOSFET plus a diode. In applications with large downstream loads and long periods of continuous power supply after power failure, the high forward voltage of the diode leads to significant losses, thus requiring more energy storage devices, increasing circuit cost and product size. Therefore, in this embodiment, referring to... Figure 3 The power-down retention control circuit 20 uses two MOSFETs connected back-to-back. The functions of the third switch Q3 and the fourth switch Q4 are: firstly, after the input power supply VIN is powered on, it isolates VDD3 and VDD4 of the energy storage circuit 10 to prevent the power supply VDD4 supplying the load circuit from backflowing into the energy storage circuit 10, which could cause the load circuit to start abnormally due to the excessive charging time of the energy storage circuit 10; secondly, after the input power supply VIN is powered off, the energy storage circuit 10 can supply power to the load circuit through the third switch Q3 and the fourth switch Q4 to maintain the processor in the load circuit to perform data storage and other related work. At the same time, it takes advantage of the low on-resistance of MOSFETs to reduce the loss of the discharge circuit, save the cost of the energy storage devices required for the energy storage circuit 10, and avoid the problem of excessive product size due to the increase of storage devices.

[0084] To better illustrate the inventive concept of this invention, the working principle of this invention will be explained below with reference to specific embodiments and circuit structure diagrams.

[0085] Reference Figure 3 , Figure 3This is a schematic diagram of a circuit structure for an embodiment of a power-down detection and power-down retention function circuit. The power-down detection circuit consists of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third diode D3, and a comparator U1. The power-down self-locking circuit consists of a first switch Q1, a third capacitor C3, and a seventh resistor group R7. The energy storage circuit 10 consists of a tenth resistor R10 and a fourth capacitor C4. The power-down retention control circuit 20 consists of an eighth resistor R8, a ninth resistor R9, a second switch Q2, a third switch Q3, and a fourth switch Q4. The power management circuit 50 consists of a power management chip U4, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a sixth capacitor C6, and a fifth switch Q5. The first power conversion circuit 30 is a power conversion chip U2, and the second power conversion circuit 30 is a power conversion chip U3.

[0086] First, combine Figure 3 The working principle of each circuit part in the power failure detection and power failure retention function circuit is explained.

[0087] The first power conversion circuit 30 and the second power conversion circuit 30: After the input power supply VIN is powered on, the power supply VIN is converted into VDD1 power supply by the power conversion chip U2. VDD1 is converted into VDD4 by the first diode D1. VDD4 then supplies power to the subsequent power management circuit 50. At the same time, VIN is converted into VDD2 power supply by the power conversion chip U3. VDD2 charges the supercapacitor C4 by the second diode D2 and the current limiting resistor R10.

[0088] Power-down detection circuit: Comparator U1 is powered by VDD4. The first resistor R1 and the second resistor R2 serve as reference sources for setting the VIN undervoltage threshold. The voltage division value of the first resistor R1 and the second resistor R2 is Vref1 = VDD4 * R1 / (R1 + R2). The sixth resistor R6 is used to set the comparator's hysteresis threshold to eliminate jitter and interference. The value of the sixth resistor R6 should be much larger than the values ​​of the third resistor R3 and the fifth resistor R5. The value of VIN after being divided by the fourth resistor R4 and the fifth resistor R5 is approximately Vref2 = VIN * R5 / (R4 + R5). According to the comparator's working principle, when Vref2 is less than Vref1, comparator U1 outputs a high level; when Vref2 is greater than Vref1, comparator U1 outputs a low level. Additionally, the first capacitor C1, together with the fourth resistor R4, forms a low-pass filter circuit to filter out transient stray interference signals from the external input, preventing the power-down detection circuit from being falsely triggered.

[0089] The operating state of MOSFET Q2 in the power-down retention control circuit 20 is controlled by comparator U1 and VDD5. When U1 outputs a high level and the VDD5 power supply value is greater than the start-up voltage Vgs-th of MOSFET Q2, MOSFET Q2 turns on, and MOSFETs Q3 and Q4 also turn on. The supercapacitor C4 in the energy storage circuit 10 supplies power to the load circuit through MOSFETs Q3 and Q4. When the comparator U1 outputs a low level, the detection signal VIN_CHECK is low, meaning MOSFET Q2 is in the off state, and MOSFETs Q3 and Q4 also turn off. Therefore, the power-down detection circuit for the input power supply VIN determines whether there is a power failure based on the level of the comparator U1 output, and the undervoltage threshold V1 of the input power supply VIN can be set to approximately Vref1*(R4+R5) / R5.

[0090] The startup threshold of the input power supply of the power conversion chip U2 must be less than the undervoltage threshold V1 of the power failure detection circuit to ensure that the power conversion chip U2 can still work normally when the undervoltage is detected, so as to keep VDD4 in a normal working state. The function of capacitor C5 is to ensure that VDD4 is in a normal working state before the energy storage circuit 10 is powered on after power failure. The startup enable pin EN of the power management chip U4 in the load circuit forms a delayed startup circuit through the eleventh resistor R11, the twelfth resistor R12 and the sixth capacitor C6. On the one hand, it ensures that U4 starts working only after the VDD4 power supply is established and stabilized. On the other hand, it is used to ensure that when the input power supply VIN value is less than the undervoltage threshold V1 of the power failure detection circuit during the power-on process, VDD5 in the load circuit has not yet been established, so as to realize that the power failure holding control circuit 20 and the power failure state self-locking circuit work in the cut-off state. When power supply VIN is initially powered on, during the rise from 0V to the normal power supply range, VDD1 establishes up early. When VIN input is less than the undervoltage threshold V1, VDD4 rises and supplies power to the load circuit and comparator U1. The non-inverting input voltage of comparator U1 is Vref1, and the inverting input voltage Vref2 is approximately equal to VIN*R5 / (R4+R5). To prevent a false power-down signal trigger when the input power supply VIN is less than the undervoltage threshold V1 of the power-down detection circuit (i.e., Vref2 is less than Vref1), causing comparator U1 to output a high level, a delay circuit is used (with VDD4*R2*C2 set to be greater than VIN*R4*C1) to ensure a longer Vref1 establishment time. Simultaneously, a delayed start circuit is formed using the eleventh resistor R11 and the sixth capacitor C6 (with VDD4*R11*C6 set to be greater than VIN*R4*C1) to ensure VDD5... The slow setup time ensures that the VIN_CHECK signal remains low during power-on, keeping switch Q2 in the off state. This means the power-down holding control circuit 20 operates in the off state, and switch Q1 in the power-down self-locking circuit is also in the off state. When the input voltage VIN exceeds the undervoltage threshold V1 of the power-down detection circuit (i.e., Vref2 exceeds Vref1), comparator U1 outputs a low level, and the VIN_CHECK signal is low. At this time, both switches Q2 and Q1 are in the off state. Simultaneously, the processor U5 in the load circuit can read the low VIN_CHECK level, indicating that the input power supply VIN is in a normal power supply state.

[0091] Power-down retention control circuit 20: P-type MOSFETs Q3 and Q4 are connected back-to-back. A ninth resistor R9 is connected in parallel between the gate (G) and source (S) terminals of MOSFETs Q3 and Q4. An N-type MOSFET Q2 is used to control MOSFETs Q3 and Q4. The eighth resistor R8 is pulled up to the power supply VDD5 in the load circuit. The control terminal of MOSFET Q2 is connected to the output pin of comparator U1 in the power-down detection circuit via the third diode D3. After power-on, because the power-down detection circuit pulls the VIN_CHECK level low, MOSFET Q2 operates in the cutoff state, so MOSFETs Q3 and Q4 are both in the cutoff state. The function of the ninth resistor R9 is to ensure that the voltages at the gate (G) and source (S) terminals of MOSFET Q2 are equal when Q2 is in the cutoff state, thus ensuring that MOSFETs Q3 and Q4 are in the fully cutoff state.

[0092] Power-down self-locking circuit: During system power-up, when the input power supply VIN is less than the undervoltage threshold V1, the delay circuit composed of the second resistor R2 and the second capacitor C2 (with the parameter VDD4*R2*C2 set to be greater than the value of VIN*R4*C1) ensures that the Vref1 establishment time is relatively long. At the same time, the delay start circuit composed of the eleventh resistor R11 and the sixth capacitor C6 (with the parameter VDD4*R11*C6 set to be greater than the value of VIN*R4*C1) makes the VDD5 establishment time relatively slow. Thus, the value of the VIN_CHECK signal is always low during the power-up process, so the switching transistor Q1 in the power-down self-locking circuit is in the cut-off working state.

[0093] During the system power-on process, when the input power supply VIN is greater than the undervoltage threshold V1, that is, Vref2 is greater than Vref1, the comparator U1 outputs a low level. At the same time, the VIN_CHECK level is pulled low through the third diode D3, and the switching transistor Q1 operates in the cut-off state. Therefore, the self-locking circuit in the power-off state is in the cut-off state throughout the entire power-on process.

[0094] Power management circuit 50: Power supply VDD4 is connected to the enable pin EN of power management chip U4 after being divided by the eleventh resistor R11 and the twelfth resistor R12. It is used to set the input power supply start-up voltage range of power management chip U4. The eleventh resistor R11 and the sixth capacitor C6 are used to set the delay start-up time of power management chip U4. On the one hand, it ensures that power management chip U4 starts working only after the VDD4 power supply is established and stabilized. On the other hand, it is used to ensure that when the input power supply VIN value is less than the undervoltage threshold V1 of the power failure detection circuit during power-on, VDD5 in the load circuit has not yet been established, so that the power failure holding control circuit 20 and the power failure state self-locking circuit are both in the cut-off state. The collector of transistor Q5 is connected to the EN enable pin of power management chip U4, the emitter is connected to GND, and the base is connected to the IO pin of processor U5 through resistor R13. During the power-on process of input power VIN, processor U5 controls the EN_RST signal to be low, so transistor Q5 is in the off state.

[0095] The following combination Figure 3 The working principle of the power-down detection and power-down retention circuit during the power-down process is explained.

[0096] When the input power supply VIN starts to lose power, and VIN is less than the undervoltage detection threshold V1 (approximately Vref1*(R4+R5) / R5), the comparator U1 outputs a high level (approximately equal to VDD4). At this time, the VIN_CHECK signal becomes high (approximately VDD5), and the switching transistor Q2 in the power-down retention control circuit 20 turns on. Switches Q3 and Q4 also turn on. The supercapacitor C4 in the energy storage circuit 10 then supplies power to the load circuit through switches Q3 and Q4. After the processor U5 in the load circuit reads the change of VIN_CHECK from low to high, it recognizes that the input power supply VIN has started to lose power, and thus begins data saving and related operations. The entire system's operation can be described in two states based on the processor U5's working state: the initial data saving operation and the completion of the data saving operation.

[0097] When processor U5 first starts data saving, the VIN_CHECK signal is high. Switch Q1, after a certain hysteresis filter delay set by the seventh resistor R7 and the second capacitor C2, becomes conductive. Immediately afterward, the fifth resistor R5 is approximately short-circuited by switch Q1, causing the detected value Vref2 to become approximately 0V. This ensures that Vref2 remains less than Vref1 after power loss. Comparator U1 maintains a high output, and the VIN_CHECK signal also remains high. Therefore, the power-down retention control circuit 20 remains conductive, and C4 in the energy storage circuit 10 continuously supplies power to the load circuit. Simultaneously, processor U5 controls the EN_RST signal to be low, so transistor Q5 operates in the off state, and the power management chip U4 remains operational.

[0098] After processor U5 completes the data saving operation, it actively pulls the VIN_CHECK signal low, causing switch Q2 to operate in the cutoff state. Switches Q3 and Q4 then operate in the cutoff state, and supercapacitor C4 stops supplying power to the load. Simultaneously, the VIN_CHECK signal goes low, switch Q1 goes to the cutoff state, and the short-circuited state of the fifth resistor R5 in the power-down detection circuit is released, thus unlocking the latched state. The active control of processor U5 pulling the VIN_CHECK signal low after completing power-down data saving and other operations serves three purposes: First, it unlocks the self-locking circuit in the power-down state, restoring it to its original state; second, it saves circuit costs, as processor U5 actively shuts down the discharge circuit of energy storage device C4, allowing VDD4 to quickly drop to 0V, preventing abnormal startup of power management chip U4 after VIN is re-energized, and eliminating the need for additional monitoring circuits for power supplies such as VDD3, thus saving circuit costs; third, it saves energy by shutting down the discharge circuit of energy storage circuit 10, avoiding energy waste in C4 within energy storage circuit 10.

[0099] Furthermore, after processor U5 completes the data saving process, it actively pulls the VIN_CHECK signal low and maintains it for a certain period of time before controlling the EN_RST signal to be high, causing transistor Q5 to operate in the on state. The enable pin EN of power management chip U4 is shorted to GND, and power management chip U4 immediately stops working. It can be understood that after the input power VIN is de-energized, if processor U5 re-energizes VIN during the data saving process, VDD4 remains in normal power supply operation. Due to the self-locking circuit for the power-down state, processor U5 is unaware that VIN has been re-energized. After the automatic control pulls the VIN_CHECK signal low and maintains it for a certain period of time, the electrical connection between the energy storage circuit 10 and the power output terminal is disconnected. However, VDD4 is always in a normal working state with power, and the power management chip U4 is also always in a normal working state. Therefore, after the data saving work is completed, the enable pin EN of the power management chip U4 needs to be reset to stop the power management chip U4 from working. The output power supply VDD5 will then be powered down, and the processor U5 will also be powered down. The power management chip U4 will only resume working after the delay start circuit of the eleventh resistor R11, the twelfth resistor R12 and the sixth capacitor C6 is re-established, thereby realizing the function of automatic restart of the processor U5.

[0100] The present invention also proposes an electronic device, including a processor and a power-down detection and power-down retention circuit as described above; wherein,

[0101] The processor's power supply terminal is connected to the power output terminal of the power-down detection and power-down retention function circuit. This electronic device includes the aforementioned power-down detection and power-down retention function circuit. The specific structure of this circuit is as described in the above embodiments. Since this electronic device employs all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0102] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A power-down detection and power-down hold function circuit applied in an electronic device, the electronic device comprising a processor, characterized in that, include: A power output terminal is used to connect to the processor; An energy storage circuit is connected to the power supply output terminal; A power-down retention control circuit is connected in series between the energy storage circuit and the power output terminal. The controlled terminal of the power-down retention control circuit is connected to the processor. The power-down retention control circuit is used to control the connection between the energy storage circuit and the power output terminal to be turned on / off. Furthermore, based on the control of the processor, the electrical connection between the energy storage circuit and the power output terminal is disconnected, so that the energy storage circuit stops supplying power to the processor; The power-down detection and power-down retention circuit also includes: A power input terminal, which is connected to the power output terminal, is used to connect to an input power source; A power detection circuit is provided, wherein the detection terminal of the power detection circuit is connected to the power input terminal, and the output terminal of the power detection circuit is connected to the controlled terminal of the power-down retention control circuit. The power detection circuit is used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit controls the energy storage circuit to be electrically connected to the power output terminal, so that the energy storage circuit supplies power to the processor. The lock detection terminal of the power detection circuit is also connected to the processor. The power detection circuit is also used to unlock when it receives the shutdown signal output by the processor and stop outputting the power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit disconnects the electrical connection between the energy storage circuit and the power output terminal, so that the energy storage circuit stops supplying power to the processor. The output terminal of the power detection circuit is also connected to the processor. The power detection circuit is also used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the processor so that the processor can store data. The power-down retention control circuit includes an eighth resistor, a ninth resistor, a second switch, a third switch, and a fourth switch. The input terminal of the third switch is connected to the output terminal of the energy storage circuit, the output terminal of the third switch is connected to the output terminal of the fourth switch, the input terminal of the fourth switch is connected to the power output terminal, the controlled terminals of the third and fourth switches are connected to the input terminal of the second switch, the output terminal of the second switch is grounded, the controlled terminal of the second switch is connected to the power supply terminal of the processor through the eighth resistor, the first terminal of the ninth resistor is connected to the output terminal of the third switch, and the second terminal of the ninth resistor is connected to the input terminal of the second switch.

2. The power-down detection and power-down hold function circuit of claim 1, wherein, The power-down detection and power-down retention circuit also includes: A power input terminal, which is connected to the power output terminal, is used to connect to an input power source; A power conversion circuit, the power conversion circuit having a first output terminal and a second output terminal, the input terminal of the power conversion circuit being connected to a power input terminal, the first output terminal of the power conversion circuit being connected to the power output terminal, and the second output terminal of the power conversion circuit being connected to the input terminal of the energy storage circuit. The power conversion circuit is used to convert the input power into a supply voltage and output it from the first output terminal to the power output terminal to power the processor. And, it is used to convert the input power supply into a charging voltage and output it from the second output terminal to the energy storage circuit to charge the energy storage circuit.

3. The power-down detection and power-down hold function circuit of claim 1, wherein, The locking detection terminal of the power detection circuit is connected to the output terminal of the power detection circuit. The power detection circuit is also used to lock when the power-down retention signal is detected, so as to continuously output the power-down retention signal.

4. The power-down detection and power-down hold function circuit of claim 1, wherein, The power detection circuit includes: A power-down detection circuit is provided, wherein the detection terminal of the power-down detection circuit is connected to the power input terminal, and the output terminal of the power-down detection circuit is connected to the controlled terminal of the power-down retention control circuit. The power-down detection circuit is used to detect the output voltage of the power input terminal, and when the output voltage of the power input terminal is less than a first preset voltage, it outputs a power-down retention signal to the power-down retention control circuit, so that the power-down retention control circuit controls the energy storage circuit to be electrically connected to the power output terminal, so that the energy storage circuit supplies power to the processor. A power-down self-locking circuit is provided, wherein the control terminal of the power-down self-locking circuit is connected to the controlled terminal of the power-down detection circuit, and the locking detection terminal of the power-down self-locking circuit is connected to the output terminal of the power-down detection circuit. The power-down self-locking circuit is used to control the power-down detection circuit to continuously output the power-down holding signal when the power-down holding signal is detected.

5. The power-down detection and power-down retention circuit as described in claim 1, characterized in that, The power-down detection and power-down retention circuit also includes: A power management circuit is provided, wherein the input terminal of the power management circuit is connected to the power output terminal, and the output terminal of the power management circuit is connected to the power supply terminal of the processor. The power management circuit is used to convert the power output terminal into a power supply and output it to the processor to power the processor.

6. The power-down detection and power-down retention circuit as described in claim 5, characterized in that, The processor's control terminal is connected to the controlled terminal of the power management circuit. The processor is also used to output a shutdown signal to the power management circuit after data storage is completed, so as to control the power management circuit to stop supplying power to the processor.

7. The power-down detection and power-down retention circuit as described in claim 5, characterized in that, The output terminal of the power management circuit is also connected to the controlled terminal of the power-down retention control circuit; The power-down retention control circuit is also used to disconnect the electrical connection between the energy storage circuit and the power output terminal when the output voltage of the power management circuit is greater than the second preset voltage.

8. An electronic device, characterized in that, Includes a processor and the power-down detection and power-down retention circuit as described in any one of claims 1-7; The processor is connected to the power output terminal of the power-down detection and power-down retention function circuit.

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