A successive approximation control circuit for DC-DC discontinuous conduction mode

Abstract

The application claims a kind of successive approximation control circuit for DC-DC discontinuous conduction mode, mainly including successive approximation control module, loop control core circuit, non-overlapping clock, RS flip-flop, DCM / CCM mode selection, rising edge detection circuit, data selector, phase-locked loop. Wherein, loop control core circuit ensures the normal work of entire DC-DC circuit;Phase-locked loop will let DC-DC be in continuous conduction mode (CCM) time, working frequency F SW Keep stable, at this time V CTRL =V A ;When DC-DC is in discontinuous conduction mode (DCM), successive approximation control module will find an output voltage V A Close to phase-locked loop as the input signal V CTRL Of voltage control core circuit, at this time V CTRL =V B Non-overlapping clock prevents H_side MOS and L_side MOS from being turned on simultaneously, causing loss;The output signal V G Of continuous conduction mode (CCM) / discontinuous conduction mode (DCM) mode selector is used to judge the working mode of circuit. Rising edge detection circuit detects the rising edge of V G , and the output signal V RST Will reset operation to successive approximation control module.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, and specifically relates to a successive approximation control circuit for DC-DC discontinuous conduction mode. Background Technology

[0002] A common feature of synchronous rectifier switching power converters is the use of a freewheeling switch instead of a freewheeling diode for the freewheeling circuit, reducing power loss and improving conversion efficiency. In CCM mode, the inductor current remains continuous. This is because when the load is heavy or the input voltage is high, the inductor stores energy for a shorter time, allowing it to be fully released within one switching cycle. In CCM mode, the variation in inductor current is related to the length of the switching cycle and the load. When the load is heavy or the input voltage is high, the inductor current remains continuous. In DCM mode, the inductor current drops to zero in each switching cycle. This is because when the load is light or the input voltage is low, the inductor stores energy for a longer time, making it impossible to fully release it within one switching cycle. In DCM mode, the variation in inductor current is related to the length of the switching cycle and the load. When the load is light or the input voltage is low, the inductor current drops to zero completely in each switching cycle.

[0003] In CCM mode, PWM modulation enables precise output voltage control with high efficiency and low ripple. The output voltage can be precisely adjusted by changing the switch duty cycle to meet application requirements. In CCM mode, the inductor current remains continuous, allowing the average output voltage to be controlled by adjusting the switch duty cycle.

[0004] PFM modulation is a modulation technique that controls the output voltage by adjusting the switching frequency. In DCM mode, PFM modulation can be achieved because the inductor current drops to zero during certain switching cycles. PFM modulation in DCM mode can achieve higher efficiency and lower ripple because it adjusts the switching frequency according to the actual output voltage requirements, avoiding unnecessary switching actions. Summary of the Invention

[0005] This invention aims to solve the problems of the prior art mentioned above. It proposes a successive approximation control circuit for DC-DC discontinuous conduction mode. The technical solution of this invention is as follows:

[0006] A successive approximation control circuit for DC-DC discontinuous conduction mode includes: a successive approximation control module, a loop control core circuit, a non-overlapping clock, an RS flip-flop, a DCM / CCM mode selector, a rising edge detection circuit, a data selector, and a phase-locked loop (PLL). The input signals to the PLL are a reference clock REF_CLK and a drive signal V. GH The output signal is V AThe input signal to the successive approximation control module is the phase-locked loop's output signal, V. A With reference clock REF_CLK, the output signal is V. B The input signals of the data selector come from the output signal V of the phase-locked loop. A The output signal of the successive approximation control module is V B The output signal is V CTRL The input signal of the core circuit of the loop control is the feedback signal V. FB Reference voltage V REF and the output signal V of the data selector CTRL The input signal of the RS flip-flop comes from the output signal V of the loop control core circuit. R and V S The output signal is V PWM The input signal for a non-overlapping clock is the duty cycle signal V. PWM The output signals are the drive signal V. GH and drive signal V GL The output signal of the DCM / CCM mode selector is V. G The input signal to the rising edge detection circuit is the output signal of the DCM / CCM mode selector, which is V. G The output signal is V RST The main function of the core circuit of the loop control is to amplify the feedback signal V. FB and reference signal V REF The difference between them, and then the control signal V generated by the control algorithm. PWM The core circuit of the loop control can adjust the feedback resistance R of the system. f1 So that the feedback signal V FB and reference signal V REF And maintain system stability; the phase-locked loop is used when the DC-DC converter is in continuous conduction mode (CCM) to ensure the operating frequency F SW Maintain stability, V CTRL =V A V CTRL V represents the output signal of the digital selector. A This represents the output signal of the phase-locked loop (PLL). The successive approximation control module is used to find a voltage VA close to the PLL's output voltage as the input signal V of the voltage control core circuit when the DC-DC converter is in discontinuous conduction mode (DCM). CTRL At this time, V CTRL =V B V BThis represents the output signal of the successive approximation control module; the non-overlapping clock is used to prevent the input voltage from being directly connected to GND and causing losses when the high-side MOS and low-side MOS are simultaneously turned on; the continuous conduction mode (CCM) / discontinuous conduction mode (DCM) selector is used to determine the operating mode of the DC-DC circuit; the rising edge detection circuit is used to detect V. G The rising edge of the signal simultaneously outputs the signal V. RST The successive approximation control module will be reset; the RS flip-flop is used to generate the duty cycle signal V required by the DC-DC circuit. PWM The data selector is used to select the appropriate output signal V. CTRL When the DC-DC circuit is in CCM mode, V CTRL =V A When the DC-DC circuit is in DCM mode, V CTRL =V B .

[0007] Furthermore, the core circuit of the loop control includes a comparator and a constant on-time generator, wherein the negative input terminal of the comparator is connected to the feedback voltage V. FB The positive input terminal is connected to the reference voltage V. REF The output voltage is V S The input voltage feedback voltage V of the constant on-time generator FB The output signal is V R When the feedback voltage V FB <V REF V REF Indicating the reference voltage, the comparator will cause V to... S ='1', V S This represents the comparator's output voltage. After the on-time TON, the constant on-time generator will cause V to... R ='1'. V R This represents the output voltage of a constant on-time generator.

[0008] Furthermore, the phase-locked loop includes a frequency and phase detector and a charge pump, wherein the input signals of the frequency and phase detector are a reference clock REF_CLK and a drive signal V. GH The output signals are UP and DOWN. The input voltage of the charge pump is the output signals UP and DOWN of the frequency and phase detector, and the output signal is the control signal V. CTRL When the DC-DC circuit is in CCM mode, the frequency and phase detector is used to detect the reference clock REF_CLK and the drive signal V. GH The frequency and phase difference are then used to calculate the phase difference signal, which is then fed into a charge pump circuit. The charge pump circuit adjusts V... AVoltage value to ensure that the reference clock REF_CLK is consistent with the drive signal V GH The frequencies are the same.

[0009] Furthermore, the successive approximation control module includes a voltage divider module, a register module, and a comparison module, wherein the voltage divider module consists of resistors R0 to R... 10 Switching transistor M N1 ~M N9 The register module consists of a 10-bit shift register, a D flip-flop with set function, and a two-input OR gate; the comparator module consists of a dynamic comparator and a D flip-flop with reset function; the voltage divider module has R0~R0... 10 Resistors in series, and switching transistor M N1 ~M N9 The drain of the transistor is connected to the upper end of the resistor, and the switching transistor M... N1 ~M N9 The gate voltage is 10, which is the output voltage Q0~Q9 of the shift register, and the switching transistor M N1 ~M N9 The source voltages are connected together; the input voltages of the two-input OR gate in the register module are the reference clock REF_CLK and the output voltage KILL of the D flip-flop in the comparator module. The D terminal of the D flip-flop with reset is connected to GND, the clock signal is connected to the output signal CLK of the two-input OR gate, and the set signal is connected to the output signal V of the rising edge detection circuit. RST The input voltage of the 10-bit shift register is the output signal V of the rising edge detection circuit. RST The output signal CLK of the two-input OR gate, the output signal Q of the D flip-flop with set function, and the output signals Q0~Q9 of the 10-bit shift register are connected to the switching transistor M of the voltage divider module. N1 ~M N9 The gate of the voltage divider module; the positive input of the dynamic comparator in the comparator module is the output voltage V of the voltage divider module. B The negative input is the output voltage V of the phase-locked loop. A The output voltage of the dynamic comparator is connected to the D terminal of the D flip-flop. The clock signal of the D flip-flop is connected to the output signal CLK of the two-input OR gate. The reset signal of the D flip-flop is connected to the output signal V of the rising edge detection circuit. RST The output signal of the D flip-flop is KILL, which serves as the input signal for the two-input OR gate of the register module.

[0010] Furthermore, the voltage divider module uses resistors R0 to R... 10 For power supply voltage V DD The voltage is divided, and the switching transistor M is controlled by the output signals Q0 to Q9 of the 10-bit shift register. N1 ~M N9 To generate different voltages V BWhen the DC-DC converter enters DCM mode, the rising edge detection circuit detects V. G At the rising edge, the output signal V RST It will perform reset and set operations on the successive approximation control module; when V RST After resetting the D flip-flop of the comparator module, its output voltage KILL = '0'. At this time, the output signal CLK of the two-input OR gate = REF_CLK, and simultaneously the output signal Q of the D flip-flop with the set signal in the register module = '1', and the output signals Q0~Q9 of the 10-bit shift register = '0000000000'; if V A >V B The comparator's output voltage V COMP ='0'.

[0011] Furthermore, when the first cycle of CLK arrives, the D flip-flop output signal KILL = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '1000000000'. At this time, the switching transistor M of the voltage divider module... N1 Open, V B =V0; When the second cycle of CLK arrives, the input voltage V of the comparator is at this time. A And V0, if V A If V0 > 0, then the D flip-flop output signal Q = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '0100000000'. At this time, the switching transistor M of the voltage divider module... N2 Open, V B =V1; When the third cycle of CLK arrives, the input voltage V of the comparator is at this time. A And V1, if V A If V1 >, then the D flip-flop output signal KILL = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '0010000000'. At this time, the switching transistor M of the voltage divider module... N3 Open, V B =V2; and so on, until V A <V n n = 0 to 9, the comparator's output voltage V COMP ='1', the output signal KILL of the D flip-flop of the comparator module is '1'. After passing through the two-input OR gate, the reference clock REF_CLK is masked, and the state of the output signals Q0~Q9 of the register module remains unchanged, VB = V n (n = 0 ~ 9) will be fed into the loop control core circuit, and the entire DC-DC converter will be in DCM mode, VB = V n (n=0~9) will reduce the overall operating frequency of the DC-DC converter and improve efficiency under light load.

[0012] The advantages and beneficial effects of this invention are as follows:

[0013] 1. This invention improves the efficiency of phase-locked loop (PLL) based DC-DC circuits under light load conditions. Since the PLL plays a role throughout the entire DC-DC circuit, it maintains a constant switching frequency under light load. However, in DCM mode, a constant switching frequency increases switching losses, severely impacting DC-DC efficiency. The successive approximation control module used in this invention automatically finds a control voltage V that matches the current load. B Reduce the switching frequency.

[0014] 2. Meets low power consumption requirements. The comparator module and register module in the successive approximation control module consume zero static power in a steady state. This is achieved by increasing the resistors R0 to R1 in the voltage divider module. 10 The resistance value is adjusted to keep the power consumption of the entire successive approximation control module in the nA level.

[0015] 3. Output voltage V B High precision, minimally affected by process temperature. The voltage V obtained from the voltage divider module of the successive approximation control module... n (n = 0 to 9) depends only on the resistance R0 to R 10 The ratio is not the value of the resistor itself.

[0016] 4. In the successive approximation control module, a D flip-flop with a set signal was added before the 10-bit register of the register module. This cleverly generated a digital signal '1' which was sent into the 10-bit register, causing the digital signal '1' to sequentially turn on the switching transistor M. N1 ~M N9 When the reference clock REF_CLK period arrives, V is assigned B Different V n (n = 0 to 9). Attached Figure Description

[0017] Figure 1 This invention provides a preferred embodiment of the DC-DC overall circuit structure;

[0018] Figure 2 Successive approximation control module;

[0019] Figure 3 Loop control core circuit;

[0020] Figure 4 Phase-locked loop circuit structure. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0022] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0023] like Figure 1 As shown: A successive approximation control circuit for DC-DC discontinuous conduction mode mainly includes a successive approximation control module, a loop control core circuit, a non-overlapping clock, an RS flip-flop, a DCM / CCM mode selector, a rising edge detection circuit, a data selector, and a phase-locked loop.

[0024] Preferably, the loop control core circuit includes a comparator and a constant on-time generator, when the feedback voltage V FB <V REF The comparator will make V S ='1', after the conduction time TON, the constant conduction time generator will make V = '1', R ='1'.

[0025] Preferably, the phase-locked loop includes a frequency and phase detector and a charge pump. When the DC-DC circuit is in CCM mode, the frequency and phase detector is used to detect the reference clock REF_CLK and the drive signal V. GH The frequency and phase difference are then used to calculate the phase difference signal, which is then fed into a charge pump circuit. The charge pump circuit adjusts V... A Voltage value to ensure that the reference clock REF_CLK is consistent with the drive signal V GH The frequencies are the same.

[0026] Preferably, in the voltage divider module of the successive approximation control module, R0~R 10 Resistors in series, and switching transistor M N1 ~M N9 The drain of the transistor is connected to the upper end of the resistor, and the switching transistor M... N1 ~M N9 The gate voltage is 10, which is the output voltage Q0~Q9 of the shift register, and the switching transistor M N1 ~M N9 The source voltages are connected together.

[0027] Preferably, in the register module of the successive approximation control module, the input voltages of the two-input OR gate are the reference clock REF_CLK and the output voltage KILL of the D flip-flop in the comparison module. The D terminal of the D flip-flop with reset is connected to GND, the clock signal is connected to the output signal CLK of the two-input OR gate, and the set signal is connected to the output signal V of the rising edge detection circuit. RST The input voltage of the 10-bit shift register is the output signal V of the rising edge detection circuit. RST The output signal CLK of the two-input OR gate, the output signal Q of the D flip-flop with set function, and the output signals Q0~Q9 of the 10-bit shift register are connected to the switching transistor M of the voltage divider module. N1~M N9 The gate.

[0028] Preferably, the positive input of the dynamic comparator in the comparison module of the successive approximation control module is the output voltage V of the voltage divider module. B The negative input is the output voltage V of the phase-locked loop. A The output voltage of the dynamic comparator is connected to the D terminal of the D flip-flop. The clock signal of the D flip-flop is connected to the output signal CLK of the two-input OR gate. The reset signal of the D flip-flop is connected to the output signal V of the rising edge detection circuit. RST The output signal of the D flip-flop is KILL, which serves as the input signal for the two-input OR gate of the register module.

[0029] Preferably, when the DC-DC converter enters DCM mode, the rising edge detection circuit detects V. G At the rising edge, the output signal V RST The successive approximation control module will be reset and set. When V RST After resetting the D flip-flop of the comparator module, its output voltage KILL = '0'. At this time, the output signal CLK of the two-input OR gate is REF_CLK. At the same time, the output signal Q of the D flip-flop with the set signal in the register module is '1', and the output signals Q0~Q9 of the 10-bit shift register are '0000000000'.

[0030] Preferably, if V A >V B The comparator's output voltage V COMP ='0', when the first cycle of CLK arrives, the D flip-flop output signal KILL of the comparator module is '0', and the output signals Q0~Q9 of the register module are '1000000000'. At this time, the switching transistor M of the voltage divider module... N1 Open, V B =V0. When the second cycle of CLK arrives, the comparator's input voltage V is at this time. A And V0, if V A If V0 > 0, then the D flip-flop output signal Q = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '0100000000'. At this time, the switching transistor M of the voltage divider module... N2 Open, V B =V1.

[0031] Preferred, and so on, until V A <V n (n = 0 ~ 9), the comparator's output voltage V COMP='1', the D flip-flop output signal KILL ='1' of the comparator module, after passing through the two-input OR gate, the reference clock REF_CLK is masked, and the state of the output signals Q0~Q9 of the register module remains unchanged, V B =V n (n = 0 ~ 9) will be fed into the loop control core circuit, and the entire DC-DC converter will be in DCM mode, V B =V n (n=0~9) will reduce the overall operating frequency of the DC-DC converter and improve efficiency under light load.

[0032] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0033] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0034] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A successive approximation control circuit for DC-DC discontinuous conduction mode, characterized in that, include: The circuit consists of a successive approximation control module, a loop control core circuit, a non-overlapping clock, an RS flip-flop, a DCM / CCM mode selector, a rising edge detection circuit, a data selector, and a phase-locked loop (PLL). The PLL's input signals are the reference clock REF_CLK and the drive signal V. GH The output signal is V A The input signal of the successive approximation control module is the phase-locked loop's output signal, V. A With reference clock REF_CLK, the output signal is V. B The input signals of the data selector come from the output signal V of the phase-locked loop. A The output signal of the successive approximation control module is V B The output signal is V CTRL The input signal of the core circuit of the loop control is the feedback signal V. FB Reference voltage V REF and the output signal V of the data selector CTRL The input signal of the RS flip-flop comes from the output signal V of the loop control core circuit. R and V S The output signal is V PWM The input signal for the non-overlapping clock is the duty cycle signal V. PWM The output signals are the drive signal V. GH and drive signal V GL The output signal of the DCM / CCM mode selector is V. G The input signal to the rising edge detection circuit is the output signal of the DCM / CCM mode selector, which is V. G The output signal is V RST The main function of the core circuit of the loop control is to amplify the feedback signal V. FB and reference signal V REF The difference between them is then used to generate a duty cycle signal V based on the control algorithm. PWM The feedback resistor R of the loop control core circuit adjustment system f1 So that the feedback signal V FB Approaching the reference signal V REF And maintain system stability; A phase-locked loop is used when the DC-DC converter is in continuous conduction mode (CCM) to enable the operating frequency F. SW Maintain stability, V CTRL =V A V CTRL V represents the output signal of the digital selector. A This represents the output signal of the phase-locked loop (PLL). The successive approximation control module is used to find a voltage VA close to the PLL's output voltage as the input signal V of the voltage control core circuit when the DC-DC converter is in discontinuous conduction mode (DCM). CTRL At this time, V CTRL =V B， V B This represents the output signal of the successive approximation control module; the non-overlapping clock is used to prevent the input voltage from being directly connected to GND and causing losses when the high-side MOS and low-side MOS are simultaneously turned on; the continuous conduction mode (CCM) / discontinuous conduction mode (DCM) selector is used to determine the operating mode of the DC-DC circuit; the rising edge detection circuit is used to detect V. G The rising edge of the signal simultaneously outputs the signal V. RST The successive approximation control module will be reset; the RS flip-flop is used to generate the duty cycle signal V required by the DC-DC circuit. PWM The data selector is used to select the appropriate output signal V. CTRL When the DC-DC circuit is in CCM mode, V CTRL =V A When the DC-DC circuit is in DCM mode, V CTRL =V B ; The core circuit of the loop control includes a comparator and a constant on-time generator, wherein the negative input terminal of the comparator is connected to the feedback voltage V. FB The positive input terminal is connected to the reference voltage V. REF The output voltage is V S The input voltage feedback voltage V of the constant on-time generator FB The output signal is V R When the feedback voltage V FB <V REF V REF Indicating the reference voltage, the comparator will cause V to... S ='1',V S This represents the comparator's output voltage; after the on-time TON, the constant on-time generator will cause V to... R ='1';V R This represents the output voltage of a constant on-time generator; The successive approximation control module includes a voltage divider module, a register module, and a comparison module, wherein the voltage divider module consists of resistors R0~R 10 Switching transistor M N1 ~M N9 The register module consists of a 10-bit shift register, a D flip-flop with set function, and a two-input OR gate; the comparator module consists of a dynamic comparator and a D flip-flop with reset function; the voltage divider module has R0~R... 10 Resistors in series, and switching transistor M N1 ~M N9 The drains are connected sequentially to R0~R 10 At the resistor series connection point, the switching transistor M N1 ~M N9 The gate voltage is 10, which is the output voltage Q0~Q9 of the shift register, and the switching transistor M N1 ~M N9 The source voltages are connected together; the input voltages of the two-input OR gate in the register module are the reference clock REF_CLK and the output voltage KILL of the D flip-flop in the comparator module. The D terminal of the D flip-flop with set is connected to GND, the clock signal is connected to the output signal CLK of the two-input OR gate, and the set signal is connected to the output signal V of the rising edge detection circuit. RST The input voltage of the 10-bit shift register is the output signal V of the rising edge detection circuit. RST The output signal CLK of the two-input OR gate, the output signal Q of the D flip-flop with set function, and the output signals Q0~Q9 of the 10-bit shift register are connected to the switching transistor M of the voltage divider module. N1 ~M N9 The gate of the voltage divider module; the positive input of the dynamic comparator in the comparator module is the output voltage V of the voltage divider module. B The negative input is the output voltage V of the phase-locked loop. A The output voltage of the dynamic comparator is connected to the D terminal of the D flip-flop. The clock signal of the D flip-flop is connected to the output signal CLK of the two-input OR gate. The reset signal of the D flip-flop is connected to the output signal V of the rising edge detection circuit. RST The output signal of the D flip-flop is KILL, which serves as the input signal for the two-input OR gate of the register module.

2. The successive approximation control circuit for DC-DC discontinuous conduction mode according to claim 1, characterized in that, The phase-locked loop includes a frequency and phase detector and a charge pump, wherein the input signals of the frequency and phase detector are a reference clock REF_CLK and a drive signal V. GH The output signals are UP and DOWN. The input voltage of the charge pump is the output signals UP and DOWN of the frequency and phase detector, and the output signal is the control signal V. A When the DC-DC circuit is in CCM mode, the frequency and phase detector is used to detect the reference clock REF_CLK and the drive signal V. GH The frequency and phase difference are then used to calculate the phase difference signal, which is then fed into a charge pump circuit. The charge pump circuit adjusts V... A Voltage value to ensure that the reference clock REF_CLK is consistent with the drive signal V GH The frequencies are the same.

3. The successive approximation control circuit for DC-DC discontinuous conduction mode according to claim 1, characterized in that, The voltage divider module is connected to resistors R0~R 10 For power supply voltage V DD The voltage is divided, and the switching transistor M is controlled by the output signals Q0~Q9 of the 10-bit shift register. N1 ~M N9 To generate different voltages V B ; When the DC-DC converter enters DCM mode, the rising edge detection circuit detects V. G At the rising edge, the output signal V RST It will perform reset and set operations on the successive approximation control module; when V RST After resetting the D flip-flop of the comparator module, its output voltage KILL = '0'. At this time, the output signal CLK of the two-input OR gate = REF_CLK, and the output signal Q of the D flip-flop with the set signal in the register module = '1', and the output signals Q0~Q9 of the 10-bit shift register = '0000000000'; if V A >V B The comparator's output voltage V COMP ='0'.

4. The successive approximation control circuit for DC-DC discontinuous conduction mode according to claim 3, characterized in that, When the first cycle of CLK arrives, the D flip-flop of the comparator module outputs signal KILL='0', and the output signals Q0~Q9 of the register module equal '1000000000'. At this time, the switching transistor M of the voltage divider module... N1 Open, V B =V0; When the second cycle of CLK arrives, the input voltage V of the comparator is at this time. A And V0, if V A If V0 > 0, then the D flip-flop output signal Q = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '0100000000'. At this time, the switching transistor M of the voltage divider module... N2 Open, V B =V1; When the third cycle of CLK arrives, the input voltage V of the comparator is... A And V1, if V A If V1 >, then the D flip-flop output signal KILL = '0' of the comparator module, and the output signals Q0~Q9 of the register module = '0010000000'. At this time, the switching transistor M of the voltage divider module... N3 Open, V B =V2; and so on, until V A <V n n=0~9, the comparator's output voltage V COMP ='1', the output signal KILL of the D flip-flop of the comparator module is '1'. After passing through the two-input OR gate, the reference clock REF_CLK is masked, and the state of the output signals Q0~Q9 of the register module remains unchanged, VB=V n The signal will be fed into the core loop control circuit, and the entire DC-DC converter will be in DCM mode, where VB=V. n It will reduce the overall operating frequency of the DC-DC converter and improve efficiency under light load.

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