Four-level active neutral point clamped inverter topology and modulation strategy, medium

Abstract

The application relates to the electrical field, in particular to a four-level active neutral point clamped inverter topology and modulation strategy and medium, which comprises a direct current input source, three series direct current bus capacitors and three-phase circuits in parallel with the direct current bus capacitors, each phase of the three-phase circuits is composed of three pairs of complementary switch tubes, the voltage stress borne by the switch tube with the maximum current flowing through the outside of the four-level active neutral point clamped topology is low, the four switch tubes with smaller current flowing through the inside bear high voltage stress, therefore, the loss distribution is more uniform, the heat dissipation of the circuit is facilitated and the working time limit is prolonged. The simplified four-level space vector voltage balance modulation strategy is based on the widely used two-level SVPWM and three-level SVPWM, the realization process is simple, the calculation amount is low, and the three capacitor voltages on the direct current side can be effectively balanced.

Description

Technical Field

[0001] This invention relates to the field of electrical engineering, and more particularly to a four-level active midpoint clamp inverter topology, modulation strategy, and dielectric. Background Technology

[0002] Multilevel inverters are widely used in various fields such as new energy power generation, rail transportation, electric vehicles, uninterruptible power supplies (UPS), and aerospace. Currently, three-level and five-level inverters are more common in the industrial sector, while four-level inverters are less common. However, with increasing and in-depth research, their application is gradually being promoted. Schneider Electric successfully commercialized a four-level inverter in 2016 for use in UPS products. Compared to three-level inverters, four-level inverters have lower harmonic distortion (THD) and lower voltage change rate (dv / dt). Compared to five-level inverters, four-level inverters have fewer DC-side capacitors and switching devices, offering greater advantages in terms of cost, losses, and size. Overall, four-level inverters have more balanced performance indicators and broad application prospects in the industrial field.

[0003] Four-level inverter topologies include flying capacitor type, diode clamp type, and midpoint clamp type. Among these, the four-level midpoint clamp inverter topology is relatively simple, with no flying capacitor and few or no diodes, making it more suitable for low-voltage, high-power applications. Existing four-level midpoint clamp inverter topologies mainly include 4L-DT (…). Figure 1 ), 4L-Nested Figure 2 ), 4L-NPC ( Figure 3 ), 4L-ANPC Figure 4 ), 4L-HNPC Figure 5 Most four-level neutral-clamp inverter topologies use only six switching transistors per phase, but a few topologies use more switching transistors or diodes. These topologies face challenges such as uneven voltage stress, uneven loss distribution, or high total loss. The performance requirements also vary depending on the application scenario, thus further optimization and improvement are still needed to enhance inverter performance and expand application scenarios.

[0004] On the other hand, all four-level neutral-point clamped inverter topologies share a common characteristic: their DC bus consists of three capacitors connected in series, thus forming two neutral points. Compared to three-level neutral-point clamped inverter topologies, four-level neutral-point clamped inverter topologies have an additional neutral point, which makes the DC bus capacitor voltage imbalance problem more prominent and its capacitor voltage balance control more difficult.

[0005] Space Vector Modulation (SVPWM) is easy to implement digitally, has high voltage utilization, and low switching losses, making it one of the main modulation methods for multilevel inverters. SVPWM generally consists of the following four steps: determining the sector where the reference vector is located, determining the sub-interval to identify the three basic vectors, calculating the duration of the basic vectors, and determining the switching sequence of the basic vectors. These steps need to be performed once within each switching cycle. n-level SVPWM can synthesize n... 3 There are n vectors, of which (3n(n-1)+1) are valid vectors, and (n-1) are valid vectors within each sector. 2 A small interval, Figure 7 and Figure 8 The space vector distributions of three-level and four-level SVPWM are shown respectively. Clearly, as the level order increases, the complexity and computational cost of implementing SVPWM increase dramatically.

[0006] In SVPWM with three or more levels, all switching states of some vectors cause one or more capacitors to continuously discharge or charge, further exacerbating the voltage imbalance problem. Although Virtual Space Vector Modulation (VSVPWM) can solve this problem, VSVPWM has higher complexity and computational load, especially at high levels. Therefore, it is urgent to explore a modulation strategy that can simplify four-level SVPWM while balancing the bus capacitor voltage. Summary of the Invention

[0007] The improved topology of the four-level midpoint clamp inverter and the simplified SVPWM method with capacitor voltage balancing disclosed in this patent are divided into two parts: one is the improved topology of the four-level midpoint clamp inverter, and the other is the simplified SVPWM method with capacitor voltage balancing.

[0008] A four-level active midpoint clamped inverter topology, including a DC input source U dc A three-phase circuit consisting of three series-connected DC bus capacitors C1, C2, and C3, and input DC bus capacitors C1, C2, and C3 connected in parallel. Each phase of the three-phase circuit is composed of three pairs of complementary switching transistors (S...). x1 ,S x1 '), (S x2 ,S x2 '), (S x3 ,S x3 It consists of three phases, a, b, and c.

[0009] Preferably, the switching transistor S x1 Switch S x2After being connected in series, it is connected in parallel with the DC bus capacitors C1 and C2; the switching transistor S x2 Switch S x3 After being connected in series, it is connected in parallel with the DC bus capacitors C2 and C3; the switching transistor S x3 Switch S x1 After being connected in series, one end is connected to the series-connected switching transistor S. x1 and switching transistor S x2 The middle connection node is connected to the other end of the series-connected switching transistor S. x2 and switching transistor S x3 The intermediate connecting node of '.

[0010] A vector voltage balance modulation strategy, applicable to a four-level active midpoint clamp inverter topology, is characterized by comprising:

[0011] Three-level SVPWM is used to generate switching signals to control the complementary switch (S x1 ,S x1 '), (S x3 ,S x3 The on / off state of ').

[0012] When a three-level SVPWM outputs positive and negative levels, that is, it outputs ±U dc / 2, and (S) x2 ,S x2 ') is irrelevant; when the output is zero level, it depends on (S) x2 ,S x2 The on / off state of ') outputs ±U dc / 6, the zero-level duration is called (S) x2 ,S x2 Effective on / off time;

[0013] During the zero-level action time T x0 Within the region (x = a, b, c), let S x2 Effective conduction time T x+ and effective shutdown time T x- If they are equal, then...

[0014]

[0015] Assuming the current is constant, the integral of the current flowing through capacitor C2 is zero during this time, and the increase and decrease of the voltage across capacitor C2 are equal, so the voltage remains constant.

[0016] Because the voltage change is symmetrical and the time is relatively short compared to the switching cycle, the integral of the output voltage with respect to time is zero. According to the principle of area equivalence, it is equivalent to a zero-level output, which can synthesize a reference voltage vector. The output voltage of the inverter is consistent with the reference input voltage of the three-level SVPWM.

[0017] Preferably, when the output voltage ±U dc When / 2, the charging and discharging of the middle capacitor C2 is consistent with the charging and discharging of the upper and lower capacitors C1 and C3.

[0018] When the output voltage ±U dc When the voltage is 6, only the intermediate capacitor C2 is charging and discharging. The voltage can be determined based on the direction of the current.

[0019] 1) Output U dc / 6,S x2 On, S x2 When the inverter is turned off, capacitor C2 discharges and the voltage drops when current flows out of the four-level midpoint clamp inverter; conversely, capacitor C2 charges and the voltage rises.

[0020] 2) Output -U dc / 6,S x2 Off, S x2 'On. When current flows into the four-level midpoint clamp inverter, capacitor C2 discharges and the voltage drops; conversely, capacitor C2 charges and the voltage rises.'

[0021] Preferably, when using the intermediate capacitor C2 for voltage balance control, an adjustment factor k is introduced to adjust the charging and discharging time of C2. The modulation factor k is generated by a PI controller, and the voltage U of capacitor C2 is... C2 and U dc The deviation of / 3 is used as the input to the PI controller, and U C2 Balance in U dc / 3 around.

[0022] Preferably, when using upper and lower capacitors C1 and C3 for voltage balance control, an adjustment factor s is introduced to adjust the duration of the two redundant states of the internal small vector storage, replacing T1 / 4 with sT1 and T1 / 2 with (1-2s)T1. The modulation factor s is also generated by a PI controller, and the voltage U of capacitors C1 and C3 is... C1 and U C3 The deviation is used as the input to the PI controller to maintain U C1 and U C3 The dynamic equilibrium.

[0023] A readable storage medium storing computer-executable instructions that, when executed by a processor, configure the processor to perform the method described above.

[0024] Therefore, the present invention has the following advantages:

[0025] 1) In the improved four-level active midpoint clamp topology proposed in this invention, the voltage stress of the switch transistor with the largest current flowing on the outer side is low, while the voltage stress of the four switches transistors with smaller current flowing on the inner side is high. Therefore, the loss distribution is more uniform, which is beneficial to the heat dissipation of the circuit and extends the working time.

[0026] 2) The simplified four-level space vector voltage balance modulation strategy proposed in this invention is based on the widely used two-level SVPWM and three-level SVPWM. The implementation process is simple, the amount of calculation is low, and it can effectively balance the voltages of the three capacitors on the DC side. Attached Figure Description

[0027] Figure 1 This is a 4L-DT inverter topology;

[0028] Figure 2 It is a 4L-Nested inverter topology;

[0029] Figure 3 For 4L-NPC inverter topology;

[0030] Figure 4 This is a 4L-ANPC inverter topology;

[0031] Figure 5 For 4L-HNPC inverter topology;

[0032] Figure 6 This invention discloses the 4L-IANPC inverter topology.

[0033] Figure 7 This is a three-level space vector diagram;

[0034] Figure 8 This is a four-level space vector diagram;

[0035] Figure 9 The equivalent circuit of the 4L-IANPC inverter;

[0036] Figure 10 For the effective switching time of (Sx2, Sx2'), the voltage change is denoted as .

[0037] Figure 11 This refers to the generation of switching signals for a four-level midpoint clamp inverter in three-level SVPWM mode.

[0038] Figure 12 The principle of voltage balance control of the three capacitors under the three-level SVPWM mode;

[0039] Figure 13 The simulation results are for the 4L-IANPC inverter. Detailed Implementation

[0040] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0041] Example 1:

[0042] This embodiment relates to a four-level active midpoint clamp inverter topology, such as... Figure 6 As shown, each phase consists of three pairs of complementary switches (S... x1 ,S x1 '), (S x2 ,S x2 '), (S x3 ,S x3 It is composed of ')(x=a,b,c). Using S xi (i = 1, 2, 3) represents the switching function, S xi Conducting and S xi 'When turned off, it equals 1, S' xi Shut down and S xi 'When on, it equals 0.' The switching states corresponding to the four output levels are recorded in Table 1, and the equivalent circuits for the corresponding switching states are as follows: Figure 9 As shown.

[0043] The analysis results of the voltage stress borne by each switching transistor under different switching states are also listed in Table 1. It can be seen from the table that the outermost switching transistor S experiences the largest current. x1 'and S x3 It withstands the lowest voltage stress, while the four inner switching transistors S x1 S x2 S x2 '、S x3 The circuit has a relatively small current flow and is subjected to high voltage stress, so the circuit has a relatively uniform loss distribution.

[0044] Table 1. Switching states corresponding to each voltage level and voltage stress borne by the switching transistor

[0045]

[0046] Example 2:

[0047] This embodiment relates to a simplified four-level space vector voltage balance modulation strategy.

[0048] In a four-level neutral-point clamped inverter topology, when the output voltage ±U dc When the voltage is ±2, the charging and discharging of the middle capacitor C2 is consistent with that of the upper and lower capacitors C1 and C3; when the output voltage ±U dc When the current is 6, only the intermediate capacitor C2 is charging and discharging, and this is related to the direction of the current. Figure 9 As shown.

[0049] 1) Output Udc / 6(S x2 On, S x2 'Shutdown': When current flows out of the four-level midpoint clamped inverter, capacitor C2 discharges and the voltage drops; conversely, capacitor C2 charges and the voltage rises.

[0050] 2) Output -U dc / 6(S x2 Off, S x2 (Conduction): When current flows into the four-level midpoint clamp inverter, capacitor C2 discharges and the voltage drops; conversely, capacitor C2 charges and the voltage rises.

[0051] In other words, the additional charging and discharging of capacitor C2 only occurs at the output voltage ±U. dc At 6 o'clock, it is controlled by the complementary switch (S) x2 ,S x2 The on / off state of ') and the output voltage ±U dc When / 2, it is not subject to (S) x2 ,S x2 The effect of switching on and off. When the switching frequency is high, it is acceptable to assume that the current remains constant within a switching cycle.

[0052] To simplify the implementation of SVPWM while maintaining capacitor voltage balance, a three-level SVPWM is first used to generate switching signals to control the complementary switch (S...). x1 ,S x1 '), (S x3 ,S x3 The on / off state of the three-level SVPWM output. When the output is positive or negative, it is the output ±U. dc / 2, and (S) x2 ,S x2 ') is irrelevant; when the output is zero level, it depends on (S) x2 ,S x2 The on / off state of ') outputs ±U dc / 6, this period of time is called (S) x2 ,S x2 Effective on / off time of ').

[0053] During the zero-level action time T x0 Within the region (x = a, b, c), let S x2 Effective conduction time T x+ and effective shutdown time T x- They are equal, as shown in equation (1).

[0054]

[0055] Since the current is assumed to be constant, the integral of the current flowing through capacitor C2 during this time is zero. Therefore, the increase and decrease in voltage across capacitor C2 are equal, and the voltage remains constant. Figure 10 As shown in (a). On the other hand, as... Figure 10 As shown in (b), since the voltage change is symmetrical and the time is shorter than the switching period, the integral of the output voltage with respect to time is zero. According to the principle of area equivalence, it is equivalent to a zero-level output. Therefore, by using the simplified SVPWM method, the reference voltage vector can still be synthesized, and the output voltage of the inverter is consistent with the reference input voltage of the three-level SVPWM.

[0056] This simplified method essentially uses three-level SVPWM to modulate a four-level NPC inverter. Compared to four-level SVPWM, the computational load and complexity are greatly reduced. Figure 11 The detailed switching process is shown (reference vector located at...). Figure 7 (as shown in the image), in particular, (S) x2 ,S x2 The switching signal is generated directly from the result of three-level SVPWM, without the need for calculation or design of the switching sequence. However, attention should be paid to maintaining the switching between adjacent levels.

[0057] a) Voltage balance control of intermediate capacitor C2

[0058] Under ideal conditions, the simplified modulation method described above can keep the voltage of C2 balanced. However, in reality, factors such as the non-ideal characteristics of the switching devices, current variations during the switching cycle, and voltage deviations must be considered, and appropriate control is still necessary.

[0059] Therefore, an adjustment factor k is introduced to adjust the charging and discharging time of C2, and equation (1) is modified as follows:

[0060]

[0061] The modulation factor k is generated by a PI controller, and the voltage U of capacitor C2 is... C2 and U dc The deviation of / 3 is used as the input to the PI controller, and U C2 Balance in U dc Around / 3, its control principle is as follows Figure 12 As shown. After introducing k, Figure 11 China T x+ / 2 and T x- / 2 are respectively determined by kT x0 and (0.5-k)T x0 Instead, when the inverter is in steady-state operation, k stabilizes around 0.25.

[0062] b) Voltage balance control of upper and lower capacitors C1 and C3

[0063] In a four-level inverter topology, the sum of the currents at midpoints N1 and N2 is the same as the midpoint current in a three-level inverter. This affects the voltage balance of the upper and lower capacitors, so the control of the voltages of the upper and lower capacitors is similar to that of a three-level inverter. The advantage of using the simplified SVPWM strategy in this invention is that it allows for the direct application of the three-level SVPWM method to control the voltage balance of the upper and lower capacitors.

[0064] In the vector diagram of a three-level SVPWM, the internal small vectors have two redundant states, such as Figure 7 As shown, their effects on the voltage deviation of the upper and lower capacitors are exactly opposite. Without control, the duration of the two states is equal, both being T1 / 2, as... Figure 11 As shown. To keep the voltages of the upper and lower capacitors balanced, an adjustment factor s is introduced to adjust the duration of the two states. Figure 11 In the original text, T1 / 4 is replaced by sT1, and T1 / 2 is replaced by (1-2s)T1. The modulation factor s is also generated by a PI controller, and the voltage U across capacitors C1 and C3... C1 and U C3 The deviation is used as the input to the PI controller to maintain U C1 and U C3 The dynamic balance, its control principle is as follows: Figure 12 As shown. Because the voltages of the upper and lower capacitors inherently fluctuate within one fundamental frequency cycle, s will not stabilize near a fixed value, but will vary significantly.

[0065] Example 3:

[0066] This embodiment is a simulation demonstration.

[0067] To demonstrate the feasibility of simplifying the four-level SVPWM voltage balance modulation strategy, a simulation model was established using the 4L-IANPC topology proposed in this patent as an example, based on the simulation parameters in Table 2. The simulation results are as follows. Figure 13 As shown.

[0068] Table 2. Simulation parameters of the inverter

[0069]

[0070] The higher the power factor, the greater the voltage imbalance among the capacitors. Therefore, a purely resistive load was used for verification in the simulation. The initial voltages of capacitors C1 and C2 were 300V, and the initial voltage of capacitor C3 was 600V. Figure 13As can be seen, the voltage reaches equilibrium in about 0.1 seconds, k stabilizes at around 0.25, and the modulation factor s changes periodically within the limiting range. Simulation results show that the four-level active midpoint clamp inverter topology and the simplified four-level space vector voltage balance modulation strategy disclosed in this patent are feasible.

[0071] Example 4:

[0072] This embodiment relates to a readable storage medium storing computer-executable instructions that, when executed by a processor, configure the processor to perform the method described according to embodiment 2.

[0073] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0074] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0075] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0076] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0077] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0078] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A four-level active midpoint clamp inverter topology, characterized in that, Including DC input source U dc Three are connected in series in the DC input source U dc The DC bus capacitors C1, C2, and C3 between the positive and negative terminals, and the DC bus capacitors input to the three-phase circuit. C 1. C 2 and C 3. A three-phase circuit connected in parallel, wherein each phase consists of three pairs of complementary switching transistors. S x1 ,S x1 ' , S x2 , S x2 ' , S x3 ,S x3 ' Composition, in which, x for a , b , c Three phases; The switching transistor S x1 、 Switching transistor S x2 ' After being connected in series, it is connected to the DC bus capacitor in series. C 1. C 2 in parallel, switching transistors S x1 The upper end is connected to the positive terminal of the DC bus capacitor C1, and the switching transistor... S x2' The lower end is connected to the negative terminal of the DC bus capacitor C2; the switching transistor S x2 、 Switching transistor S x3 ' After series ， With series DC bus capacitor C 2. C 3 in parallel, switching transistors S x2 The upper end is connected to the positive terminal of the DC bus capacitor C2, and the switching transistor... S x3' The lower end is connected to the negative terminal of the DC bus capacitor C3; the switching transistor S x3 、 Switching transistor S x1 ' After being connected in series, the switching transistor S x3 The upper end is connected to the series-connected switching transistors. S x1 and switching transistor S x2 ' intermediate connection node, switching transistor S x1' The lower end is connected to the series-connected switching transistors. S x2 and switching transistor S x3 ' The intermediate connecting node.

2. A vector voltage balance modulation strategy, applicable to the four-level active neutral-point clamped inverter topology as described in claim 1, characterized in that, Three-level SVPWM is used to generate switching signals to control complementary switching transistors. S x1 ,S x1 ' , S x3 ,S x3 ' On / off; When a three-level SVPWM outputs a positive or negative level, that is, when it outputs ± U dc / 2, and S x2 ,S x2 ' It is irrelevant; when the output is at zero level, it depends on... S x2 ,S x2 ' On / off state, output ± U dc / 6, the duration of the zero level is called S x2 ,S x2 ' Effective on / off time; During the zero-level action time T x0 Inside, x = a , b , c ,make S x2 Effective conduction time T x+ and effective shutdown time T x- If they are equal, then... Assuming the current is constant, therefore the current flowing through the capacitor... C The current of capacitor 2 integrals to zero during this time interval. C 2. The increase and decrease in voltage are equal, and the voltage remains constant. Because the voltage change is symmetrical and the time is relatively short compared to the switching cycle, the integral of the output voltage with respect to time is zero. According to the principle of area equivalence, it is equivalent to a zero-level output, which can synthesize a reference voltage vector. The output voltage of the inverter is consistent with the reference input voltage of the three-level SVPWM.

3. The vector voltage balance modulation strategy according to claim 2, characterized in that, When the output voltage ± U dc When / 2, the intermediate capacitor C 2. Charging and discharging and upper and lower capacitors C 1 and C 3. The charging and discharging are consistent; When the output voltage ± U dc When the value is 6, only the intermediate capacitor is present. C 2. During charging and discharging, determine the voltage based on the direction of the current: 1) Output U dc / 6, S x2 Conductive, S x2 ' When the four-level midpoint clamp inverter is shut off, the capacitor... C 2. Discharge, voltage drops; Conversely, the capacitor C 2. During charging, the voltage increases; 2) Output - U dc / 6, S x2 Turn off, S x2 ' When the four-level midpoint clamp inverter is turned on, the capacitor... C 2. Discharge, voltage drops; Conversely, the capacitor C 2. During charging, the voltage increases.

4. The vector voltage balance modulation strategy according to claim 3, characterized in that, When using intermediate capacitors C 2. When performing voltage balance control, an adjustment factor k is introduced to adjust the voltage. C The charge / discharge time of 2 is adjusted by a factor k generated by a PI controller, and the capacitor... C 2 voltage U C2 and U dc The deviation of / 3 is used as the input to the PI controller. U C2 Balance U dc / 3 around.

5. The vector voltage balance modulation strategy according to claim 3, characterized in that, When using upper and lower capacitors C 1 and C 3. When performing voltage balance control, an adjustment factor s is introduced to adjust the duration of the two redundant states of the internal small vector. sT1 replaces T1 / 4, and (1-2s)T1 replaces T1 / 2. T1 represents the sum of the durations of the two redundant states. The adjustment factor s is also generated through a PI controller. (The capacitor...) C 1 and C 3 voltage U C1 and U C3 The deviation is used as the input to the PI controller to maintain U C1 and U C3 The dynamic equilibrium.

6. A readable storage medium, characterized in that, The system stores computer-executable instructions that, when executed by a processor, configure the processor to perform the vector voltage balance modulation strategy according to any one of claims 2-5.

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