doherty amplifier

Abstract

The present invention relates to a Doherty amplifier. The present invention also relates to a packaged amplifier that can be used in the amplifier. The present invention proposes the use of a slot formed in a single output lead that is associated with two peak power transistors included in a single package. The slot suppresses the common push-pull type oscillation in dual peak power transistor solutions.

Description

Technical Field

[0001] This invention relates to a Dougherty amplifier. The invention also relates to a packaged amplifier that can be used in this amplifier. Background Technology

[0002] Doherty amplifiers are known in the art. Examples of known Doherty amplifiers include printed circuit boards (PCBs). Doherty splitters are disposed on and / or at least partially implemented on a PCB and are used to receive radio frequency (RF) signals and split the received RF signals into a main RF signal and a peak RF signal. A packaged main amplifier is mounted on the PCB. The packaged main amplifier includes: a main input lead for receiving the main RF signal, a main power transistor for amplifying the main RF signal, and a main output lead for outputting the main RF signal amplified by the main power transistor. Furthermore, a packaged peak amplifier is mounted on the PCB. The packaged peak amplifier includes: a peak input lead assembly for receiving the peak RF signal, a first peak power transistor for amplifying a portion of the peak RF signal, a second peak power transistor for amplifying the remaining portion of the peak RF signal, and a peak output lead. The peak output lead is used to combine the portion of the peak RF signal amplified by the first peak power transistor and the remaining portion of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal.

[0003] Known Dougherty amplifiers also include Dougherty combiners, which are disposed on and / or at least partially implemented on a printed circuit board, and are used to combine the amplified main RF signal and the amplified peak RF signal into an RF output signal and output the RF output signal.

[0004] Thanks to the high power density of GaN technology, base station RF power amplifier transistors are now being developed towards small, single-package designs with high power capabilities.

[0005] To provide sufficient power, high-power GaN transistors typically require a large gate perimeter. For example, for devices above 700W, the total gate width required for the peak path of a Doherty amplifier can even approach 60mm.

[0006] GaN semiconductor dies with integrated power transistors typically have large gate perimeters, which often introduces numerous challenges in product development and industrialization. For example, the yield of such semiconductor dies is relatively low. Dual-die configurations offer a solution to this problem.

[0007] Using large peripheral devices introduces unnecessary oscillation risks. Furthermore, push-pull oscillations may occur when using dual-power transistor solutions. Summary of the Invention

[0008] This invention provides a Doherty amplifier that solves at least one of these stability problems. To this end, the Doherty amplifier of claim 1 is provided. In the Doherty amplifier according to the invention, the peak output lead has an inner edge facing a first peak power transistor and a second peak power transistor, and an outer edge disposed opposite to the inner edge. The peak output lead includes a slot extending from the inner edge to the outer edge, and the length of the slot corresponds to A times the wavelength at the operating frequency of the Doherty amplifier, wherein A is in the range of 0.1 to 0.4.

[0009] The slot divides the peak output lead into a first section, a second section, and a common section. The first section is electrically connected to the first peak power transistor. The second section is electrically connected to the second peak power transistor. The common section is located between the outer edge and the first and second sections, and is integrally connected to both sections.

[0010] The slot ensures that a portion of the peak RF signal amplified by the first peak power transistor is combined with a portion of the peak RF signal amplified by the second peak power transistor in a common section.

[0011] The preferred length of the slot is between 1 / 8 and 1 / 4 of the wavelength at or near the operating frequency.

[0012] The applicant discovered that by using this slot, the risk of push-pull oscillations can be minimized or at least reduced. This is partly due to the increased inductance associated with the path from the outputs of the first and second peak power transistors to the common portion of the peak output leads. This increased inductance reduces the small-signal loop gain of the circuitry including the first and second peak power transistors, thereby improving the stability of the Doherty amplifier.

[0013] This application particularly relates to an asymmetric Doherty amplifier that operates in the frequency range between 1 GHz and 5 GHz and outputs power at a level exceeding 100 W, more preferably 300 W. The asymmetry of the Doherty amplifier, expressed as the ratio between the saturated output power of the peak amplifier and the saturated output power of the main amplifier, is preferably greater than 1.5:1, more preferably greater than 2:1.

[0014] Typically, each of the packaged main amplifier and the packaged peak amplifier may include a substrate. A main power transistor, a first peak power transistor, and a second peak power transistor are mounted on the substrate. Typically, these substrates are conductive and also serve as heat sinks. Various leads are fixed relative to the substrate. This can be achieved using an isolator disposed between the substrate and the leads. Alternatively, the body of the curing molding compound spacees the leads and the substrate. Furthermore, each of the packaged main amplifier and the packaged peak amplifier may include a cover to protect the various components within the package. The cover may also include a curing molding compound. In some packages, the molding compound used for the cover is the same molding compound used to fix the leads and the substrate. Additionally, in some embodiments, a cavity surrounds the power transistor within the package. Alternatively, in some embodiments, the molding compound encapsulates all components within the package.

[0015] In one embodiment, the packaged main amplifier and the packaged peak amplifier are packaged separately. However, in other embodiments, the main power transistor, the first peak power transistor, and the second peak power transistor are combined in a single package.

[0016] The first peak power transistor can be integrated on a first semiconductor die, and the second peak power transistor can be integrated on a second semiconductor die separate from the first semiconductor die. However, the present invention does not exclude embodiments in which the first peak power transistor and the second peak power transistor are integrated on the same semiconductor die. In some embodiments, the first peak power transistor and the second peak power transistor are different portions of a high-power transistor disposed on a single semiconductor die. Furthermore, the main power transistor can be integrated on a third semiconductor die separate from the first and second semiconductor dies.

[0017] The packaged main amplifier may include an input matching network disposed between the main input lead and the main power transistor, and / or an output matching network disposed between the main power transistor and the main output lead. The input matching network may include one or more impedance matching stages, wherein the relatively low input impedance of the main power transistor is converted to a higher impedance seen at the main input lead. The output matching network may also include an impedance matching stage that converts the relatively low output impedance to a higher level seen at the main output lead. The output matching network alternatively or additionally includes a shunt network comprising a series combination of an inductor and a capacitor. The latter network may be configured to resonate with the output capacitor of the main power transistor at or near the operating frequency of the Doherty amplifier.

[0018] Similarly, the packaged peak amplifier may include a first input matching network disposed between the peak input lead assembly and the first peak power transistor, and / or a first output matching network disposed between the first peak power transistor and the peak output lead. Alternatively or optionally, the packaged peak amplifier may include a second input matching network disposed between the peak input lead assembly and the second peak power transistor, and / or a second output matching network disposed between the second peak power transistor and the peak output lead.

[0019] Each of the first and second input matching networks can have the same function as the input matching network of the packaged main amplifier. Similarly, each of the first and second output matching networks can have the same function as the output matching network of the packaged main amplifier.

[0020] The Doherty amplifier may also include multiple first bond wires and / or multiple second bond wires. The multiple first bond wires connect the input terminals of the main power transistor to the main input lead directly or via an input matching network. The multiple second bond wires connect the output terminals of the main power transistor to the main output lead directly or via an output matching network. Similarly, the Doherty amplifier may also include multiple third bond wires and / or multiple fourth bond wires. The multiple third bond wires connect the input terminals of the first peak power transistor to the peak input lead assembly directly or via a first input matching network. The multiple fourth bond wires connect the input terminals of the second peak power transistor to the peak input lead assembly directly or via a second input matching network. Similarly, the Doherty amplifier may include multiple fifth bond wires and / or multiple sixth bond wires. The multiple fifth bond wires connect the output terminals of the first peak power transistor to a first portion of the peak output lead directly or via a first output matching network. The multiple sixth bond wires connect the output terminals of the second peak power transistor to a second portion of the peak output lead directly or via a second output matching network.

[0021] The peak input lead assembly may include a first peak input lead and a second peak input lead spaced apart from the first peak input lead. The first peak input lead is connected to the input terminal of a first peak power transistor using a plurality of third bonding wires, and the second peak input lead is connected to the input terminal of a second peak power transistor using a plurality of fourth bonding wires. The connection using the plurality of third and fourth bonding wires may be a direct connection or, for example, an indirect connection via the first and second input matching networks described above.

[0022] Furthermore, the Doherty splitter may include an input terminal for receiving RF signals, a main output terminal for outputting the main RF signal, and a peak output terminal for outputting the peak RF signal. In this case, the Doherty amplifier may include a first transmission line disposed between the peak output terminal and the first peak input lead, and a second transmission line disposed between the peak output terminal and the second peak input lead. The electrical lengths of the first and second transmission lines respectively correspond to B times the wavelength corresponding to the operating frequency of the Doherty amplifier, wherein B is in the range of 0.4 to 0.6. Preferably, the electrical lengths of the first and second transmission lines respectively correspond to a quarter wavelength at or near half the operating frequency.

[0023] The applicant discovered that, by using a first transmission line and a second transmission line, subharmonic oscillations associated with the voltage-dependent input capacitances of the first and second peak power transistors can be at least partially suppressed. This suppression can be further enhanced by electrically connecting a resistor between the first and second peak input leads.

[0024] A Doherty combiner may include an impedance inverter positioned between the output of the main power transistor and the combination node of the Doherty combiner. The impedance inverter may be formed from a quarter-wavelength transmission line corresponding to the operating frequency or an electrical equivalent of the operating frequency. At the operating frequency, the phase delay between the output of the first peak power transistor and the combination node may be substantially equal to 180 degrees * n1*, and at the operating frequency, the phase delay between the output of the second peak power transistor and the combination node may be substantially equal to 180 degrees * n2*, where n1 and n2 are each positive integers.

[0025] Doherty amplifiers may include a phase delay between the Doherty splitter and the peak input lead assembly. This phase delay ensures that the amplified main RF signal and the amplified peak RF signal are combined in phase at the combination node of the Doherty combiner.

[0026] According to a second aspect, the present invention provides a packaged amplifier. The packaged amplifier is configured to be mounted on a printed circuit board and includes: an input lead assembly for receiving an RF signal, a first power transistor for amplifying a portion of the RF signal, a second power transistor for amplifying the remaining portion of the RF signal, and an output lead. The output lead is used to combine a portion of the RF signal amplified by the first power transistor and the remaining portion of the RF signal amplified by the second power transistor into an amplified RF signal. The output lead has an inner edge facing the first and second power transistors, and an outer edge disposed opposite to the inner edge. The output lead includes a slot extending from the inner edge to the outer edge. The length of the slot corresponds to A times the wavelength corresponding to the operating frequency of the packaged amplifier, wherein A is in the range of 0.1 to 0.4.

[0027] The slot divides the output lead into a first portion, a second portion, and a common portion. The first portion is electrically connected to a first power transistor, the second portion is electrically connected to a second power transistor, and the common portion is located between the outer edge of the first and second portions and is integrally connected to both portions. The slot ensures that portions of the RF signal amplified by the first transistor and portions of the RF signal amplified by the second transistor are combined in the common portion. Preferably, the length of the slot is between 1 / 8 and 1 / 4 of the wavelength at or near the operating frequency.

[0028] The first power transistor can be integrated on the first semiconductor die, and the second power transistor can be integrated on the second semiconductor die, which is separate from the first semiconductor die.

[0029] According to a third aspect, the present invention provides a packaged amplifier. The packaged amplifier is configured to be mounted on a printed circuit board and includes: a main amplifier for receiving a main input lead of a main RF signal, a main power transistor for amplifying the main RF signal, and a main output lead for outputting the main RF signal amplified by the main power transistor. The packaged amplifier further includes a peak amplifier. The peak amplifier includes: a peak input lead assembly for receiving a peak RF signal, a first peak power transistor for amplifying a portion of the peak RF signal, a second peak power transistor for amplifying the remaining portion of the peak RF signal, and a peak output lead. The peak output lead is used to combine a portion of the peak RF signal amplified by the first peak power transistor and the remaining portion of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal.

[0030] The peak output lead has an inner edge facing the first peak power transistor and the second peak power transistor, and an outer edge disposed opposite to the inner edge. The peak output lead includes a slot extending from the inner edge to the outer edge. The length of the slot corresponds to A times the wavelength corresponding to the operating frequency of the packaged peak amplifier, where A is in the range of 0.1 to 0.4.

[0031] The slot divides the output lead into a first portion, a second portion, and a common portion, wherein the first portion is electrically connected to a first power transistor, the second portion is electrically connected to a second power transistor, and the common portion is disposed between the outer edge and the first and second portions and is integrally connected to the first and second portions. The slot ensures that a portion of the RF signal amplified by the first power transistor and a portion of the peak RF signal amplified by the second power transistor are combined in the common portion. The preferred length of the slot is between 1 / 8 and 1 / 4 of the wavelength at or near the operating frequency.

[0032] The first peak power transistor can be integrated on the first semiconductor die, the second peak power transistor can be integrated on the second semiconductor die which is separate from the first semiconductor die, and the main power transistor can be integrated on the third semiconductor die which is separate from the first semiconductor die and the second semiconductor die.

[0033] The packaged amplifier according to the second and third aspects of the present invention can be used in the aforementioned Doherty amplifier. Therefore, any features described in connection with the Doherty amplifier can be equally applied to the packaged amplifier according to the second and third aspects of the present invention. Attached Figure Description

[0034] The invention will now be described with reference to the accompanying drawings, wherein the same reference numerals are used to denote the same or similar parts.

[0035] Figure 1 An embodiment according to the invention is shown, in which a packaged amplifier according to the second aspect of the invention is used in the Doherty amplifier.

[0036] Figure 2 An embodiment of the Doherty amplifier according to the invention is shown, in which a packaged amplifier according to the second aspect of the invention is used. Detailed Implementation

[0037] Figure 1A Doherty amplifier 1 according to the present invention is shown. The Doherty amplifier 1 includes a packaged main amplifier 100 and a packaged peak amplifier 200, both mounted on a printed circuit board 300. The Doherty amplifier 1 includes a Doherty splitter 2, which receives an RF input signal RFin (RF... 输入 The signal is then split into a main RF signal and a peak RF signal. Doherty splitters 2 are known in the art and may be, for example, hybrid couplers and / or may include multiple transmission segments and / or lumped electrical elements.

[0038] Doherty splitter 2 has a main output and a peak output. The main output is connected to the main input lead 101 of the packaged main amplifier 100; and the peak output is connected via a transmission line having a characteristic impedance Z1 and an electrical length th1 to the first peak input lead 201A of the packaged amplifier 200, and via a transmission line having a characteristic impedance Z2 and an electrical length th2 to the second peak input lead 201B of the packaged peak amplifier 200. Alternatively, Doherty splitter 2 has two dedicated peak outputs for connecting to the first peak input lead 201A and the second peak input lead 201B respectively using the aforementioned transmission lines.

[0039] The transmission line is implemented in printed circuit board 300. Alternatively, the transmission line is implemented using a lumped equivalent, such as an LCL or CLC network with similar performance at half the operating frequency. The electrical lengths th1 and th2 preferably correspond to a quarter wavelength at half the operating frequency. The impedances Z1 and Z2 can be in the range of 40 to 70 ohms.

[0040] The Doherty amplifier 1 also includes a resistor, such as a surface mount device (SMD) resistor 203, mounted between the first peak input lead 201A and the second peak input lead 201B.

[0041] The packaged main amplifier 100 includes a semiconductor die 110. A main power transistor is integrated on the semiconductor die 110. Similarly, the packaged peak amplifier 200 includes a first semiconductor die 210 and a second semiconductor die 220. A first peak power transistor is integrated on the first semiconductor die 210. A second peak power transistor is integrated on the second semiconductor die 220. The packaged main amplifier 100 may also include a substrate 130, and the packaged peak amplifier 200 may also include a substrate 230. Substrates 130 and 230 may include, for example, a copper heat sink and can be used as an electrical ground during operation.

[0042] The packaged main amplifier 100 includes a main output lead 102. The packaged peak amplifier 200 includes a peak output lead 202. As shown, the peak output lead 202 includes a first portion 202A, a second portion 202B spaced apart from the first portion 202A by a slot 202C, and a common portion 202D integrally connected to the first portion 202A and the second portion 202B. The boundaries between portions 202A, 202B and the common portion 202D are indicated by dashed lines.

[0043] The length L1 of slot 202C is between 0.1 and 0.4 times the wavelength at the operating frequency of the Doherty amplifier. This length typically corresponds to 1 / 8 to 1 / 4 times the wavelength at the operating frequency of the Doherty amplifier. For example, when operating at around 2 GHz, the slot length is preferably 5 to 6 mm and the width is between 0.5 and 1 mm.

[0044] The main power transistor, as well as the first and second peak power transistors, can each be based on gallium nitride field-effect transistors (FETs) or silicon-based laterally diffused metal-oxide-semiconductor transistors (LDMOS), without excluding other transistor types and / or semiconductor material systems. Furthermore, the typical operating frequency range extends from 1 GHz to 5 GHz.

[0045] The packaged main amplifier 100 includes a passive semiconductor die 140A disposed between a main input lead 101 and a semiconductor die 110. More specifically, the passive semiconductor die 140A may include one or more capacitors, which, together with bond wires, form an impedance matching stage. The bond wires are formed on... Figure 1 The portions of the multiple first bonding wires are represented by straight lines. Some bonding wires extend between the main input lead 101 and the passive semiconductor die 140A, and some bonding wires extend between the passive semiconductor die 140A and the input terminal of the main power transistor.

[0046] Similarly, the packaged main amplifier 100 includes a passive semiconductor die 140B disposed between a semiconductor die 110 and a main output lead 102. This die may include a grounded capacitor connected to the output of the main power transistor on the semiconductor die 110 via a bond wire connection to the ungrounded terminal of the grounded capacitor. In this way, a shunt network is formed, comprising a series combination of inductors and capacitors. At the operating frequency, the shunt network behaves as an inductor resonating with the output capacitance of the main power transistor. As shown, the output of the main power transistor is also directly connected to the main output lead 102 using partial bond wires forming a plurality of second bond wires. Other topologies are not excluded, such as those in which the passive semiconductor die 140B includes additional capacitors, which, together with the bond wires, form one or more impedance matching stages between the output of the main power transistor and the main output lead 102. Typically, the circuitry between the output of the main power transistor and the main output lead 102 is referred to as the output matching network.

[0047] As shown in the figure, a similar network is provided in the packaged peak amplifier 200 using passive semiconductor dies 240A, 240B, 241A, and 241B. However, in this case, some bond wires corresponding to the first peak power transistor disposed on semiconductor die 210 are connected to the first portion 202A of the peak output lead 202, while some bond wires corresponding to the second peak power transistor disposed on semiconductor die 220 are connected to the second portion 202B of the peak output lead 202.

[0048] Peak output lead 202 and main output lead 102 are connected using a Doherty combiner 3. The Doherty combiner 3 combines the amplified main signal received from the main output lead 102 and the amplified peak signal received from the peak output lead 202 into an RF output signal. For example, the Doherty combiner 3 may include a component located at the output of the main power transistor and a component such as... Figure 2 The impedance inverters between the combined nodes C are shown. The impedance inverters can be implemented using quarter-wavelength transmission lines on the printed circuit board 300. Alternatively, the impedance inverters can be implemented using discrete components disposed on the printed circuit board 300. In a further embodiment, the formation of the impedance inverters takes into account the parasitic effects of bonding wires and packaging.

[0049] Typically, the Doherty combiner 3 provides a phase delay of an integer multiple of 180 degrees between the outputs of the first and second peak power transistors and the combination node C. This phase delay can be partially implemented using transmission lines on the printed circuit board 300.

[0050] The combined node C can be connected to the load ZL, optionally via one or more impedance inverters and / or other impedance matching stages. This combined node C forms the output of the Doherty amplifier 1 or is connected to the output of the Doherty amplifier 1.

[0051] Doherty splitter 2 introduces an appropriate phase delay so that at the operating frequency, the signals amplified by the main power transistor and by the first peak power transistor and the second peak power transistor are added in phase at the combination node C.

[0052] exist Figure 1 The image shows two separate packages, 100 and 200. Figure 2 In the Doherty amplifier 10 shown, the main power transistor, the first peak power transistor, and the second peak power transistor are combined in a single package 400. Figure 2 The same method is used in the embodiments. Figure 1 The components shown are, in addition to the multiple substrates that have been replaced by a single substrate 430.

[0053] Furthermore, the Doherty combiner 3 is represented by impedance inverters Z1 and Z3, and an offset line Z2. Typically, these components are implemented at least partially on a printed circuit board. As described above, the phase delay required for Doherty operation can be implemented at least partially within the package 400.

[0054] Various Doherty configurations are known in the art. It should be noted that this invention is not limited to a specific configuration. For example, this invention also relates to conventional Doherty configurations, inverted Doherty configurations, or parallel Doherty configurations. The main difference between these configurations lies in the implementation of the Doherty combiner 3.

[0055] In summary, the present invention has been described using detailed embodiments. However, the invention is not limited to these embodiments. Rather, various modifications are possible without departing from the scope of this application, which is defined by the appended claims and their equivalents.

Claims

1. A Dougherty amplifier, comprising: The packaged main amplifier includes: a main input lead for receiving a main radio frequency signal, a main power transistor for amplifying the main radio frequency signal, and a main output lead for outputting the main radio frequency signal amplified by the main power transistor. A packaged peak amplifier, the packaged peak amplifier comprising: a peak input lead assembly for receiving a peak radio frequency signal; a first peak power transistor for amplifying a portion of the peak radio frequency signal; a second peak power transistor for amplifying a remaining portion of the peak radio frequency signal; and a peak output lead for combining a portion of the peak radio frequency signal amplified by the first peak power transistor and a remaining portion of the peak radio frequency signal amplified by the second peak power transistor into an amplified peak radio frequency signal; and A Dougherty combiner, wherein the Dougherty combiner is used to combine the amplified main radio frequency signal and the amplified peak radio frequency signal into a radio frequency output signal, and output the radio frequency output signal; The peak output lead has an inner edge facing the first peak power transistor and the second peak power transistor, and an outer edge opposite to the inner edge. The peak output lead includes a slot extending from the inner edge to the outer edge, the length of which corresponds to A times the wavelength at the operating frequency of the Dougherty amplifier, where A is in the range of 0.1 to 0.

4. The slot divides the peak output lead into a first portion, a second portion, and a common portion. The first portion is electrically connected to the first peak power transistor, the second portion is electrically connected to the second peak power transistor, and the common portion is disposed between the outer edge and the first and second portions and is integrally connected to the first and second portions. The slot ensures that a portion of the peak radio frequency signal amplified by the first peak power transistor is combined with a portion of the peak radio frequency signal amplified by the second peak power transistor in the common portion.

2. The Dougherty amplifier according to claim 1, comprising: A printed circuit board on which the packaged main amplifier and the packaged peak amplifier are mounted; as well as A Dougherty splitter, wherein the Dougherty splitter is disposed on the printed circuit board and / or at least partially implemented in the printed circuit board, and is used to receive radio frequency signals and split the received radio frequency signals into the main radio frequency signal and the peak radio frequency signal; The Dougherty combiner is disposed on the printed circuit board and / or at least partially implemented in the printed circuit board.

3. The Dougherty amplifier according to claim 1, wherein, The main power transistor, the first peak power transistor, and the second peak power transistor are combined in a single package.

4. The Dougherty amplifier according to claim 1, wherein, The first peak power transistor is integrated on the first semiconductor die, and the second peak power transistor is integrated on the second semiconductor die, which is separate from the first semiconductor die.

5. The Dougherty amplifier according to claim 4, wherein, The main power transistor is integrated on a third semiconductor die, which is separate from the first semiconductor die and the second semiconductor die.

6. The Dougherty amplifier according to claim 1, wherein, The packaged main amplifier includes an input matching network disposed between the main input lead and the main power transistor, and / or an output matching network disposed between the main power transistor and the main output lead.

7. The Dougherty amplifier according to claim 1, wherein, The packaged peak amplifier includes a first input matching network disposed between the peak input lead assembly and the first peak power transistor, and / or a first output matching network disposed between the first peak power transistor and the peak output lead; and / or The packaged peak amplifier includes a second input matching network disposed between the peak input lead assembly and the second peak power transistor, and / or a second output matching network disposed between the second peak power transistor and the peak output lead.

8. The Dougherty amplifier according to claim 6, further comprising: A plurality of first bonding wires, the plurality of first bonding wires directly or via the input matching network, connect the input terminal of the main power transistor to the main input lead; as well as Multiple second bonding wires connect the output terminal of the main power transistor to the main output lead, either directly or via the output matching network.

9. The Dougherty amplifier according to claim 7, further comprising: Multiple third bonding wires connect the input terminal of the first peak power transistor to the peak input lead assembly, either directly or via the first input matching network. Multiple fourth bonding wires connect the input terminal of the second peak power transistor to the peak input lead assembly, either directly or via the second input matching network. Multiple fifth bonding wires, the multiple fifth bonding wires directly or via the first output matching network, connect the output terminal of the first peak power transistor to a first portion of the peak output lead; as well as Multiple sixth bonding wires connect the output of the second peak power transistor to a second portion of the peak output lead, either directly or via the second output matching network.

10. The Dougherty amplifier according to claim 9, wherein, The peak input lead assembly includes a first peak input lead and a second peak input lead spaced apart from the first peak input lead, wherein the first peak input lead is connected to the input terminal of the first peak power transistor using the plurality of third bonding wires, and the second peak input lead is connected to the input terminal of the second peak power transistor using the plurality of fourth bonding wires.

11. The Dougherty amplifier according to claim 10, wherein, The Doherty splitter includes an input terminal for receiving the radio frequency signal, a main output terminal for outputting the main radio frequency signal, and a peak output terminal for outputting the peak radio frequency signal. The Dougherty amplifier includes a first transmission line disposed between the peak output terminal and the first peak input lead, and a second transmission line disposed between the peak output terminal and the second peak input lead. The electrical lengths of the first transmission line and the second transmission line are respectively B times the wavelength corresponding to the operating frequency of the Dougherty amplifier, wherein B is in the range of 0.4 to 0.

6.

12. The Dougherty amplifier of claim 10, further comprising a resistor electrically connected between the first peak input lead and the second peak input lead.

13. The Dougherty amplifier according to claim 1, wherein, The Dougherty combiner includes an impedance inverter disposed between the output of the main power transistor and the combination node of the Dougherty combiner, wherein the impedance inverter is formed by a quarter-wavelength transmission line corresponding to the operating frequency or an electrical equivalent of the operating frequency.

14. The Dougherty amplifier according to claim 13, wherein, At the operating frequency, the phase delay between the output of the first peak power transistor and the combined node is substantially equal to 180 degrees n1 times, and wherein, at the operating frequency, the phase delay between the output of the second peak power transistor and the combined node is substantially equal to 180 degrees n2 times, wherein n1 and n2 are each integers greater than zero.

15. The Dougherty amplifier according to claim 13, further comprising: A Doherty splitter, wherein the Doherty splitter is used to receive radio frequency signals and split the received radio frequency signals into the main radio frequency signal and the peak radio frequency signal, and A phase delay is provided between the Dougherty splitter and the peak input lead assembly to ensure that the amplified main RF signal and the amplified peak RF signal are combined in phase at the combination node of the Dougherty combiner.

16. A packaged amplifier configured to be mounted on a printed circuit board and comprising: An input lead assembly for receiving radio frequency (RF) signals, a first power transistor for amplifying a portion of the RF signal, a second power transistor for amplifying the remaining portion of the RF signal, and an output lead for combining the portion of the RF signal amplified by the first power transistor and the remaining portion of the RF signal amplified by the second power transistor into an amplified RF signal. The output lead has an inner edge facing the first power transistor and the second power transistor, and an outer edge opposite to the inner edge. The output lead includes a slot extending from the inner edge to the outer edge, the length of which corresponds to A times the wavelength corresponding to the operating frequency of the packaged amplifier, where A is in the range of 0.1 to 0.

4. The slot divides the output lead into a first portion, a second portion, and a common portion. The first portion is electrically connected to the first power transistor, the second portion is electrically connected to the second power transistor, and the common portion is disposed between the outer edge and the first and second portions and is integrally connected to both the first and second portions. The slot ensures that a portion of the radio frequency signal amplified by the first power transistor is combined with a portion of the radio frequency signal amplified by the second power transistor in the common portion.

17. The packaged amplifier of claim 16, wherein, The first power transistor is integrated on a first semiconductor die, and the second power transistor is integrated on a second semiconductor die that is separate from the first semiconductor die.

18. A packaged amplifier configured to be mounted on a printed circuit board and comprising: The main amplifier includes: a main input lead for receiving a main radio frequency (RF) signal, a main power transistor for amplifying the RF signal, and a main output lead for outputting the RF signal amplified by the main power transistor. A peak amplifier, comprising: a peak input lead assembly for receiving a peak radio frequency signal; a first peak power transistor for amplifying a portion of the peak radio frequency signal; a second peak power transistor for amplifying a remaining portion of the peak radio frequency signal; and a peak output lead for combining a portion of the peak radio frequency signal amplified by the first peak power transistor and the remaining portion of the peak radio frequency signal amplified by the second peak power transistor into an amplified peak radio frequency signal. The peak output lead has an inner edge facing the first peak power transistor and the second peak power transistor, and an outer edge opposite to the inner edge. The peak output lead includes a slot extending from the inner edge to the outer edge, the length of which corresponds to A times the wavelength corresponding to the operating frequency of the packaged amplifier, where A is in the range of 0.1 to 0.

4. The slot divides the peak output lead into a first portion, a second portion, and a common portion. The first portion is electrically connected to the first peak power transistor, the second portion is electrically connected to the second peak power transistor, and the common portion is disposed between the outer edge and the first and second portions and is integrally connected to both the first and second portions. The slot ensures that a portion of the peak radio frequency signal amplified by the first peak power transistor is combined with a portion of the peak radio frequency signal amplified by the second peak power transistor in the common portion.

19. The packaged amplifier according to claim 18, wherein, The first peak power transistor is integrated on a first semiconductor die, the second peak power transistor is integrated on a second semiconductor die separate from the first semiconductor die, and the main power transistor is integrated on a third semiconductor die separate from the first semiconductor die and the second semiconductor die.

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