Gallium nitride limiter and method for manufacturing gallium nitride limiter

Abstract

The application provides a gallium nitride limiter and a preparation method of the gallium nitride limiter. The gallium nitride limiter comprises a three-stage limiting circuit, which is sequentially connected to a main transmission line of the gallium nitride limiter according to the signal transmission direction of the main transmission line. The first-stage limiting circuit comprises 2N gallium nitride PIN diodes. Any N gallium nitride PIN diodes are connected in series to form two gallium nitride PIN diode strings. The anode end of the first gallium nitride PIN diode string is connected to the main transmission line, and the cathode end is grounded. The cathode end of the second gallium nitride PIN diode string is connected to the main transmission line, and the anode end is grounded. The second-stage limiting circuit comprises four gallium nitride Schottky diodes. The third-stage limiting circuit comprises two gallium nitride Schottky diodes. The application can improve the power capacity and breakdown voltage of the entire gallium nitride limiter.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium nitride limiter and a method for fabricating a gallium nitride limiter. Background Technology

[0002] With the continuous advancement of technology, especially the rapid progress in microelectronics, electronic devices have been developing towards integration and miniaturization in recent years. The increasing operating frequencies and the use of more advanced and precise components have significantly increased device functionality and improved performance, but have also made the systems more complex. To ensure that the equipment can withstand the impact of high-power microwave weapons, more specialized microwave protection designs are required.

[0003] Currently, traditional microwave limiter circuits use silicon and gallium arsenide PIN diodes, but their performance is limited by the inherent properties of semiconductor materials. There is currently no limiter with high performance, high power capacity, and high breakdown voltage. Summary of the Invention

[0004] This invention provides a gallium nitride (GaN) limiter and a method for fabricating the GaN limiter, in order to solve the problems of poor performance, low power capacity, and low breakdown voltage of limiters in the prior art.

[0005] In a first aspect, embodiments of the present invention provide a gallium nitride limiter, comprising: a three-stage limiting circuit, wherein a first-stage limiting circuit, a second-stage limiting circuit, and a third-stage limiting circuit are sequentially connected to the main transmission line according to the signal transmission direction of the main transmission line of the gallium nitride limiter;

[0006] The first-stage limiting circuit includes 2N gallium nitride PIN diodes, where N is a positive integer;

[0007] Any N gallium nitride PIN diodes are connected in series to form two gallium nitride PIN diode strings. The anode of the first gallium nitride PIN diode string is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride PIN diode string is connected to the main transmission line, and the anode is grounded.

[0008] The second-stage limiting circuit includes four gallium nitride Schottky diodes;

[0009] Any two gallium nitride Schottky diodes are connected in series to form two gallium nitride Schottky diode strings. The anode of the first gallium nitride Schottky diode string is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride Schottky diode string is connected to the main transmission line, and the anode is grounded.

[0010] The third-stage limiting circuit includes two gallium nitride Schottky diodes;

[0011] The anode of the first gallium nitride Schottky diode is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride Schottky diode is connected to the main transmission line, and the anode is grounded.

[0012] In one possible implementation, the first-stage limiting circuit also includes 2N gallium nitride Schottky diodes;

[0013] Any N gallium nitride Schottky diodes are connected in series to form a third gallium nitride Schottky diode string and a fourth gallium nitride Schottky diode string. The anode of the third gallium nitride Schottky diode string is connected to the cathode of the first gallium nitride PIN diode string, and the cathode of the third gallium nitride Schottky diode string is grounded.

[0014] The cathode of the fourth gallium nitride Schottky diode string is connected to the anode of the second gallium nitride PIN diode string, and the anode of the third gallium nitride Schottky diode string is grounded.

[0015] In one possible implementation, the first-stage limiting circuit contains four gallium nitride Schottky diodes and two gallium nitride PIN diodes.

[0016] Secondly, embodiments of the present invention provide a method for fabricating a gallium nitride (GaN) limiter, used to fabricate the GaN limiter described in any of the above claims, wherein the method for fabricating the GaN limiter includes:

[0017] N is grown sequentially on a semi-insulating substrate + GaN layer and N - GaN layer;

[0018] In the N - A SiO2 layer is grown on the GaN layer, with a first predetermined position reserved. An intrinsic GaN layer (I layer) and a P layer are then sequentially grown at the first predetermined position. - GaN layer and P + GaN layer, to obtain PIN diode mesa;

[0019] After removing the SiO2 layer, in the N - The GaN layer is etched in the areas other than the first and second preset positions until the N is exposed. + On the upper surface of the GaN layer, in the N + Schottky diode mesa is obtained on the GaN layer;

[0020] In the N + The third predetermined position of the exposed area on the GaN layer is etched to isolate the PIN diode mesa and the Schottky diode mesa until the upper surface of the semi-insulating substrate is exposed.

[0021] In the N + Ohmic contacts are fabricated on the exposed areas of the GaN layer;

[0022] In the N + GaN layer and the P + The exposed areas on the GaN layer, and the N + GaN layer and N - Electrodes are fabricated on the exposed areas of the GaN layer, and a dicing machine is used to dice the GaN layer according to the predetermined dicing area to obtain a gallium nitride limiter.

[0023] In one possible implementation, the sequential growth of N on the semi-insulating substrate + GaN layer and N - GaN layers include:

[0024] N is epitaxially grown on a semi-insulating substrate using metal-organic chemical vapor deposition. + GaN layer;

[0025] In the N + N2 is epitaxially grown on a GaN layer using metal-organic chemical vapor deposition. - GaN layer.

[0026] In one possible implementation, in the N - A SiO2 layer is grown on the GaN layer, with a first predetermined position reserved. An intrinsic GaN layer (I layer) and a P layer are then sequentially grown at the first predetermined position. - GaN layer and P + A GaN layer is formed to create a PIN diode mesa, including:

[0027] In the N - A SiO2 layer is grown on the GaN layer in the region other than the first preset position;

[0028] In the N - At the first predetermined position on the GaN layer, an intrinsic GaN layer (I layer) and a P layer are sequentially grown. - GaN layer and P + GaN layer;

[0029] In the N - The SiO2 layer is etched onto the GaN layer to obtain the PIN diode mesa.

[0030] In one possible implementation, the N + The thickness of the GaN layer ranges from 2 μm to 4 μm, and the N + The GaN layer has a doping concentration on the order of 10. 18 cm -3 ~10 19 cm-3 ;

[0031] The N - The thickness of the GaN layer ranges from 200 nm to 1 μm, and the N - The GaN layer has a doping concentration on the order of 10. 14 cm -3 ~10 17 cm -3 ;

[0032] The thickness of the I-layer GaN intrinsic layer ranges from 400 nm to 800 nm;

[0033] The P - The GaN layer has a thickness ranging from 300 nm to 600 nm, and the P - The GaN layer has a doping concentration on the order of 10. 16 cm -3 ~10 17 cm -3 ;

[0034] The P + The GaN layer has a thickness ranging from 300 nm to 600 nm, and the P + The GaN layer has a doping concentration on the order of 10. 18 cm -3 ~10 20 cm -3 ;

[0035] The thickness of the SiO2 layer ranges from 400 nm to 800 nm.

[0036] In one possible implementation, in the N - The GaN layer is etched in the areas other than the first and second preset locations, including:

[0037] In the N - The GaN layer, except for the first and second preset positions, is etched using a dry etching process, employing BCL3 or CL2 gas in an inductively coupled ion etching device.

[0038] In the N + The third preset position of the exposed area on the GaN layer is etched, including:

[0039] In the N + The third preset position of the exposed area on the GaN layer is etched using a dry etching process, employing BCL3 or CL2 gas in an inductively coupled ion etching device.

[0040] In one possible implementation, the metal used to prepare the ohmic contact includes: Ti / Al / Ni / Au alloy, Ti / Au alloy, Ti / Al / Ti / Au alloy, or Ti / Al / Pt / Au alloy.

[0041] In one possible implementation, the N + GaN layer and the P + The exposed areas on the GaN layer, and the N + GaN layer and N - Electrodes are fabricated on the exposed areas of the GaN layer, and the GaN capping device is obtained by dicing the GaN layer according to a predetermined dicing area using a dicing machine, including:

[0042] A Ti / Au alloy is evaporated on an exposed semi-insulating substrate to form the peripheral metal circuitry of the gallium nitride limiter;

[0043] In the N + GaN layer and the P + The exposed areas on the GaN layer, and the N + GaN layer and N - Evaporate Ti / Au alloy or Ni / Au alloy on the exposed area of ​​the GaN layer to fabricate electrodes and obtain the front circuit of the gallium nitride limiter.

[0044] The back side of the gallium nitride limiter was thinned to 50 μm, and a Ti / Au alloy was evaporated on its surface to form a back gold layer;

[0045] A gallium nitride (GaN) limiter is obtained by dicing a predetermined area using a dicing machine. The GaN limiter is a circuit that includes a GaN PIN diode and a GaN Schottky diode.

[0046] This invention provides a gallium nitride (GaN) limiter and its fabrication method. By setting up a three-stage limiting circuit, a GaN PIN diode is incorporated in the first-stage limiting circuit. The GaN PIN diode has a large power capacity and high breakdown voltage, capable of withstanding large pulse voltages and high power inputs to the GaN limiter, preventing the subsequent GaN Schottky diodes from breaking down. The second and third-stage limiting circuits are composed of different numbers of GaN Schottky diodes, which can share the high power input of the GaN limiter, thereby increasing the overall power capacity and breakdown voltage of the GaN limiter. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the gallium nitride limiter provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of a gallium nitride limiter provided in another embodiment of the present invention.

[0050] Figure 3 This is a flowchart illustrating the fabrication method of a gallium nitride limiter provided in an embodiment of the present invention;

[0051] Figure 4-1 This invention provides a method for preparing N from a semi-insulating substrate. - A schematic diagram of the sample obtained by the GaN layer;

[0052] Figure 4-2 The preparation of P provided in the embodiments of the present invention + A schematic diagram of the GaN layer;

[0053] Figure 4-3 This is a schematic diagram of removing the SiO2 layer provided in an embodiment of the present invention;

[0054] Figure 4-4 The etching N provided in the embodiments of the present invention - A schematic diagram of the sample behind the GaN layer;

[0055] Figure 4-5 This is a schematic diagram of the countertop after isolation provided in an embodiment of the present invention;

[0056] Figure 4-6 This is a schematic diagram of a gallium nitride limiter before dicing provided in an embodiment of the present invention. Detailed Implementation

[0057] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0058] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0059] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0060] Figure 1 A schematic diagram of a gallium nitride limiter according to an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0061] like Figure 1 As shown, a gallium nitride limiter 1 includes: a three-stage limiting circuit, wherein the first-stage limiting circuit, the second-stage limiting circuit, and the third-stage limiting circuit are sequentially connected to the main transmission line according to the signal transmission direction of the main transmission line of the gallium nitride limiter;

[0062] The first-stage limiting circuit includes 2N gallium nitride PIN diodes, where N is a positive integer;

[0063] Any N gallium nitride PIN diodes are connected in series to form two gallium nitride PIN diode strings. The anode of the first gallium nitride PIN diode string is connected to the main transmission line and the cathode is grounded. The cathode of the second gallium nitride PIN diode string is connected to the main transmission line and the anode is grounded.

[0064] Because gallium nitride (GaN) PIN diodes can withstand large pulse voltages and power, they are placed at the receiver front end of the GaN limiter as protection against damage to the GaN Schottky diodes in the second and third stages. See also... Figure 1 As shown, the first-stage limiting circuit includes two gallium nitride (GaN) PIN diodes. In this embodiment, the number of GaN PIN diodes is not limited, but the number of GaN PIN diodes is related to the number of GaN Schottky diodes in the subsequent limiting circuit, requiring resistor matching between the two. Therefore, in this embodiment, two GaN PIN diodes can be used in the first-stage limiting circuit.

[0065] Gallium nitride PIN diodes can withstand high voltages due to the N-type diodes in their structure. - The doping concentration and thickness of the GaN layer determine its properties, therefore, when fabricating a gallium nitride limiter, the N-doping concentration can be set to a specific value. - The doping concentration of GaN layers is on the order of small magnitudes, for example, N - The GaN layer has a doping concentration on the order of 10. 14 cm -3 Meanwhile, N - The GaN layer is set to be thicker, for example, N - The thickness of the GaN layer can be 1 μm or close to 1 μm.

[0066] See Figure 1As shown, the second-stage limiting circuit includes four gallium nitride Schottky diodes;

[0067] Any two gallium nitride Schottky diodes are connected in series to form two gallium nitride Schottky diode strings. The anode of the first gallium nitride Schottky diode string is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride Schottky diode string is connected to the main transmission line, and the anode is grounded.

[0068] The third-stage limiting circuit includes two gallium nitride Schottky diodes;

[0069] The anode of the first gallium nitride Schottky diode is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride Schottky diode is connected to the main transmission line, and the anode is grounded.

[0070] The second-stage and third-stage limiting circuits each consist of a different number of gallium nitride (GaN) Schottky diodes. These diodes are used to share the high power output of the GaN limiter, further increasing power capacity, reducing the limiting threshold, and improving sensitivity. The second-stage limiting circuit has a lower power capacity than the third-stage circuit. This is because while increasing the number of GaN Schottky diodes increases power capacity, it also increases losses. Therefore, the structure needs to be adjusted to eliminate the impact of these losses. In this embodiment, the second-stage limiting circuit includes four GaN Schottky diodes, and the third-stage limiting circuit includes two GaN Schottky diodes.

[0071] The gallium nitride (GaN) Schottky diode is located at the back end of the GaN limiter circuit. The resistance of the GaN Schottky diode needs to be low to match the front end; therefore, an N-type diode is required. - The GaN layer has a high concentration and a relatively small thickness. For example, N - The GaN layer has a doping concentration on the order of 10. 17 cm -3 Meanwhile, N - The GaN layer is set to be relatively thin, for example, N - The thickness of the GaN layer can be 200 nm or slightly greater than 200 nm.

[0072] In one embodiment, since the forward current of the gallium nitride PIN diode is smaller than that of the gallium nitride Schottky diode, and the forward conduction resistance of the gallium nitride PIN diode is larger, the power increase of the gallium nitride PIN diode is limited. In this embodiment, by using a combination of gallium nitride PIN diode and gallium nitride Schottky diode, it is possible to withstand greater voltage and power while maintaining low insertion loss.

[0073] Therefore, the first-stage limiting circuit can also include 2N gallium nitride Schottky diodes;

[0074] Any N gallium nitride Schottky diodes are connected in series to form a third gallium nitride Schottky diode string and a fourth gallium nitride Schottky diode string. The anode of the third gallium nitride Schottky diode string is connected to the cathode of the first gallium nitride PIN diode string, and the cathode of the third gallium nitride Schottky diode string is grounded.

[0075] The cathode of the fourth gallium nitride Schottky diode string is connected to the anode of the second gallium nitride PIN diode string, and the anode of the third gallium nitride Schottky diode string is grounded.

[0076] See Figure 2 The gallium nitride limiter structure shown consists of two gallium nitride Schottky diodes connected in series with a gallium nitride PIN diode to form a diode string. Two identical diode strings form a diode string pair connected to the main transmission line.

[0077] The aforementioned gallium nitride (GaN) limiter consists of three stages of limiting circuits connected sequentially to the main transmission line according to the signal transmission direction of the GaN limiter's main transmission line. The first stage limiting circuit includes a GaN PIN diode with a high reverse breakdown voltage, used to withstand the large pulse voltage and high power of the GaN limiter, preventing the subsequent GaN Schottky diodes from breaking down. The second and third stage limiting circuits are composed of different numbers of GaN Schottky diodes to share the high power input of the GaN limiter. The second stage limiting circuit has more GaN Schottky diodes than the third stage limiting circuit to match the resistance of the first stage limiting circuit, resulting in lower insertion loss for the entire GaN limiter. This three-stage limiting circuit structure improves the overall power capacity and breakdown voltage of the GaN limiter.

[0078] A flowchart of a method for fabricating a gallium nitride limiter, also provided in this embodiment of the invention, is used to fabricate the aforementioned... Figure 1 and Figure 2 The gallium nitride (GaN) limiter shown is fabricated as follows: Figure 3 As shown, the details are as follows:

[0079] Step 301: Sequentially grow N on the semi-insulating substrate + GaN layer and N - GaN layer.

[0080] Optionally, in this embodiment, the semi-insulating substrate can be a silicon carbide substrate or sapphire.

[0081] In one embodiment, see Figure 4-1 As shown, N is sequentially grown on a semi-insulating substrate. + GaN layer and N - The GaN layer may include:

[0082] N was epitaxially grown on a semi-insulating substrate using metal-organic chemical vapor deposition (MOCVD). + GaN layer;

[0083] In N + N2 is epitaxially grown on a GaN layer using metal-organic chemical vapor deposition. - GaN layer.

[0084] Optional, N + The thickness of the GaN layer ranges from 2 μm to 4 μm, for example, N + The thickness of the GaN layer can be 2μm, 3μm, or 4μm, etc. + The GaN layer has a doping concentration on the order of 10. 18 cm -3 ~10 19 cm -3 For example, N + The doping concentration of the GaN layer can be on the order of 10. 18 cm -3 10 19 cm -3 .

[0085] N - The thickness of the GaN layer ranges from 200 nm to 1 μm, for example, N - The thickness of the GaN layer can be 200nm, 300nm, 500nm, 800nm, 1μm, etc. - The GaN layer has a doping concentration on the order of 10. 14 cm -3 ~10 17 cm -3 For example, N - The doping concentration of the GaN layer can be on the order of 10. 14 cm -3 10 15 cm -3 10 16 cm -3 10 17 cm -3 wait.

[0086] In one embodiment, see Figure 1 or Figure 2 As shown, in order for the gallium nitride PIN diode to withstand a relatively high input voltage in the first stage, N can be... - The doping concentration of the GaN layer is set to a lower level, for example, N. - The GaN layer has a doping concentration on the order of 10. 14 cm -3Meanwhile, N - The GaN layer is set to be thicker, for example, N - The thickness of the GaN layer can be 1 μm or close to 1 μm.

[0087] In one embodiment, see Figure 1 or Figure 2 As shown, the resistance of the gallium nitride Schottky diodes set in the second and third stage limiting circuits of the gallium nitride limiter needs to be matched with the front end, so it needs to be set to a smaller value. Therefore, N needs to be... - The doping concentration of the GaN layer is set to a higher level, for example, N - The GaN layer has a doping concentration on the order of 10. 17 cm -3 Meanwhile, N - The GaN layer is set to be relatively thin, for example, N - The thickness of the GaN layer can be 200 nm or slightly greater than 200 nm.

[0088] It should be noted that the aforementioned requirements of increasing the input voltage of the gallium nitride PIN diode and reducing the resistance of the gallium nitride limiter can only be implemented for one of them in a gallium nitride limiter.

[0089] Step 302, in N - A SiO2 layer is grown on the GaN layer, with a first predetermined position reserved. An intrinsic GaN layer (I layer) and a P layer are then grown sequentially at the first predetermined position. - GaN layer and P + GaN layer, to obtain PIN diode mesa.

[0090] Optional, in N - A SiO2 layer is grown on the GaN layer, except for the first preset location; a SiO2 layer is grown in the N layer. - At the first predetermined position on the GaN layer, an intrinsic GaN layer (I layer) and a P layer are sequentially grown. - GaN layer and P + GaN layer, see Figure 4-2 ; in N - Etching a SiO2 layer onto a GaN layer yields the PIN diode mesa. (See [link]) Figure 4-3 .

[0091] Step 302 may include:

[0092] In N - An intrinsic GaN layer (I layer) is epitaxially grown on the GaN layer using metal-organic chemical vapor deposition.

[0093] P-type materials were epitaxially grown on the intrinsic GaN layer using metal-organic chemical vapor deposition. - GaN layer;

[0094] In P - P-type epitaxial growth was performed on the GaN layer using metal-organic chemical vapor deposition. + GaN layer.

[0095] Optionally, the thickness of the I-layer GaN intrinsic layer can range from 400 nm to 800 nm. For example, the thickness of the I-layer GaN intrinsic layer can be 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, etc.

[0096] P - The thickness of the GaN layer ranges from 300 nm to 600 nm, and the P layer... - The GaN layer has a doping concentration on the order of 10. 16 cm -3 ~10 17 cm -3 For example, P - The thickness of the GaN layer can be 300nm, 500nm, 600nm, etc., P - The doping concentration of the GaN layer can be on the order of 10. 16 cm -3 10 17 cm -3 wait.

[0097] P + The thickness of the GaN layer ranges from 300 nm to 600 nm, and the P layer... + The GaN layer has a doping concentration on the order of 10. 18 cm -3 ~10 20 cm -3 For example, P + The thickness of the GaN layer can be 300nm, 500nm, 600nm, etc., P + The doping concentration of the GaN layer can be on the order of 10. 18 cm -3 10 19 cm -3 10 20 cm -3 wait.

[0098] The first preset position here is the position that the anode of the PIN diode needs to be set at.

[0099] Step 303, after removing the SiO2 layer, in N - The GaN layer is etched in the areas other than the first and second preset positions until N is exposed. + On the upper surface of the GaN layer, in N + Schottky diode mesa is obtained on the GaN layer.

[0100] exist Figure 4-3 Based on N - The GaN layer is etched to obtain the Schottky diode mesa.

[0101] The second preset position is the position corresponding to the Schottky diode mesa.

[0102] In one embodiment, in N - Etching is performed on the GaN layer in areas other than the first and second preset locations, including: etching the N-layer... - The GaN layer, excluding the first and second preset locations, is etched using a dry etching process with BCL3 or CL2 gas via inductively coupled ion etching equipment. (See [link to relevant documentation]). Figure 4-4 , for etching N - The sample behind the GaN layer, where N + The remaining P on the left side of the GaN layer was etched. + N corresponding to the GaN layer - GaN layer, serving as a mesa for PIN diodes, N + The remaining N on the right side of the GaN layer is etched. - The GaN layer is a Schottky diode mesa.

[0103] Inductively coupled ion etching (ICE) mainly uses high-frequency glow discharge to dissociate the reactive gas into active particles, which bombard the etching material and react with it to achieve etching. It is fast and pollution-free.

[0104] Step 304, in N + The third predetermined position of the exposed area on the GaN layer is etched to isolate the PIN diode mesa and the Schottky diode mesa until the upper surface of the semi-insulating substrate is exposed.

[0105] Continue with N + The GaN layer is etched to isolate the PIN diode mesa from the Schottky diode mesa.

[0106] See Figure 4-5 The third preset position is N + The location corresponding to the etched area in the GaN layer.

[0107] In one embodiment, in N + Etching is performed at a third predetermined location in the exposed region of the GaN layer, which may include:

[0108] In N + The third predetermined location of the exposed area on the GaN layer is etched using a dry etching process, employing BCL3 or CL2 gas in an inductively coupled ion etching (ICI) apparatus. (See also...) Figure 4-5The corresponding N is retained under the mesa of the PIN diode and the Schottky diode, respectively. + GaN layer, while in N + The GaN layer reserves the positions for the cathode and anode of the PIN diode and Schottky diode, respectively, and the remaining N... + The GaN layer was etched away.

[0109] Step 305, in N + Ohmic contacts are fabricated on GaN layers.

[0110] It should be noted that the order of steps 304 and 305 is not limited. You can perform step 304 first and then step 305, or you can perform step 305 first and then step 304.

[0111] In one embodiment, the metal used to prepare the ohmic contact includes: Ti / Al / Ni / Au alloy, Ti / Au alloy, Ti / Al / Ti / Au alloy, or Ti / Al / Pt / Au alloy.

[0112] In N + Photolithography, electron beam evaporation, metal lift-off, and high-temperature rapid annealing are performed on GaN layers. Ohmic contacts are fabricated using alloys such as Ti / Al / Ni / Au, Ti / Au, Ti / Al / Ti / Au, and Ti / Al / Pt / Au. The photolithography operation is performed on N... + Photolithographic patterns are fabricated on the GaN layer to allow electron beam evaporation in the patterned cutout areas to form a metal layer. After removing the photoresist, the metal outside the photolithographic area is glassized, leaving the metal within the photolithographic pattern. This metal is then subjected to high-temperature rapid annealing in nitrogen at 700°C to 800°C. Subsequently, the anode and cathode can be fabricated at the ohmic contact sites.

[0113] Step 306, in N + GaN layer and P + The exposed areas on the GaN layer, and N + GaN layer and N - Electrodes are fabricated on the exposed areas of the GaN layer, and a dicing machine is used to dice the GaN layer according to the predetermined dicing area to obtain a gallium nitride limiter.

[0114] In one embodiment, step 306 may include:

[0115] A Ti / Au alloy is evaporated on an exposed semi-insulating substrate to form the peripheral metal circuitry of the gallium nitride limiter;

[0116] In N + GaN layer and P + The exposed areas on the GaN layer, and N + GaN layer and N -Electrodes are fabricated by evaporating Ti / Au or Ni / Au alloys onto the exposed areas of the GaN layer to obtain the front-side circuitry of the gallium nitride limiter. See also... Figure 4-6 In the middle, on the left side of the semi-insulating substrate, N + Anodes and cathodes were fabricated on GaN, and the remaining P was etched off. + An anode is fabricated on a GaN layer, and N is used to fabricate the anode. + Anodes prepared on GaN and P + Air bridges are fabricated between the anodes on the GaN layer to connect them, forming a gallium nitride PIN diode. On the right side of the semi-insulating substrate, N... + Anodes and cathodes were fabricated on GaN, and the remaining N was etched off. - An anode is fabricated on a GaN layer, and N is used to fabricate the anode. + Anodes and N2 prepared on GaN - Air bridges are fabricated between the anodes on the GaN layer to connect the anodes together and form a gallium nitride Schottky diode. After the front circuit is fabricated, the back side of the gallium nitride limiter is thinned to 50 μm and a Ti / Au alloy is evaporated on its surface to form a back gold layer.

[0117] Use a dicing machine to dice according to the predetermined dicing area, that is, in Figure 4-6 A gallium nitride (GaN) limiter is obtained by dicing on a semi-insulating substrate between the cathode of a gallium nitride (GaN) PIN diode and the anode of a gallium nitride (GaN) Schottky diode. The GaN limiter includes circuitry comprising both a GaN PIN diode and a GaN Schottky diode. By dicing in different predetermined areas, [the following can be achieved]... Figure 1 and Figure 2 The gallium nitride limiter shown.

[0118] In this embodiment of the invention, N is grown sequentially on a semi-insulating substrate. + GaN layer and N - GaN layer; in N - A SiO2 layer is grown on the GaN layer, with a first predetermined position reserved. An intrinsic GaN layer (I layer) and a P layer are then grown sequentially at the first predetermined position. - GaN layer and P + A GaN layer is formed to obtain a PIN diode mesa; after removing the SiO2 layer, an N... - The GaN layer is etched in the areas other than the first and second preset positions until N is exposed. + On the upper surface of the GaN layer, in N + Schottky diode mesas were obtained on the GaN layer; in N + Etching is performed at the third predetermined position of the exposed region on the GaN layer to isolate the PIN diode mesa and the Schottky diode mesa until the upper surface of the semi-insulating substrate is exposed; in N +Ohmic contacts are fabricated on the exposed regions of the GaN layer; in N + GaN layer and P + The exposed areas on the GaN layer, and N + GaN layer and N - Electrodes are fabricated on the exposed areas of the GaN layer, and a dicing machine is used to dice the material according to a predetermined dicing area to obtain a gallium nitride (GaN) limiter. In this embodiment of the invention, a GaN PIN diode is fabricated through growth, and then a GaN Schottky diode is obtained through etching. This allows for the rapid production of the desired GaN limiter with minimal contamination, providing a basic chip for subsequent fabrication of GaN limiters with high power capacity and high breakdown voltage. Furthermore, by setting N... - Different doping concentrations and thicknesses of GaN layers can enable gallium nitride PIN diodes to withstand high voltages at their input terminals, or to match the power capacity of gallium nitride Schottky diodes with that of gallium nitride PIN diodes.

[0119] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0120] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a gallium nitride limiter, characterized in that, For fabricating a gallium nitride (GaN) limiter, the GaN limiter includes: a three-stage limiting circuit, wherein the first-stage limiting circuit, the second-stage limiting circuit, and the third-stage limiting circuit are sequentially connected to the main transmission line according to the signal transmission direction of the main transmission line of the GaN limiter; The first-stage limiting circuit includes 2N gallium nitride PIN diodes, where N is a positive integer; Any N gallium nitride PIN diodes are connected in series to form two gallium nitride PIN diode strings. The anode of the first gallium nitride PIN diode string is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride PIN diode string is connected to the main transmission line, and the anode is grounded. The second-stage limiting circuit includes four gallium nitride Schottky diodes; Any two gallium nitride Schottky diodes are connected in series to form two gallium nitride Schottky diode strings. The anode of the first gallium nitride Schottky diode string is connected to the main transmission line, and the cathode is grounded. The cathode of the second gallium nitride Schottky diode string is connected to the main transmission line, and the anode is grounded. The third-stage limiting circuit includes two gallium nitride Schottky diodes; The anode of the first gallium nitride Schottky diode is connected to the main transmission line, and the cathode is grounded; the cathode of the second gallium nitride Schottky diode is connected to the main transmission line, and the anode is grounded. The method for fabricating the gallium nitride limiter includes: Sequential growth on a semi-insulating substrate Layers and layer; In the A SiO2 layer is grown on the first preset position, and an intrinsic GaN layer (I layer) is sequentially grown at the first preset position. Layers and Layer, to obtain the PIN diode mesa; After removing the SiO2 layer, in the The layer is etched in the areas other than the first and second preset positions until the [other area] is exposed. The upper surface of the layer, in the Schottky diode mesa is obtained on the layer; In the The third preset position of the exposed area on the layer is etched to isolate the PIN diode mesa and the Schottky diode mesa until the upper surface of the semi-insulating substrate is exposed; In the Ohmic contacts are fabricated on the exposed areas of the layer; In the Layers and the The exposed areas on the layer, and the Layers and Electrodes are fabricated on the exposed areas of the layer, and a dicing machine is used to dice the layers according to the predetermined dicing area to obtain a gallium nitride limiter.

2. The method for fabricating a gallium nitride limiter according to claim 1, characterized in that, The sequential growth on the semi-insulating substrate Layers and Layers, including: Epitaxial growth on a semi-insulating substrate using metal-organic chemical vapor deposition layer; In the Epitaxial growth is performed on the layer using metal-organic chemical vapor deposition. layer.

3. The method for fabricating a gallium nitride limiter according to claim 2, characterized in that, In the A SiO2 layer is grown on the first preset position, and an intrinsic GaN layer (I layer) is sequentially grown at the first preset position. Layers and Layer, to obtain the PIN diode mesa, including: In the Growth in areas other than the first preset position on the layer layer; In the At the first preset position on the layer, an I-layer GaN intrinsic layer is sequentially grown. Layers and layer; In the The above-layer corrosion Layer, to obtain the PIN diode mesa.

4. The method for fabricating a gallium nitride limiter according to claim 3, characterized in that, The The thickness of the layer ranges from 2μm to 4μm. The doping concentration of the layer is on the order of magnitude of ~ ; The The thickness of the layer ranges from 200 nm to 1 μm. The doping concentration of the layer is on the order of magnitude of ~ ; The thickness of the I-layer GaN intrinsic layer ranges from 400 nm to 800 nm; The The thickness of the layer ranges from 300nm to 600nm. The doping concentration of the layer is on the order of magnitude of ~ ; The The thickness of the layer ranges from 300nm to 600nm. The doping concentration of the layer is on the order of magnitude of ~ ; The The thickness of the layer ranges from 400nm to 800nm.

5. The method for fabricating a gallium nitride limiter according to claim 1, characterized in that, In the The layer is etched in the areas other than the first preset position and the second preset position, including: In the The regions of the layer other than the first and second preset positions are etched using a dry etching process, employing an inductively coupled ion etching (ICI) device. or Etching is performed using gas; In the The third preset location of the exposed area on the layer is etched, including: In the The third preset position of the exposed area on the layer is etched using a dry etching process, employing an inductively coupled ion etching (ICI) device. or The gas is used for etching.

6. The method for fabricating a gallium nitride limiter according to claim 1, characterized in that, The metals used to prepare ohmic contacts include: Ti / Al / Ni / Au alloy, Ti / Au alloy, Ti / Al / Ti / Au alloy, or Ti / Al / Pt / Au alloy.

7. The method for fabricating a gallium nitride limiter according to any one of claims 1-6, characterized in that, The above Layers and the The exposed areas on the layer, and the Layers and Electrodes are fabricated on the exposed areas of the layer, and a dicing machine is used to dice the layers according to a predetermined dicing area to obtain a gallium nitride limiter, comprising: A Ti / Au alloy is evaporated on an exposed semi-insulating substrate to form the peripheral metal circuitry of the gallium nitride limiter; In the Layers and the The exposed areas on the layer, and the Layers and The exposed areas on the layer are evaporated with Ti / Au alloy or Ni / Au alloy to fabricate electrodes and obtain the front circuit of the gallium nitride limiter. The back side of the gallium nitride limiter was thinned to 50 μm, and a Ti / Au alloy was evaporated on its surface to form a back gold layer; A gallium nitride (GaN) limiter is obtained by dicing a predetermined area using a dicing machine. The GaN limiter is a circuit that includes a GaN PIN diode and a GaN Schottky diode.

8. The method for fabricating a gallium nitride limiter according to claim 1, characterized in that, The first-stage limiting circuit also includes 2N gallium nitride Schottky diodes; Any N gallium nitride Schottky diodes are connected in series to form a third gallium nitride Schottky diode string and a fourth gallium nitride Schottky diode string. The anode of the third gallium nitride Schottky diode string is connected to the cathode of the first gallium nitride PIN diode string, and the cathode of the third gallium nitride Schottky diode string is grounded. The cathode of the fourth gallium nitride Schottky diode string is connected to the anode of the second gallium nitride PIN diode string, and the anode of the third gallium nitride Schottky diode string is grounded.

9. The method for fabricating a gallium nitride limiter according to claim 8, characterized in that, The first-stage limiting circuit contains four gallium nitride Schottky diodes and two gallium nitride PIN diodes.

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