Semiconductor devices, circuitry, and related methods

Abstract

Semiconductor devices, circuitry, and related methods are described herein. In one embodiment of the application, a semiconductor device can generate a count signal based on a division ratio. The semiconductor device includes a select indication generator configured to generate a select indication based on the division ratio and a current clock cycle output value of the count signal, an increment selector coupled to the select indication generator and configured to select an increment value from a plurality of increment values based on the select indication, and an output stage coupled to the increment selector and configured to generate a next clock cycle output value of the count signal based on the selected increment value.

Description

Technical Field

[0001] This application generally relates to electronic circuits, and more specifically, to apparatus and methods for generating counting signals based on a frequency division ratio. Background Technology

[0002] In audio power amplifiers, triangular wave signals are typically used to sample audio signals, thereby generating pulse width modulation (PWM) signals. Triangular wave signals are obtained by processing a square wave clock signal (e.g., through integration). When the frequency of the square wave clock signal is fixed, the switching frequency of the resulting triangular wave signal is also fixed. If multiple audio channels are sampled using the same triangular wave signal with a fixed switching frequency, electromagnetic interference (EMI) problems can easily occur.

[0003] Spread spectrum technology can be used to reduce EMI. For example, a square wave clock signal with a frequency varying over time can be provided, based on which a triangular wave signal with a switching frequency varying over time (i.e., a spread-spectrum triangular wave signal) can be generated. By converting a narrowband signal into a wideband signal through spread spectrum, energy distribution can be spread across multiple frequencies, thereby reducing the peak EMI energy at a single frequency and achieving the goal of reducing EMI. Phase shifting technology can also be used to reduce EMI. For example, square wave clock signals with different phases can be provided for different audio channels, and the switching timing of the triangular wave signals generated based on these square wave clock signals is staggered, thereby reducing EMI between different audio channels.

[0004] A square wave clock signal can be generated by dividing a high-frequency clock signal (such as a system clock signal) using a counter. The conventional method is to increment the counter's output by 1 with each high-frequency clock signal pulse received (e.g., at the rising edge of each pulse). When the counter's output reaches a predetermined count value n, it is reset (e.g., the output value is reset to 0) upon receiving the next high-frequency clock signal pulse, and counting resumes. Whenever the counter's output value is 0 and n / 2 (or (n+1) / 2), the square wave clock signal is toggled (e.g., from high to low, or vice versa). In other words, the square wave clock signal toggles twice every n+1 high-frequency clock cycles (i.e., the period of the square wave clock signal is n+1 high-frequency clock cycles), therefore n+1 can also be called the "division ratio." Square wave clock signals with frequencies varying over time can be generated by setting different division ratios at different times. However, when generating a phase-shifted square wave clock signal for another audio channel, different phase shift thresholds (i.e., the output value of the counter that triggers the phase-shifted square wave clock signal to flip) need to be set for different frequencies at different times, which increases the complexity of the circuit design. On the other hand, if the same phase shift threshold is set for different frequencies, the generated phase-shifted square wave clock signal will have phase jitter. Summary of the Invention

[0005] According to some embodiments of this application, a semiconductor device is provided that generates a counting signal based on a division ratio. The semiconductor device includes: a selection indicator generator configured to generate a selection indicator based on the division ratio and a current clock cycle output value of the counting signal; an increment selector coupled to the selection indicator generator and configured to select an increment value from a plurality of increment values ​​based on the selection indicator; and an output stage coupled to the increment selector and configured to generate a next clock cycle output value of the counting signal based on the selected increment value.

[0006] According to some embodiments of this application, this application also provides a circuit system including the semiconductor device described above for generating a counting signal based on a frequency division ratio.

[0007] According to some embodiments of this application, this application also provides a method for generating a counting signal based on a frequency division ratio. The method includes: generating a selection indication based on the frequency division ratio and a current clock cycle output value of the counting signal; selecting an increment value from a plurality of increment values ​​based on the selection indication; and generating a next clock cycle output value of the counting signal based on the selected increment value.

[0008] According to some embodiments of this application, this application also provides a machine-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the above-described method for generating a counting signal based on a frequency division ratio.

[0009] Details of one or more embodiments of this application are set forth in the following figures and description. Other features, objectives, and advantages will become apparent from the description, figures, and claims. Attached Figure Description

[0010] The following figures are mentioned and included in the disclosure in this specification:

[0011] Figure 1 This is a schematic diagram of the circuit system according to some embodiments of this application;

[0012] Figure 2 An example of four square wave clock signals whose frequency varies with time is shown;

[0013] Figure 3 This is a structural block diagram of a semiconductor device according to some embodiments of this application;

[0014] Figure 4 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application;

[0015] Figure 5 This is a flowchart of a method for generating a counting signal based on a frequency division ratio, according to some embodiments of this application.

[0016] The various features illustrated in the accompanying drawings may not be drawn to scale. For clarity, the embodiments illustrated in the drawings may be simplified. Therefore, the drawings may not illustrate all components of a given device or apparatus. Detailed Implementation

[0017] To better understand the spirit of the present invention, the following description, in conjunction with some embodiments of the present invention, will provide further details.

[0018] The terms "in one embodiment" or "according to one embodiment" as used in this specification do not necessarily refer to the same specific embodiment, and the terms "in other (some / some) embodiments" or "according to other (some / some) embodiments" as used in this specification do not necessarily refer to different specific embodiments. The purpose is to, for example, include combinations of all or some of the exemplary specific embodiments. The names of various components or devices used in this specification are for illustrative purposes only and are not intended to be limiting; these components or devices may have different names in other applications.

[0019] Various embodiments of the present invention are discussed in detail below. Although specific embodiments are discussed, it should be understood that these embodiments are for illustrative purposes only. Those skilled in the art will recognize that other components and configurations can be used without departing from the spirit and scope of the invention. Implementations of the present invention need not include all components or steps described in the embodiments, and the order of execution of each step can be adjusted according to the actual application.

[0020] Figure 1 This is a schematic diagram of the structure of a circuit system 100 according to some embodiments of this application. In some embodiments, the circuit system 100 may be or may include at least a portion of an audio power amplifier. In other embodiments, the circuit system 100 may be or may include at least a portion of other devices or systems that generate or apply PWM signals, such as a motor drive circuit. Figure 1 As shown, the circuit system 100 may include a controller 101, a counter 103, a triangular wave generation circuit 105, and a comparator 107. It should be understood that the circuit system 100 may also include... Figure 1 Other components not shown in the diagram. Although Figure 1 This demonstrates that some components are directly connected, and those skilled in the art will understand that these components may be connected to other components (not shown).

[0021] exist Figure 1In the example, controller 101 can generate a square wave clock signal 106 and send it to a triangular wave generation circuit 105. Triangular wave generation circuit 105 can generate a triangular wave signal 108 based on the square wave clock signal 106 and send it to one input of comparator 107. The other input 109 of comparator 107 can receive a specific signal. In the example of an audio power amplifier, this specific signal is an audio signal. In other examples, this specific signal can be other types of signals, such as motor control signals. Comparator 107 can generate a PWM signal based on the triangular wave signal 108 and the specific signal received at input 109. Those skilled in the art are familiar with various triangular wave generation circuits and the design and implementation methods of comparators that generate PWM signals based on triangular wave signals, and therefore will not be elaborated upon here. Furthermore, the implementation of this invention is not limited to the specific structure of triangular wave generation circuit 105 or comparator 107.

[0022] In some embodiments of this application, the square wave clock signal 106 output by the controller 101 may be a square wave clock signal whose frequency varies with time. In some embodiments, the controller 101 may output multiple square wave clock signals for multiple audio channels or multiple devices, and these square wave clock signals have a phase shift between them. Figure 2 Examples of four square wave clock signals 201, 202, 203 and 204 with frequencies varying over time are shown, where square wave clock signal 202 is phase-shifted by 90° relative to square wave clock signal 201, square wave clock signal 203 is phase-shifted by 180° relative to square wave clock signal 201, and square wave clock signal 204 is phase-shifted by 270° relative to square wave clock signal 201. Figure 2 The three clock cycles with different frequencies, 206, 207 and 208, are circled in the middle. Clock cycle 206 is the lowest frequency (i.e. the longest square wave clock cycle), clock cycle 207 is the middle frequency, and clock cycle 208 is the highest frequency (i.e. the shortest square wave clock cycle).

[0023] As mentioned earlier, a square wave clock signal can be generated by dividing a high-frequency clock signal using a counter. Figure 1 In the circuit system 100 shown, the controller 101 can determine the division ratio 102 and output the division ratio 102 to the counter 103. For example, the controller 101 can determine the division ratio 102 required for each square wave clock period based on the spreading function. The implementation of the present invention is not limited to the specific method of determining the division ratio 102. The controller 101 can also receive the output value 104 of the counter 103 and generate a square wave clock signal 106 based on the output value 104 of the counter 103.

[0024] In some embodiments, the counter 103 increments the output value 104 by 1 when it receives each high-frequency clock signal pulse (not shown in the figure) (e.g., at each rising edge of the pulse); when the output value 104 reaches the division ratio 102 of the current square wave clock cycle minus one, the controller 101 resets the counter 103 (i.e., resets the output value 104 to 0) when the next high-frequency clock signal pulse arrives, and restarts counting; whenever the output value of the counter is 0 and half of the division ratio (or half of the division ratio minus one), the square wave clock signal 106 is toggled.

[0025] To generate a phase-shifted square wave clock signal, controller 101 can determine a phase shift threshold based on the frequency division ratio 102 and the desired phase shift value. Figure 2 Taking square wave clock signals 201, 202, 203, and 204 as examples, signal 205 in the figure represents the division ratio determined by controller 101 for each square wave clock period. Assuming the division ratio determined for clock period 206 is 196, when the output value 104 of counter 103 reaches 195, the output value 104 in the next clock period (referring to the high-frequency clock period) will return to 0. When the output value 104 of counter 103 is 0 and 196 / 2 = 98, square wave clock signal 201 flips. For square wave clock signal 202, which is 90° phase-shifted relative to square wave clock signal 201, controller 101 can determine the phase shift threshold as 196 / 4 = 49. That is, when the output value 104 of counter 103 is 49 and 49 + 196 / 2 = 147, square wave clock signal 202 will be triggered to flip. For a square wave clock signal 203 that is 180° phase-shifted relative to the square wave clock signal 201, the controller 101 can determine the phase shift threshold as 196 / 2 = 98. That is, when the output value 104 of the counter 103 is 98 and 98 + 196 / 2 - 196 = 0, the square wave clock signal 203 will be triggered to flip (the square wave clock signal 203 is out of phase with the square wave clock signal 201). For a square wave clock signal 204 that is 270° phase-shifted relative to the square wave clock signal 201, the controller 101 can determine the phase shift threshold as 196 * 3 / 4 ​​= 147. That is, when the output value 104 of the counter 103 is 147 and 147 + 196 / 2 - 196 = 49, the square wave clock signal 204 will be triggered to flip (the square wave clock signal 204 is out of phase with the square wave clock signal 202).

[0026] Assuming the division ratio for clock cycle 208 is 164, when the output value 104 of counter 103 reaches 163, the output value 104 will return to 0 in the next clock cycle. When the output value 104 of counter 103 is 0 and 164 / 2 = 82, the square wave clock signal 201 flips. For the square wave clock signal 202, which is 90° phase-shifted relative to the square wave clock signal 201, the controller 101 can determine the phase shift threshold as 164 / 4 = 41. That is, when the output value 104 of counter 103 is 41 and 41 + 164 / 2 = 123, the square wave clock signal 202 will be triggered to flip. For a square wave clock signal 203 that is 180° phase-shifted relative to the square wave clock signal 201, the controller 101 can determine the phase shift threshold as 164 / 2 = 82. That is, when the output value 104 of the counter 103 is 82 and 82 + 164 / 2 - 164 = 0, the square wave clock signal 203 will be triggered to flip (the square wave clock signal 203 is out of phase with the square wave clock signal 201). For a square wave clock signal 204 that is 270° phase-shifted relative to the square wave clock signal 201, the controller 101 can determine the phase shift threshold as 164 * 3 / 4 ​​= 123. That is, when the output value 104 of the counter 103 is 123 and 123 + 164 / 2 - 164 = 41, the square wave clock signal 204 will be triggered to flip (the square wave clock signal 204 is out of phase with the square wave clock signal 202).

[0027] As can be seen, the maximum output value of counter 103 differs in different square wave clock cycles due to different division ratios, thus requiring different phase shift thresholds to achieve the same phase shift value. In other words, in these embodiments, a uniform phase shift threshold cannot be set for all frequencies of the phase-shifted square wave clock signal.

[0028] In other embodiments of this application, it is possible to set a uniform phase shift threshold for all frequencies of the phase-shifted square wave clock signal by making the counter 103 have the same maximum output value in different square wave clock cycles. In these embodiments, in different square wave clock cycles, the number of steps required to complete one cycle can be adjusted by adjusting the step size of the output value of the counter 103 in one cycle (e.g., incrementing from 0 to the maximum output value and then back to 0), thereby achieving different frequency division ratios. In this document, the step size of one step refers to the increment of the output value when the counter receives a high-frequency clock signal pulse, and the step size from the maximum output value to 0 is 1. For example, a 6-bit counter has an output range of 0-63, with a maximum output value of 63. When the step size of each step is 1, it takes 64 steps to complete one cycle, achieving a frequency division ratio of 64. When the step size of each step is 2, it takes 32 steps to complete one cycle, achieving a frequency division ratio of 32. When each output value is repeated once, it takes 128 steps to complete one cycle (64 steps with a step size of 0 and the other 64 steps with a step size of 1), achieving a frequency division ratio of 128.

[0029] Simply setting the step size of each step to be equal or setting each output value to be repeated for the same number of times as in the above example can only increase or decrease an integer multiple on the basis of the fundamental frequency division ratio (that is, the frequency division ratio that can be achieved when the step size of each step is 1, the value of which is the maximum output value of the counter plus 1, for example, 64 in the above example). Replacing a counter with a fractional accumulator and adjusting the fractional addend thereof may allow finer adjustment of the frequency division ratio, but the hardware implementation cost is relatively high. Some embodiments described below provide a design with simple structure and low cost to achieve fine adjustment of the frequency division ratio.

[0030] According to some embodiments of the present application, the step size of the next step may be selected based on the required frequency division ratio and the current output value of the counter. That is, the step size of each step of the counter can be adjusted individually, so as to achieve the required frequency division ratio, instead of uniformly adjusting the step size of each step.

[0031] For example, assuming that the fundamental frequency division ratio is m, and the frequency division ratio 102 determined by the controller 101 is n. When n<m, m-n output values can be determined, for each of these output values, the step size of the next step is selected to be 2 (that is, m-n output values are skipped), and for the remaining output values, the step size of the next step is selected to be 1, then the obtained frequency division ratio is n. When n>m, n-m output values can be determined, for each of these output values, the step size of the next step is selected to be 0 (that is, n-m output values are repeated), and for the remaining output values, the step size of the next step is selected to be 1, then the obtained frequency division ratio is n. According to some embodiments of the present application, the bit-reversed values of the output values can be used to determine the output values that need to be skipped or repeated. For example, when m-n output values need to be skipped, those output values whose bit-reversed values are less than m-n can be selected to be skipped (or the step size of the next step is selected to be 2 for those output values whose bit-reversed values are less than m-n); when n-m output values need to be repeated, those output values whose bit-reversed values are less than n-m can be selected to be repeated. The output values selected in this way can be substantially uniformly distributed among all output values.

[0032] For example, when m = 16 (i.e., counter 103 is a 4-bit counter) and n = 12, mn = 4. It can be determined that the next clock cycle will skip four current output values: 0 (i.e., b0000, with its bit-reversed value b0000 = 0), 8 (i.e., b1000, with its bit-reversed value b0001 = 1), 4 (i.e., b0100, with its bit-reversed value b0010 = 2), and 12 (i.e., b1100, with its bit-reversed value b0011 = 3). The output sequence of counter 103 is: 0, 2, 3, 4, 6, 7, 8, 10, 11, 12, 14, 15. One cycle requires 12 steps, resulting in a frequency division ratio of 12. In this example, counter 103 selects a step size of 2 for the next step when the output values ​​are 0, 4, 8, and 12, and a step size of 1 for the next step when the output values ​​are other values.

[0033] For example, when m = 16 (i.e., counter 103 is a 4-bit counter), n = 20, and nm = 4, the four output values ​​to be repeated can be determined as 0 (i.e., b0000, whose bit order is reversed to b0000 = 0), 8 (i.e., b1000, whose bit order is reversed to b0001 = 1), 4 (i.e., b0100, whose bit order is reversed to b0010 = 2), and 12 (i.e., b1100, whose bit order is reversed to b0011 = 3). The output value sequence of counter 103 is: 0, 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15. One cycle requires 20 steps, resulting in a frequency division ratio of 20. It can be seen that when the output value is 0, 4, 8, or 12 for the first time, counter 103 selects a step size of 0 for the next step, while selecting a step size of 1 for the next step when the output value is other values. In this embodiment, a flag value can be set to indicate whether the output value has been repeated a required number of times r. For example, after outputting 0 once, the flag value is changed from 0 to 1. When 0 is output for the second time, it can be determined that 0 has been output once based on the current flag value of 1. Therefore, the step size for the next step should be 1, and the flag value is changed from 1 to 0.

[0034] By comparing the bit-inverted value of the counter output with the number of output values ​​that need to be skipped or repeated, the output values ​​that need to be skipped or repeated can be distributed as evenly as possible within the range of the maximum output value of the counter plus 1. Those skilled in the art can design various logic circuits or functional modules to implement the above selection method. In some other embodiments, the bit-inverted value of the output value may not be used; instead, the next step size may be selected based on the desired division ratio and the current output value of the counter in other ways. In some embodiments, when the division ratio is relatively small, a larger step size, such as 4, 8, 16, etc., can be selected. In some other embodiments, more than two step sizes can be selected. In some embodiments, when the division ratio is much larger than the basic division ratio, the required number of times r can be an integer greater than or equal to 2. Changing the flag value from 1 to 0 can be achieved by using an auxiliary counter to count the number of repetitions and comparing the number of repetitions with the required number of times r.

[0035] Figure 3 A structural block diagram of a semiconductor device 300 according to some embodiments of this application is shown. The semiconductor device 300 can be used to implement... Figure 1 The counter 103 shown, or a device with similar functionality, can generate a counting signal (e.g., the output value 104 of counter 103) based on a division ratio (e.g., division ratio 102). Figure 3 As shown, the semiconductor device 300 includes a selection indicator generator 301, an incremental selector 302, and an output stage 303. It should be understood that the semiconductor device 300 may also include... Figure 3 Other components not shown in the diagram. Although Figure 3 This demonstrates that some components are directly connected, and those skilled in the art will understand that these components may be connected to other components (not shown).

[0036] One input of the selection indicator generator 301 is used to receive the division ratio, and the other input is coupled to the output of the output stage 303 to receive the generated counting signal. The selection indicator generator 301 is configured to generate a selection indicator based on the received division ratio and the current clock cycle output value of the counting signal.

[0037] Increment selector 302 is coupled to selection indicator generator 301 and configured to select an increment value from a plurality of increment values ​​(e.g., increment value 1 to increment value N) based on the selection indicator output by selection indicator generator 301.

[0038] Output stage 303 is coupled to increment selector 302 and configured to generate the next clock cycle output value of the counting signal based on the selected increment value. Output stage 303 can output the output value for each clock cycle in response to the rising edge of the clock signal CLK.

[0039] Figure 4 A schematic diagram of the structure of a semiconductor device 401 according to some embodiments of this application is shown. The semiconductor device 401 may be... Figure 3 An example of a semiconductor device 300 is shown. Semiconductor device 401 is coupled to controller 402. Controller 402 can be... Figure 1 The controller 101 shown is similar. For example... Figure 4 As shown, controller 402 can output a division ratio div to semiconductor device 401 and receive the output value cnt[n:0] (i.e., the output value has n+1 bits) from semiconductor device 401. Controller 402 can generate a square wave clock signal based on cnt[n:0]. Semiconductor device 401 may include a bit order inverter 403, a comparator 404, a multiplexer 405, an adder 406, and a D flip-flop 407. It should be understood that semiconductor device 401 may also include... Figure 4 Other components not shown in the diagram. Although Figure 4 This demonstrates that some components are directly connected, and those skilled in the art will understand that these components may be connected to other components (not shown).

[0040] The bit inverter 403 and comparator 404 can constitute Figure 3The selection indicator generator 301 is shown. The input of a bit sequence inverter 403 is coupled to the output of a D flip-flop 407 to receive the output value cnt[n:0]. The bit sequence inverter 403 can perform a bit sequence inversion operation on cnt[n:0] and output the bit sequence inverted value of cnt[n:0]. One input terminal of a comparator 404 is coupled to the output of the bit sequence inverter 403 to receive the bit sequence inverted value of cnt[n:0]. In some embodiments, the bit sequence inversion operation of cnt[n:0] can be achieved directly by arranging the wiring order without setting up the bit sequence inverter 403. Another input terminal of the comparator 404 is coupled to a controller 402 to receive the division ratio div. The comparator 404 can output a selection indicator at its output terminal based on the bit sequence inverted value of cnt[n:0] and the division ratio div. It should be understood that, depending on the specific logic implementation, the comparator 404 may not directly compare the bit sequence inverted value of cnt[n:0] with the division ratio div. In some embodiments, inversion, shifting, and bit-order reversal operations can be performed on cnt[n:0] before comparison with the division ratio div. In some embodiments, several logical operations can also be performed on the division ratio div. For example, in some embodiments, when the bit-order reversal value of cnt[n:0] is greater than or equal to the difference between the basic division ratio and the division ratio div, the comparator 404 outputs a selection indicator of 0; when the bit-order reversal value of cnt[n:0] is less than the difference between the basic division ratio and the division ratio div, the comparator 404 outputs a selection indicator of 1. The basic division ratio is equal to the maximum output value of the counting signal plus 1. In other embodiments, when the bit-order reversal value of cnt[n:0] is less than the division ratio div, the comparator 404 outputs a selection indicator of 0; when the bit-order reversal value of cnt[n:0] is greater than or equal to the division ratio div, the comparator 404 outputs a selection indicator of 1.

[0041] The 405 multiplexer can be configured as a multiplexer Figure 3The incremental selector 302 is shown. The selection terminal of the multiplexer 405 is coupled to the output terminal of the comparator 404. The multiplexer 405 is configured to select one incremental value (e.g., 1 and 2) as its output based on a selection indication received at the selection terminal. In some embodiments, when the selection indication received at the selection terminal is 0, it indicates that the bit order inversion value of cnt[n:0] is greater than or equal to the difference between the basic division ratio and the division ratio div, and the incremental value output by the multiplexer 405 is 1; when the selection indication received at the selection terminal is 1, it indicates that the bit order inversion value of cnt[n:0] is less than the difference between the basic division ratio and the division ratio div, and the incremental value output by the multiplexer 405 is 2. In other embodiments, when the selection indication received by the selection terminal is 0, it indicates that the bit order reversal value of cnt[n:0] is less than the division ratio div, and the incremental value output by the multiplexer 405 is 1; when the selection indication received by the selection terminal is 1, it indicates that the bit order reversal value of cnt[n:0] is greater than or equal to the division ratio div, and the incremental value output by the multiplexer 405 is 2. In some embodiments, the incremental value available for selection by the multiplexer 405 may be more than two. In some embodiments, the incremental value available for selection by the multiplexer 405 may be other values.

[0042] Adder 406 and D flip-flop 407 can be configured Figure 3 The output stage 303 is shown. Adder 406 is configured to add cnt[n:0] to the incremental value output by multiplexer 405 to obtain the next clock cycle output value cnt_next[n:0]. D flip-flop 407 is coupled to adder 406 and configured to receive the output cnt_next[n:0] of adder 406. When the next rising edge of clock signal clk arrives, D flip-flop 407 outputs cnt_next[n:0]. Similar functionality can also be achieved using circuit structures containing other types of flip-flops.

[0043] Figure 5 This is a flowchart of a method for generating a counting signal based on a frequency division ratio, according to some embodiments of this application. Figure 5 The method shown can be derived from Figure 1 The counter 103 shown Figure 3 The semiconductor device 300 shown Figure 4 The illustrated semiconductor device 401 or a device with similar functionality may be implemented, or it may be implemented via software. For example, computer instructions may be stored in a machine-readable storage medium, which, when executed by a processor, causes the processor to perform certain actions. Figure 5 The method is illustrated. A machine-readable storage medium may comprise a storage medium or memory medium, such as a semiconductor storage device, a magnetic or optical medium (e.g., a magnetic disk or CD / DVD-ROM) or other storage media.

[0044] like Figure 5 As shown, in step 501, a selection indication can be generated based on the division ratio and the current clock cycle output value of the counting signal. In step 502, an increment value can be selected from a plurality of increment values ​​based on the selection indication. In step 503, the next clock cycle output value of the counting signal can be generated based on the selected increment value.

[0045] In some embodiments of this application, generating the selection indication based on the division ratio and the current clock cycle output value may include outputting the selection indication based on a comparison between the current clock cycle output value (with bit order reversed) and the division ratio.

[0046] In some embodiments of this application, outputting the selection indication may include: outputting a first selection indication when the bit-inverted current clock cycle output value is greater than or equal to the difference between the basic division ratio and the division ratio, wherein the basic division ratio is equal to the maximum output value of the counting signal plus 1; and outputting a second selection indication when the bit-inverted current clock cycle output value is less than the difference between the basic division ratio and the division ratio.

[0047] In some embodiments of this application, the plurality of incremental values ​​may include 1 and 2, and selecting an incremental value from the plurality of incremental values ​​based on the selection indication may include: selecting 1 when the selection indication is the first selection indication; and selecting 2 when the selection indication is the second selection indication.

[0048] In some embodiments of this application, generating the next clock cycle output value based on the selected increment value may include: adding the current clock cycle output value to the selected increment value to obtain the next clock cycle output value; and outputting the next clock cycle output value during the next clock cycle.

[0049] In this specification, the terms “comprising” and “including” are used in an open-ended manner and should therefore be construed as meaning “including but not limited to”. Furthermore, the term “coupling” can include direct connections or indirect connections via intermediate components.

[0050] The description in this specification is provided to enable those skilled in the art to practice or use the invention. Various modifications to the invention will readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device that generates a counting signal based on a frequency division ratio, the semiconductor device comprising: A selection indicator generator is configured to generate a selection indicator based on the division ratio and the current clock cycle output value of the counting signal; An incremental selector, coupled to the selection indication generator, and configured to select an incremental value from a plurality of incremental values ​​based on the selection indication; and An output stage, coupled to the increment selector, is configured to generate the next clock cycle output value of the counting signal based on the selected increment value.

2. The semiconductor device of claim 1, wherein the selection indication generator comprises: A first comparator includes an output terminal, the first comparator being configured to output the selection indication at the output terminal based on the bit-order-inverted current clock cycle output value and the division ratio.

3. The semiconductor device of claim 2, wherein the selection indicator generator further includes a bit order inverter coupled to the output stage and the first comparator and configured to receive the current clock cycle output value and output the bit-inverted current clock cycle output value.

4. The semiconductor device of claim 2, wherein the first comparator is configured to: When the bit-reversed current clock cycle output value is greater than or equal to the difference between the basic division ratio and the division ratio, a first selection indication is output, wherein the basic division ratio is equal to the maximum output value of the counting signal plus 1; and When the current clock cycle output value after bit reversal is less than the difference between the basic division ratio and the division ratio, a second selection indication is output.

5. The semiconductor device of claim 2, wherein the first comparator is configured to: When the current clock cycle output value after bit reversal is less than the frequency division ratio, a first selection indication is output; and When the current clock cycle output value after bit reversal is greater than or equal to the frequency division ratio, a second selection indication is output.

6. The semiconductor device of claim 4 or 5, wherein the incremental selector includes a multiplexer having a selection terminal coupled to the output terminal of the first comparator.

7. The semiconductor device of claim 4 or 5, wherein the plurality of incremental values ​​includes 1 and 2, and the incremental selector is configured to: When the selection instruction is the first selection instruction, select 1; and When the selection instruction is the second selection instruction, select 2.

8. The semiconductor device of claim 1, wherein the output stage includes an adder configured to add the current clock cycle output value to the selected increment value.

9. The semiconductor device of claim 8, wherein the output stage further includes a flip-flop coupled to the adder and configured to receive the output of the adder and output the next clock cycle output value during the next clock cycle.

10. A circuit system comprising a semiconductor device according to any one of claims 1-9.

11. A circuit system comprising a semiconductor device according to any one of claims 2-7, and further comprising a controller coupled to the first comparator and the output stage, the controller being configured to output the division ratio, receive the counting signal, and generate a square wave clock signal based on the counting signal.

12. The circuit system of claim 11, further comprising a triangular wave generation circuit coupled to the controller, the triangular wave generation circuit being configured to generate a triangular wave based on the square wave clock signal.

13. The circuit system of claim 12, further comprising a second comparator coupled to the triangular wave generation circuit, the second comparator being configured to generate a pulse width modulation signal based on the triangular wave and a specific signal.

14. A method for generating a counting signal based on a frequency division ratio, comprising: A selection indication is generated based on the frequency division ratio and the current clock cycle output value of the counting signal; Based on the selection instruction, an incremental value is selected from a plurality of incremental values; and The next clock cycle output value of the counting signal is generated based on the selected increment value.

15. The method of claim 14, wherein generating the selection indication based on the division ratio and the current clock cycle output value comprises outputting the selection indication based on the current clock cycle output value after bit reversal and the division ratio.

16. The method of claim 15, wherein outputting the selection indication comprises: When the current clock cycle output value after bit reversal is greater than or equal to the difference between the basic division ratio and the division ratio, a first selection indication is output, wherein the basic division ratio is equal to the maximum output value of the counting signal plus 1; and When the current clock cycle output value after bit reversal is less than the difference between the basic division ratio and the division ratio, a second selection indication is output.

17. The method of claim 15, wherein outputting the selection indication comprises: When the current clock cycle output value after bit reversal is less than the frequency division ratio, a first selection indication is output; and When the current clock cycle output value after bit reversal is greater than or equal to the frequency division ratio, a second selection indication is output.

18. The method of claim 16 or 17, wherein the plurality of incremental values ​​includes 1 and 2, and selecting an incremental value from the plurality of incremental values ​​based on the selection indication includes: When the selection instruction is the first selection instruction, select 1; and When the selection instruction is the second selection instruction, select 2.

19. The method of claim 14, wherein generating the next clock cycle output value based on the selected increment value comprises: The current clock cycle output value is added to the selected increment value to obtain the next clock cycle output value; and The next clock cycle output value is output during the next clock cycle.

20. A machine-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 14-19.

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